[Intel-SIG] CWF PMU legacy support including core/uncore/event and their fixes · Pull Request !18430 · openEuler/kernel

There are 3 parts for Clearwater PMU legacy support including core/uncore/events.

Here are the commit list including fixes.

# core parts
48d66c89dce1,perf/x86/intel: Add PMU support for Clearwater Forest,2025-04-17 14:21:23,Dapeng Mi <dapeng1.mi@linux.intel.com>,v6.16-rc1,v6.16-rc1
43bb700cff6b,x86/cpu: Update Intel Family comments,2025-02-22 12:50:18,Peter Zijlstra <peterz@infradead.org>,v6.15-rc1
782cffeec9ad,perf/x86/intel: Fix event constraints for LNC,2025-02-20 16:07:10,Kan Liang <kan.liang@linux.intel.com>,v6.14-rc4 # fix of a932aa0e868f
aa5d2ca7c179,perf/x86/intel: Fix bitmask of OCR and FRONTEND events for LNC,2024-12-20 15:31:14,Kan Liang <kan.liang@linux.intel.com>,v6.13-rc5 # fix of a932aa0e868f
b8c3a2502a20,perf/x86/intel/ds: Add PEBS format 6,2024-12-17 17:47:23,Kan Liang <kan.liang@linux.intel.com>,v6.13-rc5 # fix of a932aa0e868f
8ec9497d3ef3,tools/include: Sync uapi/linux/perf.h with the kernel sources,2024-08-06 14:34:29,Namhyung Kim <namhyung@kernel.org>,v6.11-rc4
608f6976c309,perf/x86/intel: Support new data source for Lunar Lake,2024-07-04 16:00:38,Kan Liang <kan.liang@linux.intel.com>,v6.11-rc1,v6.11-rc1
090262439f66,perf/x86/intel: Rename model-specific pebs_latency_data functions,2024-07-04 16:00:38,Kan Liang <kan.liang@linux.intel.com>,v6.11-rc1,v6.11-rc1
a932aa0e868f,perf/x86: Add Lunar Lake and Arrow Lake support,2024-07-04 16:00:37,Kan Liang <kan.liang@linux.intel.com>,v6.11-rc1,v6.11-rc1
e8df9d9f4209,perf/x86/intel: Correct incorrect 'or' operation for PMU capabilities,2023-11-21 09:46:28,Dapeng Mi <dapeng1.mi@linux.intel.com>,v6.7-rc3 # fix of 97588df87b56
950ecdc672ae,perf/x86/intel: Fix broken fixed event constraints extension,2023-09-11 06:51:28,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1 # fix of 97588df87b56
97588df87b56,perf/x86/intel: Add common intel_pmu_init_hybrid(),2023-08-29 20:59:23,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1,v6.7-rc1
b0560bfd4b70,perf/x86/intel: Clean up the hybrid CPU type handling code,2023-08-29 20:59:23,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1,v6.7-rc1
299a5fc8e783,perf/x86/intel: Apply the common initialization code for ADL,2023-08-29 20:59:23,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1,v6.7-rc1
d87d221f854b,perf/x86/intel: Factor out the initialization code for ADL e-core,2023-08-29 20:59:22,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1,v6.7-rc1
0ba0c03528e9,perf/x86/intel: Factor out the initialization code for SPR,2023-08-29 20:59:22,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1,v6.7-rc1
d4b5694c75d4,perf/x86/intel: Use the common uarch name for the shared functions,2023-08-29 20:59:22,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1,v6.7-rc1

## uncore parts
fca24bf2b6b6,perf/x86/intel/uncore: Support customized MMIO map size,2025-07-09 13:40:19,Kan Liang <kan.liang@linux.intel.com>,v6.17-rc1,v6.17-rc1
cf002dafedd0,perf/x86/intel/uncore: Support MSR portal for discovery tables,2025-07-09 13:40:19,Kan Liang <kan.liang@linux.intel.com>,v6.17-rc1,v6.17-rc1
b6ccddd6fe1f,perf/x86/intel/uncore: Add Clearwater Forest support,2024-12-17 17:47:23,Kan Liang <kan.liang@linux.intel.com>,v6.13-rc5,v6.13-rc5
## events parts
e415c1493fa1,perf vendor events: Add Clearwaterforest events,2025-02-12 19:54:38,Ian Rogers <irogers@google.com>,v6.15-rc1,v6.15-rc1

## GNR fixes
6d642735cdb6,perf/x86/intel/uncore: Support more units on Granite Rapids,2025-01-10 18:16:50,Kan Liang <kan.liang@linux.intel.com>,v6.14-rc1
3f710be02ea6,perf/x86/intel/uncore: Clean up func_id,2025-01-10 18:16:50,Kan Liang <kan.liang@linux.intel.com>,v6.14-rc1

some fixes defails, these fixes are included in previous commit list. here just list the details
### fixes ###
### related with 608f6976c309
8ec9497d3ef3,tools/include: Sync uapi/linux/perf.h with the kernel sources,2024-08-06 14:34:29,Namhyung Kim <namhyung@kernel.org>,v6.11-rc4

#### fixes:a932aa0e868f
782cffeec9ad,perf/x86/intel: Fix event constraints for LNC,2025-02-19 06:10:05,Kan Liang <kan.liang@linux.intel.com>,v6.14-rc4
aa5d2ca7c179,perf/x86/intel: Fix bitmask of OCR and FRONTEND events for LNC,2024-12-16 08:02:52,Kan Liang <kan.liang@linux.intel.com>,v6.13-rc5
b8c3a2502a20,perf/x86/intel/ds: Add PEBS format 6,2024-12-16 12:45:02,Kan Liang <kan.liang@linux.intel.com>,v6.13-rc5

#### fixes:97588df87b56, double check
e8df9d9f4209,perf/x86/intel: Correct incorrect 'or' operation for PMU capabilities,2023-11-21 09:46:28,Dapeng Mi <dapeng1.mi@linux.intel.com>,v6.7-rc3
950ecdc672ae,perf/x86/intel: Fix broken fixed event constraints extension,2023-09-11 06:51:28,Kan Liang <kan.liang@linux.intel.com>,v6.7-rc1

Test Result: PASS including core/uncore/event testing refer to below test contents

++ echo 'uncore test'
uncore test
++ ls /sys/devices/
++ grep uncore
uncore_b2cmi_0
uncore_b2cmi_1
uncore_b2cmi_10
uncore_b2cmi_11
uncore_b2cmi_2
uncore_b2cmi_3
uncore_b2cmi_4
uncore_b2cmi_5
uncore_b2cmi_6
uncore_b2cmi_7
uncore_b2cmi_8
uncore_b2cmi_9
uncore_b2cxl_0
uncore_b2cxl_1
uncore_b2cxl_10
uncore_b2cxl_11
uncore_b2cxl_12
uncore_b2cxl_13
uncore_b2cxl_14
uncore_b2cxl_15
uncore_b2cxl_2
uncore_b2cxl_3
uncore_b2cxl_4
uncore_b2cxl_5
uncore_b2cxl_6
uncore_b2cxl_7
uncore_b2cxl_8
uncore_b2cxl_9
uncore_b2hot_0
uncore_b2hot_1
uncore_b2hot_10
uncore_b2hot_11
uncore_b2hot_12
uncore_b2hot_13
uncore_b2hot_14
uncore_b2hot_15
uncore_b2hot_16
uncore_b2hot_17
uncore_b2hot_18
uncore_b2hot_19
uncore_b2hot_2
uncore_b2hot_3
uncore_b2hot_4
uncore_b2hot_5
uncore_b2hot_6
uncore_b2hot_7
uncore_b2hot_8
uncore_b2hot_9
uncore_b2upi_0
uncore_b2upi_1
uncore_b2upi_2
uncore_b2upi_3
uncore_b2upi_4
uncore_b2upi_5
uncore_cha_0
uncore_cha_1
uncore_cha_10
uncore_cha_11
uncore_cha_12
uncore_cha_13
uncore_cha_14
uncore_cha_15
uncore_cha_16
uncore_cha_17
uncore_cha_18
uncore_cha_19
uncore_cha_2
uncore_cha_20
uncore_cha_21
uncore_cha_22
uncore_cha_23
uncore_cha_24
uncore_cha_25
uncore_cha_26
uncore_cha_27
uncore_cha_28
uncore_cha_29
uncore_cha_3
uncore_cha_30
uncore_cha_31
uncore_cha_32
uncore_cha_33
uncore_cha_34
uncore_cha_35
uncore_cha_36
uncore_cha_37
uncore_cha_38
uncore_cha_39
uncore_cha_4
uncore_cha_40
uncore_cha_41
uncore_cha_42
uncore_cha_43
uncore_cha_44
uncore_cha_45
uncore_cha_46
uncore_cha_47
uncore_cha_48
uncore_cha_49
uncore_cha_5
uncore_cha_50
uncore_cha_51
uncore_cha_52
uncore_cha_53
uncore_cha_6
uncore_cha_7
uncore_cha_8
uncore_cha_9
uncore_cxlcm_16
uncore_cxlcm_18
uncore_cxlcm_2
uncore_cxlcm_4
uncore_cxlcm_6
uncore_cxlcm_8
uncore_cxldp_17
uncore_cxldp_19
uncore_cxldp_3
uncore_cxldp_5
uncore_cxldp_7
uncore_cxldp_9
uncore_iio_1
uncore_iio_11
uncore_iio_12
uncore_iio_14
uncore_iio_2
uncore_iio_3
uncore_iio_4
uncore_iio_5
uncore_iio_6
uncore_iio_9
uncore_iio_free_running_0
uncore_iio_free_running_1
uncore_iio_free_running_10
uncore_iio_free_running_11
uncore_iio_free_running_12
uncore_iio_free_running_13
uncore_iio_free_running_14
uncore_iio_free_running_2
uncore_iio_free_running_3
uncore_iio_free_running_4
uncore_iio_free_running_5
uncore_iio_free_running_6
uncore_iio_free_running_7
uncore_iio_free_running_8
uncore_iio_free_running_9
uncore_imc
uncore_irp_1
uncore_irp_11
uncore_irp_12
uncore_irp_14
uncore_irp_2
uncore_irp_3
uncore_irp_4
uncore_irp_5
uncore_irp_6
uncore_irp_9
uncore_mdf_sbo_0
uncore_mdf_sbo_1
uncore_mdf_sbo_10
uncore_mdf_sbo_11
uncore_mdf_sbo_12
uncore_mdf_sbo_13
uncore_mdf_sbo_14
uncore_mdf_sbo_15
uncore_mdf_sbo_16
uncore_mdf_sbo_17
uncore_mdf_sbo_18
uncore_mdf_sbo_19
uncore_mdf_sbo_2
uncore_mdf_sbo_20
uncore_mdf_sbo_21
uncore_mdf_sbo_22
uncore_mdf_sbo_23
uncore_mdf_sbo_24
uncore_mdf_sbo_25
uncore_mdf_sbo_26
uncore_mdf_sbo_27
uncore_mdf_sbo_28
uncore_mdf_sbo_29
uncore_mdf_sbo_3
uncore_mdf_sbo_30
uncore_mdf_sbo_31
uncore_mdf_sbo_32
uncore_mdf_sbo_33
uncore_mdf_sbo_34
uncore_mdf_sbo_35
uncore_mdf_sbo_36
uncore_mdf_sbo_37
uncore_mdf_sbo_38
uncore_mdf_sbo_39
uncore_mdf_sbo_4
uncore_mdf_sbo_40
uncore_mdf_sbo_41
uncore_mdf_sbo_42
uncore_mdf_sbo_43
uncore_mdf_sbo_44
uncore_mdf_sbo_45
uncore_mdf_sbo_46
uncore_mdf_sbo_47
uncore_mdf_sbo_48
uncore_mdf_sbo_49
uncore_mdf_sbo_5
uncore_mdf_sbo_50
uncore_mdf_sbo_51
uncore_mdf_sbo_52
uncore_mdf_sbo_53
uncore_mdf_sbo_54
uncore_mdf_sbo_55
uncore_mdf_sbo_56
uncore_mdf_sbo_57
uncore_mdf_sbo_58
uncore_mdf_sbo_59
uncore_mdf_sbo_6
uncore_mdf_sbo_60
uncore_mdf_sbo_61
uncore_mdf_sbo_62
uncore_mdf_sbo_63
uncore_mdf_sbo_64
uncore_mdf_sbo_65
uncore_mdf_sbo_66
uncore_mdf_sbo_67
uncore_mdf_sbo_68
uncore_mdf_sbo_69
uncore_mdf_sbo_7
uncore_mdf_sbo_70
uncore_mdf_sbo_71
uncore_mdf_sbo_72
uncore_mdf_sbo_73
uncore_mdf_sbo_74
uncore_mdf_sbo_75
uncore_mdf_sbo_76
uncore_mdf_sbo_77
uncore_mdf_sbo_78
uncore_mdf_sbo_79
uncore_mdf_sbo_8
uncore_mdf_sbo_9
uncore_pciex16_2
uncore_pciex16_3
uncore_pciex16_8
uncore_pciex8
uncore_pcu_0
uncore_pcu_1
uncore_pcu_2
uncore_pcu_3
uncore_pcu_4
uncore_ubox
uncore_upi_0
uncore_upi_1
uncore_upi_2
uncore_upi_3
uncore_upi_4
uncore_upi_5
++ perf stat -e uncore_upi/event=0x1/,uncore_cha/event=0x1/,uncore_imc/event=0x1/ -a sleep 1

Performance counter stats for 'system wide':

490,773,564      uncore_upi/event=0x1/
     4,514,681,392      uncore_cha/event=0x1/
        47,648,371      uncore_imc/event=0x1/

1.001814017 seconds time elapsed

++ echo 'core test'
core test
++ perf stat -a sleep 1

Performance counter stats for 'system wide':

145,354,804,583      cpu-clock                        #  144.101 CPUs utilized
               768      context-switches                 #    5.284 /sec
               144      cpu-migrations                   #    0.991 /sec
               689      page-faults                      #    4.740 /sec
       151,864,838      instructions                     #    1.30  insn per cycle
       116,618,702      cycles                           #    0.001 GHz
        32,433,632      branches                         #  223.134 K/sec
           418,091      branch-misses                    #    1.29% of all branches

1.008704208 seconds time elapsed

++ perf record -e instructions -Iax,bx -b -c 100000 sleep 1
[ perf record: Woken up 2 times to write data ]
[ perf record: Captured and wrote 0.029 MB perf.data (13 samples) ]
++ perf record -e branches -Iax,bx -b -c 10000 sleep 1
[ perf record: Woken up 2 times to write data ]
[ perf record: Captured and wrote 0.041 MB perf.data (30 samples) ]
++ echo 'event test'
event test
++ perf stat -e LONGEST_LAT_CACHE.MISS,LONGEST_LAT_CACHE.REFERENCE -a sleep 1

Performance counter stats for 'system wide':

119,696      LONGEST_LAT_CACHE.MISS
        18,451,510      LONGEST_LAT_CACHE.REFERENCE

1.007883825 seconds time elapsed

++ perf record -e instructions -Iax,bx -b -c 100000 sleep 1
[ perf record: Woken up 2 times to write data ]
[ perf record: Captured and wrote 0.030 MB perf.data (13 samples) ]
++ perf record -e branches -Iax,bx -b -c 10000 sleep 1
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.041 MB perf.data (30 samples) ]

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