# ComputerPrinciplesandDesign_Verilog

**Repository Path**: vzy2d/ComputerPrinciplesandDesign_Verilog

## Basic Information

- **Project Name**: ComputerPrinciplesandDesign_Verilog
- **Description**: 阅读《ComputerPrinciplesandDesign_Verilog》过程中码的一些代码
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2019-09-18
- **Last Updated**: 2020-12-19

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# ComputerPrinciplesandDesign_Verilog