diff --git a/bsp/acm32/acm32f0x0-nucleo/README.md b/bsp/acm32/acm32f0x0-nucleo/README.md index ea7fcfd283dc5f3626cc4104d6bd3eb3340c305c..4cd9c13dda8c5e5f6e1ae29e6eb6da51bda50fde 100644 --- a/bsp/acm32/acm32f0x0-nucleo/README.md +++ b/bsp/acm32/acm32f0x0-nucleo/README.md @@ -2,7 +2,7 @@ ## 1. 简介 -ACM32F0x0芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： +ACM32F0x0芯片是上海航芯电子科技股份有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： |--------------------------|--------------------| | 硬件 | 描述 | diff --git a/bsp/acm32/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c b/bsp/acm32/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c index 352f93fd59f4fac02c99a90200110694f6fcad62..fff2ffdc389aef88932a84fdaa5c3c63f527a2af 100644 --- a/bsp/acm32/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c +++ b/bsp/acm32/acm32f0x0-nucleo/libraries/Device/System_ACM32F0x0.c @@ -24,44 +24,6 @@ volatile uint32_t gu32_SystemCount; #define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ -#if 0 -/********************************************************************************* -* Function : HardFault_Handler -* Description : Hard Fault handle, while(1) loop, wait for debug -* Input : none -* Output : none -* Author : xwl -**********************************************************************************/ -void HardFault_Handler(void) -{ - while(1); -} - -/********************************************************************************* -* Function : SysTick_Handler -* Description : System tick handler -* Input : none -* Output : none -* Author : Chris_Kyle -**********************************************************************************/ -void SysTick_Handler(void) -{ - gu32_SystemCount++; -} - -/********************************************************************************* -* Function : System_SysTick_Init -* Description : System Tick Init. Period is 1 ms -* Input : none -* Output : none -* Author : Chris_Kyle -**********************************************************************************/ -void System_SysTick_Init(void) -{ - gu32_SystemCount = 0; - SysTick_Config(gu32_SystemClock / 1000); //1ms/tick -} -#endif /********************************************************************************* * Function : System_SysTick_Off * Description : Turn off System Tick diff --git a/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c b/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c index 7634e6d7d453a2adc286d8c37b012287af5fe34f..3e08ffa55cd66eea3735a2504d096f06a8a67c0f 100644 --- a/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c +++ b/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/HAL_UART.c @@ -877,25 +877,3 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) return HAL_OK; } -#if 0 -/********************************************************************************* -* Function : fputc -* Description : -* Input : -* Output : -* Author : Chris_Kyle Data : 2020 -**********************************************************************************/ -int fputc(int ch, FILE *f) -{ - if (Uart_Debug == NULL) - { - return 0; - } - - Uart_Debug->DR = ch; - - while ((Uart_Debug->FR & UART_FR_BUSY)); - - return ch; -} -#endif diff --git a/bsp/acm32/acm32f0x0-nucleo/project.uvguix.aisino b/bsp/acm32/acm32f0x0-nucleo/project.uvguix.aisino new file mode 100644 index 0000000000000000000000000000000000000000..c3ae45a801dbbf170d21d3a7f4522c4eaa59cde3 --- /dev/null +++ b/bsp/acm32/acm32f0x0-nucleo/project.uvguix.aisino @@ -0,0 +1,1905 @@ + + + + -6.1 + +
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0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\hwtimer\hwtimer.c + hwtimer.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\adc.c + adc.c + 0 + 0 + + + 4 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c + 0 + 0 + + + 4 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\dev_serial.c + dev_serial.c + 0 + 0 + + + 4 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\watchdog\dev_watchdog.c + dev_watchdog.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 5 + 39 + 1 + 0 + 0 + 0 + drivers\drv_soft_i2c.c + drv_soft_i2c.c + 0 + 0 + + + 5 + 40 + 1 + 0 + 0 + 0 + drivers\drv_rtc.c + drv_rtc.c + 0 + 0 + + + 5 + 41 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + 5 + 42 + 1 + 0 + 0 + 0 + drivers\drv_hwtimer.c + drv_hwtimer.c + 0 + 0 + + + 5 + 43 + 1 + 0 + 0 + 0 + drivers\drv_wdt.c + drv_wdt.c + 0 + 0 + + + 5 + 44 + 1 + 0 + 0 + 0 + drivers\drv_pm.c + drv_pm.c + 0 + 0 + + + 5 + 45 + 1 + 0 + 0 + 0 + drivers\drv_i2c.c + drv_i2c.c + 0 + 0 + + + 5 + 46 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 5 + 47 + 1 + 0 + 0 + 0 + drivers\drv_spi.c + drv_spi.c + 0 + 0 + + + 5 + 48 + 1 + 0 + 0 + 0 + drivers\drv_adc.c + drv_adc.c + 0 + 0 + + + 5 + 49 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 6 + 50 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 51 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 6 + 52 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 6 + 53 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 54 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_comm.c + scheduler_comm.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + 7 + 73 + 1 + 0 + 0 + 0 + ..\..\..\src\defunct.c + defunct.c + 0 + 0 + + + + + libcpu + 0 + 0 + 0 + 0 + + 8 + 74 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 8 + 76 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\context_rvds.S + context_rvds.S + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m0\cpuport.c + cpuport.c + 0 + 0 + + + diff --git a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx index e0f6df6bd25f1d1737faee876c48f991b1b7956c..97e83c10e0e38412e819b9f899ac4cbe2fda6c4a 100644 --- a/bsp/acm32/acm32f0x0-nucleo/project.uvprojx +++ b/bsp/acm32/acm32f0x0-nucleo/project.uvprojx @@ -1,7 +1,10 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ ACM32F0x0 @@ -13,31 +16,31 @@ ARMCM0 ARM - ARM.CMSIS.5.7.0 + ARM.CMSIS.5.9.0 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) 0 $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h - - - - - - - - - - + + + + + + + + + + 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf.exe --bin --output rtthread.bin ./build/keil/Obj/acm32f030.axf - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -306,7 +309,7 @@ 0x0 - + 1 @@ -333,9 +336,9 @@ 0 0 - + RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - + ..\..\..\components\drivers\include;applications;..\..\..\libcpu\arm\cortex-m0;libraries\Device;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\include;libraries\CMSIS;drivers;.;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;libraries\HAL_Driver\Inc;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include @@ -351,10 +354,10 @@ 0 4 - - - - + + + + @@ -366,13 +369,13 @@ 0 0x00000000 0x20000000 - + .\drivers\linker_scripts\link.sct - - - - - + + + + + @@ -385,92 +388,66 @@ 1 libraries\HAL_Driver\Src\HAL_IWDT.c - - HAL_UART.c 1 libraries\HAL_Driver\Src\HAL_UART.c - - HAL_RTC.c 1 libraries\HAL_Driver\Src\HAL_RTC.c - - HAL_EXTI.c 1 libraries\HAL_Driver\Src\HAL_EXTI.c - - HAL_DMA.c 1 libraries\HAL_Driver\Src\HAL_DMA.c - - HAL_TIMER.c 1 libraries\HAL_Driver\Src\HAL_TIMER.c - - HAL_ADC.c 1 libraries\HAL_Driver\Src\HAL_ADC.c - - HAL_I2C.c 1 libraries\HAL_Driver\Src\HAL_I2C.c - - Startup_ACM32F0x0.s 2 libraries\Device\Startup_ACM32F0x0.s - - HAL_CRC.c 1 libraries\HAL_Driver\Src\HAL_CRC.c - - HAL_WDT.c 1 libraries\HAL_Driver\Src\HAL_WDT.c - - HAL_SPI.c 1 libraries\HAL_Driver\Src\HAL_SPI.c - - HAL_GPIO.c 1 libraries\HAL_Driver\Src\HAL_GPIO.c - - System_ACM32F0x0.c 1 @@ -496,50 +473,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cunistd.c 1 ..\..\..\components\libc\compilers\common\cunistd.c - - cwchar.c 1 @@ -555,245 +518,534 @@ 1 ..\..\..\components\drivers\core\device.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - hwtimer.c 1 ..\..\..\components\drivers\hwtimer\hwtimer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - - completion.c + completion_up.c 1 - ..\..\..\components\drivers\ipc\completion.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\ipc\completion_up.c + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - adc.c 1 ..\..\..\components\drivers\misc\adc.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - - pin.c + dev_pin.c 1 - ..\..\..\components\drivers\pin\pin.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\pin\dev_pin.c - - - serial.c + dev_serial.c 1 - ..\..\..\components\drivers\serial\serial.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\serial\dev_serial.c - - - watchdog.c + dev_watchdog.c 1 - ..\..\..\components\drivers\watchdog\watchdog.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\watchdog\dev_watchdog.c @@ -805,71 +1057,51 @@ 1 drivers\drv_soft_i2c.c - - drv_rtc.c 1 drivers\drv_rtc.c - - drv_uart.c 1 drivers\drv_uart.c - - drv_hwtimer.c 1 drivers\drv_hwtimer.c - - drv_wdt.c 1 drivers\drv_wdt.c - - drv_pm.c 1 drivers\drv_pm.c - - drv_i2c.c 1 drivers\drv_i2c.c - - board.c 1 drivers\board.c - - drv_spi.c 1 drivers\drv_spi.c - - drv_adc.c 1 drivers\drv_adc.c - - drv_gpio.c 1 @@ -885,22 +1117,16 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 @@ -916,284 +1142,866 @@ 1 ..\..\..\src\clock.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - components.c 1 ..\..\..\src\components.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - idle.c 1 ..\..\..\src\idle.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - ipc.c 1 ..\..\..\src\ipc.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - irq.c 1 ..\..\..\src\irq.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kstdio.c 1 ..\..\..\src\klibc\kstdio.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kstring.c 1 ..\..\..\src\klibc\kstring.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kservice.c 1 ..\..\..\src\kservice.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mem.c 1 ..\..\..\src\mem.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mempool.c 1 ..\..\..\src\mempool.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - object.c 1 ..\..\..\src\object.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_comm.c 1 ..\..\..\src\scheduler_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - thread.c 1 ..\..\..\src\thread.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - timer.c 1 ..\..\..\src\timer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + defunct.c + 1 + ..\..\..\src\defunct.c + @@ -1204,22 +2012,16 @@ 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - - cpuport.c 1 @@ -1230,18 +2032,21 @@ + - - - + + + + - <Project Info> + project 0 1 + diff --git a/bsp/acm32/acm32f4xx-nucleo/README.md b/bsp/acm32/acm32f4xx-nucleo/README.md index 0a7404aa5c3ec2f210db083fcf66f0dceab4d8eb..1ce32facb17bb1a487ccd18ca29299661fdd127c 100644 --- a/bsp/acm32/acm32f4xx-nucleo/README.md +++ b/bsp/acm32/acm32f4xx-nucleo/README.md @@ -2,7 +2,7 @@ ## 1. 简介 -ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： +ACM32F4xx芯片是上海航芯电子科技股份有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： |--------------------------|--------------------| | 硬件 | 描述 | diff --git a/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.c b/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.c new file mode 100644 index 0000000000000000000000000000000000000000..33908ee3be57e3e9749d3307596010efde9f835d --- /dev/null +++ b/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.c @@ -0,0 +1,344 @@ +/* + ****************************************************************************** + * @file System_Accelerate.c + * @author AisinoChip Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief MCU Cache Peripheral Access Layer System Source File. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 AisinoChip. + * All rights reserved. + ****************************************************************************** +*/ +#include "ACM32F4.h" + +#include "System_Accelerate.h" + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +/********************************************************************************* +* Function : System_EnableIAccelerate +* Description : Enable I-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_EnableIAccelerate(void) +{ + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_DisableIAccelerate +* Description : Disable I-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_DisableIAccelerate(void) +{ + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_InvalidateIAccelerate +* Description : Invalidate I-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_InvalidateIAccelerate(void) +{ + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_EnableDAccelerate +* Description : Enable D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_EnableDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + }while (ways-- != 0U); + }while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_DisableDAccelerate +* Description : Disable D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_DisableDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + }while(ways-- != 0U); + }while(sets-- != 0U); + + __DSB(); + __ISB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + __ISB(); + +} + +/********************************************************************************* +* Function : System_InvalidateDAccelerate +* Description : Invalidate D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_InvalidateDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + }while(ways-- != 0U); + }while(sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_CleanDAccelerate +* Description : Clean D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_CleanInvalidateDAccelerate +* Description : Cleans and Invalidates D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanInvalidateDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_InvalidateDAccelerate +* Description : Invalidate D-Cache by addr +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_InvalidateDAccelerate_by_Addr (uint32_t *addr, int32_t dsize) +{ + int32_t op_size = dsize + ((uint32_t)addr & 0x1F); + uint32_t op_addr = ((uint32_t)addr & (~0x1F)); + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) + { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_CleanDAccelerate_by_Addr +* Description : Cleans D-Cache for the given address +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanDAccelerate_by_Addr (uint32_t *addr, int32_t dsize) +{ + int32_t op_size = dsize + ((uint32_t)addr & 0x1F); + uint32_t op_addr = ((uint32_t)addr & (~0x1F)); + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_CleanInvalidateDAccelerate_by_Addr +* Description : Cleans and invalidates D_Cache for the given address +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanInvalidateDAccelerate_by_Addr (uint32_t *addr, int32_t dsize) +{ + int32_t op_size = dsize + ((uint32_t)addr & 0x1F); + uint32_t op_addr = ((uint32_t)addr & (~0x1F)); + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +} + + + diff --git a/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h b/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h index 4e0c2a6fa7ad049a714795b242002b2b2c9f4918..a669f82827403dbd5bc1bc41429316e91a440e5b 100644 --- a/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h +++ b/bsp/acm32/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h @@ -1,15 +1,22 @@ /* ****************************************************************************** * @file System_Accelerate.h + * @author AisinoChip Firmware Team * @version V1.0.0 * @date 2020 * @brief MCU Accelerate Peripheral Access Layer System header File. ****************************************************************************** + * @attention + * + * Copyright (c) 2020 AisinoChip. + * All rights reserved. + ****************************************************************************** */ #ifndef __SYSTEM_ACCELERATE_H__ #define __SYSTEM_ACCELERATE_H__ - +//#include "cmsis_armclang.h" +#include "stdint.h" /* System_EnableIAccelerate */ void System_EnableIAccelerate(void); @@ -17,12 +24,29 @@ void System_EnableIAccelerate(void); /* System_DisableIAccelerate */ void System_DisableIAccelerate(void); +/* System_InvalidateIAccelerate */ +void System_InvalidateIAccelerate(void); + /* System_EnableDAccelerate */ void System_EnableDAccelerate(void); /* System_DisableDAccelerate */ void System_DisableDAccelerate(void); +/* System_InvalidateDAccelerate */ +void System_InvalidateDAccelerate(void); + +/* System_CleanDAccelerate */ +void System_CleanDAccelerate(void); + +/* System_CleanInvalidateDAccelerate */ +void System_CleanInvalidateDAccelerate(void); + +/* System_InvalidateDAccelerate_by_Addr */ +void System_InvalidateDAccelerate_by_Addr (uint32_t *addr, int32_t dsize); + +/* System_CleanInvalidateDAccelerate_by_Addr */ +void System_CleanInvalidateDAccelerate_by_Addr (uint32_t *addr, int32_t dsize); #endif diff --git a/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash_Ex.c b/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash_Ex.c new file mode 100644 index 0000000000000000000000000000000000000000..3985a0e90a6a47c33734314e1365cf6b2aca1fdd --- /dev/null +++ b/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash_Ex.c @@ -0,0 +1,201 @@ +/* + ****************************************************************************** + * @file HAL_EFlash.c + * @author AisinoChip Firmware Team + * @version V1.0.1 + * @date 2021 + * @brief EFlash HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * @ Program operations functions + * @ Erase operations functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 AisinoChip. + * All rights reserved. + ****************************************************************************** +*/ +#include "ACM32Fxx_HAL.h" + +#define REG(x) (*(volatile UINT32 *)(x)) +#define PAGE_SIZE 512U + +void HAL_EFlash_ReWrite_Word(UINT32 addr, UINT32 value) +{ + UINT32 buff[128]; + UINT32 i; + UINT32 *dst; + UINT32 dst_addr; + UINT32 page_addr; + + if(REG(addr)==value) + { + return; + } + + page_addr = addr&0xFFFFFE00; + + dst = (UINT32 *)(page_addr); + for(i=0;i<(PAGE_SIZE/4); i++) + { + buff[i]=*dst++; + } + buff[(addr-page_addr)/4] = value; + + HAL_EFlash_ErasePage(page_addr); + + dst_addr = page_addr; + for(i=0;i<(PAGE_SIZE/4); i++) + { + HAL_EFlash_Program_Word(dst_addr,buff[i]); + dst_addr +=4; + } +} + +void HAL_EFlash_Return_to_Boot(void) +{ + HAL_EFlash_ReWrite_Word(0x00080400, 0xFFFFFFFFU); +} + +void HAL_EFlash_Remap_Enable(void) +{ + HAL_EFlash_ReWrite_Word(0x00080400, 0x89BC3F51U); +} + +void HAL_EFlash_JTAG_Enable(void) +{ + HAL_EFlash_ReWrite_Word(0x0008041C, 0xFFFFFFFFU); +} + +void HAL_EFlash_JTAG_Diable(void) +{ + HAL_EFlash_ReWrite_Word(0x0008041C, 0x89BC3F51U); +} + +void HAL_EFlash_Option_LOCK(void) +{ + HAL_EFlash_ReWrite_Word(0x000805FC, 0x55AA77EEU); +} + + +void HAL_EFlash_Init_Para(uint32_t fu32_freq) +{ + uint32_t lu32_RDWait; + uint32_t lu32_TERASE; + uint32_t lu32_TPROG; + uint32_t lu32_TNVS; + + /* Eflash Config */ + + lu32_TERASE = 35 * (fu32_freq/10000U) + 1; // 3.5 ms + lu32_TPROG = 9 * (fu32_freq/1000000U) + 1; // 9us + lu32_TNVS = (51 * (fu32_freq/1000000U))/10 + 5; // 5.1us + + if (fu32_freq >= 175000000) + { + lu32_RDWait = 8; + } + else if (fu32_freq > 156000000) + { + lu32_RDWait = 7; + } + else if(fu32_freq > 136000000) + { + lu32_RDWait = 6; + } + else if(fu32_freq > 116000000) + { + lu32_RDWait = 5; + } + else if(fu32_freq > 92000000) + { + lu32_RDWait = 4; + } + else if(fu32_freq > 74000000) + { + lu32_RDWait = 3; + } + else if(fu32_freq > 52000000) + { + lu32_RDWait = 2; + } + else if(fu32_freq > 32000000) + { + lu32_RDWait = 1; + } + else + { + lu32_RDWait = 0; + } + + EFC->TNVS = lu32_TNVS; + EFC->CTRL = (EFC->CTRL & ~(0x1F << 7)) | (lu32_RDWait << 7); + EFC->TERASE = lu32_TERASE; + EFC->TPROG = lu32_TPROG; + +} + +/********************************************************************************* +* Function : HAL_EFlash_ErasePage_Ex +* Description : Erase a Page, TERASE has been configured in System_Clock_Init() +* Input : +* Output : false: FAIL + true: SUCCESS +* Author : Chris_Kyle +**********************************************************************************/ +void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr) +{ + __set_PRIMASK(1); + + EFC->CTRL |= EFC_CTRL_PAGE_ERASE_MODE; + + EFC->SEC = 0x55AAAA55; + + *((volatile uint32_t *)fu32_Addr) = 0; + + System_InvalidateDAccelerate_by_Addr((uint32_t *)0x00100014, 32); // 32 bytes = 1 cache line , cache line one time + + while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY)) + { + System_InvalidateDAccelerate_by_Addr((uint32_t *)0x00100014, 32); + } + + EFC->CTRL &= ~EFC_CTRL_PAGE_ERASE_MODE; + System_InvalidateDAccelerate_by_Addr((uint32_t *)fu32_Addr, PAGE_SIZE); + + __set_PRIMASK(0); +} + +/********************************************************************************* +* Function : HAL_EFlash_Program_Word_Ex +* Description : Program a word, TPROG has been configured in System_Clock_Init() +* Input : +* Output : false: FAIL + true: SUCCESS +* Author : Chris_Kyle +**********************************************************************************/ +void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data) +{ + __set_PRIMASK(1); + + EFC->CTRL |= EFC_CTRL_PROGRAM_MODE; + + EFC->SEC = 0x55AAAA55; + + *((volatile uint32_t *)fu32_Addr) = fu32_Data; + System_InvalidateDAccelerate_by_Addr((uint32_t *)0x00100014, 32); + + while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY)) + { + System_InvalidateDAccelerate_by_Addr((uint32_t *)0x00100014, 32); + } + + EFC->CTRL &= ~EFC_CTRL_PROGRAM_MODE; + + __set_PRIMASK(0); +} + + + + diff --git a/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c b/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c index 14530ea9216aa217fe4fc0ff4dd4ced11390512d..f345210ebc7c84379f9947d59ea1f6186e44da84 100644 --- a/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c +++ b/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c @@ -879,26 +879,4 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) return HAL_OK; } -#if 0 -/********************************************************************************* -* Function : fputc -* Description : -* Input : -* Output : -* Author : Chris_Kyle Data : 2020 -**********************************************************************************/ -__weak int fputc(int ch, FILE *f) -{ - if (Uart_Debug == NULL) - { - return 0; - } - - Uart_Debug->DR = ch; - - while ((Uart_Debug->FR & UART_FR_BUSY)); - - return ch; -} -#endif diff --git a/bsp/acm32/acm32f4xx-nucleo/project.uvguix.aisino b/bsp/acm32/acm32f4xx-nucleo/project.uvguix.aisino new file mode 100644 index 0000000000000000000000000000000000000000..3202329daae90c747247f6d60f0639a278fc7f64 --- /dev/null +++ b/bsp/acm32/acm32f4xx-nucleo/project.uvguix.aisino @@ -0,0 +1,1860 @@ + + + + -6.1 + +
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+ + + + 0 + 1366 + 768 + + + + + diff --git a/bsp/acm32/acm32f4xx-nucleo/project.uvoptx b/bsp/acm32/acm32f4xx-nucleo/project.uvoptx index 6668d384aabf873760fe65333d8cf530f3526a9f..3faceb5c15ec2c90690790ba911aa7fdf2c6201d 100644 --- a/bsp/acm32/acm32f4xx-nucleo/project.uvoptx +++ b/bsp/acm32/acm32f4xx-nucleo/project.uvoptx @@ -318,4 +318,824 @@ + + ACM32_HAL + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + libraries\HAL_Driver\Src\HAL_UART.c + HAL_UART.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + libraries\HAL_Driver\Src\HAL_EXTI.c + HAL_EXTI.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + libraries\HAL_Driver\Src\HAL_DMA.c + HAL_DMA.c + 0 + 0 + + + 1 + 4 + 2 + 0 + 0 + 0 + libraries\Device\Startup_ACM32F4.s + Startup_ACM32F4.s + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + libraries\Device\System_ACM32F4.c + System_ACM32F4.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + .\libraries\Device\System_Accelerate.c + System_Accelerate.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + libraries\HAL_Driver\Src\HAL_GPIO.c + HAL_GPIO.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + libraries\HAL_Driver\Src\HAL_EFlash.c + HAL_EFlash.c + 0 + 0 + + + 1 + 9 + 1 + 0 + 0 + 0 + .\libraries\HAL_Driver\Src\HAL_EFlash_Ex.c + HAL_EFlash_Ex.c + 0 + 0 + + + + + Applications + 1 + 0 + 0 + 0 + + 2 + 10 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + DeviceDrivers + 1 + 0 + 0 + 0 + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\dev_serial.c + dev_serial.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 5 + 31 + 1 + 0 + 0 + 0 + drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + drivers\board.c + board.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 1 + 0 + 0 + 0 + + 7 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 7 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_comm.c + scheduler_comm.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 54 + 1 + 0 + 0 + 0 + ..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\..\src\defunct.c + defunct.c + 0 + 0 + + + + + libcpu + 1 + 0 + 0 + 0 + + 8 + 58 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 8 + 60 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\context_rvds.S + context_rvds.S + 0 + 0 + + + 8 + 61 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\cpuport.c + cpuport.c + 0 + 0 + + + 8 + 62 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + syscall_rvds.S + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\trustzone.c + trustzone.c + 0 + 0 + + + diff --git a/bsp/acm32/acm32f4xx-nucleo/project.uvprojx b/bsp/acm32/acm32f4xx-nucleo/project.uvprojx index f3290dcac0683370b0ae350f993b506d88420451..5d05475bbb49b6dae92364bf5f848b5d13596503 100644 --- a/bsp/acm32/acm32f4xx-nucleo/project.uvprojx +++ b/bsp/acm32/acm32f4xx-nucleo/project.uvprojx @@ -1,43 +1,47 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ ACM32F4XX 0x4 ARM-ADS - 6140000::V6.14::ARMCLANG + 6150000::V6.15::ARMCLANG + 6150000::V6.15::ARMCLANG 1 ARMCM33_DSP_FP ARM - ARM.CMSIS.5.7.0 + ARM.CMSIS.5.9.0 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ESEL ELITTLE - - + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) 0 $$Device:ARMCM33_DSP_FP$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP.h - - - - - - - - - - + + + + + + + + + + 0 0 - - - - - + + + + + 0 0 @@ -59,8 +63,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +73,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +84,14 @@ 1 0 fromelf.exe --bin --output ./build/ACM32F4.bin ./build/ACM32F4.axf - + 0 0 0 0 0 - + 0 @@ -101,15 +105,15 @@ 0 0 3 - - + + 1 - - - - + + + + SARMV8M.DLL -MPU TCM.DLL @@ -136,10 +140,10 @@ 1 BIN\UL2V8M.DLL "" () - - - - + + + + 0 @@ -172,7 +176,7 @@ 0 0 "Cortex-M33" - + 0 0 0 @@ -306,7 +310,7 @@ 0x20000 - + 1 @@ -325,7 +329,7 @@ 0 0 0 - 3 + 5 3 1 1 @@ -333,9 +337,9 @@ 0 0 - + RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - + libraries\CMSIS;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\include;drivers;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;applications;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\epoll;libraries\Device;.;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\finsh;..\..\..\libcpu\arm\cortex-m33;libraries\HAL_Driver\Inc;..\..\..\components\libc\compilers\common\extension\fcntl\octal @@ -349,12 +353,12 @@ 0 0 0 - 4 + 1 - - - - + + + + @@ -366,13 +370,13 @@ 0 0x00000000 0x20000000 - - - - - - - + + + + + + + @@ -385,48 +389,46 @@ 1 libraries\HAL_Driver\Src\HAL_UART.c - - HAL_EXTI.c 1 libraries\HAL_Driver\Src\HAL_EXTI.c - - HAL_DMA.c 1 libraries\HAL_Driver\Src\HAL_DMA.c - - Startup_ACM32F4.s 2 libraries\Device\Startup_ACM32F4.s - - System_ACM32F4.c 1 libraries\Device\System_ACM32F4.c - - + + System_Accelerate.c + 1 + .\libraries\Device\System_Accelerate.c + HAL_GPIO.c 1 libraries\HAL_Driver\Src\HAL_GPIO.c - - HAL_EFlash.c 1 libraries\HAL_Driver\Src\HAL_EFlash.c + + HAL_EFlash_Ex.c + 1 + .\libraries\HAL_Driver\Src\HAL_EFlash_Ex.c + @@ -447,50 +449,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cunistd.c 1 ..\..\..\components\libc\compilers\common\cunistd.c - - cwchar.c 1 @@ -506,188 +494,417 @@ 1 ..\..\..\components\drivers\core\device.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - - completion.c + completion_up.c 1 - ..\..\..\components\drivers\ipc\completion.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\ipc\completion_up.c + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - - pin.c + dev_pin.c 1 - ..\..\..\components\drivers\pin\pin.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\pin\dev_pin.c - - - serial.c + dev_serial.c 1 - ..\..\..\components\drivers\serial\serial.c - - - - - - __RT_IPC_SOURCE__ - - - - - - + ..\..\..\components\drivers\serial\dev_serial.c + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c @@ -699,15 +916,11 @@ 1 drivers\drv_gpio.c - - board.c 1 drivers\board.c - - drv_uart.c 1 @@ -723,22 +936,16 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 @@ -754,284 +961,866 @@ 1 ..\..\..\src\clock.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - components.c 1 ..\..\..\src\components.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - idle.c 1 ..\..\..\src\idle.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - ipc.c 1 ..\..\..\src\ipc.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - irq.c 1 ..\..\..\src\irq.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kstdio.c 1 ..\..\..\src\klibc\kstdio.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kstring.c 1 ..\..\..\src\klibc\kstring.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kservice.c 1 ..\..\..\src\kservice.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mem.c 1 ..\..\..\src\mem.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mempool.c 1 ..\..\..\src\mempool.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - object.c 1 ..\..\..\src\object.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_comm.c 1 ..\..\..\src\scheduler_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - thread.c 1 ..\..\..\src\thread.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - timer.c 1 ..\..\..\src\timer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + defunct.c + 1 + ..\..\..\src\defunct.c + @@ -1042,36 +1831,26 @@ 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - - cpuport.c 1 ..\..\..\libcpu\arm\cortex-m33\cpuport.c - - syscall_rvds.S 2 ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - - trustzone.c 1 @@ -1082,18 +1861,21 @@ + - - - + + + + - <Project Info> + project 0 1 + diff --git a/bsp/acm32/acm32h5xx-nucleo/.config b/bsp/acm32/acm32h5xx-nucleo/.config new file mode 100644 index 0000000000000000000000000000000000000000..a827a67a5f7a655bcc4fbd53f2db2a2c4ad5f861 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/.config @@ -0,0 +1,1103 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50002 +# CONFIG_RT_USING_STDC_ATOMIC is not set +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +# CONFIG_RT_USING_KTIME is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +# CONFIG_SOC_ACM32F403KCU7 is not set +# CONFIG_SOC_ACM32F403KEU7 is not set +# CONFIG_SOC_ACM32F403CCT7 is not set +# CONFIG_SOC_ACM32F403CET7 is not set +# CONFIG_SOC_ACM32F403RCT7 is not set +CONFIG_SOC_ACM32F403RET7=y +# CONFIG_SOC_ACM32F403VCT7 is not set +# CONFIG_SOC_ACM32F403VET7 is not set + +# +# ACM32F403RET7 +# +CONFIG_SOC_SRAM_START_ADDR=0x20000000 +CONFIG_SOC_SRAM_SIZE=0xC0 +CONFIG_SOC_FLASH_START_ADDR=0x00000000 +CONFIG_SOC_FLASH_SIZE=0x8000 + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# + +# +# Hardware GPIO +# +CONFIG_BSP_USING_GPIO1=y +CONFIG_BSP_USING_GPIO2=y +CONFIG_BSP_USING_GPIO3=y +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set + +# +# Hardware UART +# +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_UART2_RX_USING_DMA=y +CONFIG_BSP_UART2_TX_USING_DMA=y +CONFIG_BSP_USING_UART3=y +CONFIG_BSP_UART3_RX_USING_DMA=y +CONFIG_BSP_UART3_TX_USING_DMA=y +CONFIG_BSP_USING_UART4=y +CONFIG_BSP_UART4_RX_USING_DMA=y +CONFIG_BSP_UART4_TX_USING_DMA=y +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_LPUART is not set + +# +# Hardware I2C +# +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_I2C2 is not set + +# +# Hardware I2S +# +# CONFIG_BSP_USING_I2S1 is not set + +# +# Hardware CAN +# +# CONFIG_BSP_USING_CAN1 is not set +# CONFIG_BSP_USING_CAN2 is not set + +# +# Hardware TIMER +# +# CONFIG_BSP_USING_TIM1 is not set +# CONFIG_BSP_USING_TIM2 is not set +# CONFIG_BSP_USING_TIM3 is not set +# CONFIG_BSP_USING_TIM4 is not set +# CONFIG_BSP_USING_TIM6 is not set +# CONFIG_BSP_USING_TIM7 is not set +# CONFIG_BSP_USING_TIM14 is not set +# CONFIG_BSP_USING_TIM15 is not set +# CONFIG_BSP_USING_TIM16 is not set +# CONFIG_BSP_USING_TIM17 is not set + +# +# Hardware WDT +# +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_IWDT is not set +# CONFIG_BSP_USING_LCD is not set + +# +# Hardware SPI +# +# CONFIG_BSP_USING_SPI1 is not set +# CONFIG_BSP_USING_SPI2 is not set +# CONFIG_BSP_USING_SPI3 is not set +# CONFIG_BSP_USING_SPI4 is not set + +# +# Hardware CRYPTO +# +# CONFIG_BSP_USING_CRC is not set +# CONFIG_BSP_USING_AES is not set +# CONFIG_BSP_USING_HRNG is not set +# CONFIG_BSP_USING_CMP is not set +# CONFIG_BSP_USING_OPA is not set +# CONFIG_BSP_USING_TKEY is not set +# CONFIG_BSP_USING_RPMU is not set +# CONFIG_BSP_USING_USBD is not set + +# +# Board extended module Drivers +# diff --git a/bsp/acm32/acm32h5xx-nucleo/.ignore_format.yml b/bsp/acm32/acm32h5xx-nucleo/.ignore_format.yml new file mode 100644 index 0000000000000000000000000000000000000000..29b7c31648ea95a91034b88c4b5ea0702c7ec9d5 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- libraries diff --git a/bsp/acm32/acm32h5xx-nucleo/Debug_XIPFLASH.ini b/bsp/acm32/acm32h5xx-nucleo/Debug_XIPFLASH.ini new file mode 100644 index 0000000000000000000000000000000000000000..75fd5fdc31a295731ac857f9d80d96b756d88a53 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/Debug_XIPFLASH.ini @@ -0,0 +1,23 @@ +/******************************************************************************/ +/* Debug_RAM.ini: Initialization File for Debugging from Internal RAM */ +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2005-2014 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + +FUNC void Setup (void) { + SP = _RDWORD(0x1FF00000); // ջָSP0x00000000ַеݸֵSP + PC = _RDWORD(0x1FF00004); // óָPC0x00000004ַеݸֵPC + _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register +} + +//LOAD CLEAR NOCODE ..\..\..\BOOT\Spi_Boot\boot.axf +//LOAD CLEAR NOCODE .\boot.axf +LOAD .\boot.axf +LOAD %L INCREMENTAL // axfļRAM +//Setup(); //涨setupл + +//g, main //תmainʾʱҪmainִУע͵ˣ뿪ʼִ diff --git a/bsp/acm32/acm32h5xx-nucleo/EventRecorderStub.scvd b/bsp/acm32/acm32h5xx-nucleo/EventRecorderStub.scvd new file mode 100644 index 0000000000000000000000000000000000000000..2956b29683898915efa436cc948384a2c431dc31 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/Kconfig b/bsp/acm32/acm32h5xx-nucleo/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f02e680ad77804d7880185ca192a95fd1b6a34f5 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/Kconfig @@ -0,0 +1,22 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +source "$BSP_DIR/drivers/Kconfig" + diff --git a/bsp/acm32/acm32h5xx-nucleo/Project_user_xflash.sct b/bsp/acm32/acm32h5xx-nucleo/Project_user_xflash.sct new file mode 100644 index 0000000000000000000000000000000000000000..5bed4f4fe0e9a53753faf39788dbab08e03ce0ce --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/Project_user_xflash.sct @@ -0,0 +1,33 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +;LR_IROM1 0x08002000 0x00020000 { ; load region size_region +; ER_IROM1 0x08002000 0x00020000 { ; load address = execution address +LR_IROM1 0x08002000 0x001FE000 { ; load region size_region + ER_IROM1 0x08002000 0x001FE000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20008000 0x00050000 { ; RW data + .ANY (+RW +ZI) + } +; RW_IRAM2 0x20030000 0x00030000 { ;for LTDC test only +; RW_IRAM2 0x20030000 0x00050000 { ;for LTDC test only (192+128)KB +; .ANY (IRAM2) +; } +; RW_IRAM3 0xC0000000 0x00800000 { +; .ANY (SDRAM1) +; } +;total SDRAM SIZE: 8MBytes + +; RW_IRAM8 0x88000000 0x00800000 { +; .ANY (OSPI2PSRAM) +; } +; RW_IRAM9 0x80000000 0x00800000 { +; .ANY (OSPI1PSRAM) +; } +} + diff --git a/bsp/acm32/acm32h5xx-nucleo/README.md b/bsp/acm32/acm32h5xx-nucleo/README.md new file mode 100644 index 0000000000000000000000000000000000000000..7a30e0dc4f0e50511ddc0a3971c7c6a76be86a97 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/README.md @@ -0,0 +1,58 @@ +# ACM32H5xx板级支持包 + +## 1. 简介 + +ACM32H5xx芯片是上海航芯电子科技股份有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性： + +|--------------------------|--------------------| +| 硬件 | 描述 | +| -------------------------|--------------------| +|芯片型号 | ACM32H5XX系列 | +|CPU | ARM Cortex-M33 | +|主频 | 220MHz | +|片内SRAM | 420K | +|叠封SDRAM | 最大64MB | +|叠封PSRAM | 最大8MB | +|叠封Flash | 最大8MB | +|--------------------------|--------------------| + +具体型号及资源请参考上海航芯官方网站[ACM32F4](https://www.aisinochip.com/index.php/product/child1.html?id=280)。 + +## 2. 编译说明 + +推荐使用[env工具][1]，可以在console下进入到`bsp/acm32H5xx-nucleo`目录中，运行以下命令： + +`scons` + +来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。 + +也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。 + +## 3. 烧写及执行 + +开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。 + +### 3.1 运行结果 + +如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： + +## 4. 驱动支持情况及计划 + +| **片上外设** | **支持情况** | **备注** | +| ------------- | ------------ | ------------------------------------- | +| GPIO | 支持 | PA0, PA1... PF4 ---> PIN: 0, 1...83 | +| UART | 支持 | UART1/UART2 | +| LED | 支持 | LED1 | + +## 5. 联系人信息 + +维护人：AisinoChip < peter.yang@aisinochip.com > + +## 6. 参考 + +* 板子[数据手册][2] +* 芯片[数据手册][3] + + [1]: https://www.rt-thread.org/download.html#download-rt-thread-env-tool + [2]: www.aisinochip.com/index.php/product/detail/id/50.html + [3]: www.aisinochip.com/index.php/product/detail/id/50.html diff --git a/bsp/acm32/acm32h5xx-nucleo/SConscript b/bsp/acm32/acm32h5xx-nucleo/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..744d8d782140ebedcf11de3c61a1fc03b3b106d2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/acm32/acm32h5xx-nucleo/SConstruct b/bsp/acm32/acm32h5xx-nucleo/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..160697d0f20eb074c550474c50079a76d29ce410 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/SConstruct @@ -0,0 +1,34 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/SConscript b/bsp/acm32/acm32h5xx-nucleo/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..9bb9abae897a67a82e373e0aac77bf847dafe1a6 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/acm32h5xx_it.c b/bsp/acm32/acm32h5xx-nucleo/applications/acm32h5xx_it.c new file mode 100644 index 0000000000000000000000000000000000000000..32c33ea34bc9b6bdae45edf6b26b236935652626 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/acm32h5xx_it.c @@ -0,0 +1,184 @@ +/** + ****************************************************************************** + * @file USB_Device/HID_Standalone/Src/stm32f7xx_it.c + * @author MCD Application Team + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +//#include "ACM32Hxx_HAL.h" +//#include "usbd_def.h" +//#include "usbh_def.h" +#include +#include +#include "board.h" + + +/** @addtogroup STM32F7xx_HAL_Applications + * @{ + */ + +/** @addtogroup USB_Device_HID_Standalone + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +//extern USBH_HandleTypeDef USBH_Host; +//extern USBD_HandleTypeDef USBD_Device; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M7 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + + + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +//void SysTick_Handler(void) +//{ +// HAL_IncTick(); +//} + +/******************************************************************************/ +/* STM32F7xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles USB-On-The-Go HS global interrupt request. + * @param None + * @retval None + */ + +void USBOTG1_IRQHandler(void) +{ + extern void USBH_IRQHandler(uint8_t busid); + +// HAL_HCD_IRQHandler(USBH_Host.pData); +} + +void USBOTG2_IRQHandler(void) +{ + extern void USBH_IRQHandler(uint8_t busid); + +// HAL_HCD_IRQHandler(USBH_Host.pData); +} + +/** + * @brief This function handles USB OTG FS/HS Wakeup IRQ Handler. + * @param None + * @retval None + */ +#ifdef USE_USB_FS +void OTG_FS_WKUP_IRQHandler(void) +#else +void OTG_HS_WKUP_IRQHandler(void) +#endif +{ + +} + + +/** + * @brief This function handles External line 0 interrupt request. + * @param None + * @retval None + */ +void EXTI0_IRQHandler(void) +{ +// HAL_GPIO_EXTI_IRQHandler(WAKEUP_BUTTON_PIN); +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/demo/SConscript b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/demo/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..9c1b6d1ebd0ba47cd31cb54827c2c25ea10d2c65 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/demo/SConscript @@ -0,0 +1,17 @@ +from building import * +import os + +cwd = GetCurrentDir() +group = [] +src = Glob('*.c') +CPPPATH = [cwd] + +list = os.listdir(cwd) +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +group = group + DefineGroup('LVGL-demo', src, depend = ['BSP_USING_LVGL', 'BSP_USING_LVGL_DEMO'], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/demo/lv_demo.c b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/demo/lv_demo.c new file mode 100644 index 0000000000000000000000000000000000000000..2825ed05c4a3b2133c8c47b638e7d813e2bd1032 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/demo/lv_demo.c @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-17 Meco Man first version + * 2022-05-10 Meco Man improve rt-thread initialization process + */ + +#include + + #ifdef PKG_USING_LVGL + +//#include "lv_demo_benchmark.h" + +void lv_user_gui_init(void) +{ + /* display demo; you may replace with your LVGL application at here */ + +// lv_demo_benchmark(LV_DEMO_BENCHMARK_MODE_RENDER_AND_DRIVER); +} + + +#endif /* PKG_USING_LVGL */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_conf.h b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..fce3765a6296491016f05f732c1845f876dd3e5c --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_conf.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-18 Meco Man First version + */ + +#ifndef LV_CONF_H +#define LV_CONF_H + + +/*1: Show CPU usage and FPS count*/ +#define LV_USE_PERF_MONITOR 1 +#if LV_USE_PERF_MONITOR + #define LV_USE_PERF_MONITOR_POS LV_ALIGN_BOTTOM_RIGHT +#endif + +/*1: Show the used memory and the memory fragmentation + * Requires LV_MEM_CUSTOM = 0*/ +#define LV_USE_MEM_MONITOR 1 +#if LV_USE_MEM_MONITOR + #define LV_USE_MEM_MONITOR_POS LV_ALIGN_BOTTOM_LEFT +#endif + + +//#define LV_USE_PERF_MONITOR 1 +#define LV_COLOR_DEPTH 16 +#define LV_HOR_RES_MAX 800 +#define LV_VER_RES_MAX 480 + +#ifdef PKG_USING_LV_MUSIC_DEMO +/* music player demo */ +#define LV_USE_DEMO_RTT_MUSIC 1 +#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1 +#define LV_FONT_MONTSERRAT_12 1 +#define LV_FONT_MONTSERRAT_16 1 +#define LV_COLOR_SCREEN_TRANSP 1 +#endif /* PKG_USING_LV_MUSIC_DEMO */ + +#define LV_USE_BUILTIN_MALLOC 0 +#define LV_USE_BUILTIN_MEMCPY 0 +#define LV_USE_BUILTIN_SNPRINTF 0 + +#define LV_MALLOC rt_malloc +#define LV_REALLOC rt_realloc +#define LV_FREE rt_free +#define LV_MEMSET rt_memset +#define LV_MEMCPY rt_memcpy +#define LV_SNPRINTF rt_snprintf +#define LV_VSNPRINTF rt_vsnprintf +#define LV_STRLEN rt_strlen +#define LV_STRNCPY rt_strncpy + +#define LV_USE_LOG 1 +#define LV_LOG_PRINTF rt_kprintf +#define LV_LOG_LEVEL LV_LOG_LEVEL_WARN + + +//#define LV_USE_LARGE_COORD 1 + + + +/*use hardware DMA2D */ +#define LV_USE_GPU_ACM32_DMA2D 1 + + + +#define LV_USE_DEMO_BENCHMARK 0 + + +#endif + + diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_port_disp.c b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_port_disp.c new file mode 100644 index 0000000000000000000000000000000000000000..c5e302a7f314a999f0e524c6e938daabfd1892ea --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_port_disp.c @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-18 Meco Man The first version + * 2021-12-24 Rb Refresh using dma2d + */ + +#include +#include + +//#define DRV_DEBUG +#define LOG_TAG "LVGL.port.disp" +#include +#include "drv_lcd.h" + +/*A static or global variable to store the buffers*/ +static lv_disp_draw_buf_t disp_buf; + +static rt_device_t lcd_device = RT_NULL; +static struct rt_device_graphic_info info; + +static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/ + + +#define LVGL_BUF_PIX_SIZE ((LV_HOR_RES_MAX * LV_VER_RES_MAX) / 4) //1/4 full screen + + +static void lcd_fb_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p) +{ + extern void lcd_fill_array(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, void *pcolor); + /* color_p is a buffer pointer; the buffer is provided by LVGL */ + lcd_fill_array(area->x1, area->y1, area->x2, area->y2, color_p); + + /*IMPORTANT!!! + *Inform the graphics library that you are ready with the flushing*/ + lv_disp_flush_ready(disp_drv); +} + + +#ifdef rt_align +rt_align(RT_ALIGN_SIZE) +#else +ALIGN(RT_ALIGN_SIZE) +#endif +lv_color_t lv_disp_buf1[LVGL_BUF_PIX_SIZE]; // SDRAM1_BANK2; + + +void lv_port_disp_init(void) +{ + rt_err_t result; + + lcd_device = rt_device_find("lcd"); + if (lcd_device == 0) + { + LOG_E("lcd_device error!"); + return; + } + + result = rt_device_open(lcd_device, 0); + if (result != RT_EOK) + { + LOG_E("error!"); + return; + } + + /* get framebuffer address */ + result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info); + if (result != RT_EOK) + { + LOG_E("error!"); + /* get device information failed */ + return; + } + + RT_ASSERT (info.bits_per_pixel == 8 || info.bits_per_pixel == 16 || + info.bits_per_pixel == 24 || info.bits_per_pixel == 32); + + /*Initialize `disp_buf` with the buffer(s).*/ + lv_disp_draw_buf_init(&disp_buf, lv_disp_buf1, RT_NULL, LVGL_BUF_PIX_SIZE); + + lv_disp_drv_init(&disp_drv); /*Basic initialization*/ + + /*Set the resolution of the display*/ + disp_drv.hor_res = info.width; + disp_drv.ver_res = info.height; + + /*Set a display buffer*/ + disp_drv.draw_buf = &disp_buf; + + /*Used to copy the buffer's content to the display*/ + disp_drv.flush_cb = lcd_fb_flush; + + /*Finally register the driver*/ + lv_disp_drv_register(&disp_drv); +} + + +bool lv_check_last_flush(void) +{ + return lv_disp_flush_is_last(&disp_drv); +} + + diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_port_indev.c b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_port_indev.c new file mode 100644 index 0000000000000000000000000000000000000000..e573723491127a29f121b8bc340c22d43e0aad51 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/lvgl/lv_port_indev.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-07-07 liYony The first version (FT6336) + * 2022-07-08 liYony Add FT6206 + */ +#include +#include +#include + +#define DBG_TAG "LVGL.port.indev" +#define DBG_LVL DBG_INFO +#include + +/* RT-Thread touch device name */ +#define TOUCH_DEV_NAME "xpt0" + +lv_indev_t * touch_indev; +rt_device_t touch_dev; +struct rt_touch_data *read_data; + +static void input_read(lv_indev_drv_t *indev_drv, lv_indev_data_t *data) +{ + rt_memset(read_data, 0, sizeof(struct rt_touch_data)); + if(1 == rt_device_read(touch_dev, 0, read_data, 1)) + { + if (read_data->event == RT_TOUCH_EVENT_NONE) + return; + rt_kprintf("=2=%d %d %d %d %d\n", + read_data->event, + read_data->x_coordinate, + read_data->y_coordinate, + read_data->timestamp, + read_data->width); + if (read_data->event == RT_TOUCH_EVENT_DOWN) + data->state = LV_INDEV_STATE_PR; + if (read_data->event == RT_TOUCH_EVENT_MOVE) + data->state = LV_INDEV_STATE_PR; + if (read_data->event == RT_TOUCH_EVENT_UP) + data->state = LV_INDEV_STATE_REL; + data->point.x = read_data->x_coordinate; + data->point.y = read_data->y_coordinate; + } +} + +void lv_port_indev_init(void) +{ + static lv_indev_drv_t indev_drv; + + lv_indev_drv_init(&indev_drv); /*Basic initialization*/ + indev_drv.type = LV_INDEV_TYPE_POINTER; + indev_drv.read_cb = input_read; + + /*Register the driver in LVGL and save the created input device object*/ + touch_indev = lv_indev_drv_register(&indev_drv); +} + +static int lv_hw_touch_init(void) +{ + touch_dev = rt_device_find(TOUCH_DEV_NAME); + if (rt_device_open(touch_dev, RT_DEVICE_FLAG_RDONLY) != RT_EOK) + { + LOG_E("Can't open touch device:%s", TOUCH_DEV_NAME); + return -RT_ERROR; + } + + read_data = (struct rt_touch_data *)rt_calloc(1, sizeof(struct rt_touch_data)); + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(lv_hw_touch_init); diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/main.c b/bsp/acm32/acm32h5xx-nucleo/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..150b54eb57025b7dbb4d311b94ddb12d087fc865 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/main.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-17 AisinoChip the first version + */ + +#include +#include +#include "board.h" +#include +#include "drv_gpio.h" + +#define LED_PIN_NUM GET_PIN(A, 5) + + +int main(void) +{ + int i; + + rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT); + + while (1) + { + rt_thread_delay(10); + rt_pin_write(LED_PIN_NUM, PIN_LOW); + rt_thread_delay(RT_TICK_PER_SECOND / 2); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); + rt_thread_delay(RT_TICK_PER_SECOND / 2); + } +} + + diff --git a/bsp/acm32/acm32h5xx-nucleo/applications/mount.c b/bsp/acm32/acm32h5xx-nucleo/applications/mount.c new file mode 100644 index 0000000000000000000000000000000000000000..59c1e4928e3280f0747bfbff03fcfad4fdbd20cb --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/applications/mount.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-17 AisinoChip the first version + */ + +#include +#include +#include "board.h" +#include +#include "drv_gpio.h" +#include "drv_usb.h" + + +#define USB1_ROOT "/" + + + +int mnt_init(struct usbh_msc *msc_class) +{ + udisk_reg(OTG1_IDX, msc_class); + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("udisk1", USB1_ROOT, "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); + + return 0; +} +//INIT_ENV_EXPORT(mnt_init); + + +int udisk_mount(struct usbh_msc *msc_class) +{ + return mnt_init(msc_class); +} + + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/board/board.c b/bsp/acm32/acm32h5xx-nucleo/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..d957a646a75d4824a0643d6797c792be32fe16e2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/board/board.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-25 AisinoChip first implementation + */ + +#include +#include +#include "board.h" +#include + +#define SOC_SRAM_END_ADDR (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024) + +extern int rt_application_init(void); + +#if defined(__ARMCC_VERSION) + extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ + #pragma section="HEAP" +#else + extern int __bss_end; +#endif + +extern void rt_hw_uart_init(void); + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial EVB board. + */ +void rt_hw_board_init(void) +{ + /* init hal library */ +#if (INS_ACCELERATE_ENABLE == 1) + System_EnableIAccelerate(); +#endif + +#if (DATA_ACCELERATE_ENABLE == 1) + System_EnableDAccelerate(); +#endif + + HAL_Init(); + SystemClock_Config(SYSCLK_220M_SRC_XTH_12M, PCLK1_DIV_SELECT, PCLK2_DIV_SELECT, PCLK3_DIV_SELECT, PCLK4_DIV_SELECT); + + rt_hw_uart_init(); + + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + +#ifdef RT_USING_HEAP +#if defined(__ARMCC_VERSION) + rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR); +#else + /* init memory system */ + rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR); +#endif +#endif /* RT_USING_HEAP */ + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + + rt_kprintf("************************************************************\r\n"); + rt_kprintf("HCK: %u\r\n", HAL_RCC_GetHCLKFreq()); + rt_kprintf("PCLK1: %u\r\n", HAL_RCC_GetPCLK1Freq()); + rt_kprintf("PCLK2: %u\r\n", HAL_RCC_GetPCLK2Freq()); + rt_kprintf("PCLK3: %u\r\n", HAL_RCC_GetPCLK3Freq()); + rt_kprintf("PCLK4: %u\r\n", HAL_RCC_GetPCLK4Freq()); + rt_kprintf("\r\n"); + rt_kprintf("************************************************************\r\n"); +} + + +#ifdef USE_FULL_ASSERT +void assert_failed(uint8_t* file, uint32_t line) +{ + printfS("failed: file:%s, line:%u\r\n", file, line); + while (1); +} +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/board/board.h b/bsp/acm32/acm32h5xx-nucleo/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..c6f4a6fc058b0dc98343a7f10993046331c9a464 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/board/board.h @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-22 AisinoCip add board.h to this bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hal.h" + + +/*-------------------------- UART CONFIG BEGIN --------------------------*/ + +/** After configuring corresponding UART or UART DMA, you can use it. + * + * STEP 1, define macro define related to the serial port opening based on the serial port number + * such as #define BSP_USING_UATR1 + * + * STEP 2, according to the corresponding pin of serial port, modify the related serial port information + * such as #define UART1_TX_PORT GPIOX -> GPIOA + * #define UART1_RX_PORT GPIOX -> GPIOA + * #define UART1_TX_PIN GPIO_PIN_X -> GPIO_PIN_9 + * #define UART1_RX_PIN GPIO_PIN_X -> GPIO_PIN_10 + * + * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings. + * RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode + * + * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file + * such as #define BSP_UART1_RX_USING_DMA + * + */ + +#if defined(BSP_USING_UART1) + #define UART1_TX_PORT GPIOA + #define UART1_RX_PORT GPIOA + #define UART1_TX_PIN GPIO_PIN_9 + #define UART1_RX_PIN GPIO_PIN_10 + #define UART1_TX_ALTERNATE GPIO_FUNCTION_1 + #define UART1_RX_ALTERNATE GPIO_FUNCTION_1 + + #if defined(BSP_UART1_RX_USING_DMA) + #define UART1_RX_DMA_INSTANCE DMA_Channel0 + #define UART1_RX_DMA_RCC BIT12 + #define UART1_RX_DMA_IRQ DMA_IRQn + #define UART1_RX_DMA_CHANNEL 0 + #define UART1_RX_DMA_REQUEST REQ6_UART1_RECV + #endif /* BSP_UART1_RX_USING_DMA */ + + #if defined(BSP_UART1_TX_USING_DMA) + #define UART1_TX_DMA_INSTANCE DMA_Channel1 + #define UART1_TX_DMA_RCC BIT12 + #define UART1_TX_DMA_IRQ DMA_IRQn + #define UART1_TX_DMA_CHANNEL 1 + #define UART1_TX_DMA_REQUEST REQ5_UART1_SEND + #endif /* BSP_UART1_TX_USING_DMA */ + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + #define UART2_TX_PORT GPIOA + #define UART2_RX_PORT GPIOA + #define UART2_TX_PIN GPIO_PIN_2 + #define UART2_RX_PIN GPIO_PIN_3 + #define UART2_TX_ALTERNATE GPIO_FUNCTION_1 + #define UART2_RX_ALTERNATE GPIO_FUNCTION_1 + + #if defined(BSP_UART2_RX_USING_DMA) + #define UART2_RX_DMA_INSTANCE DMA_Channel0 + #define UART2_RX_DMA_RCC BIT12 + #define UART2_RX_DMA_IRQ DMA_IRQn + #define UART2_RX_DMA_CHANNEL 0 + #define UART2_RX_DMA_REQUEST REQ8_UART2_RECV + #endif /* BSP_UART2_RX_USING_DMA */ + + #if defined(BSP_UART2_TX_USING_DMA) + #define UART2_TX_DMA_INSTANCE DMA_Channel1 + #define UART2_TX_DMA_RCC BIT12 + #define UART2_TX_DMA_IRQ DMA_IRQn + #define UART2_TX_DMA_CHANNEL 1 + #define UART2_TX_DMA_REQUEST REQ7_UART2_SEND + #endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + #define UART3_TX_PORT GPIOC + #define UART3_RX_PORT GPIOC + #define UART3_TX_PIN GPIO_PIN_4 + #define UART3_RX_PIN GPIO_PIN_5 + + #if defined(BSP_UART3_RX_USING_DMA) + #define UART3_RX_DMA_INSTANCE DMA_Channel2 + #define UART3_RX_DMA_RCC BIT12 + #define UART3_RX_DMA_IRQ DMA_IRQn + #define UART3_RX_DMA_CHANNEL 2 + #define UART3_RX_DMA_REQUEST REQ29_UART3_RECV + #endif /* BSP_UART3_RX_USING_DMA */ + + #if defined(BSP_UART3_TX_USING_DMA) + #define UART3_TX_DMA_INSTANCE DMA_Channel3 + #define UART3_TX_DMA_RCC BIT12 + #define UART3_TX_DMA_IRQ DMA_IRQn + #define UART3_TX_DMA_CHANNEL 3 + #define UART3_TX_DMA_REQUEST REQ27_UART3_SEND + #endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) + #define UART4_TX_PORT GPIOA + #define UART4_RX_PORT GPIOA + #define UART4_TX_PIN GPIO_PIN_0 + #define UART4_RX_PIN GPIO_PIN_1 + + #if defined(BSP_UART4_RX_USING_DMA) + #define UART4_RX_DMA_INSTANCE DMA_Channel4 + #define UART4_RX_DMA_RCC BIT12 + #define UART4_RX_DMA_IRQ DMA_IRQn + #define UART4_RX_DMA_CHANNEL 4 + #define UART4_RX_DMA_REQUEST REQ46_UART4_RECV + #endif /* BSP_UART4_RX_USING_DMA */ + + #if defined(BSP_UART4_TX_USING_DMA) + #define UART4_TX_DMA_INSTANCE DMA_Channel5 + #define UART4_TX_DMA_RCC BIT12 + #define UART4_TX_DMA_IRQ DMA_IRQn + #define UART4_TX_DMA_CHANNEL 5 + #define UART4_TX_DMA_REQUEST REQ45_UART4_SEND + #endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ +/*-------------------------- UART CONFIG END --------------------------*/ + + +/*------------ memory operation using DMA, include memcpy() and memset() CONFIG BEGIN --------------------*/ +#if defined(RT_USING_HW_MEM_OPERATION) + #define MEM_OP_DMA_BASEADDR DMA1 + #define MEMSET_DMA_INSTANCE DMA1_Channel2 + #define MEMCPY_DMA_INSTANCE DMA1_Channel3 + #define MEMSET_DMA_CH 2 + #define MEMCPY_DMA_CH 3 + + +#endif /* BSP_USING_SDRAM1 */ + + +/*------------ memcpy and memset DMA CONFIG END --------------------*/ + + + + +/* board configuration */ + +void rt_hw_board_init(void); + +#endif /* __BOARD_H__ */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_dma.h b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..2b1581631b79c3c7d9ec304e1336ee1426dd7bcd --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_dma.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-27 AisinoChip The first version + */ +#ifndef __DRV_DMA_H__ +#define __DRV_DMA_H__ + +#include +#include "rtdevice.h" + +extern int drv_dma_hw_init(void); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_gpio.h b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..cd56dcf7298a96edd5485493c2adb686af699fe7 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_gpio.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-09-18 AisinoChip first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ +#include "board.h" + +#ifdef RT_USING_PIN + + +#define GET_PIN(PORTx,PIN) ((rt_base_t)((16 * GPIO_PORT##PORTx) + PIN)) + +rt_bool_t drv_gpio_init(GPIO_TypeDef *gpiox, rt_uint32_t pin, rt_uint32_t mode, + rt_uint32_t pull, rt_uint32_t alternate); +GPIO_TypeDef* drv_gpio_get_port(rt_uint32_t index); +rt_uint32_t drv_gpio_get_pin(rt_uint32_t index); +rt_base_t drv_gpio_get_index(const char* name); +rt_bool_t drv_gpio_init_by_name(const char* name, rt_uint32_t mode, + rt_uint32_t pull, rt_uint32_t alternate); + +#endif /* #ifdef RT_USING_PIN */ + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_log.h b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_log.h new file mode 100644 index 0000000000000000000000000000000000000000..7e0bfee5b4b77b2cdb5d2bcfc5ad9c1e78b1fe05 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_uart.h b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_uart.h new file mode 100644 index 0000000000000000000000000000000000000000..f60e7ea7a52eb5430245a993558996b32330b8dc --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/Inc/drv_uart.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-27 AisinoChip The first version + */ +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +#include +#include "rtdevice.h" + + +#ifdef RT_SERIAL_USING_DMA +struct dma_config +{ + DMA_Channel_TypeDef *Instance; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + + rt_uint32_t channel; + rt_uint32_t request; +}; +#endif + + +struct acm32_uart_config +{ + const char *name; + UART_TypeDef *Instance; + IRQn_Type irq_type; + enum_Enable_ID_t enable_id; + +#ifdef RT_SERIAL_USING_DMA + struct dma_config *dma_rx; + struct dma_config *dma_tx; +#endif + + GPIO_TypeDef *tx_port; + rt_uint16_t tx_pin; + rt_uint16_t tx_alternate; + + GPIO_TypeDef *rx_port; + rt_uint16_t rx_pin; + rt_uint16_t rx_alternate; +}; + +struct acm32_uart +{ + UART_HandleTypeDef handle; + struct acm32_uart_config *config; +#ifdef RT_SERIAL_USING_DMA + struct + { + DMA_HandleTypeDef handle; + rt_size_t last_index; + } dma_rx; + + struct + { + DMA_HandleTypeDef handle; + } dma_tx; +#endif + + rt_uint16_t uart_dma_flag; + struct rt_serial_device serial; +}; + + + + + + +#endif /* __DRV_UART_H__ */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/config/acm32h5xx_hal_conf.h b/bsp/acm32/acm32h5xx-nucleo/drivers/config/acm32h5xx_hal_conf.h new file mode 100644 index 0000000000000000000000000000000000000000..44819aef38919344732d275206e20e64ba3333f0 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/config/acm32h5xx_hal_conf.h @@ -0,0 +1,306 @@ +/****************************************************************************** +*@file : acm32h5xx_hal_conf.h +*@brief : HAL configuration file +******************************************************************************/ + +#ifndef __ACM32H5XX_HAL_CONF_H__ +#define __ACM32H5XX_HAL_CONF_H__ + +#include "hal_def.h" +#include "acm32h5xx.h" +#include "hal.h" + +/******* enable printf in debug stage ****************************************/ +#define DEBUG + +#ifdef DEBUG + #define printfS(fmt, ...) printf(fmt, ##__VA_ARGS__) +#else + #define printfS(fmt, ...) +#endif + +/******* enable assert in debug stage ****************************************/ +#define USE_FULL_ASSERT + +#ifdef USE_FULL_ASSERT + void assert_failed(uint8_t* file, uint32_t line); + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +#else + #define assert_param(expr) ((void)0U) +#endif + +/******* config data if or not in extern sram *******************************/ +//#define DATA_IN_ExtSRAM + +/* Configure the Vector Table location add offset address ------------------*/ + +//#define VECT_TAB_IROM +//#define VECT_TAB_SRAM +//#define VECT_TAB_SPI_FLASH + +#define VECT_TAB_OFFSET ( 0 ) + +#ifdef VECT_TAB_IROM + #define VECT_TAB_ADDR ( 0 + VECT_TAB_OFFSET ) +#elif defined ( VECT_TAB_SRAM ) + #define VECT_TAB_ADDR ( SRAM1_BASE_ADDR + VECT_TAB_OFFSET ) +#elif defined ( VECT_TAB_SPI_FLASH ) + #define VECT_TAB_ADDR ( SPI7_MEM_BASE_ADDR + 0x00002000 + VECT_TAB_OFFSET ) +#else + #warning vector table definition error. +#endif + +/******* config extern high speed osc freq and low osc freq in Hz ************/ +#define XTH_VALUE ( 12000000U ) +#define XTL_VALUE ( 32768U ) + + +/******* SysTick interrupt priority *****************************************/ +#define TICK_INT_PRIORITY ((1<<__NVIC_PRIO_BITS)-1) + +/******* SysTick ms period set ,1ms or 10ms **********************************/ +#define TICK_PERIOD_1MS (1U) +#define TICK_PERIOD_10MS (10U) +#define TICK_PERIOD_MS (TICK_PERIOD_1MS) + + +/******* instruction and data accelerate enable ******************************/ +#define INS_ACCELERATE_ENABLE (1U) //instruction accelerate enable +#define DATA_ACCELERATE_ENABLE (0U) //data accelerate enable + +/********************* EXTERNAL RAM AREA DEFINE ******************************/ +#define MEM_USE_SDRAM 0 +#define MEM_USE_OSPI1PSRAM 1 +#define MEM_USE_OSPI2PSRAM 2 + + +#define DISP_MEM_LOCATION MEM_USE_SDRAM + + +#define SDRAM1 __attribute__((section("SDRAM1"))) +#define OSPI1PSRAM __attribute__((section("OSPI1PSRAM"))) +#define OSPI2PSRAM __attribute__((section("OSPI2PSRAM"))) +#define IRAM2 __attribute__((section("IRAM2"))) + +#define SDRAM1_BANK0 __attribute__((section("SDRAM1_BANK0"))) +#define SDRAM1_BANK1 __attribute__((section("SDRAM1_BANK1"))) +#define SDRAM1_BANK2 __attribute__((section("SDRAM1_BANK2"))) +#define SDRAM1_BANK3 __attribute__((section("SDRAM1_BANK3"))) + + +/******* module selection ****************************************************/ + +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_EFUSE_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DWT_MODULE_ENABLED +#define HAL_WDT_MODULE_ENABLED +#define HAL_IWDT_MODULE_ENABLED +#define HAL_PMU_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_FMC_MODULE_ENABLED +//#define HAL_SPI_MODULE_ENABLED +//#define HAL_TIMER_MODULE_ENABLED +//#define HAL_LPTIM_MODULE_ENABLED +//#define HAL_FSUSB_MODULE_ENABLED +//#define HAL_PUF_MODULE_ENABLED +//#define HAL_CDE_MODULE_ENABLED +//#define HAL_NORFLASH_MODULE_ENABLED +//#define HAL_CRC_MODULE_ENABLED +//#define HAL_DIVIDER_MODULE_ENABLED +//#define HAL_AES_MODULE_ENABLED +//#define HAL_HRNG_MODULE_ENABLED +//#define HAL_ECC_MODULE_ENABLED +//#define HAL_RSA_MODULE_ENABLED +//#define HAL_DRBG_MODULE_ENABLED +//#define HAL_ECDSA_MODULE_ENABLED +//#define HAL_HASH_SHA1_MODULE_ENABLED +//#define HAL_HASH_SHA256_MODULE_ENABLED +//#define HAL_HASH_SHA384_MODULE_ENABLED +//#define HAL_HMAC_MODULE_ENABLED +//#define HAL_SDMMC_ENABLED +//#define HAL_OSPI_MODULE_ENABLED +//#define HAL_LTDC_MODULE_ENABLED +#ifdef HAL_LTDC_MODULE_ENABLED + #define HAL_DMA2D_MODULE_ENABLED +#endif +//#define HAL_I2C_MODULE_ENABLED +//#define HAL_DCMI_MODULE_ENABLED + +//#define HAL_PCD_MODULE_ENABLED + +/******* include modules header file *****************************************/ + + +#if ((INS_ACCELERATE_ENABLE==1) || (DATA_ACCELERATE_ENABLE==1)) + #include "system_accelerate.h" +#endif + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "hal_cortex.h" +#endif + +#ifdef HAL_RCC_MODULE_ENABLED + #include "hal_rcc.h" +#endif + +#ifdef HAL_EFUSE_MODULE_ENABLED + #include "hal_efuse.h" +#endif + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "hal_gpio.h" +#endif + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "hal_exti.h" +#endif + +#ifdef HAL_DMA_MODULE_ENABLED + #include "hal_dma.h" +#endif + +#ifdef HAL_DWT_MODULE_ENABLED + #include "hal_dwt.h" +#endif + +#ifdef HAL_WDT_MODULE_ENABLED + #include "hal_wdt.h" +#endif + +#ifdef HAL_IWDT_MODULE_ENABLED + #include "hal_iwdt.h" +#endif + +#ifdef HAL_PMU_MODULE_ENABLED + #include "hal_pmu.h" +#endif + +#ifdef HAL_UART_MODULE_ENABLED + #include "hal_usart.h" + #include "hal_uart.h" + #include "hal_uart_ex.h" +#endif + +#ifdef HAL_FMC_MODULE_ENABLED + #include "hal_fmc.h" +#endif + +#ifdef HAL_SPI_MODULE_ENABLED + #include "hal_spi.h" +#endif + +#ifdef HAL_TIMER_MODULE_ENABLED + #include "hal_timer.h" + #include "hal_timer_ex.h" +#endif + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "hal_lptim.h" +#endif + +#ifdef HAL_FSUSB_MODULE_ENABLED + #include "hal_fsusb.h" +#endif + +#ifdef HAL_PUF_MODULE_ENABLED + #include "hal_puf.h" +#endif + +#ifdef HAL_CDE_MODULE_ENABLED + #include "hal_cde.h" +#endif + +#ifdef HAL_NORFLASH_MODULE_ENABLED + #include "hal_norflash.h" +#endif + +#ifdef HAL_CRC_MODULE_ENABLED + #include "hal_crc.h" +#endif + +#ifdef HAL_DIVIDER_MODULE_ENABLED + #include "hal_divider.h" +#endif + +#ifdef HAL_AES_MODULE_ENABLED + #include "hal_aes.h" +#endif + +#ifdef HAL_HRNG_MODULE_ENABLED + #include "hal_hrng.h" +#endif + +#ifdef HAL_ECC_MODULE_ENABLED + #include "hal_ecc.h" + #include "hal_binary_ecc.h" +#endif + +#ifdef HAL_RSA_MODULE_ENABLED + #include "hal_rsa_keygen.h" +#endif + +#ifdef HAL_DRBG_MODULE_ENABLED + #include "hal_ctr_drbg.h" +#endif + +#ifdef HAL_ECDSA_MODULE_ENABLED + #include "hal_ecdsa.h" +#endif + +#ifdef HAL_HASH_SHA1_MODULE_ENABLED + #include "hal_sha1.h" +#endif + +#ifdef HAL_HASH_SHA256_MODULE_ENABLED + #include "hal_sha224_256.h" +#endif + +#ifdef HAL_HASH_SHA384_MODULE_ENABLED + #include "hal_sha384_512.h" +#endif + +#ifdef HAL_HMAC_MODULE_ENABLED + #include "hal_hmac.h" +#endif + +#ifdef HAL_SDMMC_ENABLED + #include "hal_sdmmc.h" + #include "hal_dlyb.h" +#endif + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "hal_ltdc.h" +#endif + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "hal_dma2d.h" +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "hal_ospi.h" +#endif + +#ifdef HAL_PCD_MODULE_ENABLED +// #include "usbd_def.h" + #include "usbd_config.h" + #include "hal_pcd.h" + #include "hal_pcd_ex.h" + #include "ll_usb.h" +#endif + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "hal_dcmi.h" +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +#include "hal_i2c.h" +#endif + + +#endif /* __ACM32H5XX_HAL_CONF_H__ */ + + \ No newline at end of file diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/config/uart_config.h b/bsp/acm32/acm32h5xx-nucleo/drivers/config/uart_config.h new file mode 100644 index 0000000000000000000000000000000000000000..7c7241ab7f74922c380ec12e6beb084e76ad5b2d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/config/uart_config.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "board.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_SERIAL) + +#if defined(BSP_USING_UART1) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .dma_rcc = UART1_RX_DMA_RCC, \ + .dma_irq = UART1_RX_DMA_IRQ, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .request = UART1_RX_DMA_REQUEST, \ + } +#endif /* UART1_DMA_RX_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .dma_rcc = UART1_TX_DMA_RCC, \ + .dma_irq = UART1_TX_DMA_IRQ, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .request = UART1_RX_DMA_REQUEST, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = USART1, \ + .irq_type = USART1_IRQn, \ + .enable_id = EN_UART1, \ + .tx_port = UART1_TX_PORT, \ + .tx_pin = UART1_TX_PIN, \ + .tx_alternate = UART1_TX_ALTERNATE, \ + .rx_port = UART1_RX_PORT, \ + .rx_pin = UART1_RX_PIN, \ + .rx_alternate = UART1_RX_ALTERNATE, \ + } +#endif /* UART1_CONFIG */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .dma_rcc = UART2_RX_DMA_RCC, \ + .dma_irq = UART2_RX_DMA_IRQ, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .request = UART2_RX_DMA_REQUEST, \ + } +#endif /* UART2_DMA_RX_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .dma_rcc = UART2_TX_DMA_RCC, \ + .dma_irq = UART2_TX_DMA_IRQ, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .request = UART2_TX_DMA_REQUEST, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = USART2, \ + .irq_type = USART2_IRQn, \ + .enable_id = EN_UART2, \ + .tx_port = UART2_TX_PORT, \ + .rx_port = UART2_RX_PORT, \ + .tx_pin = UART2_TX_PIN, \ + .rx_pin = UART2_RX_PIN, \ + } +#endif /* UART2_CONFIG */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART3_RX_USING_DMA) +#ifndef UART3_DMA_RX_CONFIG +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .dma_rcc = UART3_RX_DMA_RCC, \ + .dma_irq = UART3_RX_DMA_IRQ, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .request = UART3_RX_DMA_REQUEST, \ + } +#endif /* UART3_DMA_RX_CONFIG */ +#endif /* BSP_UART3_RX_USING_DMA */ + +#if defined(BSP_UART3_TX_USING_DMA) +#ifndef UART3_DMA_TX_CONFIG +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .dma_rcc = UART3_TX_DMA_RCC, \ + .dma_irq = UART3_TX_DMA_IRQ, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .request = UART3_TX_DMA_REQUEST, \ + } +#endif /* UART3_DMA_TX_CONFIG */ +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = USART3, \ + .irq_type = USART3_IRQn, \ + .enable_id = EN_UART3, \ + .tx_port = UART3_TX_PORT, \ + .rx_port = UART3_RX_PORT, \ + .tx_pin = UART3_TX_PIN, \ + .rx_pin = UART3_RX_PIN, \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .dma_rcc = UART4_RX_DMA_RCC, \ + .dma_irq = UART4_RX_DMA_IRQ, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .request = UART4_RX_DMA_REQUEST, \ + } +#endif /* UART4_DMA_RX_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .dma_rcc = UART4_TX_DMA_RCC, \ + .dma_irq = UART4_TX_DMA_IRQ, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .request = UART4_TX_DMA_REQUEST, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = USART4, \ + .irq_type = USART4_IRQn, \ + .enable_id = EN_UART4, \ + .tx_port = UART4_TX_PORT, \ + .rx_port = UART4_RX_PORT, \ + .tx_pin = UART4_TX_PIN, \ + .rx_pin = UART4_RX_PIN, \ + } +#endif /* UART4_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#ifdef __cplusplus +} +#endif + +#endif /* RT_USING_SERIAL */ + +#endif /* __UART_CONFIG_H__ */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/drv_dma.c b/bsp/acm32/acm32h5xx-nucleo/drivers/drv_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..27cf1a8d39cdf81f74f6df8a8999ca2aa7b405fa --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/drv_dma.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-27 AisinoChip The first version + */ + +#include +#include +#include +#include "hal_dma.h" +#include "drv_dma.h" + +#include + + + +#ifdef RT_USING_HW_MEM_OPERATION + +static DMA_TypeDef *DMAAddr=MEM_OP_DMA_BASEADDR; + + +void rt_dma_mem_op_init(void) +{ + int ret; + uint32_t dest, src; + + __HAL_RCC_DMA1_CLK_ENABLE(); + + DMAAddr->INTTCCLR = (((1<INTERRCLR = ((1<CONFIG = ((DMA_MASTER1_ENDIAN_LITTLE<CXLLI = 0; + MEMCPY_DMA_INSTANCE->CXLLI = 0; + + //start a DMA transmit + MEMCPY_DMA_INSTANCE->CXSRCADDR = (uint32_t)&src; + MEMCPY_DMA_INSTANCE->CXDESTADDR = (uint32_t)&dest; + MEMCPY_DMA_INSTANCE->CXCTRL = (DMA_CXCTRL_RITEN + | (1<CXCONFIG = 1; + + //start a DMA transmit + MEMSET_DMA_INSTANCE->CXSRCADDR = (uint32_t)&src; + MEMSET_DMA_INSTANCE->CXDESTADDR = (uint32_t)&dest; + MEMSET_DMA_INSTANCE->CXCTRL = (DMA_CXCTRL_RITEN + | (1<CXCONFIG = 1; +} + + +void *dma_memcpy(void *dst, const void *src, rt_ubase_t count) +{ +// while(0==(DMAAddr->RAWINTTCSTATUS&(1<INTTCCLR = ((1<INTERRCLR = ((1<CXSRCADDR = (uint32_t)src; + MEMCPY_DMA_INSTANCE->CXDESTADDR = (uint32_t)dst; + if((((uint32_t)dst)&((uint32_t)src)&0x03) || (count<16)) //8bit + { + MEMCPY_DMA_INSTANCE->CXCTRL = (DMA_CXCTRL_RITEN + | (1<CXCONFIG = 1; + } + else //32bit + { + int i; + MEMCPY_DMA_INSTANCE->CXCTRL = (DMA_CXCTRL_RITEN + | (1<>2)); + MEMCPY_DMA_INSTANCE->CXCONFIG = ((1<<0)|(1<<11)); + + i=(count&0x03); + if(i) + { + while(i--) + { + *(((uint8_t *)dst+count-1)-i) = *(((uint8_t *)src+count-1)-i); + } + } + } + + while(0==(DMAAddr->RAWINTTCSTATUS&(1<=4) + { + ((uint8_t *)&Val)[0] = (uint8_t)c; + ((uint8_t *)&Val)[1] = (uint8_t)c; + ((uint8_t *)&Val)[2] = (uint8_t)c; + ((uint8_t *)&Val)[3] = (uint8_t)c; + + DMAAddr->INTTCCLR = ((1<INTERRCLR = ((1<CXSRCADDR = (uint32_t)&Val; + MEMSET_DMA_INSTANCE->CXDESTADDR = Addr; + MEMSET_DMA_INSTANCE->CXCTRL = (DMA_CXCTRL_RITEN + | (1<>2)); + MEMSET_DMA_INSTANCE->CXCONFIG = ((1<<0)|(1<<11)); +// MEMSET_DMA_INSTANCE->CXCONFIG = 1; + + Addr += (cnt&(~3)); + cnt &= 3; + + + while(0==(DMAAddr->RAWINTTCSTATUS&(1< +#include +#include "board.h" + + +#ifdef RT_USING_PIN + +#include "./Inc/drv_gpio.h" + + +#define __ACM32_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio, GPIO_PIN_##gpio_index \ + } + +#define __ACM32_PIN_RESERVE \ + { \ + -1, 0, 0 \ + } + + +/* ACM32 GPIO driver */ +struct pin_index +{ + int index; + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +struct pin_irq_map +{ + rt_uint16_t line; + EXTI_HandleTypeDef handle; +}; + +static const struct pin_index pins[] = +{ +#if defined(BSP_USING_GPIOA) + __ACM32_PIN(0, A, 0), + __ACM32_PIN(1, A, 1), + __ACM32_PIN(2, A, 2), + __ACM32_PIN(3, A, 3), + __ACM32_PIN(4, A, 4), + __ACM32_PIN(5, A, 5), + __ACM32_PIN(6, A, 6), + __ACM32_PIN(7, A, 7), + __ACM32_PIN(8, A, 8), + __ACM32_PIN(9, A, 9), + __ACM32_PIN(10, A, 10), + __ACM32_PIN(11, A, 11), + __ACM32_PIN(12, A, 12), + __ACM32_PIN(13, A, 13), + __ACM32_PIN(14, A, 14), + __ACM32_PIN(15, A, 15), +#endif /* defined(BSP_USING_GPIOA) */ +#if defined(BSP_USING_GPIOB) + __ACM32_PIN((16*1)+0, B, 0), + __ACM32_PIN((16*1)+1, B, 1), + __ACM32_PIN((16*1)+2, B, 2), + __ACM32_PIN((16*1)+3, B, 3), + __ACM32_PIN((16*1)+4, B, 4), + __ACM32_PIN((16*1)+5, B, 5), + __ACM32_PIN((16*1)+6, B, 6), + __ACM32_PIN((16*1)+7, B, 7), + __ACM32_PIN((16*1)+8, B, 8), + __ACM32_PIN((16*1)+9, B, 9), + __ACM32_PIN((16*1)+10, B, 10), + __ACM32_PIN((16*1)+11, B, 11), + __ACM32_PIN((16*1)+12, B, 12), + __ACM32_PIN((16*1)+13, B, 13), + __ACM32_PIN((16*1)+14, B, 14), + __ACM32_PIN((16*1)+15, B, 15), +#endif /* defined(BSP_USING_GPIOB) */ +#if defined(BSP_USING_GPIOC) + __ACM32_PIN((16*1)+0, C, 0), + __ACM32_PIN((16*1)+1, C, 1), + __ACM32_PIN((16*1)+2, C, 2), + __ACM32_PIN((16*1)+3, C, 3), + __ACM32_PIN((16*1)+4, C, 4), + __ACM32_PIN((16*1)+5, C, 5), + __ACM32_PIN((16*1)+6, C, 6), + __ACM32_PIN((16*1)+7, C, 7), + __ACM32_PIN((16*1)+8, C, 8), + __ACM32_PIN((16*1)+9, C, 9), + __ACM32_PIN((16*1)+10, C, 10), + __ACM32_PIN((16*1)+11, C, 11), + __ACM32_PIN((16*1)+12, C, 12), + __ACM32_PIN((16*1)+13, C, 13), + __ACM32_PIN((16*1)+14, C, 14), + __ACM32_PIN((16*1)+15, C, 15), +#endif /* defined(BSP_USING_GPIOC) */ +#if defined(BSP_USING_GPIOD) + __ACM32_PIN((16*1)+0, D, 0), + __ACM32_PIN((16*1)+1, D, 1), + __ACM32_PIN((16*1)+2, D, 2), + __ACM32_PIN((16*1)+3, D, 3), + __ACM32_PIN((16*1)+4, D, 4), + __ACM32_PIN((16*1)+5, D, 5), + __ACM32_PIN((16*1)+6, D, 6), + __ACM32_PIN((16*1)+7, D, 7), + __ACM32_PIN((16*1)+8, D, 8), + __ACM32_PIN((16*1)+9, D, 9), + __ACM32_PIN((16*1)+10, D, 10), + __ACM32_PIN((16*1)+11, D, 11), + __ACM32_PIN((16*1)+12, D, 12), + __ACM32_PIN((16*1)+13, D, 13), + __ACM32_PIN((16*1)+14, D, 14), + __ACM32_PIN((16*1)+15, D, 15), +#endif /* defined(BSP_USING_GPIOD) */ +#if defined(BSP_USING_GPIOE) + __ACM32_PIN((16*1)+0, E, 0), + __ACM32_PIN((16*1)+1, E, 1), + __ACM32_PIN((16*1)+2, E, 2), + __ACM32_PIN((16*1)+3, E, 3), + __ACM32_PIN((16*1)+4, E, 4), + __ACM32_PIN((16*1)+5, E, 5), + __ACM32_PIN((16*1)+6, E, 6), + __ACM32_PIN((16*1)+7, E, 7), + __ACM32_PIN((16*1)+8, E, 8), + __ACM32_PIN((16*1)+9, E, 9), + __ACM32_PIN((16*1)+10, E, 10), + __ACM32_PIN((16*1)+11, E, 11), + __ACM32_PIN((16*1)+12, E, 12), + __ACM32_PIN((16*1)+13, E, 13), + __ACM32_PIN((16*1)+14, E, 14), + __ACM32_PIN((16*1)+15, E, 15), +#endif /* defined(BSP_USING_GPIOE) */ +#if defined(BSP_USING_GPIOF) + __ACM32_PIN((16*1)+0, F, 0), + __ACM32_PIN((16*1)+1, F, 1), + __ACM32_PIN((16*1)+2, F, 2), + __ACM32_PIN((16*1)+3, F, 3), + __ACM32_PIN((16*1)+4, F, 4), + __ACM32_PIN((16*1)+5, F, 5), + __ACM32_PIN((16*1)+6, F, 6), + __ACM32_PIN((16*1)+7, F, 7), + __ACM32_PIN((16*1)+8, F, 8), + __ACM32_PIN((16*1)+9, F, 9), + __ACM32_PIN((16*1)+10, F, 10), + __ACM32_PIN((16*1)+11, F, 11), + __ACM32_PIN((16*1)+12, F, 12), + __ACM32_PIN((16*1)+13, F, 13), + __ACM32_PIN((16*1)+14, F, 14), + __ACM32_PIN((16*1)+15, F, 15), +#endif /* defined(BSP_USING_GPIOF) */ +#if defined(BSP_USING_GPIOG) + __ACM32_PIN((16*1)+0, G, 0), + __ACM32_PIN((16*1)+1, G, 1), + __ACM32_PIN((16*1)+2, G, 2), + __ACM32_PIN((16*1)+3, G, 3), + __ACM32_PIN((16*1)+4, G, 4), + __ACM32_PIN((16*1)+5, G, 5), + __ACM32_PIN((16*1)+6, G, 6), + __ACM32_PIN((16*1)+7, G, 7), + __ACM32_PIN((16*1)+8, G, 8), + __ACM32_PIN((16*1)+9, G, 9), + __ACM32_PIN((16*1)+10, G, 10), + __ACM32_PIN((16*1)+11, G, 11), + __ACM32_PIN((16*1)+12, G, 12), + __ACM32_PIN((16*1)+13, G, 13), + __ACM32_PIN((16*1)+14, G, 14), + __ACM32_PIN((16*1)+15, G, 15), +#endif /* defined(BSP_USING_GPIOG) */ +#if defined(BSP_USING_GPIOH) + __ACM32_PIN((16*1)+0, H, 0), + __ACM32_PIN((16*1)+1, H, 1), + __ACM32_PIN((16*1)+2, H, 2), + __ACM32_PIN((16*1)+3, H, 3), + __ACM32_PIN((16*1)+4, H, 4), + __ACM32_PIN((16*1)+5, H, 5), + __ACM32_PIN((16*1)+6, H, 6), + __ACM32_PIN((16*1)+7, H, 7), + __ACM32_PIN((16*1)+8, H, 8), + __ACM32_PIN((16*1)+9, H, 9), + __ACM32_PIN((16*1)+10, H, 10), + __ACM32_PIN((16*1)+11, H, 11), + __ACM32_PIN((16*1)+12, H, 12), + __ACM32_PIN((16*1)+13, H, 13), + __ACM32_PIN((16*1)+14, H, 14), + __ACM32_PIN((16*1)+15, H, 15), +#endif /* defined(BSP_USING_GPIOH) */ +}; + +static struct pin_irq_map pin_irq_map[] = +{ + {EXTI_LINE_0, {0}}, + {EXTI_LINE_1, {0}}, + {EXTI_LINE_2, {0}}, + {EXTI_LINE_3, {0}}, + {EXTI_LINE_4, {0}}, + {EXTI_LINE_5, {0}}, + {EXTI_LINE_6, {0}}, + {EXTI_LINE_7, {0}}, + {EXTI_LINE_8, {0}}, + {EXTI_LINE_9, {0}}, + {EXTI_LINE_10, {0}}, + {EXTI_LINE_11, {0}}, + {EXTI_LINE_12, {0}}, + {EXTI_LINE_13, {0}}, + {EXTI_LINE_14, {0}}, + {EXTI_LINE_15, {0}}, +}; + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +static uint32_t pin_irq_enable_mask = 0; + + +rt_bool_t drv_gpio_init(GPIO_TypeDef *gpiox, rt_uint32_t pin, rt_uint32_t mode, + rt_uint32_t pull, rt_uint32_t alternate) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + RT_ASSERT(IS_GPIO_ALL_INSTANCE(gpiox)); + RT_ASSERT(IS_GPIO_ALL_PIN(pin)); + RT_ASSERT(IS_GPIO_MODE(0, mode)); + RT_ASSERT(IS_GPIO_PULL(pull)); + RT_ASSERT(IS_GPIO_FUNCTION(alternate)); + + GPIO_InitStruct.Pin = pin; + GPIO_InitStruct.Mode = mode; + GPIO_InitStruct.Pull = pull; + GPIO_InitStruct.Alternate = alternate; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + HAL_GPIO_Init(gpiox, &GPIO_InitStruct); + + return RT_TRUE; +} + + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +static const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value); +} + +static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = HAL_GPIO_ReadPin(index->gpio, index->pin); + + return value; +} + +static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + + System_Module_Enable(EN_GPIOA+(((uint32_t)(index->gpio)-(uint32_t)GPIOA)>>10)); + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); + +} + +#define PIN2INDEX(pin) ((pin) % 16) + +static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_base_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint8_t enabled) +{ + const struct pin_index *index; + struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + + irqindex = PIN2INDEX(pin); + irqmap = &pin_irq_map[irqindex]; + + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + + irqmap->handle.u32_Line = irqmap->line; + + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + irqmap->handle.u32_Mode = EXTI_MODE_IT_RISING; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Pull = GPIO_PULLUP; + irqmap->handle.u32_Mode = EXTI_MODE_IT_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Pull = GPIO_NOPULL; + irqmap->handle.u32_Mode = EXTI_MODE_IT_RISING_FALLING; + break; + } + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); + + irqmap->handle.u32_GPIOSel = pin / 16; + + HAL_EXTI_SetConfigLine(index->gpio, irqmap->handle.u32_Line, irqmap->handle.u32_Mode); + + pin_irq_enable_mask |= 1 << irqindex; + + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + if ((pin_irq_enable_mask & (1 << irqindex)) == 0) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + + EXTI->IENR1 &= ~irqmap->line; + EXTI->EENR1 &= ~irqmap->line; + + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} + +const static struct rt_pin_ops _acm32_pin_ops = +{ + _pin_mode, + _pin_write, + _pin_read, + _pin_attach_irq, + _pin_dettach_irq, + _pin_irq_enable, +}; + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +void EXTI_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + for (int i = 0; i < 16; i++) + { + if (EXTI->PDR1 & pin_irq_map[i].line) + { + EXTI->PDR1 = pin_irq_map[i].line; + pin_irq_hdr(i); + break; + } + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + + +struct pin_index pin_tbl[5][10]; + +static void test() +{ + struct pin_index **test_pin; + + test_pin = (struct pin_index **)pin_tbl; + + test_pin[0][1].index = 0; +} + + + + + +#endif /* RT_USING_PIN */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/drivers/drv_uart.c b/bsp/acm32/acm32h5xx-nucleo/drivers/drv_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..05c5bb5bd2127d0808db93ea668721b917a620f3 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/drivers/drv_uart.c @@ -0,0 +1,631 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-08-23 AisinoChip the first version + */ + +#include +#include +#include +#include "board.h" + + +#ifdef RT_USING_SERIAL + +#include "./Inc/drv_uart.h" +#include "./config/uart_config.h" + + +#ifdef RT_SERIAL_USING_DMA +struct dma_config +{ + DMA_Channel_TypeDef *Instance; + rt_uint32_t dma_rcc; + IRQn_Type dma_irq; + + rt_uint32_t channel; + rt_uint32_t request; +}; +#endif + +#ifdef RT_SERIAL_USING_DMA + static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag); +#endif /* RT_SERIAL_USING_DMA */ + +static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size) +{ + return RT_EOK; +} + +static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + uart->handle.Instance = uart->config->Instance; + + uart->handle.Init.BaudRate = cfg->baud_rate; + if (cfg->data_bits == DATA_BITS_8) + { + uart->handle.Init.WordLength = UART_WORDLENGTH_8B; + } + else /* not support */ + { + return -RT_EINVAL; + } + + if (cfg->stop_bits == STOP_BITS_1) + { + uart->handle.Init.StopBits = UART_STOPBITS_1; + } + else if (cfg->stop_bits == STOP_BITS_2) + { + uart->handle.Init.StopBits = UART_STOPBITS_2; + } + else /* not support */ + { + return -RT_EINVAL; + } + + if (cfg->parity == PARITY_NONE) + { + uart->handle.Init.Parity = UART_PARITY_NONE; + } + else if (cfg->parity == PARITY_ODD) + { + uart->handle.Init.Parity = UART_PARITY_ODD; + } + else if (cfg->parity == PARITY_EVEN) + { + uart->handle.Init.Parity = UART_PARITY_EVEN; + } + else /* not support */ + { + return -RT_EINVAL; + } + + uart->handle.Init.Mode = UART_MODE_TX_RX; + uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + + HAL_UART_Init(&uart->handle); + + return RT_EOK; +} + +static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct acm32_uart *uart; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + NVIC_DisableIRQ(uart->config->irq_type); + /* Disable RX interrupt */ + uart->handle.Instance->IE &= ~UART_IE_RXI; + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + NVIC_EnableIRQ(uart->config->irq_type); + /* Enable RX interrupt */ + uart->handle.Instance->IE |= UART_IE_RXI; + break; +#ifdef RT_SERIAL_USING_DMA + /* UART config */ + case RT_DEVICE_CTRL_CONFIG : + DMA_Configuration(serial, (rt_uint32_t)ctrl_arg); + rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb); + break; +#endif /* RT_SERIAL_USING_DMA */ + } + return RT_EOK; +} + +static int _uart_putc(struct rt_serial_device *serial, char c) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + while (uart->handle.Instance->FR & UART_FR_TXFF); /* wait Tx FIFO not full */ + uart->handle.Instance->DR = c; + while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */ + + return 1; +} + +static int _uart_getc(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + ch = -1; + if (!(uart->handle.Instance->FR & UART_FR_RXFE)) /* Rx FIFO not empty */ + { + ch = uart->handle.Instance->DR & 0xff; + } + + return ch; +} + +#ifdef RT_SERIAL_USING_DMA +/** + * Serial port receive idle process. This need add to uart idle ISR. + * + * @param serial serial device + */ +static void dma_uart_rx_idle_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + rt_size_t recv_total_index, recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF); + recv_len = recv_total_index - uart->handle.lu32_RxCount; + uart->handle.lu32_RxCount = recv_total_index; + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +/* + DMA receive done process. This need add to DMA receive done ISR. + + @param serial serial device +*/ +static void dma_rx_done_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + rt_size_t recv_len; + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF); + uart->dma_rx.last_index = 0; + + DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel); /* clear channel0 TC flag */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + + HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz); +} + +static rt_ssize_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +{ + struct acm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = rt_container_of(serial, struct acm32_uart, serial); + + if (size == 0) + { + return 0; + } + + if (RT_SERIAL_DMA_TX == direction) + { + if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); + return size; + } + else + { + return 0; + } + } + return 0; +} + +#endif /* RT_SERIAL_USING_DMA */ + +static const struct rt_uart_ops acm32_uart_ops = +{ + _uart_configure, + _uart_control, + _uart_putc, + _uart_getc, +#ifdef RT_SERIAL_USING_DMA + _uart_dma_transmit, +#endif +}; + +#ifdef RT_SERIAL_USING_DMA +static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag) +{ + struct rt_serial_rx_fifo *rx_fifo; + DMA_HandleTypeDef *DMA_Handle; + struct dma_config *dma_config; + struct acm32_uart *uart; + + RT_ASSERT(serial != RT_NULL); + + uart = rt_container_of(serial, struct acm32_uart, serial); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle = &uart->dma_rx.handle; + dma_config = uart->config->dma_rx; + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle = &uart->dma_tx.handle; + dma_config = uart->config->dma_tx; + } + else + { + return; + } + + DMA_Handle->Instance = dma_config->Instance; + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_P2M; + DMA_Handle->Init.Mode = DMA_MODE_NORMAL; + DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE; + DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE; + + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_M2P; + DMA_Handle->Init.Mode = DMA_MODE_NORMAL; + DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE; + DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE; + } + + DMA_Handle->Init.Request_ID = dma_config->request; + DMA_Handle->Init.Source_Width = DMA_SRC_WIDTH_BYTE; + DMA_Handle->Init.Desination_Width = DMA_DST_WIDTH_BYTE; + + if (HAL_DMA_Init(DMA_Handle) != HAL_OK) + { + RT_ASSERT(0); + } + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle); + } + /* enable interrupt */ + if (flag == RT_DEVICE_FLAG_DMA_RX) + { + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + /* Start DMA transfer */ + if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK) + { + /* Transfer error in reception process */ + RT_ASSERT(0); + } + + } +} +#endif /* RT_SERIAL_USING_DMA */ + +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif + UART_MAX_INDEX, +}; + +static struct acm32_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART1 + UART1_CONFIG, +#endif +#ifdef BSP_USING_UART2 + UART2_CONFIG, +#endif +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +#ifdef BSP_USING_UART4 + UART4_CONFIG, +#endif +}; + +static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +#ifdef RT_SERIAL_USING_DMA +static void uart_get_dma_config(void) +{ +#if defined(BSP_USING_UART1) +#if defined(BSP_UART1_RX_USING_DMA) + static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf; +#endif /* BSP_UART1_RX_USING_DMA */ +#if defined(BSP_UART1_TX_USING_DMA) + static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG; + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf; +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#if defined(BSP_UART2_RX_USING_DMA) + static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf; +#endif /* BSP_UART2_RX_USING_DMA */ +#if defined(BSP_UART2_TX_USING_DMA) + static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG; + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf; +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#if defined(BSP_UART3_RX_USING_DMA) + static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf; +#endif /* BSP_UART3_RX_USING_DMA */ +#if defined(BSP_UART3_TX_USING_DMA) + static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG; + uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf; +#endif /* BSP_UART3_TX_USING_DMA */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#if defined(BSP_UART4_RX_USING_DMA) + static struct dma_config uart4_rx_dma_conf = UART4_DMA_RX_CONFIG; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + uart_config[UART4_INDEX].dma_rx = &uart4_rx_dma_conf; +#endif /* BSP_UART4_RX_USING_DMA */ +#if defined(BSP_UART3_TX_USING_DMA) + static struct dma_config uart4_tx_dma_conf = UART4_DMA_TX_CONFIG; + uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + uart_config[UART4_INDEX].dma_tx = &uart4_tx_dma_conf; +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ +} +#endif + +rt_err_t rt_hw_uart_init(void) +{ + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t rc = RT_EOK; + +#ifdef RT_SERIAL_USING_DMA + uart_get_dma_config(); +#endif + + for (int i = 0; i < obj_num; i++) + { + uart_obj[i].config = &uart_config[i]; + + uart_obj[i].serial.ops = &acm32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR + | RT_DEVICE_FLAG_INT_RX + | RT_DEVICE_FLAG_INT_TX + | uart_obj[i].uart_dma_flag + , NULL); + RT_ASSERT(rc == RT_EOK); + } + + return rc; +} + + +static void uart_isr(struct rt_serial_device *serial) +{ + struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial); + + RT_ASSERT(serial != RT_NULL); + + /* receive interrupt enabled */ + if (uart->handle.Instance->IE & UART_IE_RXI) + { + if (uart->handle.Instance->ISR & UART_ISR_RXI) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + } + +#ifdef RT_SERIAL_USING_DMA + if (uart->handle.Instance->IE & UART_IE_RTI) /* Receive TimeOut Interrupt */ + { + dma_uart_rx_idle_isr(serial); + /* Clear RTI Status */ + uart->handle.Instance->ICR = UART_ICR_RTI; + } +#endif /* RT_SERIAL_USING_DMA */ + + if (uart->handle.Instance->IE & UART_IE_TXI && \ + uart->handle.Instance->ISR & UART_ISR_TXI) + { + /* Clear TXI Status */ + uart->handle.Instance->ISR = UART_ISR_TXI; + if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE); + } + /* Disable TX interrupt */ + uart->handle.Instance->IE &= ~UART_IE_TXI; + } +} + +#if defined(BSP_USING_UART1) +void USART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART1_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART2_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +void USART3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART3_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +void USART4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[UART4_INDEX].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#ifdef RT_SERIAL_USING_DMA +void DMA_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + for (int i = 0; i < UART_MAX_INDEX; i++) + { + if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel)) + { + dma_rx_done_isr(&uart_obj[i].serial); + break; + } + + if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel)) + { + DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel); /* clear channel0 TC flag */ + break; + } + } + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* RT_SERIAL_USING_DMA */ + +void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + struct acm32_uart *uart; + GPIO_InitTypeDef GPIO_Uart; + + RT_ASSERT(huart != RT_NULL); + + /* get uart object */ + uart = rt_container_of(huart, struct acm32_uart, handle); + + /* Enable Clock */ + System_Module_Enable(uart->config->enable_id); + System_Module_Enable(EN_GPIOA+(((uint32_t)(uart->config->tx_port)-(uint32_t)GPIOA)>>10)); + System_Module_Enable(EN_GPIOA+(((uint32_t)(uart->config->rx_port)-(uint32_t)GPIOA)>>10)); + + /* Initialization GPIO */ + GPIO_Uart.Pin = uart->config->tx_pin; + GPIO_Uart.Mode = GPIO_MODE_AF_PP; + GPIO_Uart.Pull = GPIO_PULLUP; + GPIO_Uart.Alternate = uart->config->tx_alternate; + GPIO_Uart.Drive = GPIO_DRIVE_LEVEL3; + HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart); + + GPIO_Uart.Pin = uart->config->rx_pin; + GPIO_Uart.Mode = GPIO_MODE_AF_PP; + GPIO_Uart.Pull = GPIO_PULLUP; + GPIO_Uart.Alternate = uart->config->rx_alternate; + HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart); + + /* NVIC Config */ + NVIC_ClearPendingIRQ(uart->config->irq_type); + NVIC_SetPriority(uart->config->irq_type, 5); + NVIC_EnableIRQ(uart->config->irq_type); +} + +#endif /* RT_USING_SEARIAL */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_armclang.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..e917f357a328c66909aac8cefea5891211481e3e --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_compiler.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..adbf296f15a47a93e5058abddad6742bb4b9854d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_gcc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..3ddcc58b69f6a8d60f614df45fb98932b07ac9c2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_iccarm.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..12d68fd9a63b37d3a94c1114213cdd161dddbb6d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_version.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..f2e2746626afefeebcc3435ef433895b5bcc4cdb --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/core_cm33.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/core_cm33.h new file mode 100644 index 0000000000000000000000000000000000000000..420444ca58144de9e8e266c897eb0d29d9f57224 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/core_cm33.h @@ -0,0 +1,2930 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/******************************************************************************/ +/* Star QSPI registers structures */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t CR; /*!< QSPI control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< QSPI status register, Address offset: 0x04 */ + __IO uint32_t RMCR; /*!< QSPI Direct Read Access Mode Control register, Address offset: 0x08 */ + __IO uint32_t OMCR; /*!< QSPI Operation Mode Control register, Address offset: 0x0C */ + __IO uint32_t RABR; /*!< QSPI Direct Read Mode Alternate Bytes register, Address offset: 0x10 */ + __IO uint32_t OABR; /*!< QSPI direct program/indirect mode alternate bytes register, Address offset: 0x14 */ + __IO uint32_t IMAR; /*!< QSPI Indirect mode Address register, Address offset: 0x18 */ + __IO uint32_t FDR; /*!< QSPI FIFO DATA register, Address offset: 0x1C */ + __IO uint32_t DLR; /*!< QSPI Data Length register, Address offset: 0x20 */ + __IO uint32_t WCNT; /*!< QSPI Wait counter for response direct read access , Address offset: 0x24 */ +} STARQSPI_Type; + + #define STARQSPI_BASE (0xE0044000UL) + #define STARQSPI ((STARQSPI_Type *)STARQSPI_BASE) + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/mpu_armv8.h b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/mpu_armv8.h new file mode 100644 index 0000000000000000000000000000000000000000..0041d4dc6ff536afb59c5863d21f6ced2b42531f --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/CMSIS/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/Device/Templates/ARM/startup_acm32h5xx.s b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/Templates/ARM/startup_acm32h5xx.s new file mode 100644 index 0000000000000000000000000000000000000000..919c938372535f275d76075afa076dc4d9795bee --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/Templates/ARM/startup_acm32h5xx.s @@ -0,0 +1,598 @@ +;/***************************************************************************** +; * @file: startup_CM0.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * for the ARM 'Microcontroller Prototyping System' +; * @version: V1.0 +; * @date: +; * +; *****************************************************************************/ +Stack_Size EQU 0x00004000 +Heap_Size EQU 0x00010000 +;__initial_sp EQU 0x20003000 ;Define SP size + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler,SWI + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0 + DCD LVD_IRQHandler ; 1 + DCD RTC_IRQHandler ; 2 + DCD RSV3_IRQHandler ; 3 + DCD RSV4_IRQHandler ; 4 + DCD RSV5_IRQHandler ; 5 + DCD CLKRDY_IRQHandler ; 6 + DCD EXTI0_IRQHandler ; 7 + DCD EXTI1_IRQHandler ; 8 + DCD EXTI2_IRQHandler ; 9 + DCD EXTI3_IRQHandler ; 10 + DCD EXTI4_IRQHandler ; 11 + DCD RSV12_IRQHandler ; 12 + DCD RSV13_IRQHandler ; 13 + DCD ADC12_IRQHandler ; 14 + DCD ADC3_IRQHandler ; 15 + DCD DAC1_IRQHandler ; 16 + DCD COMP1_IRQHandler ; 17 + DCD USBOTG1_IRQHandler ; 18 + DCD FDCAN1_IRQHandler ; 19 + DCD FDCAN2_IRQHandler ; 20 + DCD EXTI9_5_IRQHandler ; 21 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 22 + DCD TIM1_CC_IRQHandler ; 23 + DCD TIM2_IRQHandler ; 24 + DCD TIM3_IRQHandler ; 25 + DCD TIM6_IRQHandler ; 26 + DCD TIM7_IRQHandler ; 27 + DCD TIM8_BRK_UP_TRG_COM_IRQHandler ; 28 + DCD TIM8_CC_IRQHandler ; 29 + DCD TIM15_IRQHandler ; 30 + DCD TIM16_IRQHandler ; 31 + DCD TIM17_IRQHandler ; 32 + DCD I2C1_IRQHandler ; 33 + DCD I2C2_IRQHandler ; 34 + DCD SPI1_IRQHandler ; 35 + DCD SPI2_IRQHandler ; 36: + DCD SPI3_IRQHandler ; 37 + DCD I2S1_IRQHandler ; 38 + DCD I2S2_IRQHandler ; 39 + DCD USART1_IRQHandler ; 40 + DCD USART2_IRQHandler ; 41 + DCD USART3_IRQHandler ; 42 + DCD USART4_IRQHandler ; 43 + DCD EXTI15_10_IRQHandler ; 44 + DCD USBOTG1_WKUP_IRQHandler ; 45 + DCD LPUART1_IRQHandler ; 46 + DCD LPTIM1_IRQHandler ; 47 + DCD USBOTG2_WKUP_IRQHandler ; 48 + DCD AES_IRQHandler ; 49 + DCD FPU_IRQHandler ; 50 + DCD USBOTG2_IRQHandler ; 51 + DCD DCMI_IRQHandler ; 52 + DCD TIM4_IRQHandler ; 53 + DCD RSV54_IRQHandler ; 54 + DCD IWDT_WKUP_IRQHandler ; 55 + DCD LTDC_IRQHandler ; 56 + DCD LTDC_ERR_IRQHandler ; 57 + DCD DMA2D_IRQHandler ; 58 + DCD LPTIM2_IRQHandler ; 59 + DCD LPTIM3_IRQHandler ; 60 + DCD LPTIM4_IRQHandler ; 61 + DCD LPTIM5_IRQHandler ; 62 + DCD LPTIM6_IRQHandler ; 63 + DCD AES_SPI1_IRQHandler ; 64 + DCD I2S3_IRQHandler ; 65 + DCD SPI4_IRQHandler ; 66 + DCD SPI5_IRQHandler ; 67 + DCD SPI6_IRQHandler ; 68 + DCD I2C3_IRQHandler ; 69 + DCD I2C4_IRQHandler ; 70 + DCD FDCAN3_IRQHandler ; 71 + DCD RSV72_IRQHandler ; 72 + DCD ETH_IRQHandler ; 73 + DCD ETH_WKUP_IRQHandler ; 74 + DCD SDMMC_IRQHandler ; 75 + DCD USART5_IRQHandler ; 76 + DCD USART6_IRQHandler ; 77 + DCD USART7_IRQHandler ; 78 + DCD USART8_IRQHandler ; 79 + DCD USART9_IRQHandler ; 80 + DCD USART10_IRQHandler ; 81 + DCD DAC2_IRQHandler ; 82 + DCD TIM5_IRQHandler ; 83 + DCD TIM9_IRQHandler ; 84 + DCD TIM10_IRQHandler ; 85 + DCD TIM11_IRQHandler ; 86 + DCD TIM12_IRQHandler ; 87 + DCD TIM13_IRQHandler ; 88 + DCD TIM14_IRQHandler ; 89 + DCD TIM18_IRQHandler ; 90 + DCD TIM19_IRQHandler ; 91 + DCD TIM20_BRK_UP_TRG_COM_IRQHandler ; 92 + DCD TIM20_CC_IRQHandler ; 93 + DCD TIM21_IRQHandler ; 94 + DCD TIM22_IRQHandler ; 95 + DCD TIM23_IRQHandler ; 96 + DCD TIM24_IRQHandler ; 97 + DCD TIM25_IRQHandler ; 98 + DCD TIM26_IRQHandler ; 99 + DCD SPI7_IRQHandler ; 100 + DCD SPI8_IRQHandler ; 101 + DCD OSPI1_IRQHandler ; 102 + DCD OSPI2_IRQHandler ; 103 + DCD RSV104_IRQHandler ; 104 + DCD TKEY_IRQHandler ; 105 + DCD LPT_IRQHandler ; 106 + DCD RSV107_IRQHandler ; 107 + DCD OTG1_HS_EP_OUT_IRQHandler ; 108 + DCD OTG1_HS_EP_IN_IRQHandler ; 109 + DCD OTG2_HS_EP_OUT_IRQHandler ; 110 + DCD OTG2_HS_EP_IN_IRQHandler ; 111 + DCD NDL_IRQHandler ; 112 + DCD THM_IRQHandler ; 113 + DCD STM1_PWM_IRQHandler ; 114 + DCD STM2_PWM_IRQHandler ; 115 + DCD DCM1_PWM_IRQHandler ; 116 + DCD DCM2_PWM_IRQHandler ; 117 + DCD DCM3_PWM_IRQHandler ; 118 + DCD DCM4_PWM_IRQHandler ; 119 + DCD STM3_PWM_IRQHandler ; 120 + DCD STM4_PWM_IRQHandler ; 121 + DCD STM5_PWM_IRQHandler ; 122 + DCD STM6_PWM_IRQHandler ; 123 + DCD DCM5_PWM_IRQHandler ; 124 + DCD DCM6_PWM_IRQHandler ; 125 + DCD NAND_IRQHandler ; 126 + DCD BCH_IRQHandler ; 127 + DCD SDRAM_IRQHandler ; 128 + DCD DMA1_CH0_IRQHandler ; 129 + DCD DMA1_CH1_IRQHandler ; 130 + DCD DMA1_CH2_IRQHandler ; 131 + DCD DMA1_CH3_IRQHandler ; 132 + DCD DMA1_CH4_IRQHandler ; 133 + DCD DMA1_CH5_IRQHandler ; 134 + DCD DMA1_CH6_IRQHandler ; 135 + DCD DMA1_CH7_IRQHandler ; 136 + DCD DMA2_CH0_IRQHandler ; 137 + DCD DMA2_CH1_IRQHandler ; 138 + DCD DMA2_CH2_IRQHandler ; 139 + DCD DMA2_CH3_IRQHandler ; 140 + DCD DMA2_CH4_IRQHandler ; 141 + DCD DMA2_CH5_IRQHandler ; 142 + DCD DMA2_CH6_IRQHandler ; 143 + DCD DMA2_CH7_IRQHandler ; 144 + DCD SRAM1_SEC_IRQHandler ; 145 + DCD SRAM1_DED_IRQHandler ; 146 + DCD RSV147_IRQHandler ; 147 + DCD RSV148_IRQHandler ; 148 + DCD BKPSRAM_SEC_IRQHandler ; 149 + DCD BKPSRAM_CH7_IRQHandler ; 150 + + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT main + IMPORT SystemInit + + + + LDR R0, =SystemInit + BLX R0 + + + LDR R0, =__main + BX R0 ; + ENDP + + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WDT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RSV3_IRQHandler [WEAK] + EXPORT RSV4_IRQHandler [WEAK] + EXPORT RSV5_IRQHandler [WEAK] + EXPORT CLKRDY_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT RSV12_IRQHandler [WEAK] + EXPORT RSV13_IRQHandler [WEAK] + EXPORT ADC12_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT USBOTG1_IRQHandler [WEAK] + EXPORT FDCAN1_IRQHandler [WEAK] + EXPORT FDCAN2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM8_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + EXPORT I2S2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT USART4_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT USBOTG1_WKUP_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT USBOTG2_WKUP_IRQHandler [WEAK] + EXPORT AES_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT USBOTG2_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT RSV54_IRQHandler [WEAK] + EXPORT IWDT_WKUP_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ERR_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPTIM6_IRQHandler [WEAK] + EXPORT AES_SPI1_IRQHandler [WEAK] + EXPORT I2S3_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT I2C4_IRQHandler [WEAK] + EXPORT FDCAN3_IRQHandler [WEAK] + EXPORT RSV72_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT SDMMC_IRQHandler [WEAK] + EXPORT USART5_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT USART7_IRQHandler [WEAK] + EXPORT USART8_IRQHandler [WEAK] + EXPORT USART9_IRQHandler [WEAK] + EXPORT USART10_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM18_IRQHandler [WEAK] + EXPORT TIM19_IRQHandler [WEAK] + EXPORT TIM20_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT TIM21_IRQHandler [WEAK] + EXPORT TIM22_IRQHandler [WEAK] + EXPORT TIM23_IRQHandler [WEAK] + EXPORT TIM24_IRQHandler [WEAK] + EXPORT TIM25_IRQHandler [WEAK] + EXPORT TIM26_IRQHandler [WEAK] + EXPORT SPI7_IRQHandler [WEAK] + EXPORT SPI8_IRQHandler [WEAK] + EXPORT OSPI1_IRQHandler [WEAK] + EXPORT OSPI2_IRQHandler [WEAK] + EXPORT RSV104_IRQHandler [WEAK] + EXPORT TKEY_IRQHandler [WEAK] + EXPORT LPT_IRQHandler [WEAK] + EXPORT RSV107_IRQHandler [WEAK] + EXPORT OTG1_HS_EP_OUT_IRQHandler [WEAK] + EXPORT OTG1_HS_EP_IN_IRQHandler [WEAK] + EXPORT OTG2_HS_EP_OUT_IRQHandler [WEAK] + EXPORT OTG2_HS_EP_IN_IRQHandler [WEAK] + EXPORT NDL_IRQHandler [WEAK] + EXPORT THM_IRQHandler [WEAK] + EXPORT STM1_PWM_IRQHandler [WEAK] + EXPORT STM2_PWM_IRQHandler [WEAK] + EXPORT DCM1_PWM_IRQHandler [WEAK] + EXPORT DCM2_PWM_IRQHandler [WEAK] + EXPORT DCM3_PWM_IRQHandler [WEAK] + EXPORT DCM4_PWM_IRQHandler [WEAK] + EXPORT STM3_PWM_IRQHandler [WEAK] + EXPORT STM4_PWM_IRQHandler [WEAK] + EXPORT STM5_PWM_IRQHandler [WEAK] + EXPORT STM6_PWM_IRQHandler [WEAK] + EXPORT DCM5_PWM_IRQHandler [WEAK] + EXPORT DCM6_PWM_IRQHandler [WEAK] + EXPORT NAND_IRQHandler [WEAK] + EXPORT BCH_IRQHandler [WEAK] + EXPORT SDRAM_IRQHandler [WEAK] + EXPORT DMA1_CH0_IRQHandler [WEAK] + EXPORT DMA1_CH1_IRQHandler [WEAK] + EXPORT DMA1_CH2_IRQHandler [WEAK] + EXPORT DMA1_CH3_IRQHandler [WEAK] + EXPORT DMA1_CH4_IRQHandler [WEAK] + EXPORT DMA1_CH5_IRQHandler [WEAK] + EXPORT DMA1_CH6_IRQHandler [WEAK] + EXPORT DMA1_CH7_IRQHandler [WEAK] + EXPORT DMA2_CH0_IRQHandler [WEAK] + EXPORT DMA2_CH1_IRQHandler [WEAK] + EXPORT DMA2_CH2_IRQHandler [WEAK] + EXPORT DMA2_CH3_IRQHandler [WEAK] + EXPORT DMA2_CH4_IRQHandler [WEAK] + EXPORT DMA2_CH5_IRQHandler [WEAK] + EXPORT DMA2_CH6_IRQHandler [WEAK] + EXPORT DMA2_CH7_IRQHandler [WEAK] + EXPORT SRAM1_SEC_IRQHandler [WEAK] + EXPORT SRAM1_DED_IRQHandler [WEAK] + EXPORT RSV147_IRQHandler [WEAK] + EXPORT RSV148_IRQHandler [WEAK] + EXPORT BKPSRAM_SEC_IRQHandler [WEAK] + EXPORT BKPSRAM_CH7_IRQHandler [WEAK] + +WDT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +RSV3_IRQHandler +RSV4_IRQHandler +RSV5_IRQHandler +CLKRDY_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +RSV12_IRQHandler +RSV13_IRQHandler +ADC12_IRQHandler +ADC3_IRQHandler +DAC1_IRQHandler +COMP1_IRQHandler +USBOTG1_IRQHandler +FDCAN1_IRQHandler +FDCAN2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM8_BRK_UP_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +I2S1_IRQHandler +I2S2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +USART4_IRQHandler +EXTI15_10_IRQHandler +USBOTG1_WKUP_IRQHandler +LPUART1_IRQHandler +LPTIM1_IRQHandler +USBOTG2_WKUP_IRQHandler +AES_IRQHandler +FPU_IRQHandler +USBOTG2_IRQHandler +DCMI_IRQHandler +TIM4_IRQHandler +RSV54_IRQHandler +IWDT_WKUP_IRQHandler +LTDC_IRQHandler +LTDC_ERR_IRQHandler +DMA2D_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPTIM6_IRQHandler +AES_SPI1_IRQHandler +I2S3_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +I2C3_IRQHandler +I2C4_IRQHandler +FDCAN3_IRQHandler +RSV72_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +SDMMC_IRQHandler +USART5_IRQHandler +USART6_IRQHandler +USART7_IRQHandler +USART8_IRQHandler +USART9_IRQHandler +USART10_IRQHandler +DAC2_IRQHandler +TIM5_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM18_IRQHandler +TIM19_IRQHandler +TIM20_BRK_UP_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +TIM21_IRQHandler +TIM22_IRQHandler +TIM23_IRQHandler +TIM24_IRQHandler +TIM25_IRQHandler +TIM26_IRQHandler +SPI7_IRQHandler +SPI8_IRQHandler +OSPI1_IRQHandler +OSPI2_IRQHandler +RSV104_IRQHandler +TKEY_IRQHandler +LPT_IRQHandler +RSV107_IRQHandler +OTG1_HS_EP_OUT_IRQHandler +OTG1_HS_EP_IN_IRQHandler +OTG2_HS_EP_OUT_IRQHandler +OTG2_HS_EP_IN_IRQHandler +NDL_IRQHandler +THM_IRQHandler +STM1_PWM_IRQHandler +STM2_PWM_IRQHandler +DCM1_PWM_IRQHandler +DCM2_PWM_IRQHandler +DCM3_PWM_IRQHandler +DCM4_PWM_IRQHandler +STM3_PWM_IRQHandler +STM4_PWM_IRQHandler +STM5_PWM_IRQHandler +STM6_PWM_IRQHandler +DCM5_PWM_IRQHandler +DCM6_PWM_IRQHandler +NAND_IRQHandler +BCH_IRQHandler +SDRAM_IRQHandler +DMA1_CH0_IRQHandler +DMA1_CH1_IRQHandler +DMA1_CH2_IRQHandler +DMA1_CH3_IRQHandler +DMA1_CH4_IRQHandler +DMA1_CH5_IRQHandler +DMA1_CH6_IRQHandler +DMA1_CH7_IRQHandler +DMA2_CH0_IRQHandler +DMA2_CH1_IRQHandler +DMA2_CH2_IRQHandler +DMA2_CH3_IRQHandler +DMA2_CH4_IRQHandler +DMA2_CH5_IRQHandler +DMA2_CH6_IRQHandler +DMA2_CH7_IRQHandler +SRAM1_SEC_IRQHandler +SRAM1_DED_IRQHandler +RSV147_IRQHandler +RSV148_IRQHandler +BKPSRAM_SEC_IRQHandler +BKPSRAM_CH7_IRQHandler + + + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/Device/acm32h5xx.h b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/acm32h5xx.h new file mode 100644 index 0000000000000000000000000000000000000000..93c4d8faabac6068527501f7f8c7cef3e0b51f44 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/acm32h5xx.h @@ -0,0 +1,16092 @@ + +/****************************************************************************** +*@file : acm32h5xx.h +*@brief : Device Peripheral Access Layer Header File +* This file contains: +* - Data structures and the address mapping for all peripherals +* - peripherals registers declarations and bits definition +* - Macros to access peripherals registers hardware +******************************************************************************/ + +#ifndef __ACM32H5XX_H__ +#define __ACM32H5XX_H__ + + +/* ------- Interrupt Number Definition ---------------------------------- */ + +typedef enum IRQn +{ +/* ---------------------------------- Cortex-M33 Processor Exceptions Numbers ----------------------------------- */ + Reset_IRQn = -15, /* -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* -13 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /* -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + + SVCall_IRQn = -5, /* -5 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /* -4 Debug Monitor */ + PendSV_IRQn = -2, /* -2 Pend SV Interrupt */ + SysTick_IRQn = -1, /* -1 System Tick Interrupt */ + + /* ---------------------- Chip Specific Interrupt Numbers --------------------- */ + WDT_IRQn = 0, + LVD_IRQn = 1, + RTC_XTLSD_IRQn = 2, + RSV3_IRQn = 3, + RSV4_IRQn = 4, + RSV5_IRQn = 5, + CLKRDY_IRQn = 6, + EXTI0_IRQn = 7, + EXTI1_IRQn = 8, + EXTI2_IRQn = 9, + EXTI3_IRQn = 10, + EXTI4_IRQn = 11, + RSV12_IRQn = 12, + RSV13_IRQn = 13, + ADC12_IRQn = 14, + ADC3_IRQn = 15, + DAC1_IRQn = 16, + COMP1_IRQn = 17, + USBOTG1_IRQn = 18, + FDCAN1_IRQn = 19, + FDCAN2_IRQn = 20, + EXTI9_5_IRQn = 21, + TIM1_BRK_UP_TRG_COM_IRQn = 22, + TIM1_CC_IRQn = 23, + TIM2_IRQn = 24, + TIM3_IRQn = 25, + TIM6_IRQn = 26, + TIM7_IRQn = 27, + TIM8_BRK_UP_TRG_COM_IRQn = 28, + TIM8_CC_IRQn = 29, + TIM15_IRQn = 30, + TIM16_IRQn = 31, + TIM17_IRQn = 32, + I2C1_IRQn = 33, + I2C2_IRQn = 34, + SPI1_IRQn = 35, + SPI2_IRQn = 36, + SPI3_IRQn = 37, + I2S1_IRQn = 38, + I2S2_IRQn = 39, + USART1_IRQn = 40, + USART2_IRQn = 41, + USART3_IRQn = 42, + USART4_IRQn = 43, + EXTI15_10_IRQn = 44, + USBOTG1_WKUP_IRQn = 45, + LPUART1_IRQn = 46, + LPTIM1_IRQn = 47, + USBOTG2_WKUP_IRQn = 48, + AES_IRQn = 49, + FPU_IRQn = 50, + USBOTG2_IRQn = 51, + DCMI_IRQn = 52, + TIM4_IRQn = 53, + RSV54_IRQn = 54, + IWDT_WKUP_IRQn = 55, + LTDC_IRQn = 56, + LTDC_ERR_IRQn = 57, + DMA2D_IRQn = 58, + LPTIM2_IRQn = 59, + LPTIM3_IRQn = 60, + LPTIM4_IRQn = 61, + LPTIM5_IRQn = 62, + LPTIM6_IRQn = 63, + AES_SPI1_IRQn = 64, + I2S3_IRQn = 65, + SPI4_IRQn = 66, + SPI5_IRQn = 67, + SPI6_IRQn = 68, + I2C3_IRQn = 69, + I2C4_IRQn = 70, + FDCAN3_IRQn = 71, + RSV72_IRQn = 72, + ETH_IRQn = 73, + ETH_WKUP_IRQn = 74, + SDMMC_IRQn = 75, + USART5_IRQn = 76, + USART6_IRQn = 77, + USART7_IRQn = 78, + USART8_IRQn = 79, + USART9_IRQn = 80, + USART10_IRQn = 81, + DAC2_IRQn = 82, + TIM5_IRQn = 83, + TIM9_IRQn = 84, + TIM10_IRQn = 85, + TIM11_IRQn = 86, + TIM12_IRQn = 87, + TIM13_IRQn = 88, + TIM14_IRQn = 89, + TIM18_IRQn = 90, + TIM19_IRQn = 91, + TIM20_BRK_UP_TRG_COM_IRQn = 92, + TIM20_CC_IRQn = 93, + TIM21_IRQn = 94, + TIM22_IRQn = 95, + TIM23_IRQn = 96, + TIM24_IRQn = 97, + TIM25_IRQn = 98, + TIM26_IRQn = 99, + SPI7_IRQn = 100, + SPI8_IRQn = 101, + OSPI1_IRQn = 102, + OSPI2_IRQn = 103, + RSV104_IRQn = 104, + TKEY_IRQn = 105, + LPT_IRQn = 106, + RSV107_IRQn = 107, + OTG1_HS_EP_OUT_IRQn = 108, + OTG1_HS_EP_IN_IRQn = 109, + OTG2_HS_EP_OUT_IRQn = 110, + OTG2_HS_EP_IN_IRQn = 111, + NDL_IRQn = 112, + THM_IRQn = 113, + STM1_PWM_IRQn = 114, + STM2_PWM_IRQn = 115, + DCM1_PWM_IRQn = 116, + DCM2_PWM_IRQn = 117, + DCM3_PWM_IRQn = 118, + DCM4_PWM_IRQn = 119, + STM3_PWM_IRQn = 120, + STM4_PWM_IRQn = 121, + STM5_PWM_IRQn = 122, + STM6_PWM_IRQn = 123, + DCM5_PWM_IRQn = 124, + DCM6_PWM_IRQn = 125, + NAND_IRQn = 126, + BCH_IRQn = 127, + SDRAM_IRQn = 128, + DMA1_CH0_IRQn = 129, + DMA1_CH1_IRQn = 130, + DMA1_CH2_IRQn = 131, + DMA1_CH3_IRQn = 132, + DMA1_CH4_IRQn = 133, + DMA1_CH5_IRQn = 134, + DMA1_CH6_IRQn = 135, + DMA1_CH7_IRQn = 136, + DMA2_CH0_IRQn = 137, + DMA2_CH1_IRQn = 138, + DMA2_CH2_IRQn = 139, + DMA2_CH3_IRQn = 140, + DMA2_CH4_IRQn = 141, + DMA2_CH5_IRQn = 142, + DMA2_CH6_IRQn = 143, + DMA2_CH7_IRQn = 144, + SRAM1_SEC_IRQn = 145, + SRAM1_DED_IRQn = 146, + SRAM3_SEC_IRQn = 147, + SRAM3_DED_IRQn = 148, + BKPSRAM_SEC_IRQn = 149, + BKPSRAM_DED_IRQn = 150, +} IRQn_Type; + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + + + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __MPU_PRESENT 1 /*!< cm4ikmcu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< cm4ikmcu Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +#define ARM_MATH_CM4 1 +#define __TARGET_FPU_VFP 1 +#define __FPU_PRESENT 1 +#define __DSP_PRESENT 1 +#define __ARM_COMPAT_H 1 + +#include "core_cm33.h" /* Processor and core peripherals */ +#include "system_acm32h5xx.h" +#include "stdio.h" +#include "stdint.h" +#include "stdbool.h" +#include "string.h" + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__ICCARM__) +/* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/*-------------------Bit Opertions------------------------*/ +#define BIT0 ( 1U << 0 ) +#define BIT1 ( 1U << 1 ) +#define BIT2 ( 1U << 2 ) +#define BIT3 ( 1U << 3 ) +#define BIT4 ( 1U << 4 ) +#define BIT5 ( 1U << 5 ) +#define BIT6 ( 1U << 6 ) +#define BIT7 ( 1U << 7 ) +#define BIT8 ( 1U << 8 ) +#define BIT9 ( 1U << 9 ) +#define BIT10 ( 1U << 10 ) +#define BIT11 ( 1U << 11 ) +#define BIT12 ( 1U << 12 ) +#define BIT13 ( 1U << 13 ) +#define BIT14 ( 1U << 14 ) +#define BIT15 ( 1U << 15 ) +#define BIT16 ( 1U << 16 ) +#define BIT17 ( 1U << 17 ) +#define BIT18 ( 1U << 18 ) +#define BIT19 ( 1U << 19 ) +#define BIT20 ( 1U << 20 ) +#define BIT21 ( 1U << 21 ) +#define BIT22 ( 1U << 22 ) +#define BIT23 ( 1U << 23 ) +#define BIT24 ( 1U << 24 ) +#define BIT25 ( 1U << 25 ) +#define BIT26 ( 1U << 26 ) +#define BIT27 ( 1U << 27 ) +#define BIT28 ( 1U << 28 ) +#define BIT29 ( 1U << 29 ) +#define BIT30 ( 1U << 30 ) +#define BIT31 ( 1U << 31 ) + + +/*-------------------------- ITCM memory map -------------------------*/ + +#define ITCM_CR (*(volatile uint32_t *)(0xE001E010) ) +#define ITCM_CR_SZ_Pos ( 3U ) +#define ITCM_CR_SZ_Msk ( 0x0FUL << ITCM_CR_SZ_Pos ) +#define ITCM_CR_SZ ( ITCM_CR_SZ_Msk ) +#define ITCM_CR_EN_Pos ( 0U ) +#define ITCM_CR_EN_Msk ( 0x1UL << ITCM_CR_EN_Pos ) +#define ITCM_CR_EN ( ITCM_CR_EN_Msk ) + +/*-------------------------- DTCM memory map -------------------------*/ + +#define DTCM_CR (*(volatile uint32_t *)(0xE001E014) ) +#define DTCM_CR_SZ_Pos ( 3U ) +#define DTCM_CR_SZ_Msk ( 0x0FUL << DTCM_CR_SZ_Pos ) +#define DTCM_CR_SZ ( DTCM_CR_SZ_Msk ) +#define DTCM_CR_EN_Pos ( 0U ) +#define DTCM_CR_EN_Msk ( 0x1UL << DTCM_CR_EN_Pos ) +#define DTCM_CR_EN ( DTCM_CR_EN_Msk ) + +/*-------------------------- Peripheral memory map -------------------------*/ + +#define SPI7_MEM_BASE_ADDR ( 0x08000000UL ) +#define SPI8_MEM_BASE_ADDR ( 0x10000000UL ) +#define IROM_BASE_ADDR ( 0x1FF00000UL ) + +#define SRAM_BASE_ADDR ( 0x20000000UL ) +#define DTCM_BASE_ADDR ( SRAM_BASE_ADDR + 0x00000000UL ) +#define SRAM1_BASE_ADDR ( SRAM_BASE_ADDR + 0x00008000UL ) +#define SRAM2_BASE_ADDR ( SRAM_BASE_ADDR + 0x00038000UL ) +#define SRAM3_BASE_ADDR ( SRAM_BASE_ADDR + 0x00058000UL ) + +#define PERIPH_BASE_ADDR ( 0x40000000UL) + +#define APB1PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x00000000UL ) +#define APB2PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x00010000UL ) +#define APB3PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x11000000UL ) +#define APB4PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x13000000UL ) +#define AHB1PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x00020000UL ) +#define AHB2PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x08000000UL ) +#define AHB3PERIPH_BASE_ADDR ( PERIPH_BASE_ADDR + 0x12000000UL ) + +/*---------------------------- APB1 peripherals ----------------------------*/ + +#define TIM2_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00000000UL ) +#define TIM3_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00000400UL ) +#define TIM4_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00000800UL ) +#define TIM5_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00000C00UL ) +#define TIM6_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00001000UL ) +#define TIM7_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00001400UL ) +#define TIM12_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00001800UL ) +#define TIM13_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00001C00UL ) +#define TIM14_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00002000UL ) +#define RTC_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00002800UL ) +#define WDT_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00002C00UL ) +#define IWDT_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00003000UL ) +#define I2S1_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00003400UL ) +#define I2S2_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00003800UL ) +#define I2S3_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00003C00UL ) +#define USART2_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00004400UL ) +#define USART3_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00004800UL ) +#define USART4_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00004C00UL ) +#define USART5_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00005000UL ) +#define I2C1_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00005400UL ) +#define I2C2_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00005800UL ) +#define I2C3_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00005C00UL ) +#define I2C4_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00006000UL ) +#define PMU_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00007000UL ) +#define LPTIM1_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00007C00UL ) +#define LPUART1_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00008000UL ) +#define LPTIM2_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00009400UL ) +#define USART7_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00009800UL ) +#define USART8_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x00009C00UL ) +#define TIM25_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x0000A000UL ) +#define TIM26_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x0000A400UL ) +#define EFUSE1_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x0000E000UL ) +#define EFUSE2_BASE_ADDR ( APB1PERIPH_BASE_ADDR + 0x0000E800UL ) + +/*---------------------------- APB2 peripherals ----------------------------*/ + +#define SYSCFG_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00000000UL ) +#define COMP1_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00000200UL ) +#define EXTI_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00000400UL ) +#define TIM1_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00002C00UL ) +#define TIM8_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00003400UL ) +#define USART1_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00003800UL ) +#define USART6_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00003C00UL ) +#define TIM15_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00004000UL ) +#define TIM16_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00004400UL ) +#define TIM17_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00004800UL ) +#define TIM20_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00005000UL ) +#define TKEY_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00006400UL ) +#define LTDC_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00006800UL ) +#define TIM9_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00008000UL ) +#define TIM10_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00008400UL ) +#define TIM11_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00008800UL ) +#define TIM18_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00009000UL ) +#define TIM19_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00009400UL ) +#define TIM21_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x00009C00UL ) +#define TIM22_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x0000A000UL ) +#define TIM23_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x0000A400UL ) +#define TIM24_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x0000A800UL ) +#define USART9_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x0000B000UL ) +#define USART10_BASE_ADDR ( APB2PERIPH_BASE_ADDR + 0x0000B400UL ) + +/*---------------------------- APB3 peripherals ----------------------------*/ + +#define LPTIM3_BASE_ADDR ( APB3PERIPH_BASE_ADDR + 0x00000000UL ) +#define LPTIM4_BASE_ADDR ( APB3PERIPH_BASE_ADDR + 0x00000400UL ) +#define LPTIM5_BASE_ADDR ( APB3PERIPH_BASE_ADDR + 0x00000800UL ) +#define LPTIM6_BASE_ADDR ( APB3PERIPH_BASE_ADDR + 0x00000C00UL ) + +/*---------------------------- APB4 peripherals ----------------------------*/ + +#define STM1_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00000000UL ) +#define STM2_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00000400UL ) +#define DCM1_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00000800UL ) +#define DCM2_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00000C00UL ) +#define DCM3_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00001000UL ) +#define DCM4_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00001400UL ) +#define NDL_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00001800UL ) +#define MDAC_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00001C00UL ) +#define STM3_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00002000UL ) +#define STM4_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00002400UL ) +#define STM5_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00002800UL ) +#define STM6_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00002C00UL ) +#define DCM5_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00003000UL ) +#define DCM6_PWM_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00003400UL ) +#define LPT_BASE_ADDR ( APB4PERIPH_BASE_ADDR + 0x00003800UL ) + +#define DCMPWM1_AREA1_ADDR (DCM1_PWM_BASE_ADDR+0x00) +#define DCMPWM2_AREA1_ADDR (DCM2_PWM_BASE_ADDR+0x00) +#define DCMPWM3_AREA1_ADDR (DCM3_PWM_BASE_ADDR+0x00) +#define DCMPWM4_AREA1_ADDR (DCM4_PWM_BASE_ADDR+0x00) +#define DCMPWM5_AREA1_ADDR (DCM5_PWM_BASE_ADDR+0x00) +#define DCMPWM6_AREA1_ADDR (DCM6_PWM_BASE_ADDR+0x00) + +#define DCMPWM1_AREA2_ADDR (DCM1_PWM_BASE_ADDR+0x0C) +#define DCMPWM2_AREA2_ADDR (DCM2_PWM_BASE_ADDR+0x0C) +#define DCMPWM3_AREA2_ADDR (DCM3_PWM_BASE_ADDR+0x0C) +#define DCMPWM4_AREA2_ADDR (DCM4_PWM_BASE_ADDR+0x0C) +// DCM5,DCM6Ϊ棬AREA2Ĵ + +#define DCMPWM1_AREA3_ADDR (DCM1_PWM_BASE_ADDR+0x38) +#define DCMPWM2_AREA3_ADDR (DCM2_PWM_BASE_ADDR+0x38) +#define DCMPWM3_AREA3_ADDR (DCM3_PWM_BASE_ADDR+0x38) +#define DCMPWM4_AREA3_ADDR (DCM4_PWM_BASE_ADDR+0x38) +#define DCMPWM5_AREA3_ADDR (DCM5_PWM_BASE_ADDR+0x0C) +#define DCMPWM6_AREA3_ADDR (DCM6_PWM_BASE_ADDR+0x0C) + +/*---------------------------- AHB1 peripherals ----------------------------*/ + +#define DMA1_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00000000UL ) +#define DMA1_CHANNEL0_BASE_ADDR ( DMA1_BASE_ADDR + 0x00000100UL ) +#define DMA1_CHANNEL1_BASE_ADDR ( DMA1_BASE_ADDR + 0x00000120UL ) +#define DMA1_CHANNEL2_BASE_ADDR ( DMA1_BASE_ADDR + 0x00000140UL ) +#define DMA1_CHANNEL3_BASE_ADDR ( DMA1_BASE_ADDR + 0x00000160UL ) +#define DMA1_CHANNEL4_BASE_ADDR ( DMA1_BASE_ADDR + 0x00000180UL ) +#define DMA1_CHANNEL5_BASE_ADDR ( DMA1_BASE_ADDR + 0x000001A0UL ) +#define DMA1_CHANNEL6_BASE_ADDR ( DMA1_BASE_ADDR + 0x000001C0UL ) +#define DMA1_CHANNEL7_BASE_ADDR ( DMA1_BASE_ADDR + 0x000001E0UL ) +#define DMA2_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00000400UL ) +#define DMA2_CHANNEL0_BASE_ADDR ( DMA2_BASE_ADDR + 0x00000100UL ) +#define DMA2_CHANNEL1_BASE_ADDR ( DMA2_BASE_ADDR + 0x00000120UL ) +#define DMA2_CHANNEL2_BASE_ADDR ( DMA2_BASE_ADDR + 0x00000140UL ) +#define DMA2_CHANNEL3_BASE_ADDR ( DMA2_BASE_ADDR + 0x00000160UL ) +#define DMA2_CHANNEL4_BASE_ADDR ( DMA2_BASE_ADDR + 0x00000180UL ) +#define DMA2_CHANNEL5_BASE_ADDR ( DMA2_BASE_ADDR + 0x000001A0UL ) +#define DMA2_CHANNEL6_BASE_ADDR ( DMA2_BASE_ADDR + 0x000001C0UL ) +#define DMA2_CHANNEL7_BASE_ADDR ( DMA2_BASE_ADDR + 0x000001E0UL ) +#define RCC_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00001000UL ) +#define FDCAN1_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00002000UL ) +#define FDCAN2_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00002400UL ) +#define CRC_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00003000UL ) +#define ETHMAC_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00008000UL ) +#define DMA2D_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x0000B000UL ) +#define SPI1_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00010000UL ) +#define SPI2_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00010400UL ) +#define SPI3_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00010800UL ) +#define SPI4_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00010C00UL ) +#define SPI5_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00011000UL ) +#define SPI6_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00011400UL ) +#define BKPSRAM_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00016400UL ) +#define USBOTG_HS1_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00020000UL ) +#define USBOTG_HS2_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x00060000UL ) +#define USBOTG1_PHYC_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x000A0000UL ) +#define USBOTG2_PHYC_BASE_ADDR ( AHB1PERIPH_BASE_ADDR + 0x000A0400UL ) + +/*---------------------------- AHB2 peripherals ----------------------------*/ + +#define GPIOA_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00000000UL ) +#define GPIOB_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00000400UL ) +#define GPIOC_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00000800UL ) +#define GPIOD_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00000C00UL ) +#define GPIOE_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00001000UL ) +#define GPIOF_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00001400UL ) +#define GPIOG_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00001800UL ) +#define GPIOH_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00001C00UL ) +#define GPIOI_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00002000UL ) +#define GPIOJ_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00002400UL ) +#define GPIOK_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00002800UL ) +#define GPIOL_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00002C00UL ) +#define GPIOM_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00003000UL ) +#define GPION_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00003400UL ) +#define GPIOO_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00003800UL ) +#define GPIOP_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00003C00UL ) +#define GPIOQ_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x00004000UL ) +#define ADC1_2_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08000000UL ) +#define ADC1_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08000000UL ) +#define ADC2_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08000100UL ) +#define ADC3_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08000400UL ) +#define DAC1_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08000800UL ) +#define DAC2_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08000C00UL ) +#define FDCAN3_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08001400UL ) +#define DCMI_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08050000UL ) +#define AES_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08060000UL ) +#define CORDIC_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08060400UL ) +#define HRNG_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08060800UL ) +#define HASH_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08060C00UL ) +#define AES_SPI1_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08061000UL ) + +#define THM_BASE_ADDR ( AHB2PERIPH_BASE_ADDR + 0x08080000UL ) +#define HEAD_BASE_ADDR (THM_BASE_ADDR + 0x00) +#define LUT_BASE_ADDR (THM_BASE_ADDR + 0x200) +#define DOT1_BASE_ADDR (THM_BASE_ADDR + 0x400) +#define DOT2_BASE_ADDR (THM_BASE_ADDR + 0x800) +#define DOT3_BASE_ADDR (THM_BASE_ADDR + 0xc00) +#define LCFG_BASE_ADDR (THM_BASE_ADDR + 0x2000) + +/*---------------------------- AHB3 peripherals ----------------------------*/ + +#define SPI7_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x00005000UL ) +#define SPI8_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x00005400UL ) +#define USB1_DLYB_REG_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x00006800UL ) +#define ETH_DLYB_REG_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x00006C00UL ) +#define SDIO_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000C8000UL ) +#define SDIO_DLYBS_REG_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000CA000UL ) +#define SDIO_DLYBD_REG_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000CA800UL ) +#define OSPI1_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000D1400UL ) +#define OSPI2_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000D1800UL ) +#define OSPI1_DLYB_REG_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000D2000UL ) +#define OSPI2_DLYB_REG_BASE_ADDR ( AHB3PERIPH_BASE_ADDR + 0x000D2400UL ) + +/*---------------------------- External Memory ----------------------------*/ + +#define FMC_NORSRAM_BASE_ADDR ( 0x60000000UL ) +#define SDRAM1_SDRAM2_BASE_ADDR ( 0x70000000UL ) +#define OSPI1_MEM_BASE_ADDR ( 0x80000000UL ) +#define OSPI2_MEM_BASE_ADDR ( 0x88000000UL ) +#define SPI4_MEM_BASE_ADDR ( 0x90000000UL ) + +/*-------------------------- External peripherals --------------------------*/ + +#define FMC_REG_BASE_ADDR ( 0xA0000000UL ) +#define SDRAM1_NORSRAM_BASE_ADDR ( 0xC0000000UL ) +#define SDRAM2_BASE_ADDR ( 0xD0000000UL ) + +/*--------------------- Peripheral_registers_structures --------------------*/ + +/*--------------------------------- SYSCFG ---------------------------------*/ + +typedef struct +{ + __IO uint32_t SYSCR; + __IO uint32_t WMR; + __IO uint32_t VER; + __IO uint32_t RSV0C[1]; + __IO uint32_t PHYCFG; + __IO uint32_t RSV14[1]; + __IO uint32_t RAMECCIR; + __IO uint32_t RAMECCSR; + __IO uint32_t RAMECCICR; + __IO uint32_t GPIO5VOCR1; + __IO uint32_t GPIO5VOCR2; + __IO uint32_t DFTCR; + __IO uint32_t JTAGCR; + __IO uint32_t IPDISR; + __IO uint32_t BUSLOCK; + +} SYSCFG_TypeDef; + +typedef struct +{ + __IO uint32_t RCR; + __IO uint32_t RSR; + __IO uint32_t AHB1RSTR; + __IO uint32_t AHB2RSTR; + __IO uint32_t AHB3RSTR; + __IO uint32_t APB1RSTR1; + __IO uint32_t APB1RSTR2; + __IO uint32_t APB2RSTR; + __IO uint32_t APB3RSTR; + __IO uint32_t APB4RSTR; + __IO uint32_t CCR1; + __IO uint32_t CCR2; + __IO uint32_t PERCFGR; + __IO uint32_t CIR; + __IO uint32_t AHB1CKENR; + __IO uint32_t AHB2CKENR; + __IO uint32_t AHB3CKENR; + __IO uint32_t APB1CKENR1; + __IO uint32_t APB1CKENR2; + __IO uint32_t APB2CKENR; + __IO uint32_t APB3CKENR; + __IO uint32_t APB4CKENR; + __IO uint32_t RCHCR; + __IO uint32_t XTHCR; + __IO uint32_t PLL1CR; + __IO uint32_t PLL1CFR; + __IO uint32_t PLL1SCR; + __IO uint32_t PLL2CR; + __IO uint32_t PLL2CFR; + __IO uint32_t PLL2SCR; + __IO uint32_t PLL3CR; + __IO uint32_t PLL3CFR; + __IO uint32_t RSV80; + __IO uint32_t CLKOCR; + __IO uint32_t DCKCFG; + __IO uint32_t STDBYCTRL; + +} RCC_TypeDef; + +typedef struct +{ + __IO uint32_t MD; + __IO uint32_t OTYP; + __IO uint32_t PUPD; + __IO uint32_t IDATA; + __IO uint32_t ODATA; + __IO uint32_t BSC; + __IO uint32_t AF0; + __IO uint32_t AF1; + __IO uint32_t DS0; + __IO uint32_t DS1; + __IO uint32_t SMIT; + __IO uint32_t LOCK; + __IO uint32_t AIEN; + +} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t IENR1; + __IO uint32_t IENR2; + __IO uint32_t EENR1; + __IO uint32_t EENR2; + __IO uint32_t RTENR1; + __IO uint32_t RTENR2; + __IO uint32_t FTENR1; + __IO uint32_t FTENR2; + __IO uint32_t SWIER1; + __IO uint32_t SWIER2; + __IO uint32_t PDR1; + __IO uint32_t PDR2; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + +} EXTI_TypeDef;; + +typedef struct +{ + __IO uint32_t INTSTATUS; + __IO uint32_t INTTCSTATUS; + __IO uint32_t INTTCCLR; + __IO uint32_t INTERRSTATUS; + __IO uint32_t INTERRCLR; + __IO uint32_t RAWINTTCSTATUS; + __IO uint32_t RAWINTERRSTATUS; + __IO uint32_t ENCHSTATUS; + __IO uint32_t RSV0[4]; + __IO uint32_t CONFIG; + __IO uint32_t SYNCLO; + __IO uint32_t SYNCHI; + +} DMA_TypeDef; + + +typedef struct +{ + __IO uint32_t CXSRCADDR; + __IO uint32_t CXDESTADDR; + __IO uint32_t CXLLI; + __IO uint32_t CXCTRL; + __IO uint32_t CXCONFIG; + +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t DR; + __IO uint32_t FR; + __IO uint32_t BRR; + __IO uint32_t IE; + __IO uint32_t ISR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t GTPR; + __IO uint32_t BCNT; + +} USART_TypeDef; + +/*------------------- SPI ----------------------*/ +typedef struct _SPI_MEMO_ACC +{ +__IO uint32_t acc_en:1; + uint32_t cs_tout_en:1; + uint32_t rsv4:1; + uint32_t crm_en:1; + uint32_t instr_once:1; + uint32_t wr_ab_en:1; + uint32_t rd_ab_en:1; + uint32_t alter_byte_size:2; + uint32_t rsv3:1; + uint32_t wr_db_en:1; + uint32_t rd_db_en:1; + uint32_t dummy_cycle:3; + uint32_t rsv2:2; + uint32_t addr_size:2; + uint32_t instr_mode:2; + uint32_t addr_mode:2; + uint32_t alter_byte_mode:2; + uint32_t data_mode:2; + uint32_t instr_once_clr:1; + uint32_t rsv1:4; + +} SPI_MEMO_ACC_t; + +typedef struct _SPI_MEM_CMD +{ + __IO uint32_t rd_cmd:8; + __IO uint32_t wr_cmd:8; + __IO uint32_t rsv:16; +} SPI_MEM_CMD_t; + +typedef struct +{ + __IO uint32_t DAT; //0x00 + __IO uint32_t BAUD; //0x04 + __IO uint32_t CTL; //0x08 + __IO uint32_t TX_CTL; //0x0C + __IO uint32_t RX_CTL; //0x10 + __IO uint32_t IE; //0x14 + __IO uint32_t STATUS; //0x18 + __IO uint32_t TX_DELAY; //0x1C + __IO uint32_t BATCH; //0x20 + __IO uint32_t CS; //0x24 + __IO uint32_t OUT_EN; //0x28 + SPI_MEMO_ACC_t MEMO_ACC; //2C + SPI_MEM_CMD_t CMD; //30 + __IO uint32_t ALTER_BYTE; //34 + __IO uint32_t CS_TOUT_VAL;//38 +} SPI_TypeDef; + +/*------------------- I2C ----------------------*/ +typedef struct +{ + __IO uint32_t SLAVE_ADDR1; //0x00 + __IO uint32_t CLK_DIV; //0x04 + __IO uint32_t CR; //0x08 + __IO uint32_t SR; //0x0C + __IO uint32_t DR; //0x10 + __IO uint32_t SLAVE_ADDR2_3; //0x14 + __IO uint32_t DET; //0x18 + __IO uint32_t FILTER; //0x1C + __IO uint32_t RSV1; //0x20 + __IO uint32_t TIMEOUT; //0x24 +} I2C_TypeDef; + + +/////////////////////////////////////////////////////////////////////////////////// +/* FDCAN timming */ +typedef union +{ + struct{ + __IO uint32_t SEG1:8; + __IO uint32_t SEG2:8; + __IO uint32_t SJW:8; + __IO uint32_t PRESC:8; + }b; + __IO uint32_t w; +} fdcan_btr_u; + +/* FDCAN error cnt */ +typedef union +{ + struct{ + __IO uint32_t ALC:5; + __IO uint32_t KOER:3; + __IO uint32_t RSV:8; + __IO uint32_t RECNT:8; + __IO uint32_t TECNT:8; + }b; + __IO uint32_t w; +}fdcan_ecc_u; + +typedef union +{ + struct{ + __IO uint32_t ACFADR:4; + __IO uint32_t RSV:1; + __IO uint32_t SELMASK:1; + __IO uint32_t RSV1:10; + __IO uint32_t AE:16; + }b; + __IO uint32_t w; +} fdcan_acfctrl_u; + +typedef union +{ + struct{ + __IO uint32_t ACM:29; //Acceptance Code or Mask + __IO uint32_t AIDE:1; + __IO uint32_t AIDEE:1; + __IO uint32_t RSV:1; + }b; + __IO uint32_t w; +} fdcan_acodr_u; + + + +typedef union +{ + struct{ + uint32_t REF_ID:29; + uint32_t RSV:2; + uint32_t REF_IDE:1; + }b; + __IO uint32_t w; +} ttcan_refmsg_u; + +typedef union +{ + struct{ + __IO uint32_t TRIGCFG0:8; + __IO uint32_t TRIGCFG1:8; + __IO uint32_t TRIG0:8; + __IO uint32_t TRIG1:8; + }b; + __IO uint32_t w; +} ttcan_trig_ctrl_u; + + +typedef union +{ + struct{ + __IO uint32_t TTPTR:6; + __IO uint32_t RSV:2; + __IO uint32_t TTYPE:3; + __IO uint32_t RSV1:1; + __IO uint32_t TEW:4; + __IO uint32_t RSV2:16; + }b; + __IO uint32_t w; +}ttcan_trig_cfg_u; + +typedef union +{ + struct{ + __IO uint32_t WTRIG0:8; + __IO uint32_t WTRIG1:8; + __IO uint32_t RSV:16; + }b; + __IO uint32_t w; +} ttcan_wtrig_u; + + +typedef struct +{ + __IO uint32_t RBUF[20]; + __IO uint32_t TBUF[18]; //50 + __IO uint32_t TTSL; //98 + __IO uint32_t TTSH; //9C + __IO uint32_t CR; //A0 + __IO uint32_t IR; //A4 + __IO uint32_t LIMIT; //A8 + __IO fdcan_btr_u SBTR; //AC + __IO fdcan_btr_u FBTR; //B0 + __IO uint32_t TDC; //B4 + __IO fdcan_ecc_u ECC; //B8 + __IO fdcan_acfctrl_u ACFCR; //BC + __IO uint32_t ACFMODE; //C0 + __IO uint32_t ACODR; //C4 + __IO uint32_t TIMECFG; //C8 + __IO uint32_t TTCFG; //CC + __IO ttcan_refmsg_u TTREFMSG; //D0 + __IO ttcan_trig_cfg_u TTTRIGCFG; //D4 + __IO uint32_t TTTRIG; //D8 + __IO ttcan_wtrig_u TTWTRIGR; //DC + +} FDCAN_GlobalTypeDef; + +///*------------------- LPUART Registers ----------------------*/ +typedef struct +{ + __IO uint32_t RXDR; // 0x00 + __IO uint32_t TXDR; // 0x04 + __IO uint32_t LCR; // 0x08 + __IO uint32_t CR; // 0x0C + __IO uint32_t IBAUD; // 0x10 + __IO uint32_t FBAUD; // 0x14 + __IO uint32_t IE; // 0x18 + __IO uint32_t SR; // 0x1C + __IO uint32_t ADDR; // 0x20 +} LPUART_TypeDef; + +typedef struct +{ + __IO uint32_t TXDR; + __IO uint32_t RXDR; + __IO uint32_t CR; + __IO uint32_t PR; + __IO uint32_t DIER; + __IO uint32_t SR; + __IO uint32_t RSV18; + __IO uint32_t RSIZE; + +} I2S_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + +} DLYB_TypeDef; + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + __IO uint32_t RSV0020[1]; + __IO uint32_t MACDBGR; + __IO uint32_t MACRWUFF; + __IO uint32_t MACPMTCSR; + __IO uint32_t MACLPICSR; + __IO uint32_t MACLPITCR; + __IO uint32_t MACISR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + __IO uint32_t RSV0060[31]; + __IO uint32_t MACWTR; + __IO uint32_t RSV00E0[8]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + __IO uint32_t RSV0114[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMCCR; + __IO uint32_t RSV0154[5]; + __IO uint32_t MMCTGFCR; + __IO uint32_t RSV016C[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + __IO uint32_t RSV019C[10]; + __IO uint32_t MMCRGUFCR; + __IO uint32_t RSV01C8[142]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + __IO uint32_t RSV0408[2]; + __IO uint32_t MACL3A00R; + __IO uint32_t MACL3A10R; + __IO uint32_t MACL3A20R; + __IO uint32_t MACL3A30R; + __IO uint32_t RSV0420[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + __IO uint32_t RSV0438[2]; + __IO uint32_t MACL3A01R; + __IO uint32_t MACL3A11R; + __IO uint32_t MACL3A21R; + __IO uint32_t MACL3A31R; + __IO uint32_t RSV0450[77]; + __IO uint32_t MACVTIRR; + __IO uint32_t MACVHTR; + __IO uint32_t RSV058C[93]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RSV0724[1]; + __IO uint32_t PTPTSSR; + __IO uint32_t PTPPPSCR; + __IO uint32_t PTPATSNR; + __IO uint32_t PTPATSSR; + __IO uint32_t RSV0738[10]; + __IO uint32_t PTPPPSIR; + __IO uint32_t PTPPPSWR; + __IO uint32_t RSV0768[550]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARIWTR; + __IO uint32_t RSV1028[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; + +} ETH_TypeDef; + +///*------------------- PMU ----------------------*/ +typedef struct +{ + __IO uint32_t CTRL0; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; + __IO uint32_t SR; + __IO uint32_t STCLR; + __IO uint32_t IOSEL; + __IO uint32_t RSV0[41]; + __IO uint32_t TEST_ANATEST_SR; + __IO uint32_t TEST_LDOCAL; + __IO uint32_t TEST_LDOCR; + +} PMU_TypeDef; + +///*------------------- RTC ----------------------*/ +typedef struct +{ + __IO uint32_t WP; + __IO uint32_t IE; + __IO uint32_t SR; + __IO uint32_t SEC; + __IO uint32_t MIN; + __IO uint32_t HOUR; + __IO uint32_t DAY; + __IO uint32_t WEEK; + __IO uint32_t MONTH; + __IO uint32_t YEAR; + __IO uint32_t ALM; + __IO uint32_t CR; + __IO uint32_t ADJUST; + __IO uint32_t RSV0[2]; + __IO uint32_t MSECCNT; + __IO uint32_t RSV1[1]; + __IO uint32_t CLKSTAMP1; + __IO uint32_t CALSTAMP1; + __IO uint32_t CLKSTAMP2; + __IO uint32_t CALSTAMP2; + __IO uint32_t WUTR; + __IO uint32_t RSV2[6]; + __IO uint32_t BAKUP[16]; +} RTC_TypeDef; + +///*------------------- WDT ----------------------*/ +typedef struct +{ + __IO uint32_t LOAD; + __IO uint32_t COUNT; + __IO uint32_t CTRL; + __IO uint32_t FEED; + __IO uint32_t INTCLRTIME; + __IO uint32_t RIS; + +} WDT_TypeDef; + +///*------------------- IWDT ----------------------*/ +typedef struct +{ + __IO uint32_t CMDR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; + __IO uint32_t WINR; + __IO uint32_t WUTR; + +} IWDT_TypeDef; + +///*------------------- ADC ----------------------*/ +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t IE; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t SMPR3; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR[4]; + __IO uint32_t RSV0[1]; + __IO uint32_t DR; + __IO uint32_t DIFSEL; + __IO uint32_t RSV1[4]; + __IO uint32_t OFR[4]; + __IO uint32_t RSV2[5]; + __IO uint32_t CALFACT; + __IO uint32_t CHDR[9]; + __IO uint32_t TEST_DATA[10]; +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t CCR; + __IO uint32_t CDR; + __IO uint32_t CVRB; +} ADC_Common_TypeDef; + +///*------------------- DAC ----------------------*/ +typedef struct +{ + __IO uint32_t CR; //0x00 + __IO uint32_t SWTRIGR; //0x04 + __IO uint32_t DHR12R1; //0x08 + __IO uint32_t DHR12L1; //0x0C + __IO uint32_t DHR8R1; //0x10 + __IO uint32_t DHR12R2; //0x14 + __IO uint32_t DHR12L2; //0x18 + __IO uint32_t DHR8R2; //0x1C + __IO uint32_t DHR12RD; //0x20 + __IO uint32_t DHR12LD; //0x24 + __IO uint32_t DHR8RD; //0x28 + __IO uint32_t DOR1; //0x2C + __IO uint32_t DOR2; //0x30 + __IO uint32_t SR; //0x34 + __IO uint32_t CCR; //0x38 + __IO uint32_t MCR; //0x3C + __IO uint32_t SHSR1; //0x40 + __IO uint32_t SHSR2; //0x44 + __IO uint32_t SHHR; //0x48 + __IO uint32_t SHRR; //0x4C + __IO uint32_t RSV[2]; //0x50~0x54 + __IO uint32_t STR1; //0x58 + __IO uint32_t STR2; //0x5C + __IO uint32_t STMODR; //0x60 +} DAC_TypeDef; + +///*------------------- MDAC ----------------------*/ +typedef struct{ + __IO uint32_t VDACx_CTRL[12]; //0x00~0x2c + __IO uint32_t IDACx_CTRL[4]; //0x30~0x3c + __IO uint32_t DACx_DOR[16]; //0x40~0x7c +} MDAC_TypeDef; + + +///*------------------- TKEY ----------------------*/ +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t IER; + __IO uint32_t CR; + __IO uint32_t CFGR1; + __IO uint32_t CFGR2; + __IO uint32_t INTVLR; + __IO uint32_t DIVR; + __IO uint32_t SCCR; + __IO uint32_t TSETR; + __IO uint32_t CXENR; + __IO uint32_t DR; + __IO uint32_t TH[16]; + __IO uint32_t CH[16]; + __IO uint32_t CFLTR; + __IO uint32_t NSETR; + __IO uint32_t TWAITR; + __IO uint32_t MUTUALR; + __IO uint32_t TXENR[2]; + +} TKEY_TypeDef; + +///*------------------- OSPI ----------------------*/ +typedef struct +{ + __IO uint32_t DAT; + __IO uint32_t BAUD; + __IO uint32_t CTL; + __IO uint32_t TX_CTL; + __IO uint32_t RX_CTL; + __IO uint32_t IE; + __IO uint32_t STATUS; + __IO uint32_t TX_DELAY; + __IO uint32_t BATCH; + __IO uint32_t CS; + __IO uint32_t OUT_EN; + __IO uint32_t MEMO_ACC1; + __IO uint32_t CMD; + __IO uint32_t ALTER_BYTE; + __IO uint32_t CS_TIMEOUT_VAL; + __IO uint32_t MEMO_ACC2; +} OSPI_TypeDef; + +///*------------------- FMC ----------------------*/ +typedef struct +{ + __IO uint32_t SNCTLCFG[8]; + __IO uint32_t RSV0[57]; + __IO uint32_t SNWTCFG[7]; + +} FMC_NORSRAM_TypeDef; + +typedef struct +{ + __IO uint32_t SDRCR[2]; + __IO uint32_t SDRTR[2]; + __IO uint32_t SDRCMD; + __IO uint32_t SDRART; + __IO uint32_t SDRSR; + __IO uint32_t SDRSMA1; + __IO uint32_t SDRSMA2; + +} FMC_SDRAM_TypeDef; + + +typedef struct +{ + __IO uint32_t CR1; // 0x00 + __IO uint32_t CR2; // 0x04 + __IO uint32_t SMCR; // 0x08 + __IO uint32_t DIER; // 0x0C + __IO uint32_t SR; // 0x10 + __IO uint32_t EGR; // 0x14 + __IO uint32_t CCMR1; // 0x18 + __IO uint32_t CCMR2; // 0x1C + __IO uint32_t CCER; // 0x20 + __IO uint32_t CNT; // 0x24 + __IO uint32_t PSC; // 0x28 + __IO uint32_t ARR; // 0x2C + __IO uint32_t RCR; // 0x30 + __IO uint32_t CCR1; // 0x34 + __IO uint32_t CCR2; // 0x38 + __IO uint32_t CCR3; // 0x3C + __IO uint32_t CCR4; // 0x40 + __IO uint32_t BDTR; // 0x44 + __IO uint32_t DCR; // 0x48 + __IO uint32_t DMAR; // 0x4C + __IO uint32_t OR1; // 0x50 + __IO uint32_t CCMR3; // 0x54 + __IO uint32_t CCR5; // 0x58 + __IO uint32_t CCR6; // 0x5C + __IO uint32_t AF1; // 0x60 + __IO uint32_t AF2; // 0x64 + __IO uint32_t TISEL; // 0x68 + __IO uint32_t DBER; // 0x6C +} TIM_TypeDef; + +typedef struct +{ + __IO uint32_t CTRL; // 0x00 + __IO uint32_t SR; // 0x04 + __IO uint32_t ARR_LOW; // 0x08 + __IO uint32_t ARR_HIGH; // 0x0c + __IO uint32_t CNT_LOW; // 0x10 + __IO uint32_t CNT_HIGH; // 0x14 +} TIM_64BIT_TypeDef; + + +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GGPIO; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved7; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ + + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ +} USB_OTG_GlobalTypeDef; + + +typedef struct +{ + __IO uint32_t TR0; //00 + __IO uint32_t TR1; //04 + __IO uint32_t TR2; //08 + __IO uint32_t TR3; //0C + __IO uint32_t TR4; //10 + __IO uint32_t TR5; //14 + __IO uint32_t TR6; //18 + __IO uint32_t TR7; //1C + __IO uint32_t RSV0[2]; //20 + __IO uint32_t TR8; //28 + __IO uint32_t TR9; //2C + __IO uint32_t RSV1[20]; //30 + __IO uint32_t CR; //80 +} USB_HS_PHYC_GlobalTypeDef; + +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + __IO uint32_t DINEP0MSK; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t IER; + __IO uint32_t CFGR1; + __IO uint32_t CR; + __IO uint32_t CMP; + __IO uint32_t ARR; + __IO uint32_t CNT; + __IO uint32_t RSV0[1]; + __IO uint32_t CFGR2; + __IO uint32_t RCR; + +} LPTIM_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RIS; + __IO uint32_t IER; + __IO uint32_t MIS; + __IO uint32_t ICR; + __IO uint32_t ESCR; + __IO uint32_t ESUR; + __IO uint32_t CWSTRT; + __IO uint32_t CWSIZE; + __IO uint32_t DR; + +} DCMI_TypeDef; + +///*------------------- LTDC ----------------------*/ +typedef struct +{ + __IO uint32_t RSV1[2]; + __IO uint32_t SSCR; + __IO uint32_t BPCR; + __IO uint32_t AWCR; //0x10 + __IO uint32_t TWCR; + __IO uint32_t GCR; + __IO uint32_t RSV2[2]; + __IO uint32_t SRCR; + __IO uint32_t RSV3; + __IO uint32_t BCCR; + __IO uint32_t RSV4; //0x30 + __IO uint32_t IER; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t LIPCR; //0x40 + __IO uint32_t CPSR; + __IO uint32_t CDSR; +} LTDC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WHPCR; + __IO uint32_t WVPCR; + __IO uint32_t CKCR; //0x90 + __IO uint32_t PFCR; + __IO uint32_t CACR; + __IO uint32_t DCCR; + __IO uint32_t BFCR; //0xA0 + __IO uint32_t RSV1[2]; + __IO uint32_t CFBAR; + __IO uint32_t CFBLR; //0xB0 + __IO uint32_t CFBLNR; + __IO uint32_t RSV2[3]; + __IO uint32_t CLUTWR; +} LTDC_Layer_TypeDef; + +///*------------------- CRC ----------------------*/ +typedef struct +{ + __IO uint32_t DATA; + __IO uint32_t CTRL; + __IO uint32_t INIT; + __IO uint32_t RSV0; + __IO uint32_t OUTXOR; + __IO uint32_t POLY; + __IO uint32_t FDATA; +} CRC_TypeDef; + +///*------------------- FMC_NAND ----------------------*/ +typedef union +{ + uint8_t FMC_NAND_BCHCODE_CH8; + uint16_t FMC_NAND_BCHCODE_CH16; + uint32_t FMC_NAND_BCHCODE_CH32; +} FMC_NAND_BCH_CODE_t; + +typedef union +{ + uint8_t FMC_NAND_ECCDATA_CH8; + uint16_t FMC_NAND_ECCDATA_CH16; + uint32_t FMC_NAND_ECCDATA_CH32; +} FMC_NAND_ECCDATA_t; + +typedef union +{ + uint8_t FMC_NAND_NECCDATA_CH8; + uint16_t FMC_NAND_NECCDATA_CH16; + uint32_t FMC_NAND_NECCDATA_CH32; +} FMC_NAND_NECCDATA_t; + +typedef struct +{ + __IO uint32_t CTRL; //0x00 + __IO uint32_t WST; //0x04 + __IO uint32_t STATUS; //0x08 + __IO uint32_t RSV0; //0x0c + __IO uint32_t BCH_CFG; //0x10 + __IO uint32_t BCH_CTRL; //0x14 + __IO uint32_t BCH_STATUS; //0x18 + FMC_NAND_BCH_CODE_t BCH_CODE; //0x1c + __IO uint32_t BCH_ERRADR; //0x20 + __IO uint32_t BCH_ERRVEC; //0x24 + __IO uint32_t BCH_BASEADDR; //0x28 + __IO uint32_t BCH_CODEPTR; + __IO uint32_t BCH_ERRADDRPTR; + __IO uint32_t BCH_ERRVECPTR; + __IO uint32_t BCH_PAGENUM; + __IO uint32_t BCH_ADDRLATCH; + __IO uint32_t CMD; + __IO uint32_t ADDR; + FMC_NAND_ECCDATA_t FMC_NAND_ECCDATA; + FMC_NAND_NECCDATA_t FMC_NAND_NECCDATA; + +} FMC_NAND_TypeDef; + +///*------------------- DMA2D ----------------------*/ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t ISR; + __IO uint32_t IFCR; + __IO uint32_t FGMAR; + __IO uint32_t FGOR; //0x10 + __IO uint32_t BGMAR; + __IO uint32_t BGOR; + __IO uint32_t FGPFCCR; + __IO uint32_t FGCOLR; //0x20 + __IO uint32_t BGPFCCR; + __IO uint32_t BGCOLR; + __IO uint32_t FGCMAR; + __IO uint32_t BGCMAR; //0x30 + __IO uint32_t OPFCCR; + __IO uint32_t OCOLR; + __IO uint32_t OMAR; + __IO uint32_t OOR; //0x40 + __IO uint32_t NLR; + __IO uint32_t LWR; + __IO uint32_t AMTCR; +} DMA2D_TypeDef; + +typedef struct +{ + __IO uint32_t CR; //0x0 + __IO uint32_t SR; //0x4 + +}COMP_TypeDef; + +typedef struct +{ + __IO uint32_t WP; //0x0 + __IO uint32_t CTRL; //0x4 + __IO uint32_t AR; //0x8 + __IO uint32_t DWR; //0xc + __IO uint32_t SR; //0x10 + __IO uint32_t CLR; //0x14 + __IO uint32_t DR; //0x18 + __IO uint32_t DSDP; //0x1c + __IO uint32_t BYTEWP; //0x20 + __IO uint32_t PGCFG; //0x24 + __IO uint32_t RSV0[246]; //0x28 + __IO uint32_t DSR[16]; //0x400 + +}EFUSE_TypeDef; + +typedef struct +{ + __IO uint32_t DATAIN; //0x00 + __IO uint32_t KEYIN; //0x04 + __IO uint32_t IVIN; //0x08 + __IO uint32_t CTRL; //0x0C + __IO uint32_t STATE; //0x10 + __IO uint32_t DATAOUT; //0x14 + __IO uint32_t STARTADDR; //0x18 + __IO uint32_t ENDADDR; //0x1C + __IO uint32_t INIDATA; //0x20 + __IO uint32_t ADDR; //0x24 + +}AES_TypeDef; + +typedef struct +{ + __IO uint32_t CTRL; //0x00 + __IO uint32_t STAUTS; //0x04 + __IO uint32_t X_DATAIN; //0x08 + __IO uint32_t Y_DATAIN; //0x0c + __IO uint32_t RESULT1; //0x10 + __IO uint32_t RESULT2; //0x14 +}CORDIC_TypeDef; + + +typedef struct +{ + __IO uint32_t DATAIN; //0x00 + __IO uint32_t KEYIN; //0x04 + __IO uint32_t OTFDEC_CTRL; //0x08 + __IO uint32_t CTRL; //0x0C + __IO uint32_t STATE; //0x10 + __IO uint32_t DATAOUT; //0x14 + __IO uint32_t STARTADDR; //0x18 + __IO uint32_t ENDADDR; //0x1C + __IO uint32_t INIDATA; //0x20 + __IO uint32_t ADDR; //0x24 + __IO uint32_t UID; //0x28 + __IO uint32_t RAND0; //0x2C + __IO uint32_t RAND1; //0x30 + __IO uint32_t RSV0; //0x34 + __IO uint32_t OTFDEC_SPI_CTRL; //0x38 + __IO uint32_t ENDADDR2; //0x3c + __IO uint32_t ENDADDR3; //0x40 + __IO uint32_t RAND2; //0x44 + __IO uint32_t RAND3; //0x48 + __IO uint32_t KEYIN1; //0x4c + __IO uint32_t KEYIN2; //0x50 + __IO uint32_t KEYIN3; //0x54 + __IO uint32_t ADDR1; //0x58 + __IO uint32_t DATAOUT1; //0x5C +}AES_SPI_TypeDef; + + +///*------------------- SDMMC Registers ----------------------*/ +typedef struct +{ + __IO uint32_t SDMMC_CTRL; //00H + __IO uint32_t SDMMC_PWREN; //04H + __IO uint32_t SDMMC_CLKDIV; //08H + __IO uint32_t SDMMC_CLKSRC; //0CH + __IO uint32_t SDMMC_CLKENA; //10H + __IO uint32_t SDMMC_TMOUT; //14H + __IO uint32_t SDMMC_CTYPE; //18H + __IO uint32_t SDMMC_BLKSIZ; //1CH + __IO uint32_t SDMMC_BYTCNT; //20H + __IO uint32_t SDMMC_INTMASK; //24H + __IO uint32_t SDMMC_CMDARG; //28H + __IO uint32_t SDMMC_CMD; //2CH + __IO uint32_t SDMMC_RESP0; //30H + __IO uint32_t SDMMC_RESP1; //34H + __IO uint32_t SDMMC_RESP2; //38H + __IO uint32_t SDMMC_RESP3; //3CH + __IO uint32_t SDMMC_MINTSTS; //40H + __IO uint32_t SDMMC_RINTSTS; //44H + __IO uint32_t SDMMC_STATUS; //48H + __IO uint32_t SDMMC_FIFOTH; //4CH + __IO uint32_t SDMMC_CDETECT; //50H + __IO uint32_t SDMMC_WRTPRT; //54H + __IO uint32_t SDMMC_GPIO; //58H + __IO uint32_t SDMMC_TCBCNT; //5CH + __IO uint32_t SDMMC_TBBCNT; //60H + __IO uint32_t SDMMC_DEBNCE; //64H + __IO uint32_t SDMMC_RSV0[3]; //68H + __IO uint32_t SDMMC_UHS_REG; //74H + __IO uint32_t SDMMC_RSTN; //78H + __IO uint32_t SDMMC_RSV1; //7CH + __IO uint32_t SDMMC_BMOD; //80H + __IO uint32_t SDMMC_PLDMND; //84H + __IO uint32_t SDMMC_DBADDR; //88H + __IO uint32_t SDMMC_IDSTS; //8CH + __IO uint32_t SDMMC_IDINTEN; //90H + __IO uint32_t SDMMC_DSCADDR; //94H + __IO uint32_t SDMMC_BUFADDR; //98H + __IO uint32_t SDMMC_RSV2[25]; //9CH + __IO uint32_t SDMMC_CTHCTL; //100H + __IO uint32_t SDMMC_BKDPWR; //104H + __IO uint32_t SDMMC_UHS_EXT; //108H + __IO uint32_t SDMMC_EMMC_DDR; //10CH + __IO uint32_t SDMMC_ENA_SHIFT; //110H + __IO uint32_t SDMMC_RSV3[59]; //114H + __IO uint32_t SDMMC_DATA; //200H +} SDMMC_TypeDef; + + +///*----------------------- HDL registers ------------------------*/ + +typedef struct +{ + __IO uint32_t NDL_CTR; //0x000 + __IO uint32_t NDL_EN; //0x004 + __IO uint32_t NDL_CLKDIV; //0x008 + __IO uint32_t INT_MASK; //0x00c + __IO uint32_t INT_MIS; //0x010 + __IO uint32_t INT_CLR; //0x014 + __IO uint32_t WG_CTR; //0x018 + __IO uint32_t WG_PRD; //0x01c + __IO uint32_t HPSA_FLT; //0x020 + __IO uint32_t RAS_CNT_CTREN; //0x024 + __IO uint32_t RAS_CNT_CTR; //0x028 + __IO uint32_t RAS_CNT_VAL; //0x02c + __IO uint32_t RAS_SPEED; //0x030 + __IO uint32_t RAS_HSYNC; //0x034 + __IO uint32_t CORR_CNT; //0x038 + __IO uint32_t HPSA_CNT; //0x03c + __IO uint32_t FINE_STEP_PREC; //0x040 + __IO uint32_t FINE_STEP_CNT; //0x044 + __IO uint32_t PRINT_DELAY; //0x048 + __IO uint32_t PRINT_CTR; //0x04c + __IO uint32_t PRINT_START_POS; //0x050 + __IO uint32_t PRINT_INIT_POS[24]; //0x054~0x0b0 + __IO uint32_t PRINT_REQ_NUM; //0x0b4 + __IO uint32_t PRINT_DPI_SET; //0x0b8 + __IO uint32_t PRINT_DATA; //0x0bc + __IO uint32_t DMA_BUF_CTR; //0x0c0 + __IO uint32_t SPEED_UP_CNT; //0x0c4 + __IO uint32_t ADO_MODE_CTR; //0x0c8 + __IO uint32_t WAVE_TFG[24]; //0x0cc~0x128 + __IO uint32_t WAVE_TGHIJ; //0x12C + __IO uint32_t SURGE_TGKL; //0x130 + __IO uint32_t RSV0; //0x133 + __IO uint32_t PROT_TFMN; //0x138 + __IO uint32_t PROT_EN; //0x13C + __IO uint32_t PIN_CFG[24]; //0x140~0x19c + __IO uint32_t RSV1[24]; //0x1a0~0x1fc + __IO uint32_t DOT_CNT_VAL[24]; //0x200~0x25c + __IO uint32_t MS_CTR; //0x260 + __IO uint32_t MS_TGHIJ; //0x264, MS_TGHIJ_CHJ + __IO uint32_t MS_TGN; //0x268 + __IO uint32_t MS_TGQR; //0x26c + __IO uint32_t MS_ON_OFF; //0x270 + __IO uint32_t MS_PROT_TFMN; //0x274 + __IO uint32_t MS_PROT_EN; //0x278 + __IO uint32_t INT_RIS; //0x27c + __IO uint32_t DMA_DATA_STA; //0x280 + __IO uint32_t SURGE_CFG[24]; //0x284~0x2e0 + __IO uint32_t CLK_TFG; //0x2e4 + __IO uint32_t FEED_CTL; //0x2e8 +}NDL_TypeDef; + + +///*----------------------- HEAD registers ------------------------*/ +typedef struct +{ + __IO uint32_t PRINT_DATA; //0x000 ӡݼĴ + __IO uint32_t PRINT_DIV; //0x004 ӡƵĴ + __IO uint32_t PRINT_CFG1; //0x008 ӡüĴ1 + __IO uint32_t PRINT_CFG2; //0x00c ӡüĴ2 + __IO uint32_t PRINT_CFG3; //0x010 ӡüĴ3 + __IO uint32_t PRINT_TRIGR; //0x014 ӡѡĴ + __IO uint32_t PRINT_CR; //0x018 ӡƼĴ + __IO uint32_t PRINT_ERR; //0x01c ӡĴ + __IO uint32_t PRINT_SR; //0x020 ӡ״̬Ĵ + __IO uint32_t PRINT_IE; //0x024 ӡжʹܼĴ + + __IO uint32_t PRINT_ERR_IE; //0x028 ӡ״̬Ĵ // 2023/12/12 + __IO uint32_t RSV0[1]; //0x2c + + __IO uint32_t DATA_BASE[16]; //0x030~0x6c nʼַĴ + __IO uint32_t PRINT_SUBDATA; //0x070 ӡĴ + + __IO uint32_t CYC1_CFG; //0x74 // 2023/2/14 YZR + __IO uint32_t TIMERCR; //0x78 // 2023/6/6 YZR + __IO uint32_t DELAY; //0x7c // 2023/6/6 YZR + + __IO uint32_t DROP; //0x080 DROP + __IO uint32_t DROP_MAX; //0x084 + __IO uint32_t DROP_B; //0x088 + + __IO uint32_t DROP_IGN; //0x08c // 2023/2/14 YZR + __IO uint32_t RSV2[4]; //0x090~0x9c + + __IO uint32_t S_COR; //0x0a0 + __IO uint32_t Z_COR; //0x0a4 + __IO uint32_t M_COR; //0x0a8 + __IO uint32_t Z_ADD; //0x0ac + __IO uint32_t N_ADD; //0x0b0 + __IO uint32_t Z_RAD; //0x0b4 + __IO uint32_t M_ADD; //0x0b8 + __IO uint32_t MAIN; //0x0bc + __IO uint32_t M_RAD; //0x0c0 + __IO uint32_t P_ADD; //0x0c4 + __IO uint32_t S_COR_MAX; //0x0c8 + __IO uint32_t Z_ADD1; //0x0cc + __IO uint32_t MAX_OT; //0x0d0 + __IO uint32_t M_ADD1; //0x0d4 + __IO uint32_t MAX_OT_ZEN; //0x0d8 + __IO uint32_t MAX_OT_MEM; //0x0dc + + __IO uint32_t PREHEAT_CFG1; //0x0e0 ԤüĴ1 + __IO uint32_t PREHEAT_CFG2; //0x0e4 + __IO uint32_t PREHEAT_CFG3; //0x0e8 + __IO uint32_t PREHEAT_CR; //0x0ec + __IO uint32_t RSV3[4]; //0x0f0~0xfc + __IO uint32_t DOT_CFG; //0x100 + __IO uint32_t IBF_DATA; //0x104 + __IO uint32_t RSV4[6]; //0x108~11c + __IO uint32_t DOT_RST[8]; //0x120~13c + + __IO uint32_t YMC_THRSLD; //0x140 + __IO uint32_t YMC_OT; //0x144 + __IO uint32_t YMC_ZEN; //0x148 + __IO uint32_t YMC_MEM; //0x14c + __IO uint32_t ZEN_RDATA; //0x150 + __IO uint32_t MEM_RDATA; //0x154 + __IO uint32_t LUTSUM_CUR; //0x158 + __IO uint32_t LUTSUM_LATCH; //0x15c + __IO uint32_t OTSUM_CUR; //0x160 + __IO uint32_t OTSUM_LATCH; //0x164 + + __IO uint32_t RSV5[6]; //0x168~0x17c + __IO uint32_t DATA_BASE2[16]; //0x180~0x1bc + __IO uint32_t DATA_BASE3[16]; //0x1c0~0x1fc +}HEAD_TypeDef; + +typedef struct +{ + __IO uint32_t LUT_n[128]; //0x200~3fc +}LUT_TypeDef; + +typedef struct +{ + __IO uint32_t FLT0; // Զn˼Ĵ0 + __IO uint32_t FLT1; + __IO uint32_t FLT2; + __IO uint32_t MASK0; // ԶnμĴ0 + __IO uint32_t MASK1; + __IO uint32_t MASK2; +}UDF_TypeDef; + +typedef struct +{ + __IO uint32_t DOT_DATA; //0x400 xݼĴ + __IO uint32_t WRITE_MODE; //0x404 + __IO uint32_t BUFF_RDATA; //0x408 ֻBUFFxжĴ + __IO uint32_t RSV0; //0x40c + __IO uint32_t FIXCMP_EN[14]; //0x410~444 ̶ȽʹܼĴ + __IO uint32_t RSV1[2]; //0x448~44c + __IO uint32_t FIX_RSTSEL[107]; //0x450~5f8 + __IO uint32_t RSV2[21]; //0x5fc~0x64c + __IO uint32_t UDFCMP_EN; //0x650 ԶȽʹܼĴ + __IO uint32_t UDF_RSTSEL0; //0x654 + __IO uint32_t UDF_RSTSEL1; //0x658 + __IO uint32_t RSV3; //0x65c + UDF_TypeDef UDF_P[8]; //0x660 +}DOT_TypeDef; + +typedef struct +{ + __IO uint32_t PRTH_CFG1; //0xa00 // PRTHn_CFG1 ӡnüĴ1 + __IO uint32_t PRTH_CFG2; //0xa04 + __IO uint32_t PRTH_CFG3; //0xa08 + __IO uint32_t PRTH_CFG4; //0xa0c + __IO uint32_t PRTH_CFG5; //0xa10 + __IO uint32_t PRTH_CFG6; //0xa14 + __IO uint32_t RSV0[2]; //0xa18 a1c +}HCFG_TypeDef; + +#define PRT_HCFG_LEN 256 +typedef struct +{ + HCFG_TypeDef PRT_HCFG[PRT_HCFG_LEN] ; // ӡνã256 +}LCFG_TypeDef; + + +///*----------------------- STM_PWM registers ------------------------*/ + +typedef struct +{ + // all registers are valid for stmpwm12 + // 0~0X24 registers are valid for stmpwm3456 + __IO uint32_t CTL; //0x00, PWM Control Register + __IO uint32_t CSR; //0x04, PWM Current Status Register + __IO uint32_t MSK_ISR; //0x08, PWM Masked Interrupt Status Register + __IO uint32_t ICLR; //0x0C, PWM Interrupt Clear Register + __IO uint32_t IENR; //0x10, PWM Interrupt Enable Register + __IO uint32_t CCR; //0x14, PWM Clock Control Register + __IO uint32_t LWR; //0x18, PWM Low Level Width Register + __IO uint32_t OPR; //0x1C, PWM Original Period Register + __IO uint32_t CNT; //0x20, PWM Counter Register + __IO uint32_t UMK_ISR; //0x24, PWM Unmasked Interrupt Status Register + + __IO uint32_t FINE_PH_CTL; //0x28, PWM FINE PH Control Register + __IO uint32_t FINEA_OPR; //0x2C, PWM FINEA Original Period Register + //---------------------------------------------------------------------------------- + __IO uint32_t CNTX_CTL; //0x30, PWM Counter X Control Register + __IO uint32_t CNT1_TH; //0x34, PWM Counter 1 Threshold Register + __IO uint32_t CNT1; //0x38, PWM Counter 1 Register + __IO uint32_t CNT2_TH; //0x3C, PWM Counter 2 Threshold Register + __IO uint32_t CNT2; //0x40, PWM Counter 2 Register + __IO uint32_t CNT3_TH; //0x44, PWM Counter 3Threshold Register + __IO uint32_t CNT3; //0x48, PWM Counter 3 Register + //---------------------------------------------------------------------------------- + __IO uint32_t CNTY_CTL; //0x4C, PWM Counter Y Control Register + __IO uint32_t CNTA_TH; //0x50, PWM Counter A Threshold Register + __IO uint32_t CNTA; //0x54, PWM Counter A Register + __IO uint32_t CNTB_TH; //0x58, PWM Counter B Threshold Register + __IO uint32_t CNTB; //0x5C, PWM Counter B Register + __IO uint32_t CNTC_TH; //0x60, PWM Counter C Threshold Register + __IO uint32_t CNTC; //0x64, PWM Counter C Register + //---------------------------------------------------------------------------------- + __IO uint32_t PWM1; //0x68, PWM PWMx Register + __IO uint32_t PWM2; //0x6C + __IO uint32_t PWM3; //0x70 + __IO uint32_t PWM4; //0x74 + __IO uint32_t PWM5; //0x78 + __IO uint32_t PWM6; //0x7C + __IO uint32_t PWM7; //0x80 + __IO uint32_t PWM8; //0x84 + __IO uint32_t PWM9; //0x88 + __IO uint32_t PWM10; //0x8C + __IO uint32_t PWM11; //0x90 + __IO uint32_t PWM12; //0x94 + __IO uint32_t PWM13; //0x98 + __IO uint32_t PWM14; //0x9C + __IO uint32_t PWM15; //0xA0 + __IO uint32_t PWM16; //0xA4 +}STMPWM_TypeDef; + +///*----------------------- DCM_PWM registers ------------------------*/ + +typedef struct +{ + //----------------------------------------------AREA1 + __IO uint32_t REG_DCM_PWM_CCR; //0x00 + __IO uint32_t REG_DCM_PWM_CFG; //0x04 + __IO uint32_t REG_DCM_PWM_SR; //0x08 + //----------------------------------------------AREA2 + __IO uint32_t REG_ENC_IN_CFG; //0x0C + __IO uint32_t REG_ENC_CNT; //0x10 + __IO uint32_t REG_ENC_CNT_CMP; //0x14 + __IO uint32_t REG_ENC_FLT_CFG; //0x18 + __IO uint32_t REG_SNS1_FLT_CFG; //0x1C + __IO uint32_t REG_SNS2_FLT_CFG; //0x20 + __IO uint32_t REG_SNS3_FLT_CFG; //0x24 + __IO uint32_t REG_TIMA_SET_VAL; //0x28 + __IO uint32_t REG_TIMA_LATCH; //0x2C + __IO uint32_t REG_TIMB_SET_VAL; //0x30 + __IO uint32_t REG_TIMB_LATCH; //0x34 + //----------------------------------------------AREA3 + __IO uint32_t REG_PWM_CYC_S1_S3;//0x38 + __IO uint32_t REG_PWM_CYC_TL_S2;//0x3C + __IO uint32_t REG_PWM_NUM_S1; //0x40 + __IO uint32_t REG_PWM_NUM_S2; //0x44 + __IO uint32_t REG_PWM_NUM_S3; //0x48 + __IO uint32_t REG_PWM_DIR; //0x4C + __IO uint32_t REG_DCM_PWM_IENR; //0x50 + __IO uint32_t REG_DCM_PWM_UMK_ISR;//0x54 + __IO uint32_t REG_DCM_PWM_MSK_ISR;//0x58 + __IO uint32_t REG_DCM_PWM_ICLR; //0x5C + __IO uint32_t REG_DCM_PWM_CNT; //0x60 +}DCM_PWM_TypeDef; // + + + +typedef struct +{ + //----------------------------------------------AREA1 + __IO uint32_t REG_DCM_PWM_CCR; //0x00 + __IO uint32_t REG_DCM_PWM_CFG; //0x04 + __IO uint32_t REG_DCM_PWM_SR; //0x08 +// //----------------------------------------------AREA2 +// __IO uint32_t REG_ENC_IN_CFG; +// __IO uint32_t REG_ENC_CNT; +// __IO uint32_t REG_ENC_CNT_CMP; +// __IO uint32_t REG_ENC_FLT_CFG; +// __IO uint32_t REG_SNS1_FLT_CFG; +// __IO uint32_t REG_SNS2_FLT_CFG; +// __IO uint32_t REG_SNS3_FLT_CFG; +// __IO uint32_t REG_TIMA_SET_VAL; +// __IO uint32_t REG_TIMA_LATCH; +// __IO uint32_t REG_TIMB_SET_VAL; +// __IO uint32_t REG_TIMB_LATCH; + //----------------------------------------------AREA3 + __IO uint32_t REG_PWM_CYC_S1_S3;//0x0C + __IO uint32_t REG_PWM_CYC_TL_S2;//0x10 + __IO uint32_t REG_PWM_NUM_S1; //0x14 + __IO uint32_t REG_PWM_NUM_S2; //0x18 + __IO uint32_t REG_PWM_NUM_S3; //0x1C + __IO uint32_t REG_PWM_DIR; //0x20 + __IO uint32_t REG_DCM_PWM_IENR; //0x24 + __IO uint32_t REG_DCM_PWM_UMK_ISR;//0x28 + __IO uint32_t REG_DCM_PWM_MSK_ISR;//0x2C + __IO uint32_t REG_DCM_PWM_ICLR; //0x30 + __IO uint32_t REG_DCM_PWM_CNT; //0x34 +}DCM_PWM_SE_TypeDef; // + + +// ԭĴṹ3ٴظ + +typedef struct +{ + __IO uint32_t REG_DCM_PWM_CCR; + __IO uint32_t REG_DCM_PWM_CFG; + __IO uint32_t REG_DCM_PWM_SR; +}DCM_PWM_AREA1_TypeDef; + + +typedef struct +{ + __IO uint32_t REG_ENC_IN_CFG; + __IO uint32_t REG_ENC_CNT; + __IO uint32_t REG_ENC_CNT_CMP; + __IO uint32_t REG_ENC_FLT_CFG; + __IO uint32_t REG_SNS1_FLT_CFG; + __IO uint32_t REG_SNS2_FLT_CFG; + __IO uint32_t REG_SNS3_FLT_CFG; + __IO uint32_t REG_TIMA_SET_VAL; + __IO uint32_t REG_TIMA_LATCH; + __IO uint32_t REG_TIMB_SET_VAL; + __IO uint32_t REG_TIMB_LATCH; +}DCM_PWM_AREA2_TypeDef; + + +typedef struct +{ + __IO uint32_t REG_PWM_CYC_S1_S3; + __IO uint32_t REG_PWM_CYC_TL_S2; + __IO uint32_t REG_PWM_NUM_S1; + __IO uint32_t REG_PWM_NUM_S2; + __IO uint32_t REG_PWM_NUM_S3; + __IO uint32_t REG_PWM_DIR; + __IO uint32_t REG_DCM_PWM_IENR; + __IO uint32_t REG_DCM_PWM_UMK_ISR; + __IO uint32_t REG_DCM_PWM_MSK_ISR; + __IO uint32_t REG_DCM_PWM_ICLR; + __IO uint32_t REG_DCM_PWM_CNT; +}DCM_PWM_AREA3_TypeDef; + + +///*----------------------- LPT registers ------------------------*/ + +typedef struct +{ + __IO uint32_t PARIF_MMR; //0x00 Parallel-Interface Master Mode Register + __IO uint32_t PARIF_DINR; //0x04 Parallel-Interface Data Input Register + __IO uint32_t PARIF_HMR; //0x08 Parallel-Interface Handshake Mode Register + __IO uint32_t RES; //0x0c + __IO uint32_t PARIF_TBAR; //0x10 Parallel-Interface Trigger Busy/Ack# Register + __IO uint32_t PARIF_CINR; //0x14 Parallel-Interface Control Input Register + __IO uint32_t PARIF_COUTR; //0x18 Parallel-Interface Control Output Register + __IO uint32_t PARIF_FCR; //0x1c Parallel-Interface Filter Configuration Register + __IO uint32_t PARIF_DATR; //0x20 Parallel-Interface Data Transparent Register + __IO uint32_t PARIF_NIBDR; //0x24 Parallel-Interface Nibble Data Register + __IO uint32_t PARIF_HMR2; //0x28 Parallel-Interface Handshake Mode Register2 + __IO uint32_t PARIF_ALR; //0x2c Parallel-Interface Ack# Load Register + __IO uint32_t PARIF_AWR; //0x30 Parallel-Interface Ack# Width Register + __IO uint32_t PARIF_BWR; //0x34 Parallel-Interface Busy Width Register + __IO uint32_t PARIF_ISR; //0x38 Parallel-Interface Interrupt Status Register + __IO uint32_t PARIF_IDBR; //0x3c Parallel-Interface ID Data Register + __IO uint32_t PARIF_RDBR; //0x40 Parallel-Interface Reverse Data Register + __IO uint32_t PARIF_NCR; //0x44 Parallel-Interface Nibble Mode Configure Register + __IO uint32_t PARIF_EXDBR; //0x48 Parallel-Interface Extra Data Register + __IO uint32_t PARIF_DTR; //0x4c Parallel-Interface Delay Timer1 Register + __IO uint32_t PARIF_DTR2; //0x50 Parallel-Interface Delay Timer2 Register + __IO uint32_t PARIF_RSTR; //0x54 Parallel-Interface Reset Register + __IO uint32_t PARIF_FRQR; //0x58 Parallel-Interface Data Request Enable Register + __IO uint32_t PARIF_FDR; //0x5c Parallel-Interface Data FIFO Deep Register + __IO uint32_t PARIF_TOR; //0x60 Parallel-Interface Data Request Timer Out Register + __IO uint32_t PARIF_DCNTR; //0x64 Parallel-Interface Data Counter Register + __IO uint32_t PARIF_NIBDR2; //0x68 Parallel-Interface Nibble Data Register2 + __IO uint32_t PARIF_EXR; //0x6c Parallel-Interface Extra Respond Register + __IO uint32_t PARIF_FCR2; //0x70 Parallel-Interface Filter Configuration Register2 + __IO uint32_t PARIF_PCKFR; //0x74 Parallel-Interface PCLK Frequency Register + __IO uint32_t PARIF_CK19DR; //0x78 Parallel-Interface CLK19 Divider Register + __IO uint32_t PARIF_FCR3; //0x7c Parallel-Interface Filter Configuration Register3 + __IO uint32_t PARIF_FCR4; //0x80 Parallel-Interface Filter Configuration Register4 + __IO uint32_t PARIF_DTR3; //0x84 Parallel-Interface Delay Timer3 Register +}LPT_TypeDef; + + +/*------------------------- USB OTG defined -------------------------*/ + +#define USB_OTG_GLOBAL_BASE 0x0000UL +#define USB_OTG_DEVICE_BASE 0x0800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL +#define USB_OTG_EP_REG_SIZE 0x0020UL +#define USB_OTG_HOST_BASE 0x0400UL +#define USB_OTG_HOST_PORT_BASE 0x0440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL +#define USB_OTG_PCGCCTL_BASE 0x0E00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/*------------------------- Peripheral declatation -------------------------*/ + + +#define SYSCFG ( (SYSCFG_TypeDef *)SYSCFG_BASE_ADDR ) +#define RCC ( (RCC_TypeDef *)RCC_BASE_ADDR ) +#define GPIOA ( (GPIO_TypeDef *)GPIOA_BASE_ADDR ) +#define GPIOB ( (GPIO_TypeDef *)GPIOB_BASE_ADDR ) +#define GPIOC ( (GPIO_TypeDef *)GPIOC_BASE_ADDR ) +#define GPIOD ( (GPIO_TypeDef *)GPIOD_BASE_ADDR ) +#define GPIOE ( (GPIO_TypeDef *)GPIOE_BASE_ADDR ) +#define GPIOF ( (GPIO_TypeDef *)GPIOF_BASE_ADDR ) +#define GPIOG ( (GPIO_TypeDef *)GPIOG_BASE_ADDR ) +#define GPIOH ( (GPIO_TypeDef *)GPIOH_BASE_ADDR ) +#define GPIOI ( (GPIO_TypeDef *)GPIOI_BASE_ADDR ) +#define GPIOJ ( (GPIO_TypeDef *)GPIOJ_BASE_ADDR ) +#define GPIOK ( (GPIO_TypeDef *)GPIOK_BASE_ADDR ) +#define GPIOL ( (GPIO_TypeDef *)GPIOL_BASE_ADDR ) +#define GPIOM ( (GPIO_TypeDef *)GPIOM_BASE_ADDR ) +#define GPION ( (GPIO_TypeDef *)GPION_BASE_ADDR ) +#define GPIOO ( (GPIO_TypeDef *)GPIOO_BASE_ADDR ) +#define GPIOP ( (GPIO_TypeDef *)GPIOP_BASE_ADDR ) +#define GPIOQ ( (GPIO_TypeDef *)GPIOQ_BASE_ADDR ) +#define EXTI ( (EXTI_TypeDef *)EXTI_BASE_ADDR ) +#define DMA1 ( (DMA_TypeDef *)DMA1_BASE_ADDR ) +#define DMA1_Channel0 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL0_BASE_ADDR ) +#define DMA1_Channel1 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL1_BASE_ADDR ) +#define DMA1_Channel2 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL2_BASE_ADDR ) +#define DMA1_Channel3 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL3_BASE_ADDR ) +#define DMA1_Channel4 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL4_BASE_ADDR ) +#define DMA1_Channel5 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL5_BASE_ADDR ) +#define DMA1_Channel6 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL6_BASE_ADDR ) +#define DMA1_Channel7 ( (DMA_Channel_TypeDef *)DMA1_CHANNEL7_BASE_ADDR ) +#define DMA2 ( (DMA_TypeDef *)DMA2_BASE_ADDR ) +#define DMA2_Channel0 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL0_BASE_ADDR ) +#define DMA2_Channel1 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL1_BASE_ADDR ) +#define DMA2_Channel2 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL2_BASE_ADDR ) +#define DMA2_Channel3 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL3_BASE_ADDR ) +#define DMA2_Channel4 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL4_BASE_ADDR ) +#define DMA2_Channel5 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL5_BASE_ADDR ) +#define DMA2_Channel6 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL6_BASE_ADDR ) +#define DMA2_Channel7 ( (DMA_Channel_TypeDef *)DMA2_CHANNEL7_BASE_ADDR ) +#define TIM1 ( (TIM_TypeDef *)TIM1_BASE_ADDR ) +#define TIM2 ( (TIM_TypeDef *)TIM2_BASE_ADDR ) +#define TIM3 ( (TIM_TypeDef *)TIM3_BASE_ADDR ) +#define TIM4 ( (TIM_TypeDef *)TIM4_BASE_ADDR ) +#define TIM5 ( (TIM_TypeDef *)TIM5_BASE_ADDR ) +#define TIM6 ( (TIM_TypeDef *)TIM6_BASE_ADDR ) +#define TIM7 ( (TIM_TypeDef *)TIM7_BASE_ADDR ) +#define TIM8 ( (TIM_TypeDef *)TIM8_BASE_ADDR ) +#define TIM9 ( (TIM_TypeDef *)TIM9_BASE_ADDR ) +#define TIM10 ( (TIM_TypeDef *)TIM10_BASE_ADDR ) +#define TIM11 ( (TIM_TypeDef *)TIM11_BASE_ADDR ) +#define TIM12 ( (TIM_TypeDef *)TIM12_BASE_ADDR ) +#define TIM13 ( (TIM_TypeDef *)TIM13_BASE_ADDR ) +#define TIM14 ( (TIM_TypeDef *)TIM14_BASE_ADDR ) +#define TIM15 ( (TIM_TypeDef *)TIM15_BASE_ADDR ) +#define TIM16 ( (TIM_TypeDef *)TIM16_BASE_ADDR ) +#define TIM17 ( (TIM_TypeDef *)TIM17_BASE_ADDR ) +#define TIM18 ( (TIM_TypeDef *)TIM18_BASE_ADDR ) +#define TIM19 ( (TIM_TypeDef *)TIM19_BASE_ADDR ) +#define TIM20 ( (TIM_TypeDef *)TIM20_BASE_ADDR ) +#define TIM21 ( (TIM_TypeDef *)TIM21_BASE_ADDR ) +#define TIM22 ( (TIM_TypeDef *)TIM22_BASE_ADDR ) +#define TIM23 ( (TIM_TypeDef *)TIM23_BASE_ADDR ) +#define TIM24 ( (TIM_TypeDef *)TIM24_BASE_ADDR ) +#define TIM25 ( (TIM_TypeDef *)TIM25_BASE_ADDR ) +#define TIM26 ( (TIM_64BIT_TypeDef *)TIM26_BASE_ADDR ) +#define RTC ( (RTC_TypeDef *)RTC_BASE_ADDR ) +#define PMU ( (PMU_TypeDef *)PMU_BASE_ADDR ) +#define WDT ( (WDT_TypeDef *)WDT_BASE_ADDR ) +#define IWDT ( (IWDT_TypeDef *)IWDT_BASE_ADDR ) +#define I2S1 ( (I2S_TypeDef *)I2S1_BASE_ADDR ) +#define I2S2 ( (I2S_TypeDef *)I2S2_BASE_ADDR ) +#define I2S3 ( (I2S_TypeDef *)I2S3_BASE_ADDR ) +#define I2C1 ( (I2C_TypeDef *)I2C1_BASE_ADDR ) +#define I2C2 ( (I2C_TypeDef *)I2C2_BASE_ADDR ) +#define I2C3 ( (I2C_TypeDef *)I2C3_BASE_ADDR ) +#define I2C4 ( (I2C_TypeDef *)I2C4_BASE_ADDR ) +#define USART1 ( (USART_TypeDef *)USART1_BASE_ADDR ) +#define USART2 ( (USART_TypeDef *)USART2_BASE_ADDR ) +#define USART3 ( (USART_TypeDef *)USART3_BASE_ADDR ) +#define USART4 ( (USART_TypeDef *)USART4_BASE_ADDR ) +#define USART5 ( (USART_TypeDef *)USART5_BASE_ADDR ) +#define USART6 ( (USART_TypeDef *)USART6_BASE_ADDR ) +#define USART7 ( (USART_TypeDef *)USART7_BASE_ADDR ) +#define USART8 ( (USART_TypeDef *)USART8_BASE_ADDR ) +#define USART9 ( (USART_TypeDef *)USART9_BASE_ADDR ) +#define USART10 ( (USART_TypeDef *)USART10_BASE_ADDR ) +#define FDCAN1 ( (FDCAN_GlobalTypeDef *)FDCAN1_BASE_ADDR ) +#define FDCAN2 ( (FDCAN_GlobalTypeDef *)FDCAN2_BASE_ADDR ) +#define FDCAN3 ( (FDCAN_GlobalTypeDef *)FDCAN3_BASE_ADDR ) +#define LPTIM1 ( (LPTIM_TypeDef *)LPTIM1_BASE_ADDR ) +#define LPTIM2 ( (LPTIM_TypeDef *)LPTIM2_BASE_ADDR ) +#define LPTIM3 ( (LPTIM_TypeDef *)LPTIM3_BASE_ADDR ) +#define LPTIM4 ( (LPTIM_TypeDef *)LPTIM4_BASE_ADDR ) +#define LPTIM5 ( (LPTIM_TypeDef *)LPTIM5_BASE_ADDR ) +#define LPTIM6 ( (LPTIM_TypeDef *)LPTIM6_BASE_ADDR ) +#define LPUART1 ( (LPUART_TypeDef *)LPUART1_BASE_ADDR ) +#define EFUSE1 ( (EFUSE_TypeDef *)EFUSE1_BASE_ADDR ) +#define EFUSE2 ( (EFUSE_TypeDef *)EFUSE2_BASE_ADDR ) +#define COMP1 ( (COMP_TypeDef *)COMP1_BASE_ADDR ) +#define TKEY ( (TKEY_TypeDef *)TKEY_BASE_ADDR ) +#define LTDC ( (LTDC_TypeDef *)LTDC_BASE_ADDR ) +#define MDAC ( (MDAC_TypeDef *)MDAC_BASE_ADDR ) + + +#define CRC ( (CRC_TypeDef *)CRC_BASE_ADDR ) +#define ETH ( (ETH_TypeDef *)ETHMAC_BASE_ADDR ) +#define DMA2D ( (DMA2D_TypeDef *)DMA2D_BASE_ADDR ) +#define SPI1 ( (SPI_TypeDef *)SPI1_BASE_ADDR ) +#define SPI2 ( (SPI_TypeDef *)SPI2_BASE_ADDR ) +#define SPI3 ( (SPI_TypeDef *)SPI3_BASE_ADDR ) +#define SPI4 ( (SPI_TypeDef *)SPI4_BASE_ADDR ) +#define SPI5 ( (SPI_TypeDef *)SPI5_BASE_ADDR ) +#define SPI6 ( (SPI_TypeDef *)SPI6_BASE_ADDR ) +#define SPI7 ( (SPI_TypeDef *)SPI7_BASE_ADDR ) +#define SPI8 ( (SPI_TypeDef *)SPI8_BASE_ADDR ) +#define USB_OTG_HS1 ( (USB_OTG_GlobalTypeDef *) USBOTG_HS1_BASE_ADDR ) +#define USB_OTG_HS2 ( (USB_OTG_GlobalTypeDef *) USBOTG_HS2_BASE_ADDR ) +#define USBOTG_PHY1 ( (USBOTG_PHY_TypeDef *)USBOTG_PHY1_BASE_ADDR ) +#define USBOTG_PHY2 ( (USBOTG_PHY_TypeDef *)USBOTG_PHY2_BASE_ADDR ) +#define ADC1 ( (ADC_TypeDef *)ADC1_BASE_ADDR ) +#define ADC2 ( (ADC_TypeDef *)ADC2_BASE_ADDR ) +#define ADC12_COMMON ( (ADC_Common_TypeDef *)(ADC1_BASE_ADDR + 0x0300UL) ) +#define ADC3 ( (ADC_TypeDef *)ADC3_BASE_ADDR ) +#define ADC3_COMMON ( (ADC_Common_TypeDef *)(ADC3_BASE_ADDR + 0x0300UL) ) +#define DAC1 ( (DAC_TypeDef *)DAC1_BASE_ADDR ) +#define DAC2 ( (DAC_TypeDef *)DAC2_BASE_ADDR ) +#define DCMI ( (DCMI_TypeDef *)DCMI_BASE_ADDR ) +#define AES ( (AES_TypeDef *)AES_BASE_ADDR ) +#define CORDIC ( (CORDIC_TypeDef *)CORDIC_BASE_ADDR ) +#define HRNG ( (HRNG_TypeDef *)HRNG_BASE_ADDR ) +#define HASH ( (HASH_TypeDef *)HASH_BASE_ADDR ) + +#define FMC_NORSRAM ( (FMC_NORSRAM_TypeDef *)FMC_REG_BASE_ADDR ) +#define FMC_SDRAM ( (FMC_SDRAM_TypeDef *)(FMC_REG_BASE_ADDR + 0x0140UL) ) +#define FMC_NAND ( (FMC_NAND_TypeDef *)(FMC_REG_BASE_ADDR + 0x0200UL) ) +#define OSPI1 ( (OSPI_TypeDef *) OSPI1_BASE_ADDR ) +#define OSPI2 ( (OSPI_TypeDef *) OSPI2_BASE_ADDR ) + +#define USB1_DLYB ( (DLYB_TypeDef *) USB1_DLYB_REG_BASE_ADDR ) +#define ETH_DLYB ( (DLYB_TypeDef *) ETH_DLYB_REG_BASE_ADDR ) +#define SDMMC_DLYBS ( (DLYB_TypeDef *) SDIO_DLYBS_REG_BASE_ADDR ) +#define SDMMC_DLYBD ( (DLYB_TypeDef *) SDIO_DLYBD_REG_BASE_ADDR ) +#define OSPI1_DLYB ( (DLYB_TypeDef *) OSPI1_DLYB_REG_BASE_ADDR ) +#define OSPI2_DLYB ( (DLYB_TypeDef *) OSPI2_DLYB_REG_BASE_ADDR ) +#define SDMMC_SAMPLE_DLYB ( (DLYB_TypeDef *)SDIO_DLYBS_REG_BASE_ADDR ) +#define SDMMC_DRIVE_DLYB ( (DLYB_TypeDef *)SDIO_DLYBD_REG_BASE_ADDR ) +#define AES_SPI1 ( (AES_SPI_TypeDef *)AES_SPI1_BASE_ADDR ) +#define SDMMC ( (SDMMC_TypeDef *)SDIO_BASE_ADDR ) +#define USBOTG1_PHYC ( (USB_HS_PHYC_GlobalTypeDef *)USBOTG1_PHYC_BASE_ADDR ) +#define USBOTG2_PHYC ( (USB_HS_PHYC_GlobalTypeDef *)USBOTG2_PHYC_BASE_ADDR ) + +///*------------------------- printer Peripheral declatation -------------------------*/ +#define NDL ( (NDL_TypeDef *)NDL_BASE_ADDR ) + +#define HEAD ( (HEAD_TypeDef *)HEAD_BASE_ADDR) +#define LUT ( (LUT_TypeDef *)LUT_BASE_ADDR) +#define DOT1 ( (DOT_TypeDef *)DOT1_BASE_ADDR) +#define DOT2 ( (DOT_TypeDef *)DOT2_BASE_ADDR) +#define DOT3 ( (DOT_TypeDef *)DOT3_BASE_ADDR) +#define LCFG ( (LCFG_TypeDef *)LCFG_BASE_ADDR) + +#define STMPWM1 ( (STMPWM_TypeDef *)STM1_PWM_BASE_ADDR ) +#define STMPWM2 ( (STMPWM_TypeDef *)STM2_PWM_BASE_ADDR ) +#define STMPWM3 ( (STMPWM_TypeDef *)STM3_PWM_BASE_ADDR ) // 򻯰棬ֻ0x00~0x24Ĵ +#define STMPWM4 ( (STMPWM_TypeDef *)STM4_PWM_BASE_ADDR ) // 򻯰棬ֻ0x00~0x24Ĵ +#define STMPWM5 ( (STMPWM_TypeDef *)STM5_PWM_BASE_ADDR ) // 򻯰棬ֻ0x00~0x24Ĵ +#define STMPWM6 ( (STMPWM_TypeDef *)STM6_PWM_BASE_ADDR ) // 򻯰棬ֻ0x00~0x24Ĵ + +#define DCMPWM1 ( (DCM_PWM_TypeDef *)DCM1_PWM_BASE_ADDR ) +#define DCMPWM2 ( (DCM_PWM_TypeDef *)DCM2_PWM_BASE_ADDR ) +#define DCMPWM3 ( (DCM_PWM_TypeDef *)DCM3_PWM_BASE_ADDR ) +#define DCMPWM4 ( (DCM_PWM_TypeDef *)DCM4_PWM_BASE_ADDR ) +#define DCMPWM5 ( (DCM_PWM_SE_TypeDef *)DCM5_PWM_BASE_ADDR ) +#define DCMPWM6 ( (DCM_PWM_SE_TypeDef *)DCM6_PWM_BASE_ADDR ) + +#define DCMPWM1_AREA1 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM1_AREA1_ADDR) +#define DCMPWM2_AREA1 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM2_AREA1_ADDR) +#define DCMPWM3_AREA1 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM3_AREA1_ADDR) +#define DCMPWM4_AREA1 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM4_AREA1_ADDR) +#define DCMPWM5_AREA1 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM5_AREA1_ADDR) +#define DCMPWM6_AREA1 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM6_AREA1_ADDR) + +#define DCMPWM1_AREA2 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM1_AREA2_ADDR) +#define DCMPWM2_AREA2 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM2_AREA2_ADDR) +#define DCMPWM3_AREA2 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM3_AREA2_ADDR) +#define DCMPWM4_AREA2 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM4_AREA2_ADDR) + +#define DCMPWM1_AREA3 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM1_AREA3_ADDR) +#define DCMPWM2_AREA3 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM2_AREA3_ADDR) +#define DCMPWM3_AREA3 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM3_AREA3_ADDR) +#define DCMPWM4_AREA3 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM4_AREA3_ADDR) +#define DCMPWM5_AREA3 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM5_AREA3_ADDR) +#define DCMPWM6_AREA3 ( (DCM_PWM_AREA1_TypeDef *)DCMPWM6_AREA3_ADDR) +#define LPT ( (LPT_TypeDef *)LPT_BASE_ADDR ) + +/*------------------ Peripheral_Registers_Bits_Definition ------------------*/ + +/*************** Bits definition for SYSCFG_SYSCR **********************/ + +#define SYSCFG_SYSCR_ETHMAC_RX_DLYSEL_Pos ( 20U ) +#define SYSCFG_SYSCR_ETHMAC_RX_DLYSEL_Msk ( 0x1UL << SYSCFG_SYSCR_ETHMAC_RX_DLYSEL_Pos ) +#define SYSCFG_SYSCR_ETHMAC_RX_DLYSEL ( SYSCFG_SYSCR_ETHMAC_RX_DLYSEL_Msk ) + +#define SYSCFG_SYSCR_BOOT_PUN_Pos ( 19U ) +#define SYSCFG_SYSCR_BOOT_PUN_Msk ( 0x1UL << SYSCFG_SYSCR_BOOT_PUN_Pos ) +#define SYSCFG_SYSCR_BOOT_PUN ( SYSCFG_SYSCR_BOOT_PUN_Msk ) + +#define SYSCFG_SYSCR_IR_MODE_Pos ( 17U ) +#define SYSCFG_SYSCR_IR_MODE_Msk ( 0x3UL << SYSCFG_SYSCR_IR_MODE_Pos ) +#define SYSCFG_SYSCR_IR_MODE ( SYSCFG_SYSCR_IR_MODE_Msk ) +#define SYSCFG_SYSCR_IR_MODE_0 ( 0x1UL << SYSCFG_SYSCR_IR_MODE_Pos ) +#define SYSCFG_SYSCR_IR_MODE_1 ( 0x2UL << SYSCFG_SYSCR_IR_MODE_Pos ) + +#define SYSCFG_SYSCR_IR_POL_Pos ( 16U ) +#define SYSCFG_SYSCR_IR_POL_Msk ( 0x1UL << SYSCFG_SYSCR_IR_POL_Pos ) +#define SYSCFG_SYSCR_IR_POL ( SYSCFG_SYSCR_IR_POL_Msk ) + +#define SYSCFG_SYSCR_EPIS_Pos ( 13U ) +#define SYSCFG_SYSCR_EPIS_Msk ( 0x7UL << SYSCFG_SYSCR_EPIS_Pos ) +#define SYSCFG_SYSCR_EPIS ( SYSCFG_SYSCR_EPIS_Msk ) +#define SYSCFG_SYSCR_EPIS_0 ( 0x1UL << SYSCFG_SYSCR_EPIS_Pos ) +#define SYSCFG_SYSCR_EPIS_1 ( 0x2UL << SYSCFG_SYSCR_EPIS_Pos ) +#define SYSCFG_SYSCR_EPIS_2 ( 0x4UL << SYSCFG_SYSCR_EPIS_Pos ) + +#define SYSCFG_SYSCR_ETHMAC_TX_CLKGE_Pos ( 12U ) +#define SYSCFG_SYSCR_ETHMAC_TX_CLKGE_Msk ( 0x1UL << SYSCFG_SYSCR_ETHMAC_TX_CLKGE_Pos ) +#define SYSCFG_SYSCR_ETHMAC_TX_CLKGE ( SYSCFG_SYSCR_ETHMAC_TX_CLKGE_Msk ) + +#define SYSCFG_SYSCR_BKPSRAM_LOCK_Pos ( 11U ) +#define SYSCFG_SYSCR_BKPSRAM_LOCK_Msk ( 0x1UL << SYSCFG_SYSCR_BKPSRAM_LOCK_Pos ) +#define SYSCFG_SYSCR_BKPSRAM_LOCK ( SYSCFG_SYSCR_BKPSRAM_LOCK_Msk ) + +#define SYSCFG_SYSCR_SRAM3_LOCK_Pos ( 10U ) +#define SYSCFG_SYSCR_SRAM3_LOCK_Msk ( 0x1UL << SYSCFG_SYSCR_SRAM3_LOCK_Pos ) +#define SYSCFG_SYSCR_SRAM3_LOCK ( SYSCFG_SYSCR_SRAM3_LOCK_Msk ) + +#define SYSCFG_SYSCR_SRAM1_LOCK_Pos ( 9U ) +#define SYSCFG_SYSCR_SRAM1_LOCK_Msk ( 0x1UL << SYSCFG_SYSCR_SRAM1_LOCK_Pos ) +#define SYSCFG_SYSCR_SRAM1_LOCK ( SYSCFG_SYSCR_SRAM1_LOCK_Msk ) + +#define SYSCFG_SYSCR_SDRAM_IO_SWP_Pos ( 7U ) +#define SYSCFG_SYSCR_SDRAM_IO_SWP_Msk ( 0x1UL << SYSCFG_SYSCR_SDRAM_IO_SWP_Pos ) +#define SYSCFG_SYSCR_SDRAM_IO_SWP ( SYSCFG_SYSCR_SDRAM_IO_SWP_Msk ) + +#define SYSCFG_SYSCR_FMC_SWP_Pos ( 4U ) +#define SYSCFG_SYSCR_FMC_SWP_Msk ( 0x3UL << SYSCFG_SYSCR_FMC_SWP_Pos ) +#define SYSCFG_SYSCR_FMC_SWP ( SYSCFG_SYSCR_FMC_SWP_Msk ) +#define SYSCFG_SYSCR_FMC_SWP_0 ( 0x1UL << SYSCFG_SYSCR_FMC_SWP_Pos ) +#define SYSCFG_SYSCR_FMC_SWP_1 ( 0x2UL << SYSCFG_SYSCR_FMC_SWP_Pos ) + +#define SYSCFG_SYSCR_LVD_LOCK_Pos ( 2U ) +#define SYSCFG_SYSCR_LVD_LOCK_Msk ( 0x1UL << SYSCFG_SYSCR_LVD_LOCK_Pos ) +#define SYSCFG_SYSCR_LVD_LOCK ( SYSCFG_SYSCR_LVD_LOCK_Msk ) + +#define SYSCFG_SYSCR_LOCKUP_LOCK_Pos ( 0U ) +#define SYSCFG_SYSCR_LOCKUP_LOCK_Msk ( 0x1UL << SYSCFG_SYSCR_LOCKUP_LOCK_Pos ) +#define SYSCFG_SYSCR_LOCKUP_LOCK ( SYSCFG_SYSCR_LOCKUP_LOCK_Msk ) + + +/*************** Bits definition for SYSCFG_WMR **********************/ + +#define SYSCFG_WMR_BOOTDEVICE_Pos ( 8U ) +#define SYSCFG_WMR_BOOTDEVICE_Msk ( 0x3UL << SYSCFG_WMR_RTC_READY_Pos ) +#define SYSCFG_WMR_BOOTDEVICE ( SYSCFG_WMR_RTC_READY_Msk ) + +#define SYSCFG_WMR_RTCREADY_Pos ( 6U ) +#define SYSCFG_WMR_RTCREADY_Msk ( 0x1UL << SYSCFG_WMR_RTCREADY_Pos ) +#define SYSCFG_WMR_RTCREADY ( SYSCFG_WMR_RTCREADY_Msk ) + +#define SYSCFG_WMR_BOOTMODE_Pos ( 3U ) +#define SYSCFG_WMR_BOOTMODE_Msk ( 0x1UL << SYSCFG_WMR_BOOTMODE_Pos ) +#define SYSCFG_WMR_BOOTMODE ( SYSCFG_WMR_BOOTMODE_Msk ) + + +/*************** Bits definition for SYSCFG_VER **********************/ + +#define SYSCFG_VER_VERSION_Pos ( 0U ) +#define SYSCFG_VER_VERSION_Msk ( 0xffffffffUL << SYSCFG_VER_VERSION_Pos ) +#define SYSCFG_VER_VERSION ( SYSCFG_VER_VERSION_Msk ) + + +/*************** Bits definition for SYSCFG_PHYCFG **********************/ + +#define SYSCFG_PHYCFG_USB1_ULPI_DLYSEL_Pos ( 8U ) +#define SYSCFG_PHYCFG_USB1_ULPI_DLYSEL_Msk ( 0x1UL << SYSCFG_PHYCFG_USB1_ULPI_DLYSEL_Pos ) +#define SYSCFG_PHYCFG_USB1_ULPI_DLYSEL ( SYSCFG_PHYCFG_USB1_ULPI_DLYSEL_Msk ) + +#define SYSCFG_PHYCFG_USB2_PHY_RSTN_Pos ( 4U ) +#define SYSCFG_PHYCFG_USB2_PHY_RSTN_Msk ( 0x1UL << SYSCFG_PHYCFG_USB2_PHY_RSTN_Pos ) +#define SYSCFG_PHYCFG_USB2_PHY_RSTN ( SYSCFG_PHYCFG_USB2_PHY_RSTN_Msk ) + +#define SYSCFG_PHYCFG_USB1_PHY_RSTN_Pos ( 0U ) +#define SYSCFG_PHYCFG_USB1_PHY_RSTN_Msk ( 0x1UL << SYSCFG_PHYCFG_USB1_PHY_RSTN_Pos ) +#define SYSCFG_PHYCFG_USB1_PHY_RSTN ( SYSCFG_PHYCFG_USB1_PHY_RSTN_Msk ) + +/*************** Bits definition for SYSCFG_RAMECCIR **********************/ + +#define SYSCFG_RAMECCIR_BKPSRAM_DED_IE_Pos ( 9U ) +#define SYSCFG_RAMECCIR_BKPSRAM_DED_IE_Msk ( 0x1UL << SYSCFG_RAMECCIR_BKPSRAM_DED_IE_Pos ) +#define SYSCFG_RAMECCIR_BKPSRAM_DED_IE ( SYSCFG_RAMECCIR_BKPSRAM_DED_IE_Msk ) + +#define SYSCFG_RAMECCIR_BKPSRAM_SEC_IE_Pos ( 8U ) +#define SYSCFG_RAMECCIR_BKPSRAM_SEC_IE_Msk ( 0x1UL << SYSCFG_RAMECCIR_BKPSRAM_SEC_IE_Pos ) +#define SYSCFG_RAMECCIR_BKPSRAM_SEC_IE ( SYSCFG_RAMECCIR_BKPSRAM_SEC_IE_Msk ) + +#define SYSCFG_RAMECCIR_SRAM3_DED_IE_Pos ( 5U ) +#define SYSCFG_RAMECCIR_SRAM3_DED_IE_Msk ( 0x1UL << SYSCFG_RAMECCIR_SRAM3_DED_IE_Pos ) +#define SYSCFG_RAMECCIR_SRAM3_DED_IE ( SYSCFG_RAMECCIR_SRAM3_DED_IE_Msk ) + +#define SYSCFG_RAMECCIR_SRAM3_SEC_IE_Pos ( 4U ) +#define SYSCFG_RAMECCIR_SRAM3_SEC_IE_Msk ( 0x1UL << SYSCFG_RAMECCIR_SRAM3_SEC_IE_Pos ) +#define SYSCFG_RAMECCIR_SRAM3_SEC_IE ( SYSCFG_RAMECCIR_SRAM3_SEC_IE_Msk ) + +#define SYSCFG_RAMECCIR_SRAM1_DED_IE_Pos ( 1U ) +#define SYSCFG_RAMECCIR_SRAM1_DED_IE_Msk ( 0x1UL << SYSCFG_RAMECCIR_SRAM1_DED_IE_Pos ) +#define SYSCFG_RAMECCIR_SRAM1_DED_IE ( SYSCFG_RAMECCIR_SRAM1_DED_IE_Msk ) + +#define SYSCFG_RAMECCIR_SRAM1_SEC_IE_Pos ( 0U ) +#define SYSCFG_RAMECCIR_SRAM1_SEC_IE_Msk ( 0x1UL << SYSCFG_RAMECCIR_SRAM1_SEC_IE_Pos ) +#define SYSCFG_RAMECCIR_SRAM1_SEC_IE ( SYSCFG_RAMECCIR_SRAM1_SEC_IE_Msk ) + + +/*************** Bits definition for SYSCFG_RAMECCSR **********************/ + +#define SYSCFG_RAMECCSR_BKPSRAM_DED_IF_Pos ( 9U ) +#define SYSCFG_RAMECCSR_BKPSRAM_DED_IF_Msk ( 0x1UL << SYSCFG_RAMECCSR_BKPSRAM_DED_IF_Pos ) +#define SYSCFG_RAMECCSR_BKPSRAM_DED_IF ( SYSCFG_RAMECCSR_BKPSRAM_DED_IF_Msk ) + +#define SYSCFG_RAMECCSR_BKPSRAM_SEC_IF_Pos ( 8U ) +#define SYSCFG_RAMECCSR_BKPSRAM_SEC_IF_Msk ( 0x1UL << SYSCFG_RAMECCSR_BKPSRAM_SEC_IF_Pos ) +#define SYSCFG_RAMECCSR_BKPSRAM_SEC_IF ( SYSCFG_RAMECCSR_BKPSRAM_SEC_IF_Msk ) + +#define SYSCFG_RAMECCSR_SRAM3_DED_IF_Pos ( 5U ) +#define SYSCFG_RAMECCSR_SRAM3_DED_IF_Msk ( 0x1UL << SYSCFG_RAMECCSR_SRAM3_DED_IF_Pos ) +#define SYSCFG_RAMECCSR_SRAM3_DED_IF ( SYSCFG_RAMECCSR_SRAM3_DED_IF_Msk ) + +#define SYSCFG_RAMECCSR_SRAM3_SEC_IF_Pos ( 4U ) +#define SYSCFG_RAMECCSR_SRAM3_SEC_IF_Msk ( 0x1UL << SYSCFG_RAMECCSR_SRAM3_SEC_IF_Pos ) +#define SYSCFG_RAMECCSR_SRAM3_SEC_IF ( SYSCFG_RAMECCSR_SRAM3_SEC_IF_Msk ) + +#define SYSCFG_RAMECCSR_SRAM1_DED_IF_Pos ( 1U ) +#define SYSCFG_RAMECCSR_SRAM1_DED_IF_Msk ( 0x1UL << SYSCFG_RAMECCSR_SRAM1_DED_IF_Pos ) +#define SYSCFG_RAMECCSR_SRAM1_DED_IF ( SYSCFG_RAMECCSR_SRAM1_DED_IF_Msk ) + +#define SYSCFG_RAMECCSR_SRAM1_SEC_IF_Pos ( 0U ) +#define SYSCFG_RAMECCSR_SRAM1_SEC_IF_Msk ( 0x1UL << SYSCFG_RAMECCSR_SRAM1_SEC_IF_Pos ) +#define SYSCFG_RAMECCSR_SRAM1_SEC_IF ( SYSCFG_RAMECCSR_SRAM1_SEC_IF_Msk ) + + +/*************** Bits definition for SYSCFG_RAMECCICR **********************/ + +#define SYSCFG_RAMECCICR_BKPSRAM_DED_IC_Pos ( 9U ) +#define SYSCFG_RAMECCICR_BKPSRAM_DED_IC_Msk ( 0x1UL << SYSCFG_RAMECCICR_BKPSRAM_DED_IC_Pos ) +#define SYSCFG_RAMECCICR_BKPSRAM_DED_IC ( SYSCFG_RAMECCICR_BKPSRAM_DED_IC_Msk ) + +#define SYSCFG_RAMECCICR_BKPSRAM_SEC_IC_Pos ( 8U ) +#define SYSCFG_RAMECCICR_BKPSRAM_SEC_IC_Msk ( 0x1UL << SYSCFG_RAMECCICR_BKPSRAM_SEC_IC_Pos ) +#define SYSCFG_RAMECCICR_BKPSRAM_SEC_IC ( SYSCFG_RAMECCICR_BKPSRAM_SEC_IC_Msk ) + +#define SYSCFG_RAMECCICR_SRAM3_DED_IC_Pos ( 5U ) +#define SYSCFG_RAMECCICR_SRAM3_DED_IC_Msk ( 0x1UL << SYSCFG_RAMECCICR_SRAM3_DED_IC_Pos ) +#define SYSCFG_RAMECCICR_SRAM3_DED_IC ( SYSCFG_RAMECCICR_SRAM3_DED_IC_Msk ) + +#define SYSCFG_RAMECCICR_SRAM3_SEC_IC_Pos ( 4U ) +#define SYSCFG_RAMECCICR_SRAM3_SEC_IC_Msk ( 0x1UL << SYSCFG_RAMECCICR_SRAM3_SEC_IC_Pos ) +#define SYSCFG_RAMECCICR_SRAM3_SEC_IC ( SYSCFG_RAMECCICR_SRAM3_SEC_IC_Msk ) + +#define SYSCFG_RAMECCICR_SRAM1_DED_IC_Pos ( 1U ) +#define SYSCFG_RAMECCICR_SRAM1_DED_IC_Msk ( 0x1UL << SYSCFG_RAMECCICR_SRAM1_DED_IC_Pos ) +#define SYSCFG_RAMECCICR_SRAM1_DED_IC ( SYSCFG_RAMECCICR_SRAM1_DED_IC_Msk ) + +#define SYSCFG_RAMECCICR_SRAM1_SEC_IC_Pos ( 0U ) +#define SYSCFG_RAMECCICR_SRAM1_SEC_IC_Msk ( 0x1UL << SYSCFG_RAMECCICR_SRAM1_SEC_IC_Pos ) +#define SYSCFG_RAMECCICR_SRAM1_SEC_IC ( SYSCFG_RAMECCICR_SRAM1_SEC_IC_Msk ) + + +/*************** Bits definition for SYSCFG_GPIO5VOCR1 **********************/ + +#define SYSCFG_GPIO5VOCR1_PK13OE5V_Pos ( 31U ) +#define SYSCFG_GPIO5VOCR1_PK13OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK13OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK13OE5V ( SYSCFG_GPIO5VOCR1_PK13OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK12OE5V_Pos ( 30U ) +#define SYSCFG_GPIO5VOCR1_PK12OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK12OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK12OE5V ( SYSCFG_GPIO5VOCR1_PK12OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK11OE5V_Pos ( 29U ) +#define SYSCFG_GPIO5VOCR1_PK11OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK11OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK11OE5V ( SYSCFG_GPIO5VOCR1_PK11OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK10OE5V_Pos ( 28U ) +#define SYSCFG_GPIO5VOCR1_PK10OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK10OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK10OE5V ( SYSCFG_GPIO5VOCR1_PK10OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK9OE5V_Pos ( 27U ) +#define SYSCFG_GPIO5VOCR1_PK9OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK9OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK9OE5V ( SYSCFG_GPIO5VOCR1_PK9OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK8OE5V_Pos ( 26U ) +#define SYSCFG_GPIO5VOCR1_PK8OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK8OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK8OE5V ( SYSCFG_GPIO5VOCR1_PK8OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK7OE5V_Pos ( 25U ) +#define SYSCFG_GPIO5VOCR1_PK7OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK7OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK7OE5V ( SYSCFG_GPIO5VOCR1_PK7OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK6OE5V_Pos ( 24U ) +#define SYSCFG_GPIO5VOCR1_PK6OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK6OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK6OE5V ( SYSCFG_GPIO5VOCR1_PK6OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK5OE5V_Pos ( 23U ) +#define SYSCFG_GPIO5VOCR1_PK5OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK5OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK5OE5V ( SYSCFG_GPIO5VOCR1_PK5OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK4OE5V_Pos ( 22U ) +#define SYSCFG_GPIO5VOCR1_PK4OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK4OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK4OE5V ( SYSCFG_GPIO5VOCR1_PK4OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK3OE5V_Pos ( 21U ) +#define SYSCFG_GPIO5VOCR1_PK3OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK3OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK3OE5V ( SYSCFG_GPIO5VOCR1_PK3OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK2OE5V_Pos ( 20U ) +#define SYSCFG_GPIO5VOCR1_PK2OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK2OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK2OE5V ( SYSCFG_GPIO5VOCR1_PK2OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK1OE5V_Pos ( 19U ) +#define SYSCFG_GPIO5VOCR1_PK1OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK1OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK1OE5V ( SYSCFG_GPIO5VOCR1_PK1OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PK0OE5V_Pos ( 18U ) +#define SYSCFG_GPIO5VOCR1_PK0OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PK0OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PK0OE5V ( SYSCFG_GPIO5VOCR1_PK0OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ15OE5V_Pos ( 17U ) +#define SYSCFG_GPIO5VOCR1_PJ15OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ15OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ15OE5V ( SYSCFG_GPIO5VOCR1_PJ15OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ14OE5V_Pos ( 16U ) +#define SYSCFG_GPIO5VOCR1_PJ14OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ14OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ14OE5V ( SYSCFG_GPIO5VOCR1_PJ14OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ13OE5V_Pos ( 15U ) +#define SYSCFG_GPIO5VOCR1_PJ13OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ13OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ13OE5V ( SYSCFG_GPIO5VOCR1_PJ13OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ12OE5V_Pos ( 14U ) +#define SYSCFG_GPIO5VOCR1_PJ12OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ12OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ12OE5V ( SYSCFG_GPIO5VOCR1_PJ12OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ11OE5V_Pos ( 13U ) +#define SYSCFG_GPIO5VOCR1_PJ11OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ11OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ11OE5V ( SYSCFG_GPIO5VOCR1_PJ11OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ10OE5V_Pos ( 12U ) +#define SYSCFG_GPIO5VOCR1_PJ10OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ10OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ10OE5V ( SYSCFG_GPIO5VOCR1_PJ10OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ9OE5V_Pos ( 11U ) +#define SYSCFG_GPIO5VOCR1_PJ9OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ9OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ9OE5V ( SYSCFG_GPIO5VOCR1_PJ9OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ8OE5V_Pos ( 10U ) +#define SYSCFG_GPIO5VOCR1_PJ8OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ8OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ8OE5V ( SYSCFG_GPIO5VOCR1_PJ8OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ7OE5V_Pos ( 9U ) +#define SYSCFG_GPIO5VOCR1_PJ7OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ7OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ7OE5V ( SYSCFG_GPIO5VOCR1_PJ7OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PJ6OE5V_Pos ( 8U ) +#define SYSCFG_GPIO5VOCR1_PJ6OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PJ6OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PJ6OE5V ( SYSCFG_GPIO5VOCR1_PJ6OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PI14OE5V_Pos ( 7U ) +#define SYSCFG_GPIO5VOCR1_PI14OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PI14OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PI14OE5V ( SYSCFG_GPIO5VOCR1_PI14OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH12OE5V_Pos ( 6U ) +#define SYSCFG_GPIO5VOCR1_PH12OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH12OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH12OE5V ( SYSCFG_GPIO5VOCR1_PH12OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH11OE5V_Pos ( 5U ) +#define SYSCFG_GPIO5VOCR1_PH11OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH11OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH11OE5V ( SYSCFG_GPIO5VOCR1_PH11OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH10OE5V_Pos ( 4U ) +#define SYSCFG_GPIO5VOCR1_PH10OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH10OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH10OE5V ( SYSCFG_GPIO5VOCR1_PH10OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH9OE5V_Pos ( 3U ) +#define SYSCFG_GPIO5VOCR1_PH9OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH9OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH9OE5V ( SYSCFG_GPIO5VOCR1_PH9OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH8OE5V_Pos ( 2U ) +#define SYSCFG_GPIO5VOCR1_PH8OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH8OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH8OE5V ( SYSCFG_GPIO5VOCR1_PH8OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH7OE5V_Pos ( 1U ) +#define SYSCFG_GPIO5VOCR1_PH7OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH7OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH7OE5V ( SYSCFG_GPIO5VOCR1_PH7OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR1_PH6OE5V_Pos ( 0U ) +#define SYSCFG_GPIO5VOCR1_PH6OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR1_PH6OE5V_Pos ) +#define SYSCFG_GPIO5VOCR1_PH6OE5V ( SYSCFG_GPIO5VOCR1_PH6OE5V_Msk ) + + +/*************** Bits definition for SYSCFG_GPIO5VOCR2 **********************/ + +#define SYSCFG_GPIO5VOCR2_PP15OE5V_Pos ( 17U ) +#define SYSCFG_GPIO5VOCR2_PP15OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PP15OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PP15OE5V ( SYSCFG_GPIO5VOCR2_PP15OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PP14OE5V_Pos ( 16U ) +#define SYSCFG_GPIO5VOCR2_PP14OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PP14OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PP14OE5V ( SYSCFG_GPIO5VOCR2_PP14OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PP13OE5V_Pos ( 15U ) +#define SYSCFG_GPIO5VOCR2_PP13OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PP13OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PP13OE5V ( SYSCFG_GPIO5VOCR2_PP13OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PP12OE5V_Pos ( 14U ) +#define SYSCFG_GPIO5VOCR2_PP12OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PP12OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PP12OE5V ( SYSCFG_GPIO5VOCR2_PP12OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PP11OE5V_Pos ( 13U ) +#define SYSCFG_GPIO5VOCR2_PP11OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PP11OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PP11OE5V ( SYSCFG_GPIO5VOCR2_PP11OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PP10OE5V_Pos ( 12U ) +#define SYSCFG_GPIO5VOCR2_PP10OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PP10OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PP10OE5V ( SYSCFG_GPIO5VOCR2_PP10OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO15OE5V_Pos ( 11U ) +#define SYSCFG_GPIO5VOCR2_PO15OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO15OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO15OE5V ( SYSCFG_GPIO5VOCR2_PO15OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO14OE5V_Pos ( 10U ) +#define SYSCFG_GPIO5VOCR2_PO14OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO14OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO14OE5V ( SYSCFG_GPIO5VOCR2_PO14OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO13OE5V_Pos ( 9U ) +#define SYSCFG_GPIO5VOCR2_PO13OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO13OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO13OE5V ( SYSCFG_GPIO5VOCR2_PO13OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO12OE5V_Pos ( 8U ) +#define SYSCFG_GPIO5VOCR2_PO12OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO12OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO12OE5V ( SYSCFG_GPIO5VOCR2_PO12OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO3OE5V_Pos ( 7U ) +#define SYSCFG_GPIO5VOCR2_PO3OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO3OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO3OE5V ( SYSCFG_GPIO5VOCR2_PO3OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO2OE5V_Pos ( 6U ) +#define SYSCFG_GPIO5VOCR2_PO2OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO2OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO2OE5V ( SYSCFG_GPIO5VOCR2_PO2OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO1OE5V_Pos ( 5U ) +#define SYSCFG_GPIO5VOCR2_PO1OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO1OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO1OE5V ( SYSCFG_GPIO5VOCR2_PO1OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PO0OE5V_Pos ( 4U ) +#define SYSCFG_GPIO5VOCR2_PO0OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PO0OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PO0OE5V ( SYSCFG_GPIO5VOCR2_PO0OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PM13OE5V_Pos ( 3U ) +#define SYSCFG_GPIO5VOCR2_PM13OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PM13OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PM13OE5V ( SYSCFG_GPIO5VOCR2_PM13OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PM12OE5V_Pos ( 2U ) +#define SYSCFG_GPIO5VOCR2_PM12OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PM12OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PM12OE5V ( SYSCFG_GPIO5VOCR2_PM12OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PM11OE5V_Pos ( 1U ) +#define SYSCFG_GPIO5VOCR2_PM11OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PM11OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PM11OE5V ( SYSCFG_GPIO5VOCR2_PM11OE5V_Msk ) + +#define SYSCFG_GPIO5VOCR2_PM10OE5V_Pos ( 0U ) +#define SYSCFG_GPIO5VOCR2_PM10OE5V_Msk ( 0x1UL << SYSCFG_GPIO5VOCR2_PM10OE5V_Pos ) +#define SYSCFG_GPIO5VOCR2_PM10OE5V ( SYSCFG_GPIO5VOCR2_PM10OE5V_Msk ) + + +/*************** Bits definition for RCC_RCR **********************/ + +#define RCC_RCR_SRST_MAP_Pos ( 31U ) +#define RCC_RCR_SRST_MAP_Msk ( 0x1UL << RCC_RCR_SRST_MAP_Pos ) +#define RCC_RCR_SRST_MAP ( RCC_RCR_SRST_MAP_Msk ) + +#define RCC_RCR_IWDTRST_DIS_Pos ( 8U ) +#define RCC_RCR_IWDTRST_DIS_Msk ( 0xFFUL << RCC_RCR_IWDTRST_DIS_Pos ) +#define RCC_RCR_IWDTRST_DIS ( RCC_RCR_IWDTRST_DIS_Msk ) + +#define RCC_RCR_LOCKRST_EN_Pos ( 3U ) +#define RCC_RCR_LOCKRST_EN_Msk ( 0x1UL << RCC_RCR_LOCKRST_EN_Pos ) +#define RCC_RCR_LOCKRST_EN ( RCC_RCR_LOCKRST_EN_Msk ) + +#define RCC_RCR_IWDTRST_EN_Pos ( 2U ) +#define RCC_RCR_IWDTRST_EN_Msk ( 0x1UL << RCC_RCR_IWDTRST_EN_Pos ) +#define RCC_RCR_IWDTRST_EN ( RCC_RCR_IWDTRST_EN_Msk ) + +#define RCC_RCR_WDTRST_EN_Pos ( 1U ) +#define RCC_RCR_WDTRST_EN_Msk ( 0x1UL << RCC_RCR_WDTRST_EN_Pos ) +#define RCC_RCR_WDTRST_EN ( RCC_RCR_WDTRST_EN_Msk ) + +#define RCC_RCR_LVDRST_EN_Pos ( 0U ) +#define RCC_RCR_LVDRST_EN_Msk ( 0x1UL << RCC_RCR_LVDRST_EN_Pos ) +#define RCC_RCR_LVDRST_EN ( RCC_RCR_LVDRST_EN_Msk ) + + +/*************** Bits definition for RCC_RSR **********************/ + +#define RCC_RSR_RSTFLAGCLR_Pos ( 16U ) +#define RCC_RSR_RSTFLAGCLR_Msk ( 0x1UL << RCC_RSR_RSTFLAGCLR_Pos ) +#define RCC_RSR_RSTFLAGCLR ( RCC_RSR_RSTFLAGCLR_Msk ) + +#define RCC_RSR_PWRRSTF_Pos ( 10U ) +#define RCC_RSR_PWRRSTF_Msk ( 0x1UL << RCC_RSR_PWRRSTF_Pos ) +#define RCC_RSR_PWRRSTF ( RCC_RSR_PWRRSTF_Msk ) + +#define RCC_RSR_POR12RSTF_Pos ( 9U ) +#define RCC_RSR_POR12RSTF_Msk ( 0x1UL << RCC_RSR_POR12RSTF_Pos ) +#define RCC_RSR_POR12RSTF ( RCC_RSR_POR12RSTF_Msk ) + +#define RCC_RSR_SRSTF_Pos ( 8U ) +#define RCC_RSR_SRSTF_Msk ( 0x1UL << RCC_RSR_SRSTF_Pos ) +#define RCC_RSR_SRSTF ( RCC_RSR_SRSTF_Msk ) + +#define RCC_RSR_RSTNF_Pos ( 5U ) +#define RCC_RSR_RSTNF_Msk ( 0x1UL << RCC_RSR_RSTNF_Pos ) +#define RCC_RSR_RSTNF ( RCC_RSR_RSTNF_Msk ) + +#define RCC_RSR_SYSREQRSTF_Pos ( 4U ) +#define RCC_RSR_SYSREQRSTF_Msk ( 0x1UL << RCC_RSR_SYSREQRSTF_Pos ) +#define RCC_RSR_SYSREQRSTF ( RCC_RSR_SYSREQRSTF_Msk ) + +#define RCC_RSR_LOCKUPRSTF_Pos ( 3U ) +#define RCC_RSR_LOCKUPRSTF_Msk ( 0x1UL << RCC_RSR_LOCKUPRSTF_Pos ) +#define RCC_RSR_LOCKUPRSTF ( RCC_RSR_LOCKUPRSTF_Msk ) + +#define RCC_RSR_IWDTRSTF_Pos ( 2U ) +#define RCC_RSR_IWDTRSTF_Msk ( 0x1UL << RCC_RSR_IWDTRSTF_Pos ) +#define RCC_RSR_IWDTRSTF ( RCC_RSR_IWDTRSTF_Msk ) + +#define RCC_RSR_WDTRSTF_Pos ( 1U ) +#define RCC_RSR_WDTRSTF_Msk ( 0x1UL << RCC_RSR_WDTRSTF_Pos ) +#define RCC_RSR_WDTRSTF ( RCC_RSR_WDTRSTF_Msk ) + +#define RCC_RSR_LVDRSTF_Pos ( 0U ) +#define RCC_RSR_LVDRSTF_Msk ( 0x1UL << RCC_RSR_LVDRSTF_Pos ) +#define RCC_RSR_LVDRSTF ( RCC_RSR_LVDRSTF_Msk ) + + +/*************** Bits definition for RCC_AHB1RSTR **********************/ + +#define RCC_AHB1RSTR_FDCAN2RST_Pos ( 23U ) +#define RCC_AHB1RSTR_FDCAN2RST_Msk ( 0x1UL << RCC_AHB1RSTR_FDCAN2RST_Pos ) +#define RCC_AHB1RSTR_FDCAN2RST ( RCC_AHB1RSTR_FDCAN2RST_Msk ) + +#define RCC_AHB1RSTR_FDCAN1RST_Pos ( 22U ) +#define RCC_AHB1RSTR_FDCAN1RST_Msk ( 0x1UL << RCC_AHB1RSTR_FDCAN1RST_Pos ) +#define RCC_AHB1RSTR_FDCAN1RST ( RCC_AHB1RSTR_FDCAN1RST_Msk ) + +#define RCC_AHB1RSTR_USB2CRST_Pos ( 21U ) +#define RCC_AHB1RSTR_USB2CRST_Msk ( 0x1UL << RCC_AHB1RSTR_USB2CRST_Pos ) +#define RCC_AHB1RSTR_USB2CRST ( RCC_AHB1RSTR_USB2CRST_Msk ) + +#define RCC_AHB1RSTR_USB1CRST_Pos ( 20U ) +#define RCC_AHB1RSTR_USB1CRST_Msk ( 0x1UL << RCC_AHB1RSTR_USB1CRST_Pos ) +#define RCC_AHB1RSTR_USB1CRST ( RCC_AHB1RSTR_USB1CRST_Msk ) + +#define RCC_AHB1RSTR_SPI6RST_Pos ( 15U ) +#define RCC_AHB1RSTR_SPI6RST_Msk ( 0x1UL << RCC_AHB1RSTR_SPI6RST_Pos ) +#define RCC_AHB1RSTR_SPI6RST ( RCC_AHB1RSTR_SPI6RST_Msk ) + +#define RCC_AHB1RSTR_SPI5RST_Pos ( 14U ) +#define RCC_AHB1RSTR_SPI5RST_Msk ( 0x1UL << RCC_AHB1RSTR_SPI5RST_Pos ) +#define RCC_AHB1RSTR_SPI5RST ( RCC_AHB1RSTR_SPI5RST_Msk ) + +#define RCC_AHB1RSTR_SPI4RST_Pos ( 13U ) +#define RCC_AHB1RSTR_SPI4RST_Msk ( 0x1UL << RCC_AHB1RSTR_SPI4RST_Pos ) +#define RCC_AHB1RSTR_SPI4RST ( RCC_AHB1RSTR_SPI4RST_Msk ) + +#define RCC_AHB1RSTR_SPI3RST_Pos ( 12U ) +#define RCC_AHB1RSTR_SPI3RST_Msk ( 0x1UL << RCC_AHB1RSTR_SPI3RST_Pos ) +#define RCC_AHB1RSTR_SPI3RST ( RCC_AHB1RSTR_SPI3RST_Msk ) + +#define RCC_AHB1RSTR_SPI2RST_Pos ( 11U ) +#define RCC_AHB1RSTR_SPI2RST_Msk ( 0x1UL << RCC_AHB1RSTR_SPI2RST_Pos ) +#define RCC_AHB1RSTR_SPI2RST ( RCC_AHB1RSTR_SPI2RST_Msk ) + +#define RCC_AHB1RSTR_SPI1RST_Pos ( 10U ) +#define RCC_AHB1RSTR_SPI1RST_Msk ( 0x1UL << RCC_AHB1RSTR_SPI1RST_Pos ) +#define RCC_AHB1RSTR_SPI1RST ( RCC_AHB1RSTR_SPI1RST_Msk ) + +#define RCC_AHB1RSTR_DMA2DRST_Pos ( 9U ) +#define RCC_AHB1RSTR_DMA2DRST_Msk ( 0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos ) +#define RCC_AHB1RSTR_DMA2DRST ( RCC_AHB1RSTR_DMA2DRST_Msk ) + +#define RCC_AHB1RSTR_ETHRST_Pos ( 6U ) +#define RCC_AHB1RSTR_ETHRST_Msk ( 0x1UL << RCC_AHB1RSTR_ETHRST_Pos ) +#define RCC_AHB1RSTR_ETHRST ( RCC_AHB1RSTR_ETHRST_Msk ) + +#define RCC_AHB1RSTR_CRCRST_Pos ( 5U ) +#define RCC_AHB1RSTR_CRCRST_Msk ( 0x1UL << RCC_AHB1RSTR_CRCRST_Pos ) +#define RCC_AHB1RSTR_CRCRST ( RCC_AHB1RSTR_CRCRST_Msk ) + +#define RCC_AHB1RSTR_DMA2RST_Pos ( 1U ) +#define RCC_AHB1RSTR_DMA2RST_Msk ( 0x1UL << RCC_AHB1RSTR_DMA2RST_Pos ) +#define RCC_AHB1RSTR_DMA2RST ( RCC_AHB1RSTR_DMA2RST_Msk ) + +#define RCC_AHB1RSTR_DMA1RST_Pos ( 0U ) +#define RCC_AHB1RSTR_DMA1RST_Msk ( 0x1UL << RCC_AHB1RSTR_DMA1RST_Pos ) +#define RCC_AHB1RSTR_DMA1RST ( RCC_AHB1RSTR_DMA1RST_Msk ) + + +/*************** Bits definition for RCC_AHB2RSTR **********************/ + +#define RCC_AHB2RSTR_THMRST_Pos ( 31U ) +#define RCC_AHB2RSTR_THMRST_Msk ( 0x1UL << RCC_AHB2RSTR_THMRST_Pos ) +#define RCC_AHB2RSTR_THMRST ( RCC_AHB2RSTR_THMRST_Msk ) + +#define RCC_AHB2RSTR_FDCAN3RST_Pos ( 28U ) +#define RCC_AHB2RSTR_FDCAN3RST_Msk ( 0x1UL << RCC_AHB2RSTR_FDCAN3RST_Pos ) +#define RCC_AHB2RSTR_FDCAN3RST ( RCC_AHB2RSTR_FDCAN3RST_Msk ) + +#define RCC_AHB2RSTR_UACRST_Pos ( 27U ) +#define RCC_AHB2RSTR_UACRST_Msk ( 0x1UL << RCC_AHB2RSTR_UACRST_Pos ) +#define RCC_AHB2RSTR_UACRST ( RCC_AHB2RSTR_UACRST_Msk ) + +#define RCC_AHB2RSTR_DCMIRST_Pos ( 23U ) +#define RCC_AHB2RSTR_DCMIRST_Msk ( 0x1UL << RCC_AHB2RSTR_DCMIRST_Pos ) +#define RCC_AHB2RSTR_DCMIRST ( RCC_AHB2RSTR_DCMIRST_Msk ) + +#define RCC_AHB2RSTR_DAC2RST_Pos ( 20U ) +#define RCC_AHB2RSTR_DAC2RST_Msk ( 0x1UL << RCC_AHB2RSTR_DAC2RST_Pos ) +#define RCC_AHB2RSTR_DAC2RST ( RCC_AHB2RSTR_DAC2RST_Msk ) + +#define RCC_AHB2RSTR_DAC1RST_Pos ( 19U ) +#define RCC_AHB2RSTR_DAC1RST_Msk ( 0x1UL << RCC_AHB2RSTR_DAC1RST_Pos ) +#define RCC_AHB2RSTR_DAC1RST ( RCC_AHB2RSTR_DAC1RST_Msk ) + +#define RCC_AHB2RSTR_ADC3RST_Pos ( 18U ) +#define RCC_AHB2RSTR_ADC3RST_Msk ( 0x1UL << RCC_AHB2RSTR_ADC3RST_Pos ) +#define RCC_AHB2RSTR_ADC3RST ( RCC_AHB2RSTR_ADC3RST_Msk ) + +#define RCC_AHB2RSTR_ADC12RST_Pos ( 17U ) +#define RCC_AHB2RSTR_ADC12RST_Msk ( 0x1UL << RCC_AHB2RSTR_ADC12RST_Pos ) +#define RCC_AHB2RSTR_ADC12RST ( RCC_AHB2RSTR_ADC12RST_Msk ) + +#define RCC_AHB2RSTR_GPIOQRST_Pos ( 16U ) +#define RCC_AHB2RSTR_GPIOQRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOQRST_Pos ) +#define RCC_AHB2RSTR_GPIOQRST ( RCC_AHB2RSTR_GPIOQRST_Msk ) + +#define RCC_AHB2RSTR_GPIOPRST_Pos ( 15U ) +#define RCC_AHB2RSTR_GPIOPRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOPRST_Pos ) +#define RCC_AHB2RSTR_GPIOPRST ( RCC_AHB2RSTR_GPIOPRST_Msk ) + +#define RCC_AHB2RSTR_GPIOORST_Pos ( 14U ) +#define RCC_AHB2RSTR_GPIOORST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOORST_Pos ) +#define RCC_AHB2RSTR_GPIOORST ( RCC_AHB2RSTR_GPIOORST_Msk ) + +#define RCC_AHB2RSTR_GPIONRST_Pos ( 13U ) +#define RCC_AHB2RSTR_GPIONRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIONRST_Pos ) +#define RCC_AHB2RSTR_GPIONRST ( RCC_AHB2RSTR_GPIONRST_Msk ) + +#define RCC_AHB2RSTR_GPIOMRST_Pos ( 12U ) +#define RCC_AHB2RSTR_GPIOMRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOMRST_Pos ) +#define RCC_AHB2RSTR_GPIOMRST ( RCC_AHB2RSTR_GPIOMRST_Msk ) + +#define RCC_AHB2RSTR_GPIOLRST_Pos ( 11U ) +#define RCC_AHB2RSTR_GPIOLRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOLRST_Pos ) +#define RCC_AHB2RSTR_GPIOLRST ( RCC_AHB2RSTR_GPIOLRST_Msk ) + +#define RCC_AHB2RSTR_GPIOKRST_Pos ( 10U ) +#define RCC_AHB2RSTR_GPIOKRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOKRST_Pos ) +#define RCC_AHB2RSTR_GPIOKRST ( RCC_AHB2RSTR_GPIOKRST_Msk ) + +#define RCC_AHB2RSTR_GPIOJRST_Pos ( 9U ) +#define RCC_AHB2RSTR_GPIOJRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOJRST_Pos ) +#define RCC_AHB2RSTR_GPIOJRST ( RCC_AHB2RSTR_GPIOJRST_Msk ) + +#define RCC_AHB2RSTR_GPIOIRST_Pos ( 8U ) +#define RCC_AHB2RSTR_GPIOIRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOIRST_Pos ) +#define RCC_AHB2RSTR_GPIOIRST ( RCC_AHB2RSTR_GPIOIRST_Msk ) + +#define RCC_AHB2RSTR_GPIOHRST_Pos ( 7U ) +#define RCC_AHB2RSTR_GPIOHRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos ) +#define RCC_AHB2RSTR_GPIOHRST ( RCC_AHB2RSTR_GPIOHRST_Msk ) + +#define RCC_AHB2RSTR_GPIOGRST_Pos ( 6U ) +#define RCC_AHB2RSTR_GPIOGRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos ) +#define RCC_AHB2RSTR_GPIOGRST ( RCC_AHB2RSTR_GPIOGRST_Msk ) + +#define RCC_AHB2RSTR_GPIOFRST_Pos ( 5U ) +#define RCC_AHB2RSTR_GPIOFRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos ) +#define RCC_AHB2RSTR_GPIOFRST ( RCC_AHB2RSTR_GPIOFRST_Msk ) + +#define RCC_AHB2RSTR_GPIOERST_Pos ( 4U ) +#define RCC_AHB2RSTR_GPIOERST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOERST_Pos ) +#define RCC_AHB2RSTR_GPIOERST ( RCC_AHB2RSTR_GPIOERST_Msk ) + +#define RCC_AHB2RSTR_GPIODRST_Pos ( 3U ) +#define RCC_AHB2RSTR_GPIODRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIODRST_Pos ) +#define RCC_AHB2RSTR_GPIODRST ( RCC_AHB2RSTR_GPIODRST_Msk ) + +#define RCC_AHB2RSTR_GPIOCRST_Pos ( 2U ) +#define RCC_AHB2RSTR_GPIOCRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos ) +#define RCC_AHB2RSTR_GPIOCRST ( RCC_AHB2RSTR_GPIOCRST_Msk ) + +#define RCC_AHB2RSTR_GPIOBRST_Pos ( 1U ) +#define RCC_AHB2RSTR_GPIOBRST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos ) +#define RCC_AHB2RSTR_GPIOBRST ( RCC_AHB2RSTR_GPIOBRST_Msk ) + +#define RCC_AHB2RSTR_GPIOARST_Pos ( 0U ) +#define RCC_AHB2RSTR_GPIOARST_Msk ( 0x1UL << RCC_AHB2RSTR_GPIOARST_Pos ) +#define RCC_AHB2RSTR_GPIOARST ( RCC_AHB2RSTR_GPIOARST_Msk ) + + +/*************** Bits definition for RCC_AHB3RSTR **********************/ + +#define RCC_AHB3RSTR_FMCRST_Pos ( 12U ) +#define RCC_AHB3RSTR_FMCRST_Msk ( 0x1UL << RCC_AHB3RSTR_FMCRST_Pos ) +#define RCC_AHB3RSTR_FMCRST ( RCC_AHB3RSTR_FMCRST_Msk ) + +#define RCC_AHB3RSTR_OSPI2RST_Pos ( 9U ) +#define RCC_AHB3RSTR_OSPI2RST_Msk ( 0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos ) +#define RCC_AHB3RSTR_OSPI2RST ( RCC_AHB3RSTR_OSPI2RST_Msk ) + +#define RCC_AHB3RSTR_OSPI1RST_Pos ( 8U ) +#define RCC_AHB3RSTR_OSPI1RST_Msk ( 0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos ) +#define RCC_AHB3RSTR_OSPI1RST ( RCC_AHB3RSTR_OSPI1RST_Msk ) + +#define RCC_AHB3RSTR_SDMMCRST_Pos ( 4U ) +#define RCC_AHB3RSTR_SDMMCRST_Msk ( 0x1UL << RCC_AHB3RSTR_SDMMCRST_Pos ) +#define RCC_AHB3RSTR_SDMMCRST ( RCC_AHB3RSTR_SDMMCRST_Msk ) + +#define RCC_AHB3RSTR_SPI8RST_Pos ( 1U ) +#define RCC_AHB3RSTR_SPI8RST_Msk ( 0x1UL << RCC_AHB3RSTR_SPI8RST_Pos ) +#define RCC_AHB3RSTR_SPI8RST ( RCC_AHB3RSTR_SPI8RST_Msk ) + +#define RCC_AHB3RSTR_SPI7RST_Pos ( 0U ) +#define RCC_AHB3RSTR_SPI7RST_Msk ( 0x1UL << RCC_AHB3RSTR_SPI7RST_Pos ) +#define RCC_AHB3RSTR_SPI7RST ( RCC_AHB3RSTR_SPI7RST_Msk ) + + +/*************** Bits definition for RCC_APB1RSTR1 **********************/ + +#define RCC_APB1RSTR1_LPUART1RST_Pos ( 31U ) +#define RCC_APB1RSTR1_LPUART1RST_Msk ( 0x1UL << RCC_APB1RSTR1_LPUART1RST_Pos ) +#define RCC_APB1RSTR1_LPUART1RST ( RCC_APB1RSTR1_LPUART1RST_Msk ) + +#define RCC_APB1RSTR1_LPTIM1RST_Pos ( 30U ) +#define RCC_APB1RSTR1_LPTIM1RST_Msk ( 0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos ) +#define RCC_APB1RSTR1_LPTIM1RST ( RCC_APB1RSTR1_LPTIM1RST_Msk ) + +#define RCC_APB1RSTR1_PMURST_Pos ( 27U ) +#define RCC_APB1RSTR1_PMURST_Msk ( 0x1UL << RCC_APB1RSTR1_PMURST_Pos ) +#define RCC_APB1RSTR1_PMURST ( RCC_APB1RSTR1_PMURST_Msk ) + +#define RCC_APB1RSTR1_I2C4RST_Pos ( 24U ) +#define RCC_APB1RSTR1_I2C4RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2C4RST_Pos ) +#define RCC_APB1RSTR1_I2C4RST ( RCC_APB1RSTR1_I2C4RST_Msk ) + +#define RCC_APB1RSTR1_I2C3RST_Pos ( 23U ) +#define RCC_APB1RSTR1_I2C3RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2C3RST_Pos ) +#define RCC_APB1RSTR1_I2C3RST ( RCC_APB1RSTR1_I2C3RST_Msk ) + +#define RCC_APB1RSTR1_I2C2RST_Pos ( 22U ) +#define RCC_APB1RSTR1_I2C2RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2C2RST_Pos ) +#define RCC_APB1RSTR1_I2C2RST ( RCC_APB1RSTR1_I2C2RST_Msk ) + +#define RCC_APB1RSTR1_I2C1RST_Pos ( 21U ) +#define RCC_APB1RSTR1_I2C1RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2C1RST_Pos ) +#define RCC_APB1RSTR1_I2C1RST ( RCC_APB1RSTR1_I2C1RST_Msk ) + +#define RCC_APB1RSTR1_USART5RST_Pos ( 20U ) +#define RCC_APB1RSTR1_USART5RST_Msk ( 0x1UL << RCC_APB1RSTR1_USART5RST_Pos ) +#define RCC_APB1RSTR1_USART5RST ( RCC_APB1RSTR1_USART5RST_Msk ) + +#define RCC_APB1RSTR1_USART4RST_Pos ( 19U ) +#define RCC_APB1RSTR1_USART4RST_Msk ( 0x1UL << RCC_APB1RSTR1_USART4RST_Pos ) +#define RCC_APB1RSTR1_USART4RST ( RCC_APB1RSTR1_USART4RST_Msk ) + +#define RCC_APB1RSTR1_USART3RST_Pos ( 18U ) +#define RCC_APB1RSTR1_USART3RST_Msk ( 0x1UL << RCC_APB1RSTR1_USART3RST_Pos ) +#define RCC_APB1RSTR1_USART3RST ( RCC_APB1RSTR1_USART3RST_Msk ) + +#define RCC_APB1RSTR1_USART2RST_Pos ( 17U ) +#define RCC_APB1RSTR1_USART2RST_Msk ( 0x1UL << RCC_APB1RSTR1_USART2RST_Pos ) +#define RCC_APB1RSTR1_USART2RST ( RCC_APB1RSTR1_USART2RST_Msk ) + +#define RCC_APB1RSTR1_I2S3RST_Pos ( 16U ) +#define RCC_APB1RSTR1_I2S3RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2S3RST_Pos ) +#define RCC_APB1RSTR1_I2S3RST ( RCC_APB1RSTR1_I2S3RST_Msk ) + +#define RCC_APB1RSTR1_I2S2RST_Pos ( 15U ) +#define RCC_APB1RSTR1_I2S2RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2S2RST_Pos ) +#define RCC_APB1RSTR1_I2S2RST ( RCC_APB1RSTR1_I2S2RST_Msk ) + +#define RCC_APB1RSTR1_I2S1RST_Pos ( 14U ) +#define RCC_APB1RSTR1_I2S1RST_Msk ( 0x1UL << RCC_APB1RSTR1_I2S1RST_Pos ) +#define RCC_APB1RSTR1_I2S1RST ( RCC_APB1RSTR1_I2S1RST_Msk ) + +#define RCC_APB1RSTR1_WDTRST_Pos ( 11U ) +#define RCC_APB1RSTR1_WDTRST_Msk ( 0x1UL << RCC_APB1RSTR1_WDTRST_Pos ) +#define RCC_APB1RSTR1_WDTRST ( RCC_APB1RSTR1_WDTRST_Msk ) + +#define RCC_APB1RSTR1_TIM14RST_Pos ( 8U ) +#define RCC_APB1RSTR1_TIM14RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM14RST_Pos ) +#define RCC_APB1RSTR1_TIM14RST ( RCC_APB1RSTR1_TIM14RST_Msk ) + +#define RCC_APB1RSTR1_TIM13RST_Pos ( 7U ) +#define RCC_APB1RSTR1_TIM13RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM13RST_Pos ) +#define RCC_APB1RSTR1_TIM13RST ( RCC_APB1RSTR1_TIM13RST_Msk ) + +#define RCC_APB1RSTR1_TIM12RST_Pos ( 6U ) +#define RCC_APB1RSTR1_TIM12RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM12RST_Pos ) +#define RCC_APB1RSTR1_TIM12RST ( RCC_APB1RSTR1_TIM12RST_Msk ) + +#define RCC_APB1RSTR1_TIM7RST_Pos ( 5U ) +#define RCC_APB1RSTR1_TIM7RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM7RST_Pos ) +#define RCC_APB1RSTR1_TIM7RST ( RCC_APB1RSTR1_TIM7RST_Msk ) + +#define RCC_APB1RSTR1_TIM6RST_Pos ( 4U ) +#define RCC_APB1RSTR1_TIM6RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM6RST_Pos ) +#define RCC_APB1RSTR1_TIM6RST ( RCC_APB1RSTR1_TIM6RST_Msk ) + +#define RCC_APB1RSTR1_TIM5RST_Pos ( 3U ) +#define RCC_APB1RSTR1_TIM5RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM5RST_Pos ) +#define RCC_APB1RSTR1_TIM5RST ( RCC_APB1RSTR1_TIM5RST_Msk ) + +#define RCC_APB1RSTR1_TIM4RST_Pos ( 2U ) +#define RCC_APB1RSTR1_TIM4RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM4RST_Pos ) +#define RCC_APB1RSTR1_TIM4RST ( RCC_APB1RSTR1_TIM4RST_Msk ) + +#define RCC_APB1RSTR1_TIM3RST_Pos ( 1U ) +#define RCC_APB1RSTR1_TIM3RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM3RST_Pos ) +#define RCC_APB1RSTR1_TIM3RST ( RCC_APB1RSTR1_TIM3RST_Msk ) + +#define RCC_APB1RSTR1_TIM2RST_Pos ( 0U ) +#define RCC_APB1RSTR1_TIM2RST_Msk ( 0x1UL << RCC_APB1RSTR1_TIM2RST_Pos ) +#define RCC_APB1RSTR1_TIM2RST ( RCC_APB1RSTR1_TIM2RST_Msk ) + + +/*************** Bits definition for RCC_APB1RSTR2 **********************/ + +#define RCC_APB1RSTR2_EFUSE2RST_Pos ( 7U ) +#define RCC_APB1RSTR2_EFUSE2RST_Msk ( 0x1UL << RCC_APB1RSTR2_EFUSE2RST_Pos ) +#define RCC_APB1RSTR2_EFUSE2RST ( RCC_APB1RSTR2_EFUSE2RST_Msk ) + +#define RCC_APB1RSTR2_EFUSE1RST_Pos ( 6U ) +#define RCC_APB1RSTR2_EFUSE1RST_Msk ( 0x1UL << RCC_APB1RSTR2_EFUSE1RST_Pos ) +#define RCC_APB1RSTR2_EFUSE1RST ( RCC_APB1RSTR2_EFUSE1RST_Msk ) + +#define RCC_APB1RSTR2_TIM26RST_Pos ( 5U ) +#define RCC_APB1RSTR2_TIM26RST_Msk ( 0x1UL << RCC_APB1RSTR2_TIM26RST_Pos ) +#define RCC_APB1RSTR2_TIM26RST ( RCC_APB1RSTR2_TIM26RST_Msk ) + +#define RCC_APB1RSTR2_TIM25RST_Pos ( 4U ) +#define RCC_APB1RSTR2_TIM25RST_Msk ( 0x1UL << RCC_APB1RSTR2_TIM25RST_Pos ) +#define RCC_APB1RSTR2_TIM25RST ( RCC_APB1RSTR2_TIM25RST_Msk ) + +#define RCC_APB1RSTR2_USART8RST_Pos ( 3U ) +#define RCC_APB1RSTR2_USART8RST_Msk ( 0x1UL << RCC_APB1RSTR2_USART8RST_Pos ) +#define RCC_APB1RSTR2_USART8RST ( RCC_APB1RSTR2_USART8RST_Msk ) + +#define RCC_APB1RSTR2_USART7RST_Pos ( 2U ) +#define RCC_APB1RSTR2_USART7RST_Msk ( 0x1UL << RCC_APB1RSTR2_USART7RST_Pos ) +#define RCC_APB1RSTR2_USART7RST ( RCC_APB1RSTR2_USART7RST_Msk ) + +#define RCC_APB1RSTR2_LPTIM2RST_Pos ( 1U ) +#define RCC_APB1RSTR2_LPTIM2RST_Msk ( 0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos ) +#define RCC_APB1RSTR2_LPTIM2RST ( RCC_APB1RSTR2_LPTIM2RST_Msk ) + + +/*************** Bits definition for RCC_APB2RSTR **********************/ + +#define RCC_APB2RSTR_USART10RST_Pos ( 31U ) +#define RCC_APB2RSTR_USART10RST_Msk ( 0x1UL << RCC_APB2RSTR_USART10RST_Pos ) +#define RCC_APB2RSTR_USART10RST ( RCC_APB2RSTR_USART10RST_Msk ) + +#define RCC_APB2RSTR_USART9RST_Pos ( 30U ) +#define RCC_APB2RSTR_USART9RST_Msk ( 0x1UL << RCC_APB2RSTR_USART9RST_Pos ) +#define RCC_APB2RSTR_USART9RST ( RCC_APB2RSTR_USART9RST_Msk ) + +#define RCC_APB2RSTR_TIM24RST_Pos ( 29U ) +#define RCC_APB2RSTR_TIM24RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM24RST_Pos ) +#define RCC_APB2RSTR_TIM24RST ( RCC_APB2RSTR_TIM24RST_Msk ) + +#define RCC_APB2RSTR_TIM23RST_Pos ( 28U ) +#define RCC_APB2RSTR_TIM23RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM23RST_Pos ) +#define RCC_APB2RSTR_TIM23RST ( RCC_APB2RSTR_TIM23RST_Msk ) + +#define RCC_APB2RSTR_TIM22RST_Pos ( 27U ) +#define RCC_APB2RSTR_TIM22RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM22RST_Pos ) +#define RCC_APB2RSTR_TIM22RST ( RCC_APB2RSTR_TIM22RST_Msk ) + +#define RCC_APB2RSTR_TIM21RST_Pos ( 26U ) +#define RCC_APB2RSTR_TIM21RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM21RST_Pos ) +#define RCC_APB2RSTR_TIM21RST ( RCC_APB2RSTR_TIM21RST_Msk ) + +#define RCC_APB2RSTR_TIM19RST_Pos ( 25U ) +#define RCC_APB2RSTR_TIM19RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM19RST_Pos ) +#define RCC_APB2RSTR_TIM19RST ( RCC_APB2RSTR_TIM19RST_Msk ) + +#define RCC_APB2RSTR_TIM18RST_Pos ( 24U ) +#define RCC_APB2RSTR_TIM18RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM18RST_Pos ) +#define RCC_APB2RSTR_TIM18RST ( RCC_APB2RSTR_TIM18RST_Msk ) + +#define RCC_APB2RSTR_TIM11RST_Pos ( 23U ) +#define RCC_APB2RSTR_TIM11RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM11RST_Pos ) +#define RCC_APB2RSTR_TIM11RST ( RCC_APB2RSTR_TIM11RST_Msk ) + +#define RCC_APB2RSTR_TIM10RST_Pos ( 22U ) +#define RCC_APB2RSTR_TIM10RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM10RST_Pos ) +#define RCC_APB2RSTR_TIM10RST ( RCC_APB2RSTR_TIM10RST_Msk ) + +#define RCC_APB2RSTR_TIM9RST_Pos ( 21U ) +#define RCC_APB2RSTR_TIM9RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM9RST_Pos ) +#define RCC_APB2RSTR_TIM9RST ( RCC_APB2RSTR_TIM9RST_Msk ) + +#define RCC_APB2RSTR_LTDCRST_Pos ( 19U ) +#define RCC_APB2RSTR_LTDCRST_Msk ( 0x1UL << RCC_APB2RSTR_LTDCRST_Pos ) +#define RCC_APB2RSTR_LTDCRST ( RCC_APB2RSTR_LTDCRST_Msk ) + +#define RCC_APB2RSTR_TKEYRST_Pos ( 18U ) +#define RCC_APB2RSTR_TKEYRST_Msk ( 0x1UL << RCC_APB2RSTR_TKEYRST_Pos ) +#define RCC_APB2RSTR_TKEYRST ( RCC_APB2RSTR_TKEYRST_Msk ) + +#define RCC_APB2RSTR_TIM20RST_Pos ( 15U ) +#define RCC_APB2RSTR_TIM20RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM20RST_Pos ) +#define RCC_APB2RSTR_TIM20RST ( RCC_APB2RSTR_TIM20RST_Msk ) + +#define RCC_APB2RSTR_TIM17RST_Pos ( 13U ) +#define RCC_APB2RSTR_TIM17RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM17RST_Pos ) +#define RCC_APB2RSTR_TIM17RST ( RCC_APB2RSTR_TIM17RST_Msk ) + +#define RCC_APB2RSTR_TIM16RST_Pos ( 12U ) +#define RCC_APB2RSTR_TIM16RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM16RST_Pos ) +#define RCC_APB2RSTR_TIM16RST ( RCC_APB2RSTR_TIM16RST_Msk ) + +#define RCC_APB2RSTR_TIM15RST_Pos ( 11U ) +#define RCC_APB2RSTR_TIM15RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM15RST_Pos ) +#define RCC_APB2RSTR_TIM15RST ( RCC_APB2RSTR_TIM15RST_Msk ) + +#define RCC_APB2RSTR_USART6RST_Pos ( 10U ) +#define RCC_APB2RSTR_USART6RST_Msk ( 0x1UL << RCC_APB2RSTR_USART6RST_Pos ) +#define RCC_APB2RSTR_USART6RST ( RCC_APB2RSTR_USART6RST_Msk ) + +#define RCC_APB2RSTR_USART1RST_Pos ( 9U ) +#define RCC_APB2RSTR_USART1RST_Msk ( 0x1UL << RCC_APB2RSTR_USART1RST_Pos ) +#define RCC_APB2RSTR_USART1RST ( RCC_APB2RSTR_USART1RST_Msk ) + +#define RCC_APB2RSTR_TIM8RST_Pos ( 8U ) +#define RCC_APB2RSTR_TIM8RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM8RST_Pos ) +#define RCC_APB2RSTR_TIM8RST ( RCC_APB2RSTR_TIM8RST_Msk ) + +#define RCC_APB2RSTR_TIM1RST_Pos ( 6U ) +#define RCC_APB2RSTR_TIM1RST_Msk ( 0x1UL << RCC_APB2RSTR_TIM1RST_Pos ) +#define RCC_APB2RSTR_TIM1RST ( RCC_APB2RSTR_TIM1RST_Msk ) + +#define RCC_APB2RSTR_EXTIRST_Pos ( 4U ) +#define RCC_APB2RSTR_EXTIRST_Msk ( 0x1UL << RCC_APB2RSTR_EXTIRST_Pos ) +#define RCC_APB2RSTR_EXTIRST ( RCC_APB2RSTR_EXTIRST_Msk ) + +#define RCC_APB2RSTR_CMP1RST_A_Pos ( 2U ) +#define RCC_APB2RSTR_CMP1RST_A_Msk ( 0x1UL << RCC_APB2RSTR_CMP1RST_A_Pos ) +#define RCC_APB2RSTR_CMP1RST_A ( RCC_APB2RSTR_CMP1RST_A_Msk ) + +#define RCC_APB2RSTR_SYSCFGRST_Pos ( 0U ) +#define RCC_APB2RSTR_SYSCFGRST_Msk ( 0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos ) +#define RCC_APB2RSTR_SYSCFGRST ( RCC_APB2RSTR_SYSCFGRST_Msk ) + + +/*************** Bits definition for RCC_APB3RSTR **********************/ + +#define RCC_APB3RSTR_LPTIM6RST_Pos ( 3U ) +#define RCC_APB3RSTR_LPTIM6RST_Msk ( 0x1UL << RCC_APB3RSTR_LPTIM6RST_Pos ) +#define RCC_APB3RSTR_LPTIM6RST ( RCC_APB3RSTR_LPTIM6RST_Msk ) + +#define RCC_APB3RSTR_LPTIM5RST_Pos ( 2U ) +#define RCC_APB3RSTR_LPTIM5RST_Msk ( 0x1UL << RCC_APB3RSTR_LPTIM5RST_Pos ) +#define RCC_APB3RSTR_LPTIM5RST ( RCC_APB3RSTR_LPTIM5RST_Msk ) + +#define RCC_APB3RSTR_LPTIM4RST_Pos ( 1U ) +#define RCC_APB3RSTR_LPTIM4RST_Msk ( 0x1UL << RCC_APB3RSTR_LPTIM4RST_Pos ) +#define RCC_APB3RSTR_LPTIM4RST ( RCC_APB3RSTR_LPTIM4RST_Msk ) + +#define RCC_APB3RSTR_LPTIM3RST_Pos ( 0U ) +#define RCC_APB3RSTR_LPTIM3RST_Msk ( 0x1UL << RCC_APB3RSTR_LPTIM3RST_Pos ) +#define RCC_APB3RSTR_LPTIM3RST ( RCC_APB3RSTR_LPTIM3RST_Msk ) + + +/*************** Bits definition for RCC_APB4RSTR **********************/ + +#define RCC_APB4RSTR_DPWM6RST_Pos ( 17U ) +#define RCC_APB4RSTR_DPWM6RST_Msk ( 0x1UL << RCC_APB4RSTR_DPWM6RST_Pos ) +#define RCC_APB4RSTR_DPWM6RST ( RCC_APB4RSTR_DPWM6RST_Msk ) + +#define RCC_APB4RSTR_DPWM5RST_Pos ( 16U ) +#define RCC_APB4RSTR_DPWM5RST_Msk ( 0x1UL << RCC_APB4RSTR_DPWM5RST_Pos ) +#define RCC_APB4RSTR_DPWM5RST ( RCC_APB4RSTR_DPWM5RST_Msk ) + +#define RCC_APB4RSTR_SPWM6RST_Pos ( 15U ) +#define RCC_APB4RSTR_SPWM6RST_Msk ( 0x1UL << RCC_APB4RSTR_SPWM6RST_Pos ) +#define RCC_APB4RSTR_SPWM6RST ( RCC_APB4RSTR_SPWM6RST_Msk ) + +#define RCC_APB4RSTR_SPWM5RST_Pos ( 14U ) +#define RCC_APB4RSTR_SPWM5RST_Msk ( 0x1UL << RCC_APB4RSTR_SPWM5RST_Pos ) +#define RCC_APB4RSTR_SPWM5RST ( RCC_APB4RSTR_SPWM5RST_Msk ) + +#define RCC_APB4RSTR_SPWM4RST_Pos ( 13U ) +#define RCC_APB4RSTR_SPWM4RST_Msk ( 0x1UL << RCC_APB4RSTR_SPWM4RST_Pos ) +#define RCC_APB4RSTR_SPWM4RST ( RCC_APB4RSTR_SPWM4RST_Msk ) + +#define RCC_APB4RSTR_SPWM3RST_Pos ( 12U ) +#define RCC_APB4RSTR_SPWM3RST_Msk ( 0x1UL << RCC_APB4RSTR_SPWM3RST_Pos ) +#define RCC_APB4RSTR_SPWM3RST ( RCC_APB4RSTR_SPWM3RST_Msk ) + +#define RCC_APB4RSTR_MDACRST_Pos ( 8U ) +#define RCC_APB4RSTR_MDACRST_Msk ( 0x1UL << RCC_APB4RSTR_MDACRST_Pos ) +#define RCC_APB4RSTR_MDACRST ( RCC_APB4RSTR_MDACRST_Msk ) + +#define RCC_APB4RSTR_LPTRST_Pos ( 7U ) +#define RCC_APB4RSTR_LPTRST_Msk ( 0x1UL << RCC_APB4RSTR_LPTRST_Pos ) +#define RCC_APB4RSTR_LPTRST ( RCC_APB4RSTR_LPTRST_Msk ) + +#define RCC_APB4RSTR_PNDLRST_Pos ( 6U ) +#define RCC_APB4RSTR_PNDLRST_Msk ( 0x1UL << RCC_APB4RSTR_PNDLRST_Pos ) +#define RCC_APB4RSTR_PNDLRST ( RCC_APB4RSTR_PNDLRST_Msk ) + +#define RCC_APB4RSTR_DPWM4RST_Pos ( 5U ) +#define RCC_APB4RSTR_DPWM4RST_Msk ( 0x1UL << RCC_APB4RSTR_DPWM4RST_Pos ) +#define RCC_APB4RSTR_DPWM4RST ( RCC_APB4RSTR_DPWM4RST_Msk ) + +#define RCC_APB4RSTR_DPWM3RST_Pos ( 4U ) +#define RCC_APB4RSTR_DPWM3RST_Msk ( 0x1UL << RCC_APB4RSTR_DPWM3RST_Pos ) +#define RCC_APB4RSTR_DPWM3RST ( RCC_APB4RSTR_DPWM3RST_Msk ) + +#define RCC_APB4RSTR_DPWM2RST_Pos ( 3U ) +#define RCC_APB4RSTR_DPWM2RST_Msk ( 0x1UL << RCC_APB4RSTR_DPWM2RST_Pos ) +#define RCC_APB4RSTR_DPWM2RST ( RCC_APB4RSTR_DPWM2RST_Msk ) + +#define RCC_APB4RSTR_DPWM1RST_Pos ( 2U ) +#define RCC_APB4RSTR_DPWM1RST_Msk ( 0x1UL << RCC_APB4RSTR_DPWM1RST_Pos ) +#define RCC_APB4RSTR_DPWM1RST ( RCC_APB4RSTR_DPWM1RST_Msk ) + +#define RCC_APB4RSTR_SPWM2RST_Pos ( 1U ) +#define RCC_APB4RSTR_SPWM2RST_Msk ( 0x1UL << RCC_APB4RSTR_SPWM2RST_Pos ) +#define RCC_APB4RSTR_SPWM2RST ( RCC_APB4RSTR_SPWM2RST_Msk ) + +#define RCC_APB4RSTR_SPWM1RST_Pos ( 0U ) +#define RCC_APB4RSTR_SPWM1RST_Msk ( 0x1UL << RCC_APB4RSTR_SPWM1RST_Pos ) +#define RCC_APB4RSTR_SPWM1RST ( RCC_APB4RSTR_SPWM1RST_Msk ) + + +/*************** Bits definition for RCC_CCR1 **********************/ + +#define RCC_CCR1_SYSCLKSEL_Pos ( 0U ) +#define RCC_CCR1_SYSCLKSEL_Msk ( 0x3UL << RCC_CCR1_SYSCLKSEL_Pos ) +#define RCC_CCR1_SYSCLKSEL ( RCC_CCR1_SYSCLKSEL_Msk ) +#define RCC_CCR1_SYSCLKSEL_0 ( 0x1UL << RCC_CCR1_SYSCLKSEL_Pos ) +#define RCC_CCR1_SYSCLKSEL_1 ( 0x2UL << RCC_CCR1_SYSCLKSEL_Pos ) + + +/*************** Bits definition for RCC_CCR2 **********************/ + +#define RCC_CCR2_DIVDONE_Pos ( 31U ) +#define RCC_CCR2_DIVDONE_Msk ( 0x1UL << RCC_CCR2_DIVDONE_Pos ) +#define RCC_CCR2_DIVDONE ( RCC_CCR2_DIVDONE_Msk ) + +#define RCC_CCR2_HRNGSDIV_Pos ( 24U ) +#define RCC_CCR2_HRNGSDIV_Msk ( 0x7FUL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV ( RCC_CCR2_HRNGSDIV_Msk ) +#define RCC_CCR2_HRNGSDIV_0 ( 0x01UL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV_1 ( 0x02UL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV_2 ( 0x04UL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV_3 ( 0x08UL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV_4 ( 0x10UL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV_5 ( 0x20UL << RCC_CCR2_HRNGSDIV_Pos ) +#define RCC_CCR2_HRNGSDIV_6 ( 0x40UL << RCC_CCR2_HRNGSDIV_Pos ) + +#define RCC_CCR2_FLTCLKSEL_Pos ( 20U ) +#define RCC_CCR2_FLTCLKSEL_Msk ( 0x1UL << RCC_CCR2_FLTCLKSEL_Pos ) +#define RCC_CCR2_FLTCLKSEL ( RCC_CCR2_FLTCLKSEL_Msk ) + +#define RCC_CCR2_PCLK4DIV_Pos ( 17U ) +#define RCC_CCR2_PCLK4DIV_Msk ( 0x7UL << RCC_CCR2_PCLK4DIV_Pos ) +#define RCC_CCR2_PCLK4DIV ( RCC_CCR2_PCLK4DIV_Msk ) +#define RCC_CCR2_PCLK4DIV_0 ( 0x1UL << RCC_CCR2_PCLK4DIV_Pos ) +#define RCC_CCR2_PCLK4DIV_1 ( 0x2UL << RCC_CCR2_PCLK4DIV_Pos ) +#define RCC_CCR2_PCLK4DIV_2 ( 0x4UL << RCC_CCR2_PCLK4DIV_Pos ) + +#define RCC_CCR2_PCLK3DIV_Pos ( 14U ) +#define RCC_CCR2_PCLK3DIV_Msk ( 0x7UL << RCC_CCR2_PCLK3DIV_Pos ) +#define RCC_CCR2_PCLK3DIV ( RCC_CCR2_PCLK3DIV_Msk ) +#define RCC_CCR2_PCLK3DIV_0 ( 0x1UL << RCC_CCR2_PCLK3DIV_Pos ) +#define RCC_CCR2_PCLK3DIV_1 ( 0x2UL << RCC_CCR2_PCLK3DIV_Pos ) +#define RCC_CCR2_PCLK3DIV_2 ( 0x4UL << RCC_CCR2_PCLK3DIV_Pos ) + +#define RCC_CCR2_PCLK2DIV_Pos ( 11U ) +#define RCC_CCR2_PCLK2DIV_Msk ( 0x7UL << RCC_CCR2_PCLK2DIV_Pos ) +#define RCC_CCR2_PCLK2DIV ( RCC_CCR2_PCLK2DIV_Msk ) +#define RCC_CCR2_PCLK2DIV_0 ( 0x1UL << RCC_CCR2_PCLK2DIV_Pos ) +#define RCC_CCR2_PCLK2DIV_1 ( 0x2UL << RCC_CCR2_PCLK2DIV_Pos ) +#define RCC_CCR2_PCLK2DIV_2 ( 0x4UL << RCC_CCR2_PCLK2DIV_Pos ) + +#define RCC_CCR2_PCLK1DIV_Pos ( 8U ) +#define RCC_CCR2_PCLK1DIV_Msk ( 0x7UL << RCC_CCR2_PCLK1DIV_Pos ) +#define RCC_CCR2_PCLK1DIV ( RCC_CCR2_PCLK1DIV_Msk ) +#define RCC_CCR2_PCLK1DIV_0 ( 0x1UL << RCC_CCR2_PCLK1DIV_Pos ) +#define RCC_CCR2_PCLK1DIV_1 ( 0x2UL << RCC_CCR2_PCLK1DIV_Pos ) +#define RCC_CCR2_PCLK1DIV_2 ( 0x4UL << RCC_CCR2_PCLK1DIV_Pos ) + +#define RCC_CCR2_SYSDIV1_Pos ( 4U ) +#define RCC_CCR2_SYSDIV1_Msk ( 0xFUL << RCC_CCR2_SYSDIV1_Pos ) +#define RCC_CCR2_SYSDIV1 ( RCC_CCR2_SYSDIV1_Msk ) +#define RCC_CCR2_SYSDIV1_0 ( 0x1UL << RCC_CCR2_SYSDIV1_Pos ) +#define RCC_CCR2_SYSDIV1_1 ( 0x2UL << RCC_CCR2_SYSDIV1_Pos ) +#define RCC_CCR2_SYSDIV1_2 ( 0x4UL << RCC_CCR2_SYSDIV1_Pos ) +#define RCC_CCR2_SYSDIV1_3 ( 0x8UL << RCC_CCR2_SYSDIV1_Pos ) + +#define RCC_CCR2_SYSDIV0_Pos ( 0U ) +#define RCC_CCR2_SYSDIV0_Msk ( 0xFUL << RCC_CCR2_SYSDIV0_Pos ) +#define RCC_CCR2_SYSDIV0 ( RCC_CCR2_SYSDIV0_Msk ) +#define RCC_CCR2_SYSDIV0_0 ( 0x1UL << RCC_CCR2_SYSDIV0_Pos ) +#define RCC_CCR2_SYSDIV0_1 ( 0x2UL << RCC_CCR2_SYSDIV0_Pos ) +#define RCC_CCR2_SYSDIV0_2 ( 0x4UL << RCC_CCR2_SYSDIV0_Pos ) +#define RCC_CCR2_SYSDIV0_3 ( 0x8UL << RCC_CCR2_SYSDIV0_Pos ) + + +/*************** Bits definition for RCC_PERCFGR **********************/ + +#define RCC_PERCFGR_LPUART1CKS_Pos ( 26U ) +#define RCC_PERCFGR_LPUART1CKS_Msk ( 0x3UL << RCC_PERCFGR_LPUART1CKS_Pos ) +#define RCC_PERCFGR_LPUART1CKS ( RCC_PERCFGR_LPUART1CKS_Msk ) +#define RCC_PERCFGR_LPUART1CKS_0 ( 0x1UL << RCC_PERCFGR_LPUART1CKS_Pos ) +#define RCC_PERCFGR_LPUART1CKS_1 ( 0x2UL << RCC_PERCFGR_LPUART1CKS_Pos ) + +#define RCC_PERCFGR_LPUART1DIV_Pos ( 24U ) +#define RCC_PERCFGR_LPUART1DIV_Msk ( 0x3UL << RCC_PERCFGR_LPUART1DIV_Pos ) +#define RCC_PERCFGR_LPUART1DIV ( RCC_PERCFGR_LPUART1DIV_Msk ) +#define RCC_PERCFGR_LPUART1DIV_0 ( 0x1UL << RCC_PERCFGR_LPUART1DIV_Pos ) +#define RCC_PERCFGR_LPUART1DIV_1 ( 0x2UL << RCC_PERCFGR_LPUART1DIV_Pos ) + +#define RCC_PERCFGR_LPTIM6CKS_Pos ( 22U ) +#define RCC_PERCFGR_LPTIM6CKS_Msk ( 0x3UL << RCC_PERCFGR_LPTIM6CKS_Pos ) +#define RCC_PERCFGR_LPTIM6CKS ( RCC_PERCFGR_LPTIM6CKS_Msk ) +#define RCC_PERCFGR_LPTIM6CKS_0 ( 0x1UL << RCC_PERCFGR_LPTIM6CKS_Pos ) +#define RCC_PERCFGR_LPTIM6CKS_1 ( 0x2UL << RCC_PERCFGR_LPTIM6CKS_Pos ) + +#define RCC_PERCFGR_LPTIM345CKS_Pos ( 20U ) +#define RCC_PERCFGR_LPTIM345CKS_Msk ( 0x3UL << RCC_PERCFGR_LPTIM345CKS_Pos ) +#define RCC_PERCFGR_LPTIM345CKS ( RCC_PERCFGR_LPTIM345CKS_Msk ) +#define RCC_PERCFGR_LPTIM345CKS_0 ( 0x1UL << RCC_PERCFGR_LPTIM345CKS_Pos ) +#define RCC_PERCFGR_LPTIM345CKS_1 ( 0x2UL << RCC_PERCFGR_LPTIM345CKS_Pos ) + +#define RCC_PERCFGR_LPTIM2CKS_Pos ( 18U ) +#define RCC_PERCFGR_LPTIM2CKS_Msk ( 0x3UL << RCC_PERCFGR_LPTIM2CKS_Pos ) +#define RCC_PERCFGR_LPTIM2CKS ( RCC_PERCFGR_LPTIM2CKS_Msk ) +#define RCC_PERCFGR_LPTIM2CKS_0 ( 0x1UL << RCC_PERCFGR_LPTIM2CKS_Pos ) +#define RCC_PERCFGR_LPTIM2CKS_1 ( 0x2UL << RCC_PERCFGR_LPTIM2CKS_Pos ) + +#define RCC_PERCFGR_LPTIM1CKS_Pos ( 16U ) +#define RCC_PERCFGR_LPTIM1CKS_Msk ( 0x3UL << RCC_PERCFGR_LPTIM1CKS_Pos ) +#define RCC_PERCFGR_LPTIM1CKS ( RCC_PERCFGR_LPTIM1CKS_Msk ) +#define RCC_PERCFGR_LPTIM1CKS_0 ( 0x1UL << RCC_PERCFGR_LPTIM1CKS_Pos ) +#define RCC_PERCFGR_LPTIM1CKS_1 ( 0x2UL << RCC_PERCFGR_LPTIM1CKS_Pos ) + +#define RCC_PERCFGR_SDMMCCKS_Pos ( 11U ) +#define RCC_PERCFGR_SDMMCCKS_Msk ( 0x1UL << RCC_PERCFGR_SDMMCCKS_Pos ) +#define RCC_PERCFGR_SDMMCCKS ( RCC_PERCFGR_SDMMCCKS_Msk ) + +#define RCC_PERCFGR_SDMMCSCKS_Pos ( 8U ) +#define RCC_PERCFGR_SDMMCSCKS_Msk ( 0x3UL << RCC_PERCFGR_SDMMCSCKS_Pos ) +#define RCC_PERCFGR_SDMMCSCKS ( RCC_PERCFGR_SDMMCSCKS_Msk ) +#define RCC_PERCFGR_SDMMCSCKS_0 ( 0x1UL << RCC_PERCFGR_SDMMCSCKS_Pos ) +#define RCC_PERCFGR_SDMMCSCKS_1 ( 0x2UL << RCC_PERCFGR_SDMMCSCKS_Pos ) + +/*************** Bits definition for RCC_CIR **********************/ + +#define RCC_CIR_XTLSDF_Pos ( 31U ) +#define RCC_CIR_XTLSDF_Msk ( 0x1UL << RCC_CIR_XTLSDF_Pos ) +#define RCC_CIR_XTLSDF ( RCC_CIR_XTLSDF_Msk ) + +#define RCC_CIR_XTLSDIC_Pos ( 29U ) +#define RCC_CIR_XTLSDIC_Msk ( 0x1UL << RCC_CIR_XTLSDIC_Pos ) +#define RCC_CIR_XTLSDIC ( RCC_CIR_XTLSDIC_Msk ) + +#define RCC_CIR_XTLSDIE_Pos ( 28U ) +#define RCC_CIR_XTLSDIE_Msk ( 0x1UL << RCC_CIR_XTLSDIE_Pos ) +#define RCC_CIR_XTLSDIE ( RCC_CIR_XTLSDIE_Msk ) + +#define RCC_CIR_XTHSDF_Pos ( 27U ) +#define RCC_CIR_XTHSDF_Msk ( 0x1UL << RCC_CIR_XTHSDF_Pos ) +#define RCC_CIR_XTHSDF ( RCC_CIR_XTHSDF_Msk ) + +#define RCC_CIR_XTHSDIC_Pos ( 25U ) +#define RCC_CIR_XTHSDIC_Msk ( 0x1UL << RCC_CIR_XTHSDIC_Pos ) +#define RCC_CIR_XTHSDIC ( RCC_CIR_XTHSDIC_Msk ) + +#define RCC_CIR_XTHSDIE_Pos ( 24U ) +#define RCC_CIR_XTHSDIE_Msk ( 0x1UL << RCC_CIR_XTHSDIE_Pos ) +#define RCC_CIR_XTHSDIE ( RCC_CIR_XTHSDIE_Msk ) + +#define RCC_CIR_PLL3LOCKIC_Pos ( 22U ) +#define RCC_CIR_PLL3LOCKIC_Msk ( 0x1UL << RCC_CIR_PLL3LOCKIC_Pos ) +#define RCC_CIR_PLL3LOCKIC ( RCC_CIR_PLL3LOCKIC_Msk ) + +#define RCC_CIR_PLL2LOCKIC_Pos ( 21U ) +#define RCC_CIR_PLL2LOCKIC_Msk ( 0x1UL << RCC_CIR_PLL2LOCKIC_Pos ) +#define RCC_CIR_PLL2LOCKIC ( RCC_CIR_PLL2LOCKIC_Msk ) + +#define RCC_CIR_PLL1LOCKIC_Pos ( 20U ) +#define RCC_CIR_PLL1LOCKIC_Msk ( 0x1UL << RCC_CIR_PLL1LOCKIC_Pos ) +#define RCC_CIR_PLL1LOCKIC ( RCC_CIR_PLL1LOCKIC_Msk ) + +#define RCC_CIR_XTHRDYIC_Pos ( 19U ) +#define RCC_CIR_XTHRDYIC_Msk ( 0x1UL << RCC_CIR_XTHRDYIC_Pos ) +#define RCC_CIR_XTHRDYIC ( RCC_CIR_XTHRDYIC_Msk ) + +#define RCC_CIR_RCHRDYIC_Pos ( 18U ) +#define RCC_CIR_RCHRDYIC_Msk ( 0x1UL << RCC_CIR_RCHRDYIC_Pos ) +#define RCC_CIR_RCHRDYIC ( RCC_CIR_RCHRDYIC_Msk ) + +#define RCC_CIR_XTLRDYIC_Pos ( 17U ) +#define RCC_CIR_XTLRDYIC_Msk ( 0x1UL << RCC_CIR_XTLRDYIC_Pos ) +#define RCC_CIR_XTLRDYIC ( RCC_CIR_XTLRDYIC_Msk ) + +#define RCC_CIR_RCLRDYIC_Pos ( 16U ) +#define RCC_CIR_RCLRDYIC_Msk ( 0x1UL << RCC_CIR_RCLRDYIC_Pos ) +#define RCC_CIR_RCLRDYIC ( RCC_CIR_RCLRDYIC_Msk ) + +#define RCC_CIR_PLL3LOCKIE_Pos ( 14U ) +#define RCC_CIR_PLL3LOCKIE_Msk ( 0x1UL << RCC_CIR_PLL3LOCKIE_Pos ) +#define RCC_CIR_PLL3LOCKIE ( RCC_CIR_PLL3LOCKIE_Msk ) + +#define RCC_CIR_PLL2LOCKIE_Pos ( 13U ) +#define RCC_CIR_PLL2LOCKIE_Msk ( 0x1UL << RCC_CIR_PLL2LOCKIE_Pos ) +#define RCC_CIR_PLL2LOCKIE ( RCC_CIR_PLL2LOCKIE_Msk ) + +#define RCC_CIR_PLL1LOCKIE_Pos ( 12U ) +#define RCC_CIR_PLL1LOCKIE_Msk ( 0x1UL << RCC_CIR_PLL1LOCKIE_Pos ) +#define RCC_CIR_PLL1LOCKIE ( RCC_CIR_PLL1LOCKIE_Msk ) + +#define RCC_CIR_XTHRDYIE_Pos ( 11U ) +#define RCC_CIR_XTHRDYIE_Msk ( 0x1UL << RCC_CIR_XTHRDYIE_Pos ) +#define RCC_CIR_XTHRDYIE ( RCC_CIR_XTHRDYIE_Msk ) + +#define RCC_CIR_RCHRDYIE_Pos ( 10U ) +#define RCC_CIR_RCHRDYIE_Msk ( 0x1UL << RCC_CIR_RCHRDYIE_Pos ) +#define RCC_CIR_RCHRDYIE ( RCC_CIR_RCHRDYIE_Msk ) + +#define RCC_CIR_XTLRDYIE_Pos ( 9U ) +#define RCC_CIR_XTLRDYIE_Msk ( 0x1UL << RCC_CIR_XTLRDYIE_Pos ) +#define RCC_CIR_XTLRDYIE ( RCC_CIR_XTLRDYIE_Msk ) + +#define RCC_CIR_RCLRDYIE_Pos ( 8U ) +#define RCC_CIR_RCLRDYIE_Msk ( 0x1UL << RCC_CIR_RCLRDYIE_Pos ) +#define RCC_CIR_RCLRDYIE ( RCC_CIR_RCLRDYIE_Msk ) + +#define RCC_CIR_PLL3LOCKIF_Pos ( 6U ) +#define RCC_CIR_PLL3LOCKIF_Msk ( 0x1UL << RCC_CIR_PLL3LOCKIF_Pos ) +#define RCC_CIR_PLL3LOCKIF ( RCC_CIR_PLL3LOCKIF_Msk ) + +#define RCC_CIR_PLL2LOCKIF_Pos ( 5U ) +#define RCC_CIR_PLL2LOCKIF_Msk ( 0x1UL << RCC_CIR_PLL2LOCKIF_Pos ) +#define RCC_CIR_PLL2LOCKIF ( RCC_CIR_PLL2LOCKIF_Msk ) + +#define RCC_CIR_PLL1LOCKIF_Pos ( 4U ) +#define RCC_CIR_PLL1LOCKIF_Msk ( 0x1UL << RCC_CIR_PLL1LOCKIF_Pos ) +#define RCC_CIR_PLL1LOCKIF ( RCC_CIR_PLL1LOCKIF_Msk ) + +#define RCC_CIR_XTHRDYIF_Pos ( 3U ) +#define RCC_CIR_XTHRDYIF_Msk ( 0x1UL << RCC_CIR_XTHRDYIF_Pos ) +#define RCC_CIR_XTHRDYIF ( RCC_CIR_XTHRDYIF_Msk ) + +#define RCC_CIR_RCHRDYIF_Pos ( 2U ) +#define RCC_CIR_RCHRDYIF_Msk ( 0x1UL << RCC_CIR_RCHRDYIF_Pos ) +#define RCC_CIR_RCHRDYIF ( RCC_CIR_RCHRDYIF_Msk ) + +#define RCC_CIR_XTLRDYIF_Pos ( 1U ) +#define RCC_CIR_XTLRDYIF_Msk ( 0x1UL << RCC_CIR_XTLRDYIF_Pos ) +#define RCC_CIR_XTLRDYIF ( RCC_CIR_XTLRDYIF_Msk ) + +#define RCC_CIR_RCLRDYIF_Pos ( 0U ) +#define RCC_CIR_RCLRDYIF_Msk ( 0x1UL << RCC_CIR_RCLRDYIF_Pos ) +#define RCC_CIR_RCLRDYIF ( RCC_CIR_RCLRDYIF_Msk ) + + +/*************** Bits definition for RCC_AHB1CKENR **********************/ + +#define RCC_AHB1CKENR_SRAM3CKEN_Pos ( 31U ) +#define RCC_AHB1CKENR_SRAM3CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SRAM3CKEN_Pos ) +#define RCC_AHB1CKENR_SRAM3CKEN ( RCC_AHB1CKENR_SRAM3CKEN_Msk ) + +#define RCC_AHB1CKENR_SRAM2CKEN_Pos ( 30U ) +#define RCC_AHB1CKENR_SRAM2CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SRAM2CKEN_Pos ) +#define RCC_AHB1CKENR_SRAM2CKEN ( RCC_AHB1CKENR_SRAM2CKEN_Msk ) + +#define RCC_AHB1CKENR_SRAM1CKEN_Pos ( 29U ) +#define RCC_AHB1CKENR_SRAM1CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SRAM1CKEN_Pos ) +#define RCC_AHB1CKENR_SRAM1CKEN ( RCC_AHB1CKENR_SRAM1CKEN_Msk ) + +#define RCC_AHB1CKENR_ROMCKEN_Pos ( 28U ) +#define RCC_AHB1CKENR_ROMCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_ROMCKEN_Pos ) +#define RCC_AHB1CKENR_ROMCKEN ( RCC_AHB1CKENR_ROMCKEN_Msk ) + +#define RCC_AHB1CKENR_BKPSRAMCKEN_Pos ( 27U ) +#define RCC_AHB1CKENR_BKPSRAMCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_BKPSRAMCKEN_Pos ) +#define RCC_AHB1CKENR_BKPSRAMCKEN ( RCC_AHB1CKENR_BKPSRAMCKEN_Msk ) + +#define RCC_AHB1CKENR_FDCAN2CKEN_Pos ( 23U ) +#define RCC_AHB1CKENR_FDCAN2CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_FDCAN2CKEN_Pos ) +#define RCC_AHB1CKENR_FDCAN2CKEN ( RCC_AHB1CKENR_FDCAN2CKEN_Msk ) + +#define RCC_AHB1CKENR_FDCAN1CKEN_Pos ( 22U ) +#define RCC_AHB1CKENR_FDCAN1CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_FDCAN1CKEN_Pos ) +#define RCC_AHB1CKENR_FDCAN1CKEN ( RCC_AHB1CKENR_FDCAN1CKEN_Msk ) + +#define RCC_AHB1CKENR_USB2CCKEN_Pos ( 21U ) +#define RCC_AHB1CKENR_USB2CCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_USB2CCKEN_Pos ) +#define RCC_AHB1CKENR_USB2CCKEN ( RCC_AHB1CKENR_USB2CCKEN_Msk ) + +#define RCC_AHB1CKENR_USB1CCKEN_Pos ( 20U ) +#define RCC_AHB1CKENR_USB1CCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_USB1CCKEN_Pos ) +#define RCC_AHB1CKENR_USB1CCKEN ( RCC_AHB1CKENR_USB1CCKEN_Msk ) + +#define RCC_AHB1CKENR_SPI6CKEN_Pos ( 15U ) +#define RCC_AHB1CKENR_SPI6CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SPI6CKEN_Pos ) +#define RCC_AHB1CKENR_SPI6CKEN ( RCC_AHB1CKENR_SPI6CKEN_Msk ) + +#define RCC_AHB1CKENR_SPI5CKEN_Pos ( 14U ) +#define RCC_AHB1CKENR_SPI5CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SPI5CKEN_Pos ) +#define RCC_AHB1CKENR_SPI5CKEN ( RCC_AHB1CKENR_SPI5CKEN_Msk ) + +#define RCC_AHB1CKENR_SPI4CKEN_Pos ( 13U ) +#define RCC_AHB1CKENR_SPI4CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SPI4CKEN_Pos ) +#define RCC_AHB1CKENR_SPI4CKEN ( RCC_AHB1CKENR_SPI4CKEN_Msk ) + +#define RCC_AHB1CKENR_SPI3CKEN_Pos ( 12U ) +#define RCC_AHB1CKENR_SPI3CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SPI3CKEN_Pos ) +#define RCC_AHB1CKENR_SPI3CKEN ( RCC_AHB1CKENR_SPI3CKEN_Msk ) + +#define RCC_AHB1CKENR_SPI2CKEN_Pos ( 11U ) +#define RCC_AHB1CKENR_SPI2CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SPI2CKEN_Pos ) +#define RCC_AHB1CKENR_SPI2CKEN ( RCC_AHB1CKENR_SPI2CKEN_Msk ) + +#define RCC_AHB1CKENR_SPI1CKEN_Pos ( 10U ) +#define RCC_AHB1CKENR_SPI1CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_SPI1CKEN_Pos ) +#define RCC_AHB1CKENR_SPI1CKEN ( RCC_AHB1CKENR_SPI1CKEN_Msk ) + +#define RCC_AHB1CKENR_DMA2DCKEN_Pos ( 9U ) +#define RCC_AHB1CKENR_DMA2DCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_DMA2DCKEN_Pos ) +#define RCC_AHB1CKENR_DMA2DCKEN ( RCC_AHB1CKENR_DMA2DCKEN_Msk ) + +#define RCC_AHB1CKENR_ETHRXCKEN_Pos ( 8U ) +#define RCC_AHB1CKENR_ETHRXCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_ETHRXCKEN_Pos ) +#define RCC_AHB1CKENR_ETHRXCKEN ( RCC_AHB1CKENR_ETHRXCKEN_Msk ) + +#define RCC_AHB1CKENR_ETHTXCKEN_Pos ( 7U ) +#define RCC_AHB1CKENR_ETHTXCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_ETHTXCKEN_Pos ) +#define RCC_AHB1CKENR_ETHTXCKEN ( RCC_AHB1CKENR_ETHTXCKEN_Msk ) + +#define RCC_AHB1CKENR_ETHMACCKEN_Pos ( 6U ) +#define RCC_AHB1CKENR_ETHMACCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_ETHMACCKEN_Pos ) +#define RCC_AHB1CKENR_ETHMACCKEN ( RCC_AHB1CKENR_ETHMACCKEN_Msk ) + +#define RCC_AHB1CKENR_CRCCKEN_Pos ( 5U ) +#define RCC_AHB1CKENR_CRCCKEN_Msk ( 0x1UL << RCC_AHB1CKENR_CRCCKEN_Pos ) +#define RCC_AHB1CKENR_CRCCKEN ( RCC_AHB1CKENR_CRCCKEN_Msk ) + +#define RCC_AHB1CKENR_DMA2CKEN_Pos ( 1U ) +#define RCC_AHB1CKENR_DMA2CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_DMA2CKEN_Pos ) +#define RCC_AHB1CKENR_DMA2CKEN ( RCC_AHB1CKENR_DMA2CKEN_Msk ) + +#define RCC_AHB1CKENR_DMA1CKEN_Pos ( 0U ) +#define RCC_AHB1CKENR_DMA1CKEN_Msk ( 0x1UL << RCC_AHB1CKENR_DMA1CKEN_Pos ) +#define RCC_AHB1CKENR_DMA1CKEN ( RCC_AHB1CKENR_DMA1CKEN_Msk ) + + +/*************** Bits definition for RCC_AHB2CKENR **********************/ + +#define RCC_AHB2CKENR_THMCKEN_Pos ( 31U ) +#define RCC_AHB2CKENR_THMCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_THMCKEN_Pos ) +#define RCC_AHB2CKENR_THMCKEN ( RCC_AHB2CKENR_THMCKEN_Msk ) + +#define RCC_AHB2CKENR_FDCAN3CKEN_Pos ( 28U ) +#define RCC_AHB2CKENR_FDCAN3CKEN_Msk ( 0x1UL << RCC_AHB2CKENR_FDCAN3CKEN_Pos ) +#define RCC_AHB2CKENR_FDCAN3CKEN ( RCC_AHB2CKENR_FDCAN3CKEN_Msk ) + +#define RCC_AHB2CKENR_CORDICCKEN_Pos ( 27U ) +#define RCC_AHB2CKENR_CORDICCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_CORDICCKEN_Pos ) +#define RCC_AHB2CKENR_CORDICCKEN ( RCC_AHB2CKENR_CORDICCKEN_Msk ) + +#define RCC_AHB2CKENR_HRNGCKEN_Pos ( 26U ) +#define RCC_AHB2CKENR_HRNGCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_HRNGCKEN_Pos ) +#define RCC_AHB2CKENR_HRNGCKEN ( RCC_AHB2CKENR_HRNGCKEN_Msk ) + +#define RCC_AHB2CKENR_AESCKEN_Pos ( 25U ) +#define RCC_AHB2CKENR_AESCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_AESCKEN_Pos ) +#define RCC_AHB2CKENR_AESCKEN ( RCC_AHB2CKENR_AESCKEN_Msk ) + +#define RCC_AHB2CKENR_AESSPI1CKEN_Pos ( 24U ) +#define RCC_AHB2CKENR_AESSPI1CKEN_Msk ( 0x1UL << RCC_AHB2CKENR_AESSPI1CKEN_Pos ) +#define RCC_AHB2CKENR_AESSPI1CKEN ( RCC_AHB2CKENR_AESSPI1CKEN_Msk ) + +#define RCC_AHB2CKENR_DCMICKEN_Pos ( 23U ) +#define RCC_AHB2CKENR_DCMICKEN_Msk ( 0x1UL << RCC_AHB2CKENR_DCMICKEN_Pos ) +#define RCC_AHB2CKENR_DCMICKEN ( RCC_AHB2CKENR_DCMICKEN_Msk ) + +#define RCC_AHB2CKENR_DAC2CKEN_Pos ( 20U ) +#define RCC_AHB2CKENR_DAC2CKEN_Msk ( 0x1UL << RCC_AHB2CKENR_DAC2CKEN_Pos ) +#define RCC_AHB2CKENR_DAC2CKEN ( RCC_AHB2CKENR_DAC2CKEN_Msk ) + +#define RCC_AHB2CKENR_DAC1CKEN_Pos ( 19U ) +#define RCC_AHB2CKENR_DAC1CKEN_Msk ( 0x1UL << RCC_AHB2CKENR_DAC1CKEN_Pos ) +#define RCC_AHB2CKENR_DAC1CKEN ( RCC_AHB2CKENR_DAC1CKEN_Msk ) + +#define RCC_AHB2CKENR_ADC3CKEN_Pos ( 18U ) +#define RCC_AHB2CKENR_ADC3CKEN_Msk ( 0x1UL << RCC_AHB2CKENR_ADC3CKEN_Pos ) +#define RCC_AHB2CKENR_ADC3CKEN ( RCC_AHB2CKENR_ADC3CKEN_Msk ) + +#define RCC_AHB2CKENR_ADC12CKEN_Pos ( 17U ) +#define RCC_AHB2CKENR_ADC12CKEN_Msk ( 0x1UL << RCC_AHB2CKENR_ADC12CKEN_Pos ) +#define RCC_AHB2CKENR_ADC12CKEN ( RCC_AHB2CKENR_ADC12CKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOQCKEN_Pos ( 16U ) +#define RCC_AHB2CKENR_GPIOQCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOQCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOQCKEN ( RCC_AHB2CKENR_GPIOQCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOPCKEN_Pos ( 15U ) +#define RCC_AHB2CKENR_GPIOPCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOPCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOPCKEN ( RCC_AHB2CKENR_GPIOPCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOOCKEN_Pos ( 14U ) +#define RCC_AHB2CKENR_GPIOOCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOOCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOOCKEN ( RCC_AHB2CKENR_GPIOOCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIONCKEN_Pos ( 13U ) +#define RCC_AHB2CKENR_GPIONCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIONCKEN_Pos ) +#define RCC_AHB2CKENR_GPIONCKEN ( RCC_AHB2CKENR_GPIONCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOMCKEN_Pos ( 12U ) +#define RCC_AHB2CKENR_GPIOMCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOMCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOMCKEN ( RCC_AHB2CKENR_GPIOMCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOLCKEN_Pos ( 11U ) +#define RCC_AHB2CKENR_GPIOLCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOLCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOLCKEN ( RCC_AHB2CKENR_GPIOLCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOKCKEN_Pos ( 10U ) +#define RCC_AHB2CKENR_GPIOKCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOKCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOKCKEN ( RCC_AHB2CKENR_GPIOKCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOJCKEN_Pos ( 9U ) +#define RCC_AHB2CKENR_GPIOJCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOJCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOJCKEN ( RCC_AHB2CKENR_GPIOJCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOICKEN_Pos ( 8U ) +#define RCC_AHB2CKENR_GPIOICKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOICKEN_Pos ) +#define RCC_AHB2CKENR_GPIOICKEN ( RCC_AHB2CKENR_GPIOICKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOHCKEN_Pos ( 7U ) +#define RCC_AHB2CKENR_GPIOHCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOHCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOHCKEN ( RCC_AHB2CKENR_GPIOHCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOGCKEN_Pos ( 6U ) +#define RCC_AHB2CKENR_GPIOGCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOGCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOGCKEN ( RCC_AHB2CKENR_GPIOGCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOFCKEN_Pos ( 5U ) +#define RCC_AHB2CKENR_GPIOFCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOFCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOFCKEN ( RCC_AHB2CKENR_GPIOFCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOECKEN_Pos ( 4U ) +#define RCC_AHB2CKENR_GPIOECKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOECKEN_Pos ) +#define RCC_AHB2CKENR_GPIOECKEN ( RCC_AHB2CKENR_GPIOECKEN_Msk ) + +#define RCC_AHB2CKENR_GPIODCKEN_Pos ( 3U ) +#define RCC_AHB2CKENR_GPIODCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIODCKEN_Pos ) +#define RCC_AHB2CKENR_GPIODCKEN ( RCC_AHB2CKENR_GPIODCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOCCKEN_Pos ( 2U ) +#define RCC_AHB2CKENR_GPIOCCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOCCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOCCKEN ( RCC_AHB2CKENR_GPIOCCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOBCKEN_Pos ( 1U ) +#define RCC_AHB2CKENR_GPIOBCKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOBCKEN_Pos ) +#define RCC_AHB2CKENR_GPIOBCKEN ( RCC_AHB2CKENR_GPIOBCKEN_Msk ) + +#define RCC_AHB2CKENR_GPIOACKEN_Pos ( 0U ) +#define RCC_AHB2CKENR_GPIOACKEN_Msk ( 0x1UL << RCC_AHB2CKENR_GPIOACKEN_Pos ) +#define RCC_AHB2CKENR_GPIOACKEN ( RCC_AHB2CKENR_GPIOACKEN_Msk ) + + +/*************** Bits definition for RCC_AHB3CKENR **********************/ + +#define RCC_AHB3CKENR_FMCCKEN_Pos ( 12U ) +#define RCC_AHB3CKENR_FMCCKEN_Msk ( 0x1UL << RCC_AHB3CKENR_FMCCKEN_Pos ) +#define RCC_AHB3CKENR_FMCCKEN ( RCC_AHB3CKENR_FMCCKEN_Msk ) + +#define RCC_AHB3CKENR_OSPI2CKEN_Pos ( 9U ) +#define RCC_AHB3CKENR_OSPI2CKEN_Msk ( 0x1UL << RCC_AHB3CKENR_OSPI2CKEN_Pos ) +#define RCC_AHB3CKENR_OSPI2CKEN ( RCC_AHB3CKENR_OSPI2CKEN_Msk ) + +#define RCC_AHB3CKENR_OSPI1CKEN_Pos ( 8U ) +#define RCC_AHB3CKENR_OSPI1CKEN_Msk ( 0x1UL << RCC_AHB3CKENR_OSPI1CKEN_Pos ) +#define RCC_AHB3CKENR_OSPI1CKEN ( RCC_AHB3CKENR_OSPI1CKEN_Msk ) + +#define RCC_AHB3CKENR_SDMMCCKEN_Pos ( 4U ) +#define RCC_AHB3CKENR_SDMMCCKEN_Msk ( 0x1UL << RCC_AHB3CKENR_SDMMCCKEN_Pos ) +#define RCC_AHB3CKENR_SDMMCCKEN ( RCC_AHB3CKENR_SDMMCCKEN_Msk ) + +#define RCC_AHB3CKENR_SPI8CKEN_Pos ( 1U ) +#define RCC_AHB3CKENR_SPI8CKEN_Msk ( 0x1UL << RCC_AHB3CKENR_SPI8CKEN_Pos ) +#define RCC_AHB3CKENR_SPI8CKEN ( RCC_AHB3CKENR_SPI8CKEN_Msk ) + +#define RCC_AHB3CKENR_SPI7CKEN_Pos ( 0U ) +#define RCC_AHB3CKENR_SPI7CKEN_Msk ( 0x1UL << RCC_AHB3CKENR_SPI7CKEN_Pos ) +#define RCC_AHB3CKENR_SPI7CKEN ( RCC_AHB3CKENR_SPI7CKEN_Msk ) + + +/*************** Bits definition for RCC_APB1CKENR1 **********************/ + +#define RCC_APB1CKENR1_LPUART1CKEN_Pos ( 31U ) +#define RCC_APB1CKENR1_LPUART1CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_LPUART1CKEN_Pos ) +#define RCC_APB1CKENR1_LPUART1CKEN ( RCC_APB1CKENR1_LPUART1CKEN_Msk ) + +#define RCC_APB1CKENR1_LPTIM1CKEN_Pos ( 30U ) +#define RCC_APB1CKENR1_LPTIM1CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_LPTIM1CKEN_Pos ) +#define RCC_APB1CKENR1_LPTIM1CKEN ( RCC_APB1CKENR1_LPTIM1CKEN_Msk ) + +#define RCC_APB1CKENR1_PMUCKEN_Pos ( 27U ) +#define RCC_APB1CKENR1_PMUCKEN_Msk ( 0x1UL << RCC_APB1CKENR1_PMUCKEN_Pos ) +#define RCC_APB1CKENR1_PMUCKEN ( RCC_APB1CKENR1_PMUCKEN_Msk ) + +#define RCC_APB1CKENR1_I2C4CKEN_Pos ( 24U ) +#define RCC_APB1CKENR1_I2C4CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2C4CKEN_Pos ) +#define RCC_APB1CKENR1_I2C4CKEN ( RCC_APB1CKENR1_I2C4CKEN_Msk ) + +#define RCC_APB1CKENR1_I2C3CKEN_Pos ( 23U ) +#define RCC_APB1CKENR1_I2C3CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2C3CKEN_Pos ) +#define RCC_APB1CKENR1_I2C3CKEN ( RCC_APB1CKENR1_I2C3CKEN_Msk ) + +#define RCC_APB1CKENR1_I2C2CKEN_Pos ( 22U ) +#define RCC_APB1CKENR1_I2C2CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2C2CKEN_Pos ) +#define RCC_APB1CKENR1_I2C2CKEN ( RCC_APB1CKENR1_I2C2CKEN_Msk ) + +#define RCC_APB1CKENR1_I2C1CKEN_Pos ( 21U ) +#define RCC_APB1CKENR1_I2C1CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2C1CKEN_Pos ) +#define RCC_APB1CKENR1_I2C1CKEN ( RCC_APB1CKENR1_I2C1CKEN_Msk ) + +#define RCC_APB1CKENR1_USART5CKEN_Pos ( 20U ) +#define RCC_APB1CKENR1_USART5CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_USART5CKEN_Pos ) +#define RCC_APB1CKENR1_USART5CKEN ( RCC_APB1CKENR1_USART5CKEN_Msk ) + +#define RCC_APB1CKENR1_USART4CKEN_Pos ( 19U ) +#define RCC_APB1CKENR1_USART4CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_USART4CKEN_Pos ) +#define RCC_APB1CKENR1_USART4CKEN ( RCC_APB1CKENR1_USART4CKEN_Msk ) + +#define RCC_APB1CKENR1_USART3CKEN_Pos ( 18U ) +#define RCC_APB1CKENR1_USART3CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_USART3CKEN_Pos ) +#define RCC_APB1CKENR1_USART3CKEN ( RCC_APB1CKENR1_USART3CKEN_Msk ) + +#define RCC_APB1CKENR1_USART2CKEN_Pos ( 17U ) +#define RCC_APB1CKENR1_USART2CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_USART2CKEN_Pos ) +#define RCC_APB1CKENR1_USART2CKEN ( RCC_APB1CKENR1_USART2CKEN_Msk ) + +#define RCC_APB1CKENR1_I2S3CKEN_Pos ( 16U ) +#define RCC_APB1CKENR1_I2S3CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2S3CKEN_Pos ) +#define RCC_APB1CKENR1_I2S3CKEN ( RCC_APB1CKENR1_I2S3CKEN_Msk ) + +#define RCC_APB1CKENR1_I2S2CKEN_Pos ( 15U ) +#define RCC_APB1CKENR1_I2S2CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2S2CKEN_Pos ) +#define RCC_APB1CKENR1_I2S2CKEN ( RCC_APB1CKENR1_I2S2CKEN_Msk ) + +#define RCC_APB1CKENR1_I2S1CKEN_Pos ( 14U ) +#define RCC_APB1CKENR1_I2S1CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_I2S1CKEN_Pos ) +#define RCC_APB1CKENR1_I2S1CKEN ( RCC_APB1CKENR1_I2S1CKEN_Msk ) + +#define RCC_APB1CKENR1_WDTCKEN_Pos ( 11U ) +#define RCC_APB1CKENR1_WDTCKEN_Msk ( 0x1UL << RCC_APB1CKENR1_WDTCKEN_Pos ) +#define RCC_APB1CKENR1_WDTCKEN ( RCC_APB1CKENR1_WDTCKEN_Msk ) + +#define RCC_APB1CKENR1_RTCCKEN_Pos ( 10U ) +#define RCC_APB1CKENR1_RTCCKEN_Msk ( 0x1UL << RCC_APB1CKENR1_RTCCKEN_Pos ) +#define RCC_APB1CKENR1_RTCCKEN ( RCC_APB1CKENR1_RTCCKEN_Msk ) + +#define RCC_APB1CKENR1_TIM14CKEN_Pos ( 8U ) +#define RCC_APB1CKENR1_TIM14CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM14CKEN_Pos ) +#define RCC_APB1CKENR1_TIM14CKEN ( RCC_APB1CKENR1_TIM14CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM13CKEN_Pos ( 7U ) +#define RCC_APB1CKENR1_TIM13CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM13CKEN_Pos ) +#define RCC_APB1CKENR1_TIM13CKEN ( RCC_APB1CKENR1_TIM13CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM12CKEN_Pos ( 6U ) +#define RCC_APB1CKENR1_TIM12CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM12CKEN_Pos ) +#define RCC_APB1CKENR1_TIM12CKEN ( RCC_APB1CKENR1_TIM12CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM7CKEN_Pos ( 5U ) +#define RCC_APB1CKENR1_TIM7CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM7CKEN_Pos ) +#define RCC_APB1CKENR1_TIM7CKEN ( RCC_APB1CKENR1_TIM7CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM6CKEN_Pos ( 4U ) +#define RCC_APB1CKENR1_TIM6CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM6CKEN_Pos ) +#define RCC_APB1CKENR1_TIM6CKEN ( RCC_APB1CKENR1_TIM6CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM5CKEN_Pos ( 3U ) +#define RCC_APB1CKENR1_TIM5CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM5CKEN_Pos ) +#define RCC_APB1CKENR1_TIM5CKEN ( RCC_APB1CKENR1_TIM5CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM4CKEN_Pos ( 2U ) +#define RCC_APB1CKENR1_TIM4CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM4CKEN_Pos ) +#define RCC_APB1CKENR1_TIM4CKEN ( RCC_APB1CKENR1_TIM4CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM3CKEN_Pos ( 1U ) +#define RCC_APB1CKENR1_TIM3CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM3CKEN_Pos ) +#define RCC_APB1CKENR1_TIM3CKEN ( RCC_APB1CKENR1_TIM3CKEN_Msk ) + +#define RCC_APB1CKENR1_TIM2CKEN_Pos ( 0U ) +#define RCC_APB1CKENR1_TIM2CKEN_Msk ( 0x1UL << RCC_APB1CKENR1_TIM2CKEN_Pos ) +#define RCC_APB1CKENR1_TIM2CKEN ( RCC_APB1CKENR1_TIM2CKEN_Msk ) + + +/*************** Bits definition for RCC_APB1CKENR2 **********************/ + +#define RCC_APB1CKENR2_EFUSE2CKEN_Pos ( 7U ) +#define RCC_APB1CKENR2_EFUSE2CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_EFUSE2CKEN_Pos ) +#define RCC_APB1CKENR2_EFUSE2CKEN ( RCC_APB1CKENR2_EFUSE2CKEN_Msk ) + +#define RCC_APB1CKENR2_EFUSE1CKEN_Pos ( 6U ) +#define RCC_APB1CKENR2_EFUSE1CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_EFUSE1CKEN_Pos ) +#define RCC_APB1CKENR2_EFUSE1CKEN ( RCC_APB1CKENR2_EFUSE1CKEN_Msk ) + +#define RCC_APB1CKENR2_TIM26CKEN_Pos ( 5U ) +#define RCC_APB1CKENR2_TIM26CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_TIM26CKEN_Pos ) +#define RCC_APB1CKENR2_TIM26CKEN ( RCC_APB1CKENR2_TIM26CKEN_Msk ) + +#define RCC_APB1CKENR2_TIM25CKEN_Pos ( 4U ) +#define RCC_APB1CKENR2_TIM25CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_TIM25CKEN_Pos ) +#define RCC_APB1CKENR2_TIM25CKEN ( RCC_APB1CKENR2_TIM25CKEN_Msk ) + +#define RCC_APB1CKENR2_USART8CKEN_Pos ( 3U ) +#define RCC_APB1CKENR2_USART8CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_USART8CKEN_Pos ) +#define RCC_APB1CKENR2_USART8CKEN ( RCC_APB1CKENR2_USART8CKEN_Msk ) + +#define RCC_APB1CKENR2_USART7CKEN_Pos ( 2U ) +#define RCC_APB1CKENR2_USART7CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_USART7CKEN_Pos ) +#define RCC_APB1CKENR2_USART7CKEN ( RCC_APB1CKENR2_USART7CKEN_Msk ) + +#define RCC_APB1CKENR2_LPTIM2CKEN_Pos ( 1U ) +#define RCC_APB1CKENR2_LPTIM2CKEN_Msk ( 0x1UL << RCC_APB1CKENR2_LPTIM2CKEN_Pos ) +#define RCC_APB1CKENR2_LPTIM2CKEN ( RCC_APB1CKENR2_LPTIM2CKEN_Msk ) + + +/*************** Bits definition for RCC_APB2CKENR **********************/ + +#define RCC_APB2CKENR_USART10CKEN_Pos ( 31U ) +#define RCC_APB2CKENR_USART10CKEN_Msk ( 0x1UL << RCC_APB2CKENR_USART10CKEN_Pos ) +#define RCC_APB2CKENR_USART10CKEN ( RCC_APB2CKENR_USART10CKEN_Msk ) + +#define RCC_APB2CKENR_USART9CKEN_Pos ( 30U ) +#define RCC_APB2CKENR_USART9CKEN_Msk ( 0x1UL << RCC_APB2CKENR_USART9CKEN_Pos ) +#define RCC_APB2CKENR_USART9CKEN ( RCC_APB2CKENR_USART9CKEN_Msk ) + +#define RCC_APB2CKENR_TIM24CKEN_Pos ( 29U ) +#define RCC_APB2CKENR_TIM24CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM24CKEN_Pos ) +#define RCC_APB2CKENR_TIM24CKEN ( RCC_APB2CKENR_TIM24CKEN_Msk ) + +#define RCC_APB2CKENR_TIM23CKEN_Pos ( 28U ) +#define RCC_APB2CKENR_TIM23CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM23CKEN_Pos ) +#define RCC_APB2CKENR_TIM23CKEN ( RCC_APB2CKENR_TIM23CKEN_Msk ) + +#define RCC_APB2CKENR_TIM22CKEN_Pos ( 27U ) +#define RCC_APB2CKENR_TIM22CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM22CKEN_Pos ) +#define RCC_APB2CKENR_TIM22CKEN ( RCC_APB2CKENR_TIM22CKEN_Msk ) + +#define RCC_APB2CKENR_TIM21CKEN_Pos ( 26U ) +#define RCC_APB2CKENR_TIM21CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM21CKEN_Pos ) +#define RCC_APB2CKENR_TIM21CKEN ( RCC_APB2CKENR_TIM21CKEN_Msk ) + +#define RCC_APB2CKENR_TIM19CKEN_Pos ( 25U ) +#define RCC_APB2CKENR_TIM19CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM19CKEN_Pos ) +#define RCC_APB2CKENR_TIM19CKEN ( RCC_APB2CKENR_TIM19CKEN_Msk ) + +#define RCC_APB2CKENR_TIM18CKEN_Pos ( 24U ) +#define RCC_APB2CKENR_TIM18CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM18CKEN_Pos ) +#define RCC_APB2CKENR_TIM18CKEN ( RCC_APB2CKENR_TIM18CKEN_Msk ) + +#define RCC_APB2CKENR_TIM11CKEN_Pos ( 23U ) +#define RCC_APB2CKENR_TIM11CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM11CKEN_Pos ) +#define RCC_APB2CKENR_TIM11CKEN ( RCC_APB2CKENR_TIM11CKEN_Msk ) + +#define RCC_APB2CKENR_TIM10CKEN_Pos ( 22U ) +#define RCC_APB2CKENR_TIM10CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM10CKEN_Pos ) +#define RCC_APB2CKENR_TIM10CKEN ( RCC_APB2CKENR_TIM10CKEN_Msk ) + +#define RCC_APB2CKENR_TIM9CKEN_Pos ( 21U ) +#define RCC_APB2CKENR_TIM9CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM9CKEN_Pos ) +#define RCC_APB2CKENR_TIM9CKEN ( RCC_APB2CKENR_TIM9CKEN_Msk ) + +#define RCC_APB2CKENR_LTDCCKEN_Pos ( 19U ) +#define RCC_APB2CKENR_LTDCCKEN_Msk ( 0x1UL << RCC_APB2CKENR_LTDCCKEN_Pos ) +#define RCC_APB2CKENR_LTDCCKEN ( RCC_APB2CKENR_LTDCCKEN_Msk ) + +#define RCC_APB2CKENR_TKEYCKEN_Pos ( 18U ) +#define RCC_APB2CKENR_TKEYCKEN_Msk ( 0x1UL << RCC_APB2CKENR_TKEYCKEN_Pos ) +#define RCC_APB2CKENR_TKEYCKEN ( RCC_APB2CKENR_TKEYCKEN_Msk ) + +#define RCC_APB2CKENR_TIM20CKEN_Pos ( 15U ) +#define RCC_APB2CKENR_TIM20CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM20CKEN_Pos ) +#define RCC_APB2CKENR_TIM20CKEN ( RCC_APB2CKENR_TIM20CKEN_Msk ) + +#define RCC_APB2CKENR_TIM17CKEN_Pos ( 13U ) +#define RCC_APB2CKENR_TIM17CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM17CKEN_Pos ) +#define RCC_APB2CKENR_TIM17CKEN ( RCC_APB2CKENR_TIM17CKEN_Msk ) + +#define RCC_APB2CKENR_TIM16CKEN_Pos ( 12U ) +#define RCC_APB2CKENR_TIM16CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM16CKEN_Pos ) +#define RCC_APB2CKENR_TIM16CKEN ( RCC_APB2CKENR_TIM16CKEN_Msk ) + +#define RCC_APB2CKENR_TIM15CKEN_Pos ( 11U ) +#define RCC_APB2CKENR_TIM15CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM15CKEN_Pos ) +#define RCC_APB2CKENR_TIM15CKEN ( RCC_APB2CKENR_TIM15CKEN_Msk ) + +#define RCC_APB2CKENR_USART6CKEN_Pos ( 10U ) +#define RCC_APB2CKENR_USART6CKEN_Msk ( 0x1UL << RCC_APB2CKENR_USART6CKEN_Pos ) +#define RCC_APB2CKENR_USART6CKEN ( RCC_APB2CKENR_USART6CKEN_Msk ) + +#define RCC_APB2CKENR_USART1CKEN_Pos ( 9U ) +#define RCC_APB2CKENR_USART1CKEN_Msk ( 0x1UL << RCC_APB2CKENR_USART1CKEN_Pos ) +#define RCC_APB2CKENR_USART1CKEN ( RCC_APB2CKENR_USART1CKEN_Msk ) + +#define RCC_APB2CKENR_TIM8CKEN_Pos ( 8U ) +#define RCC_APB2CKENR_TIM8CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM8CKEN_Pos ) +#define RCC_APB2CKENR_TIM8CKEN ( RCC_APB2CKENR_TIM8CKEN_Msk ) + +#define RCC_APB2CKENR_TIM1CKEN_Pos ( 6U ) +#define RCC_APB2CKENR_TIM1CKEN_Msk ( 0x1UL << RCC_APB2CKENR_TIM1CKEN_Pos ) +#define RCC_APB2CKENR_TIM1CKEN ( RCC_APB2CKENR_TIM1CKEN_Msk ) + +#define RCC_APB2CKENR_EXTICKEN_Pos ( 4U ) +#define RCC_APB2CKENR_EXTICKEN_Msk ( 0x1UL << RCC_APB2CKENR_EXTICKEN_Pos ) +#define RCC_APB2CKENR_EXTICKEN ( RCC_APB2CKENR_EXTICKEN_Msk ) + +#define RCC_APB2CKENR_CMP1CKEN_A_Pos ( 2U ) +#define RCC_APB2CKENR_CMP1CKEN_A_Msk ( 0x1UL << RCC_APB2CKENR_CMP1CKEN_A_Pos ) +#define RCC_APB2CKENR_CMP1CKEN_A ( RCC_APB2CKENR_CMP1CKEN_A_Msk ) + +#define RCC_APB2CKENR_SYSCFGCKEN_Pos ( 0U ) +#define RCC_APB2CKENR_SYSCFGCKEN_Msk ( 0x1UL << RCC_APB2CKENR_SYSCFGCKEN_Pos ) +#define RCC_APB2CKENR_SYSCFGCKEN ( RCC_APB2CKENR_SYSCFGCKEN_Msk ) + + +/*************** Bits definition for RCC_APB3CKENR **********************/ + +#define RCC_APB3CKENR_LPTIM6CKEN_Pos ( 3U ) +#define RCC_APB3CKENR_LPTIM6CKEN_Msk ( 0x1UL << RCC_APB3CKENR_LPTIM6CKEN_Pos ) +#define RCC_APB3CKENR_LPTIM6CKEN ( RCC_APB3CKENR_LPTIM6CKEN_Msk ) + +#define RCC_APB3CKENR_LPTIM5CKEN_Pos ( 2U ) +#define RCC_APB3CKENR_LPTIM5CKEN_Msk ( 0x1UL << RCC_APB3CKENR_LPTIM5CKEN_Pos ) +#define RCC_APB3CKENR_LPTIM5CKEN ( RCC_APB3CKENR_LPTIM5CKEN_Msk ) + +#define RCC_APB3CKENR_LPTIM4CKEN_Pos ( 1U ) +#define RCC_APB3CKENR_LPTIM4CKEN_Msk ( 0x1UL << RCC_APB3CKENR_LPTIM4CKEN_Pos ) +#define RCC_APB3CKENR_LPTIM4CKEN ( RCC_APB3CKENR_LPTIM4CKEN_Msk ) + +#define RCC_APB3CKENR_LPTIM3CKEN_Pos ( 0U ) +#define RCC_APB3CKENR_LPTIM3CKEN_Msk ( 0x1UL << RCC_APB3CKENR_LPTIM3CKEN_Pos ) +#define RCC_APB3CKENR_LPTIM3CKEN ( RCC_APB3CKENR_LPTIM3CKEN_Msk ) + +/*************** Bits definition for RCC_APB4CKENR **********************/ + +#define RCC_APB4CKENR_DPWM6CKEN_Pos ( 17U ) +#define RCC_APB4CKENR_DPWM6CKEN_Msk ( 0x1UL << RCC_APB4CKENR_DPWM6CKEN_Pos ) +#define RCC_APB4CKENR_DPWM6CKEN ( RCC_APB4CKENR_DPWM6CKEN_Msk ) + +#define RCC_APB4CKENR_DPWM5CKEN_Pos ( 16U ) +#define RCC_APB4CKENR_DPWM5CKEN_Msk ( 0x1UL << RCC_APB4CKENR_DPWM5CKEN_Pos ) +#define RCC_APB4CKENR_DPWM5CKEN ( RCC_APB4CKENR_DPWM5CKEN_Msk ) + +#define RCC_APB4CKENR_SPWM6CKEN_Pos ( 15U ) +#define RCC_APB4CKENR_SPWM6CKEN_Msk ( 0x1UL << RCC_APB4CKENR_SPWM6CKEN_Pos ) +#define RCC_APB4CKENR_SPWM6CKEN ( RCC_APB4CKENR_SPWM6CKEN_Msk ) + +#define RCC_APB4CKENR_SPWM5CKEN_Pos ( 14U ) +#define RCC_APB4CKENR_SPWM5CKEN_Msk ( 0x1UL << RCC_APB4CKENR_SPWM5CKEN_Pos ) +#define RCC_APB4CKENR_SPWM5CKEN ( RCC_APB4CKENR_SPWM5CKEN_Msk ) + +#define RCC_APB4CKENR_SPWM4CKEN_Pos ( 13U ) +#define RCC_APB4CKENR_SPWM4CKEN_Msk ( 0x1UL << RCC_APB4CKENR_SPWM4CKEN_Pos ) +#define RCC_APB4CKENR_SPWM4CKEN ( RCC_APB4CKENR_SPWM4CKEN_Msk ) + +#define RCC_APB4CKENR_SPWM3CKEN_Pos ( 12U ) +#define RCC_APB4CKENR_SPWM3CKEN_Msk ( 0x1UL << RCC_APB4CKENR_SPWM3CKEN_Pos ) +#define RCC_APB4CKENR_SPWM3CKEN ( RCC_APB4CKENR_SPWM3CKEN_Msk ) + +#define RCC_APB4CKENR_MDACCKEN_Pos ( 8U ) +#define RCC_APB4CKENR_MDACCKEN_Msk ( 0x1UL << RCC_APB4CKENR_MDACCKEN_Pos ) +#define RCC_APB4CKENR_MDACCKEN ( RCC_APB4CKENR_MDACCKEN_Msk ) + +#define RCC_APB4CKENR_LPTCKEN_Pos ( 7U ) +#define RCC_APB4CKENR_LPTCKEN_Msk ( 0x1UL << RCC_APB4CKENR_LPTCKEN_Pos ) +#define RCC_APB4CKENR_LPTCKEN ( RCC_APB4CKENR_LPTCKEN_Msk ) + +#define RCC_APB4CKENR_PNDLCKEN_Pos ( 6U ) +#define RCC_APB4CKENR_PNDLCKEN_Msk ( 0x1UL << RCC_APB4CKENR_PNDLCKEN_Pos ) +#define RCC_APB4CKENR_PNDLCKEN ( RCC_APB4CKENR_PNDLCKEN_Msk ) + +#define RCC_APB4CKENR_DPWM4CKEN_Pos ( 5U ) +#define RCC_APB4CKENR_DPWM4CKEN_Msk ( 0x1UL << RCC_APB4CKENR_DPWM4CKEN_Pos ) +#define RCC_APB4CKENR_DPWM4CKEN ( RCC_APB4CKENR_DPWM4CKEN_Msk ) + +#define RCC_APB4CKENR_DPWM3CKEN_Pos ( 4U ) +#define RCC_APB4CKENR_DPWM3CKEN_Msk ( 0x1UL << RCC_APB4CKENR_DPWM3CKEN_Pos ) +#define RCC_APB4CKENR_DPWM3CKEN ( RCC_APB4CKENR_DPWM3CKEN_Msk ) + +#define RCC_APB4CKENR_DPWM2CKEN_Pos ( 3U ) +#define RCC_APB4CKENR_DPWM2CKEN_Msk ( 0x1UL << RCC_APB4CKENR_DPWM2CKEN_Pos ) +#define RCC_APB4CKENR_DPWM2CKEN ( RCC_APB4CKENR_DPWM2CKEN_Msk ) + +#define RCC_APB4CKENR_DPWM1CKEN_Pos ( 2U ) +#define RCC_APB4CKENR_DPWM1CKEN_Msk ( 0x1UL << RCC_APB4CKENR_DPWM1CKEN_Pos ) +#define RCC_APB4CKENR_DPWM1CKEN ( RCC_APB4CKENR_DPWM1CKEN_Msk ) + +#define RCC_APB4CKENR_SPWM2CKEN_Pos ( 1U ) +#define RCC_APB4CKENR_SPWM2CKEN_Msk ( 0x1UL << RCC_APB4CKENR_SPWM2CKEN_Pos ) +#define RCC_APB4CKENR_SPWM2CKEN ( RCC_APB4CKENR_SPWM2CKEN_Msk ) + +#define RCC_APB4CKENR_SPWM1CKEN_Pos ( 0U ) +#define RCC_APB4CKENR_SPWM1CKEN_Msk ( 0x1UL << RCC_APB4CKENR_SPWM1CKEN_Pos ) +#define RCC_APB4CKENR_SPWM1CKEN ( RCC_APB4CKENR_SPWM1CKEN_Msk ) + + +/*************** Bits definition for RCC_RCHCR **********************/ + +#define RCC_RCHCR_RCHPRDY_Pos ( 24U ) +#define RCC_RCHCR_RCHPRDY_Msk ( 0x1UL << RCC_RCHCR_RCHPRDY_Pos ) +#define RCC_RCHCR_RCHPRDY ( RCC_RCHCR_RCHPRDY_Msk ) + +#define RCC_RCHCR_RCHSEL_Pos ( 21U ) +#define RCC_RCHCR_RCHSEL_Msk ( 0x1UL << RCC_RCHCR_RCHSEL_Pos ) +#define RCC_RCHCR_RCHSEL ( RCC_RCHCR_RCHSEL_Msk ) + +#define RCC_RCHCR_RCHPEN_Pos ( 20U ) +#define RCC_RCHCR_RCHPEN_Msk ( 0x1UL << RCC_RCHCR_RCHPEN_Pos ) +#define RCC_RCHCR_RCHPEN ( RCC_RCHCR_RCHPEN_Msk ) + +#define RCC_RCHCR_RCHTRIMH_Pos ( 15U ) +#define RCC_RCHCR_RCHTRIMH_Msk ( 0x3UL << RCC_RCHCR_RCHTRIMH_Pos ) +#define RCC_RCHCR_RCHTRIMH ( RCC_RCHCR_RCHTRIMH_Msk ) + +#define RCC_RCHCR_RCHTRIML_Pos ( 8U ) +#define RCC_RCHCR_RCHTRIML_Msk ( 0x7FUL << RCC_RCHCR_RCHTRIML_Pos ) +#define RCC_RCHCR_RCHTRIML ( RCC_RCHCR_RCHTRIML_Msk ) + +#define RCC_RCHCR_RCHRDY_Pos ( 4U ) +#define RCC_RCHCR_RCHRDY_Msk ( 0x1UL << RCC_RCHCR_RCHRDY_Pos ) +#define RCC_RCHCR_RCHRDY ( RCC_RCHCR_RCHRDY_Msk ) + +#define RCC_RCHCR_RCHDIV_Pos ( 3U ) +#define RCC_RCHCR_RCHDIV_Msk ( 0x1UL << RCC_RCHCR_RCHDIV_Pos ) +#define RCC_RCHCR_RCHDIV ( RCC_RCHCR_RCHDIV_Msk ) + +#define RCC_RCHCR_RCHEN_Pos ( 0U ) +#define RCC_RCHCR_RCHEN_Msk ( 0x1UL << RCC_RCHCR_RCHEN_Pos ) +#define RCC_RCHCR_RCHEN ( RCC_RCHCR_RCHEN_Msk ) + + +/*************** Bits definition for RCC_XTHCR **********************/ + +#define RCC_XTHCR_XTHSDEN_Pos ( 8U ) +#define RCC_XTHCR_XTHSDEN_Msk ( 0x1UL << RCC_XTHCR_XTHSDEN_Pos ) +#define RCC_XTHCR_XTHSDEN ( RCC_XTHCR_XTHSDEN_Msk ) + +#define RCC_XTHCR_XTHRDY_Pos ( 4U ) +#define RCC_XTHCR_XTHRDY_Msk ( 0x1UL << RCC_XTHCR_XTHRDY_Pos ) +#define RCC_XTHCR_XTHRDY ( RCC_XTHCR_XTHRDY_Msk ) + +#define RCC_XTHCR_XTHRDYTIME_Pos ( 2U ) +#define RCC_XTHCR_XTHRDYTIME_Msk ( 0x3UL << RCC_XTHCR_XTHRDYTIME_Pos ) +#define RCC_XTHCR_XTHRDYTIME ( RCC_XTHCR_XTHRDYTIME_Msk ) +#define RCC_XTHCR_XTHRDYTIME_0 ( 0x1UL << RCC_XTHCR_XTHRDYTIME_Pos ) +#define RCC_XTHCR_XTHRDYTIME_1 ( 0x2UL << RCC_XTHCR_XTHRDYTIME_Pos ) + +#define RCC_XTHCR_XTHBYP_Pos ( 1U ) +#define RCC_XTHCR_XTHBYP_Msk ( 0x1UL << RCC_XTHCR_XTHBYP_Pos ) +#define RCC_XTHCR_XTHBYP ( RCC_XTHCR_XTHBYP_Msk ) + +#define RCC_XTHCR_XTHEN_Pos ( 0U ) +#define RCC_XTHCR_XTHEN_Msk ( 0x1UL << RCC_XTHCR_XTHEN_Pos ) +#define RCC_XTHCR_XTHEN ( RCC_XTHCR_XTHEN_Msk ) + + +/*************** Bits definition for RCC_PLL1CR **********************/ + +#define RCC_PLL1CR_PLL1LOCKSEL_Pos ( 31U ) +#define RCC_PLL1CR_PLL1LOCKSEL_Msk ( 0x1UL << RCC_PLL1CR_PLL1LOCKSEL_Pos ) +#define RCC_PLL1CR_PLL1LOCKSEL ( RCC_PLL1CR_PLL1LOCKSEL_Msk ) + +#define RCC_PLL1CR_PLL1FREERUN_Pos ( 30U ) +#define RCC_PLL1CR_PLL1FREERUN_Msk ( 0x1UL << RCC_PLL1CR_PLL1FREERUN_Pos ) +#define RCC_PLL1CR_PLL1FREERUN ( RCC_PLL1CR_PLL1FREERUN_Msk ) + +#define RCC_PLL1CR_PLL1LOCK_Pos ( 29U ) +#define RCC_PLL1CR_PLL1LOCK_Msk ( 0x1UL << RCC_PLL1CR_PLL1LOCK_Pos ) +#define RCC_PLL1CR_PLL1LOCK ( RCC_PLL1CR_PLL1LOCK_Msk ) + +#define RCC_PLL1CR_PLL1LOCKDLY_Pos ( 23U ) +#define RCC_PLL1CR_PLL1LOCKDLY_Msk ( 0x3FUL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) +#define RCC_PLL1CR_PLL1LOCKDLY ( RCC_PLL1CR_PLL1LOCKDLY_Msk ) +#define RCC_PLL1CR_PLL1LOCKDLY_0 ( 0x1UL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) +#define RCC_PLL1CR_PLL1LOCKDLY_1 ( 0x2UL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) +#define RCC_PLL1CR_PLL1LOCKDLY_2 ( 0x4UL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) +#define RCC_PLL1CR_PLL1LOCKDLY_3 ( 0x8UL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) +#define RCC_PLL1CR_PLL1LOCKDLY_4 ( 0x10UL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) +#define RCC_PLL1CR_PLL1LOCKDLY_5 ( 0x20UL << RCC_PLL1CR_PLL1LOCKDLY_Pos ) + +#define RCC_PLL1CR_PLL1UPDATEEN_Pos ( 22U ) +#define RCC_PLL1CR_PLL1UPDATEEN_Msk ( 0x1UL << RCC_PLL1CR_PLL1UPDATEEN_Pos ) +#define RCC_PLL1CR_PLL1UPDATEEN ( RCC_PLL1CR_PLL1UPDATEEN_Msk ) + +#define RCC_PLL1CR_PLL1SLEEP_Pos ( 21U ) +#define RCC_PLL1CR_PLL1SLEEP_Msk ( 0x1UL << RCC_PLL1CR_PLL1SLEEP_Pos ) +#define RCC_PLL1CR_PLL1SLEEP ( RCC_PLL1CR_PLL1SLEEP_Msk ) + +#define RCC_PLL1CR_PLL1QCLKEN_Pos ( 5U ) +#define RCC_PLL1CR_PLL1QCLKEN_Msk ( 0x1UL << RCC_PLL1CR_PLL1QCLKEN_Pos ) +#define RCC_PLL1CR_PLL1QCLKEN ( RCC_PLL1CR_PLL1QCLKEN_Msk ) + +#define RCC_PLL1CR_PLL1PCLKEN_Pos ( 4U ) +#define RCC_PLL1CR_PLL1PCLKEN_Msk ( 0x1UL << RCC_PLL1CR_PLL1PCLKEN_Pos ) +#define RCC_PLL1CR_PLL1PCLKEN ( RCC_PLL1CR_PLL1PCLKEN_Msk ) + +#define RCC_PLL1CR_PLL1SRCSEL_Pos ( 1U ) +#define RCC_PLL1CR_PLL1SRCSEL_Msk ( 0x1UL << RCC_PLL1CR_PLL1SRCSEL_Pos ) +#define RCC_PLL1CR_PLL1SRCSEL ( RCC_PLL1CR_PLL1SRCSEL_Msk ) + +#define RCC_PLL1CR_PLL1EN_Pos ( 0U ) +#define RCC_PLL1CR_PLL1EN_Msk ( 0x1UL << RCC_PLL1CR_PLL1EN_Pos ) +#define RCC_PLL1CR_PLL1EN ( RCC_PLL1CR_PLL1EN_Msk ) + + +/*************** Bits definition for RCC_PLL1CFR **********************/ + +#define RCC_PLL1CFR_PLL1Q_Pos ( 24U ) +#define RCC_PLL1CFR_PLL1Q_Msk ( 0xfUL << RCC_PLL1CFR_PLL1Q_Pos ) +#define RCC_PLL1CFR_PLL1Q ( RCC_PLL1CFR_PLL1Q_Msk ) +#define RCC_PLL1CFR_PLL1Q_0 ( 0x1UL << RCC_PLL1CFR_PLL1Q_Pos ) +#define RCC_PLL1CFR_PLL1Q_1 ( 0x2UL << RCC_PLL1CFR_PLL1Q_Pos ) +#define RCC_PLL1CFR_PLL1Q_2 ( 0x4UL << RCC_PLL1CFR_PLL1Q_Pos ) +#define RCC_PLL1CFR_PLL1Q_3 ( 0x8UL << RCC_PLL1CFR_PLL1Q_Pos ) + +#define RCC_PLL1CFR_PLL1P_Pos ( 20U ) +#define RCC_PLL1CFR_PLL1P_Msk ( 0x3UL << RCC_PLL1CFR_PLL1P_Pos ) +#define RCC_PLL1CFR_PLL1P ( RCC_PLL1CFR_PLL1P_Msk ) +#define RCC_PLL1CFR_PLL1P_0 ( 0x1UL << RCC_PLL1CFR_PLL1P_Pos ) +#define RCC_PLL1CFR_PLL1P_1 ( 0x2UL << RCC_PLL1CFR_PLL1P_Pos ) + +#define RCC_PLL1CFR_PLL1N_Pos ( 12U ) +#define RCC_PLL1CFR_PLL1N_Msk ( 0x3fUL << RCC_PLL1CFR_PLL1N_Pos ) +#define RCC_PLL1CFR_PLL1N ( RCC_PLL1CFR_PLL1N_Msk ) +#define RCC_PLL1CFR_PLL1N_0 ( 0x1UL << RCC_PLL1CFR_PLL1N_Pos ) +#define RCC_PLL1CFR_PLL1N_1 ( 0x2UL << RCC_PLL1CFR_PLL1N_Pos ) +#define RCC_PLL1CFR_PLL1N_2 ( 0x4UL << RCC_PLL1CFR_PLL1N_Pos ) +#define RCC_PLL1CFR_PLL1N_3 ( 0x8UL << RCC_PLL1CFR_PLL1N_Pos ) +#define RCC_PLL1CFR_PLL1N_4 ( 0x10UL << RCC_PLL1CFR_PLL1N_Pos ) +#define RCC_PLL1CFR_PLL1N_5 ( 0x20UL << RCC_PLL1CFR_PLL1N_Pos ) + +#define RCC_PLL1CFR_PLL1F_Pos ( 0U ) +#define RCC_PLL1CFR_PLL1F_Msk ( 0x1ffUL << RCC_PLL1CFR_PLL1F_Pos ) +#define RCC_PLL1CFR_PLL1F ( RCC_PLL1CFR_PLL1F_Msk ) + + +/*************** Bits definition for RCC_PLL1SCR **********************/ + +#define RCC_PLL1SCR_PLL1SSCSTP_Pos ( 17U ) +#define RCC_PLL1SCR_PLL1SSCSTP_Msk ( 0x7fffUL << RCC_PLL1SCR_PLL1SSCSTP_Pos ) +#define RCC_PLL1SCR_PLL1SSCSTP ( RCC_PLL1SCR_PLL1SSCSTP_Msk ) + +#define RCC_PLL1SCR_PLL1SSCPER_Pos ( 4U ) +#define RCC_PLL1SCR_PLL1SSCPER_Msk ( 0x1fffUL << RCC_PLL1SCR_PLL1SSCPER_Pos ) +#define RCC_PLL1SCR_PLL1SSCPER ( RCC_PLL1SCR_PLL1SSCPER_Msk ) + +#define RCC_PLL1SCR_PLL1SSCMD_Pos ( 1U ) +#define RCC_PLL1SCR_PLL1SSCMD_Msk ( 0x1UL << RCC_PLL1SCR_PLL1SSCMD_Pos ) +#define RCC_PLL1SCR_PLL1SSCMD ( RCC_PLL1SCR_PLL1SSCMD_Msk ) + +#define RCC_PLL1SCR_PLL1SSCEN_Pos ( 0U ) +#define RCC_PLL1SCR_PLL1SSCEN_Msk ( 0x1UL << RCC_PLL1SCR_PLL1SSCEN_Pos ) +#define RCC_PLL1SCR_PLL1SSCEN ( RCC_PLL1SCR_PLL1SSCEN_Msk ) + + +/*************** Bits definition for RCC_PLL2CR **********************/ + +#define RCC_PLL2CR_PLL2LOCKSEL_Pos ( 31U ) +#define RCC_PLL2CR_PLL2LOCKSEL_Msk ( 0x1UL << RCC_PLL2CR_PLL2LOCKSEL_Pos ) +#define RCC_PLL2CR_PLL2LOCKSEL ( RCC_PLL2CR_PLL2LOCKSEL_Msk ) + +#define RCC_PLL2CR_PLL2FREERUN_Pos ( 30U ) +#define RCC_PLL2CR_PLL2FREERUN_Msk ( 0x1UL << RCC_PLL2CR_PLL2FREERUN_Pos ) +#define RCC_PLL2CR_PLL2FREERUN ( RCC_PLL2CR_PLL2FREERUN_Msk ) + +#define RCC_PLL2CR_PLL2LOCK_Pos ( 29U ) +#define RCC_PLL2CR_PLL2LOCK_Msk ( 0x1UL << RCC_PLL2CR_PLL2LOCK_Pos ) +#define RCC_PLL2CR_PLL2LOCK ( RCC_PLL2CR_PLL2LOCK_Msk ) + +#define RCC_PLL2CR_PLL2LOCKDLY_Pos ( 23U ) +#define RCC_PLL2CR_PLL2LOCKDLY_Msk ( 0x3fUL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) +#define RCC_PLL2CR_PLL2LOCKDLY ( RCC_PLL2CR_PLL2LOCKDLY_Msk ) +#define RCC_PLL2CR_PLL2LOCKDLY_0 ( 0x1UL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) +#define RCC_PLL2CR_PLL2LOCKDLY_1 ( 0x2UL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) +#define RCC_PLL2CR_PLL2LOCKDLY_2 ( 0x4UL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) +#define RCC_PLL2CR_PLL2LOCKDLY_3 ( 0x8UL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) +#define RCC_PLL2CR_PLL2LOCKDLY_4 ( 0x10UL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) +#define RCC_PLL2CR_PLL2LOCKDLY_5 ( 0x20UL << RCC_PLL2CR_PLL2LOCKDLY_Pos ) + +#define RCC_PLL2CR_PLL2UPDATEEN_Pos ( 22U ) +#define RCC_PLL2CR_PLL2UPDATEEN_Msk ( 0x1UL << RCC_PLL2CR_PLL2UPDATEEN_Pos ) +#define RCC_PLL2CR_PLL2UPDATEEN ( RCC_PLL2CR_PLL2UPDATEEN_Msk ) + +#define RCC_PLL2CR_PLL2SLEEP_Pos ( 21U ) +#define RCC_PLL2CR_PLL2SLEEP_Msk ( 0x1UL << RCC_PLL2CR_PLL2SLEEP_Pos ) +#define RCC_PLL2CR_PLL2SLEEP ( RCC_PLL2CR_PLL2SLEEP_Msk ) + +#define RCC_PLL2CR_PLL2QCLKEN_Pos ( 5U ) +#define RCC_PLL2CR_PLL2QCLKEN_Msk ( 0x1UL << RCC_PLL2CR_PLL2QCLKEN_Pos ) +#define RCC_PLL2CR_PLL2QCLKEN ( RCC_PLL2CR_PLL2QCLKEN_Msk ) + +#define RCC_PLL2CR_PLL2PCLKEN_Pos ( 4U ) +#define RCC_PLL2CR_PLL2PCLKEN_Msk ( 0x1UL << RCC_PLL2CR_PLL2PCLKEN_Pos ) +#define RCC_PLL2CR_PLL2PCLKEN ( RCC_PLL2CR_PLL2PCLKEN_Msk ) + +#define RCC_PLL2CR_PLL2SRCSEL_Pos ( 1U ) +#define RCC_PLL2CR_PLL2SRCSEL_Msk ( 0x1UL << RCC_PLL2CR_PLL2SRCSEL_Pos ) +#define RCC_PLL2CR_PLL2SRCSEL ( RCC_PLL2CR_PLL2SRCSEL_Msk ) + +#define RCC_PLL2CR_PLL2EN_Pos ( 0U ) +#define RCC_PLL2CR_PLL2EN_Msk ( 0x1UL << RCC_PLL2CR_PLL2EN_Pos ) +#define RCC_PLL2CR_PLL2EN ( RCC_PLL2CR_PLL2EN_Msk ) + + +/*************** Bits definition for RCC_PLL2CFR **********************/ + +#define RCC_PLL2CFR_PLL2Q_Pos ( 24U ) +#define RCC_PLL2CFR_PLL2Q_Msk ( 0xfUL << RCC_PLL2CFR_PLL2Q_Pos ) +#define RCC_PLL2CFR_PLL2Q ( RCC_PLL2CFR_PLL2Q_Msk ) +#define RCC_PLL2CFR_PLL2Q_0 ( 0x1UL << RCC_PLL2CFR_PLL2Q_Pos ) +#define RCC_PLL2CFR_PLL2Q_1 ( 0x2UL << RCC_PLL2CFR_PLL2Q_Pos ) +#define RCC_PLL2CFR_PLL2Q_2 ( 0x4UL << RCC_PLL2CFR_PLL2Q_Pos ) +#define RCC_PLL2CFR_PLL2Q_3 ( 0x8UL << RCC_PLL2CFR_PLL2Q_Pos ) + +#define RCC_PLL2CFR_PLL2P_Pos ( 20U ) +#define RCC_PLL2CFR_PLL2P_Msk ( 0x3UL << RCC_PLL2CFR_PLL2P_Pos ) +#define RCC_PLL2CFR_PLL2P ( RCC_PLL2CFR_PLL2P_Msk ) +#define RCC_PLL2CFR_PLL2P_0 ( 0x1UL << RCC_PLL2CFR_PLL2P_Pos ) +#define RCC_PLL2CFR_PLL2P_1 ( 0x2UL << RCC_PLL2CFR_PLL2P_Pos ) + +#define RCC_PLL2CFR_PLL2N_Pos ( 12U ) +#define RCC_PLL2CFR_PLL2N_Msk ( 0x3fUL << RCC_PLL2CFR_PLL2N_Pos ) +#define RCC_PLL2CFR_PLL2N ( RCC_PLL2CFR_PLL2N_Msk ) +#define RCC_PLL2CFR_PLL2N_0 ( 0x1UL << RCC_PLL2CFR_PLL2N_Pos ) +#define RCC_PLL2CFR_PLL2N_1 ( 0x2UL << RCC_PLL2CFR_PLL2N_Pos ) +#define RCC_PLL2CFR_PLL2N_2 ( 0x4UL << RCC_PLL2CFR_PLL2N_Pos ) +#define RCC_PLL2CFR_PLL2N_3 ( 0x8UL << RCC_PLL2CFR_PLL2N_Pos ) +#define RCC_PLL2CFR_PLL2N_4 ( 0x10UL << RCC_PLL2CFR_PLL2N_Pos ) +#define RCC_PLL2CFR_PLL2N_5 ( 0x20UL << RCC_PLL2CFR_PLL2N_Pos ) + +#define RCC_PLL2CFR_PLL2F_Pos ( 0U ) +#define RCC_PLL2CFR_PLL2F_Msk ( 0x1ffUL << RCC_PLL2CFR_PLL2F_Pos ) +#define RCC_PLL2CFR_PLL2F ( RCC_PLL2CFR_PLL2F_Msk ) + + +/*************** Bits definition for RCC_PLL2SCR **********************/ + +#define RCC_PLL2SCR_PLL2SSCSTP_Pos ( 17U ) +#define RCC_PLL2SCR_PLL2SSCSTP_Msk ( 0x7fffUL << RCC_PLL2SCR_PLL2SSCSTP_Pos ) +#define RCC_PLL2SCR_PLL2SSCSTP ( RCC_PLL2SCR_PLL2SSCSTP_Msk ) + +#define RCC_PLL2SCR_PLL2SSCPER_Pos ( 4U ) +#define RCC_PLL2SCR_PLL2SSCPER_Msk ( 0x1fffUL << RCC_PLL2SCR_PLL2SSCPER_Pos ) +#define RCC_PLL2SCR_PLL2SSCPER ( RCC_PLL2SCR_PLL2SSCPER_Msk ) + +#define RCC_PLL2SCR_PLL2SSCMD_Pos ( 1U ) +#define RCC_PLL2SCR_PLL2SSCMD_Msk ( 0x1UL << RCC_PLL2SCR_PLL2SSCMD_Pos ) +#define RCC_PLL2SCR_PLL2SSCMD ( RCC_PLL2SCR_PLL2SSCMD_Msk ) + +#define RCC_PLL2SCR_PLL2SSCEN_Pos ( 0U ) +#define RCC_PLL2SCR_PLL2SSCEN_Msk ( 0x1UL << RCC_PLL2SCR_PLL2SSCEN_Pos ) +#define RCC_PLL2SCR_PLL2SSCEN ( RCC_PLL2SCR_PLL2SSCEN_Msk ) + + +/*************** Bits definition for RCC_PLL3CR **********************/ + +#define RCC_PLL3CR_PLL3LOCKSEL_Pos ( 31U ) +#define RCC_PLL3CR_PLL3LOCKSEL_Msk ( 0x1UL << RCC_PLL3CR_PLL3LOCKSEL_Pos ) +#define RCC_PLL3CR_PLL3LOCKSEL ( RCC_PLL3CR_PLL3LOCKSEL_Msk ) + +#define RCC_PLL3CR_PLL3FREERUN_Pos ( 30U ) +#define RCC_PLL3CR_PLL3FREERUN_Msk ( 0x1UL << RCC_PLL3CR_PLL3FREERUN_Pos ) +#define RCC_PLL3CR_PLL3FREERUN ( RCC_PLL3CR_PLL3FREERUN_Msk ) + +#define RCC_PLL3CR_PLL3LOCK_Pos ( 29U ) +#define RCC_PLL3CR_PLL3LOCK_Msk ( 0x1UL << RCC_PLL3CR_PLL3LOCK_Pos ) +#define RCC_PLL3CR_PLL3LOCK ( RCC_PLL3CR_PLL3LOCK_Msk ) + +#define RCC_PLL3CR_PLL3LOCKDLY_Pos ( 23U ) +#define RCC_PLL3CR_PLL3LOCKDLY_Msk ( 0x3fUL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) +#define RCC_PLL3CR_PLL3LOCKDLY ( RCC_PLL3CR_PLL3LOCKDLY_Msk ) +#define RCC_PLL3CR_PLL3LOCKDLY_0 ( 0x1UL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) +#define RCC_PLL3CR_PLL3LOCKDLY_1 ( 0x2UL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) +#define RCC_PLL3CR_PLL3LOCKDLY_2 ( 0x4UL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) +#define RCC_PLL3CR_PLL3LOCKDLY_3 ( 0x8UL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) +#define RCC_PLL3CR_PLL3LOCKDLY_4 ( 0x10UL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) +#define RCC_PLL3CR_PLL3LOCKDLY_5 ( 0x20UL << RCC_PLL3CR_PLL3LOCKDLY_Pos ) + +#define RCC_PLL3CR_PLL3UPDATEEN_Pos ( 22U ) +#define RCC_PLL3CR_PLL3UPDATEEN_Msk ( 0x1UL << RCC_PLL3CR_PLL3UPDATEEN_Pos ) +#define RCC_PLL3CR_PLL3UPDATEEN ( RCC_PLL3CR_PLL3UPDATEEN_Msk ) + +#define RCC_PLL3CR_PLL3SLEEP_Pos ( 21U ) +#define RCC_PLL3CR_PLL3SLEEP_Msk ( 0x1UL << RCC_PLL3CR_PLL3SLEEP_Pos ) +#define RCC_PLL3CR_PLL3SLEEP ( RCC_PLL3CR_PLL3SLEEP_Msk ) + +#define RCC_PLL3CR_PLL3QCLKEN_Pos ( 5U ) +#define RCC_PLL3CR_PLL3QCLKEN_Msk ( 0x1UL << RCC_PLL3CR_PLL3QCLKEN_Pos ) +#define RCC_PLL3CR_PLL3QCLKEN ( RCC_PLL3CR_PLL3QCLKEN_Msk ) + +#define RCC_PLL3CR_PLL3PCLKEN_Pos ( 4U ) +#define RCC_PLL3CR_PLL3PCLKEN_Msk ( 0x1UL << RCC_PLL3CR_PLL3PCLKEN_Pos ) +#define RCC_PLL3CR_PLL3PCLKEN ( RCC_PLL3CR_PLL3PCLKEN_Msk ) + +#define RCC_PLL3CR_PLL3SRCSEL_Pos ( 1U ) +#define RCC_PLL3CR_PLL3SRCSEL_Msk ( 0x1UL << RCC_PLL3CR_PLL3SRCSEL_Pos ) +#define RCC_PLL3CR_PLL3SRCSEL ( RCC_PLL3CR_PLL3SRCSEL_Msk ) + +#define RCC_PLL3CR_PLL3EN_Pos ( 0U ) +#define RCC_PLL3CR_PLL3EN_Msk ( 0x1UL << RCC_PLL3CR_PLL3EN_Pos ) +#define RCC_PLL3CR_PLL3EN ( RCC_PLL3CR_PLL3EN_Msk ) + + +/*************** Bits definition for RCC_PLL3CFR **********************/ + +#define RCC_PLL3CFR_PLL3Q_Pos ( 24U ) +#define RCC_PLL3CFR_PLL3Q_Msk ( 0x3UL << RCC_PLL3CFR_PLL3Q_Pos ) +#define RCC_PLL3CFR_PLL3Q ( RCC_PLL3CFR_PLL3Q_Msk ) +#define RCC_PLL3CFR_PLL3Q_0 ( 0x1UL << RCC_PLL3CFR_PLL3Q_Pos ) +#define RCC_PLL3CFR_PLL3Q_1 ( 0x2UL << RCC_PLL3CFR_PLL3Q_Pos ) + +#define RCC_PLL3CFR_PLL3P_Pos ( 20U ) +#define RCC_PLL3CFR_PLL3P_Msk ( 0x3UL << RCC_PLL3CFR_PLL3P_Pos ) +#define RCC_PLL3CFR_PLL3P ( RCC_PLL3CFR_PLL3P_Msk ) +#define RCC_PLL3CFR_PLL3P_0 ( 0x1UL << RCC_PLL3CFR_PLL3P_Pos ) +#define RCC_PLL3CFR_PLL3P_1 ( 0x2UL << RCC_PLL3CFR_PLL3P_Pos ) + +#define RCC_PLL3CFR_PLL3N_Pos ( 12U ) +#define RCC_PLL3CFR_PLL3N_Msk ( 0x3fUL << RCC_PLL3CFR_PLL3N_Pos ) +#define RCC_PLL3CFR_PLL3N ( RCC_PLL3CFR_PLL3N_Msk ) +#define RCC_PLL3CFR_PLL3N_0 ( 0x1UL << RCC_PLL3CFR_PLL3N_Pos ) +#define RCC_PLL3CFR_PLL3N_1 ( 0x2UL << RCC_PLL3CFR_PLL3N_Pos ) + +#define RCC_PLL3CFR_PLL3F_Pos ( 0U ) +#define RCC_PLL3CFR_PLL3F_Msk ( 0x7fUL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F ( RCC_PLL3CFR_PLL3F_Msk ) +#define RCC_PLL3CFR_PLL3F_0 ( 0x01UL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F_1 ( 0x02UL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F_2 ( 0x04UL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F_3 ( 0x08UL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F_4 ( 0x10UL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F_5 ( 0x20UL << RCC_PLL3CFR_PLL3F_Pos ) +#define RCC_PLL3CFR_PLL3F_6 ( 0x40UL << RCC_PLL3CFR_PLL3F_Pos ) + +/*************** Bits definition for RCC_CLKOCR **********************/ + +#define RCC_CLKOCR_MCO2EN_Pos ( 31U ) +#define RCC_CLKOCR_MCO2EN_Msk ( 0x1UL << RCC_CLKOCR_MCO2EN_Pos ) +#define RCC_CLKOCR_MCO2EN ( RCC_CLKOCR_MCO2EN_Msk ) + +#define RCC_CLKOCR_MCO2POL_Pos ( 30U ) +#define RCC_CLKOCR_MCO2POL_Msk ( 0x1UL << RCC_CLKOCR_MCO2POL_Pos ) +#define RCC_CLKOCR_MCO2POL ( RCC_CLKOCR_MCO2POL_Msk ) + +#define RCC_CLKOCR_MCO2DIV_Pos ( 24U ) +#define RCC_CLKOCR_MCO2DIV_Msk ( 0x3fUL << RCC_CLKOCR_MCO2DIV_Pos ) +#define RCC_CLKOCR_MCO2DIV ( RCC_CLKOCR_MCO2DIV_Msk ) +#define RCC_CLKOCR_MCO2DIV_0 ( 0x1UL << RCC_CLKOCR_MCO2DIV_Pos ) +#define RCC_CLKOCR_MCO2DIV_1 ( 0x2UL << RCC_CLKOCR_MCO2DIV_Pos ) +#define RCC_CLKOCR_MCO2DIV_2 ( 0x4UL << RCC_CLKOCR_MCO2DIV_Pos ) +#define RCC_CLKOCR_MCO2DIV_3 ( 0x8UL << RCC_CLKOCR_MCO2DIV_Pos ) +#define RCC_CLKOCR_MCO2DIV_4 ( 0x10UL << RCC_CLKOCR_MCO2DIV_Pos ) +#define RCC_CLKOCR_MCO2DIV_5 ( 0x20UL << RCC_CLKOCR_MCO2DIV_Pos ) + +#define RCC_CLKOCR_MCO1EN_Pos ( 23U ) +#define RCC_CLKOCR_MCO1EN_Msk ( 0x1UL << RCC_CLKOCR_MCO1EN_Pos ) +#define RCC_CLKOCR_MCO1EN ( RCC_CLKOCR_MCO1EN_Msk ) + +#define RCC_CLKOCR_MCO1POL_Pos ( 22U ) +#define RCC_CLKOCR_MCO1POL_Msk ( 0x1UL << RCC_CLKOCR_MCO1POL_Pos ) +#define RCC_CLKOCR_MCO1POL ( RCC_CLKOCR_MCO1POL_Msk ) + +#define RCC_CLKOCR_MCO1DIV_Pos ( 6U ) +#define RCC_CLKOCR_MCO1DIV_Msk ( 0xffffUL << RCC_CLKOCR_MCO1DIV_Pos ) +#define RCC_CLKOCR_MCO1DIV ( RCC_CLKOCR_MCO1DIV_Msk ) + +#define RCC_CLKOCR_MCO1SEL_Pos ( 5U ) +#define RCC_CLKOCR_MCO1SEL_Msk ( 0x1UL << RCC_CLKOCR_MCO1SEL_Pos ) +#define RCC_CLKOCR_MCO1SEL ( RCC_CLKOCR_MCO1SEL_Msk ) + +#define RCC_CLKOCR_MCOCLKS_Pos ( 0U ) +#define RCC_CLKOCR_MCOCLKS_Msk ( 0x1fUL << RCC_CLKOCR_MCOCLKS_Pos ) +#define RCC_CLKOCR_MCOCLKS ( RCC_CLKOCR_MCOCLKS_Msk ) +#define RCC_CLKOCR_MCOCLKS_0 ( 0x01UL << RCC_CLKOCR_MCOCLKS_Pos ) +#define RCC_CLKOCR_MCOCLKS_1 ( 0x02UL << RCC_CLKOCR_MCOCLKS_Pos ) +#define RCC_CLKOCR_MCOCLKS_2 ( 0x04UL << RCC_CLKOCR_MCOCLKS_Pos ) +#define RCC_CLKOCR_MCOCLKS_3 ( 0x08UL << RCC_CLKOCR_MCOCLKS_Pos ) +#define RCC_CLKOCR_MCOCLKS_4 ( 0x10UL << RCC_CLKOCR_MCOCLKS_Pos ) + + +/*************** Bits definition for RCC_DCKCFG **********************/ + +#define RCC_DCKCFG_LCDDIV_Pos ( 0U ) +#define RCC_DCKCFG_LCDDIV_Msk ( 0x3UL << RCC_DCKCFG_LCDDIV_Pos ) +#define RCC_DCKCFG_LCDDIV ( RCC_DCKCFG_LCDDIV_Msk ) +#define RCC_DCKCFG_LCDDIV_0 ( 0x1UL << RCC_DCKCFG_LCDDIV_Pos ) +#define RCC_DCKCFG_LCDDIV_1 ( 0x2UL << RCC_DCKCFG_LCDDIV_Pos ) + + +/*************** Bits definition for RCC_STDBYCTRL **********************/ + +#define RCC_STDBYCTRL_STDBYRST_Pos ( 23U ) +#define RCC_STDBYCTRL_STDBYRST_Msk ( 0x1UL << RCC_STDBYCTRL_STDBYRST_Pos ) +#define RCC_STDBYCTRL_STDBYRST ( RCC_STDBYCTRL_STDBYRST_Msk ) + +#define RCC_STDBYCTRL_RTCEN_Pos ( 22U ) +#define RCC_STDBYCTRL_RTCEN_Msk ( 0x1UL << RCC_STDBYCTRL_RTCEN_Pos ) +#define RCC_STDBYCTRL_RTCEN ( RCC_STDBYCTRL_RTCEN_Msk ) + +#define RCC_STDBYCTRL_RTCSEL_Pos ( 20U ) +#define RCC_STDBYCTRL_RTCSEL_Msk ( 0x3UL << RCC_STDBYCTRL_RTCSEL_Pos ) +#define RCC_STDBYCTRL_RTCSEL ( RCC_STDBYCTRL_RTCSEL_Msk ) +#define RCC_STDBYCTRL_RTCSEL_0 ( 0x1UL << RCC_STDBYCTRL_RTCSEL_Pos ) +#define RCC_STDBYCTRL_RTCSEL_1 ( 0x2UL << RCC_STDBYCTRL_RTCSEL_Pos ) + +#define RCC_STDBYCTRL_RCLDIS_Pos ( 16U ) +#define RCC_STDBYCTRL_RCLDIS_Msk ( 0xFUL << RCC_STDBYCTRL_RCLDIS_Pos ) +#define RCC_STDBYCTRL_RCLDIS ( RCC_STDBYCTRL_RCLDIS_Msk ) +#define RCC_STDBYCTRL_RCLDIS_0 ( 0x1UL << RCC_STDBYCTRL_RCLDIS_Pos ) +#define RCC_STDBYCTRL_RCLDIS_1 ( 0x2UL << RCC_STDBYCTRL_RCLDIS_Pos ) +#define RCC_STDBYCTRL_RCLDIS_2 ( 0x4UL << RCC_STDBYCTRL_RCLDIS_Pos ) +#define RCC_STDBYCTRL_RCLDIS_3 ( 0x8UL << RCC_STDBYCTRL_RCLDIS_Pos ) + +#define RCC_STDBYCTRL_RCLTRIM_Pos ( 10U ) +#define RCC_STDBYCTRL_RCLTRIM_Msk ( 0x3fUL << RCC_STDBYCTRL_RCLTRIM_Pos ) +#define RCC_STDBYCTRL_RCLTRIM ( RCC_STDBYCTRL_RCLTRIM_Msk ) +#define RCC_STDBYCTRL_RCLTRIM_0 ( 0x1UL << RCC_STDBYCTRL_RCLTRIM_Pos ) +#define RCC_STDBYCTRL_RCLTRIM_1 ( 0x2UL << RCC_STDBYCTRL_RCLTRIM_Pos ) +#define RCC_STDBYCTRL_RCLTRIM_2 ( 0x4UL << RCC_STDBYCTRL_RCLTRIM_Pos ) +#define RCC_STDBYCTRL_RCLTRIM_3 ( 0x8UL << RCC_STDBYCTRL_RCLTRIM_Pos ) +#define RCC_STDBYCTRL_RCLTRIM_4 ( 0x10UL << RCC_STDBYCTRL_RCLTRIM_Pos ) +#define RCC_STDBYCTRL_RCLTRIM_5 ( 0x20UL << RCC_STDBYCTRL_RCLTRIM_Pos ) + +#define RCC_STDBYCTRL_RCLRDY_Pos ( 9U ) +#define RCC_STDBYCTRL_RCLRDY_Msk ( 0x1UL << RCC_STDBYCTRL_RCLRDY_Pos ) +#define RCC_STDBYCTRL_RCLRDY ( RCC_STDBYCTRL_RCLRDY_Msk ) + +#define RCC_STDBYCTRL_RCLEN_Pos ( 8U ) +#define RCC_STDBYCTRL_RCLEN_Msk ( 0x1UL << RCC_STDBYCTRL_RCLEN_Pos ) +#define RCC_STDBYCTRL_RCLEN ( RCC_STDBYCTRL_RCLEN_Msk ) + +#define RCC_STDBYCTRL_XTLSDEN_Pos ( 6U ) +#define RCC_STDBYCTRL_XTLSDEN_Msk ( 0x1UL << RCC_STDBYCTRL_XTLSDEN_Pos ) +#define RCC_STDBYCTRL_XTLSDEN ( RCC_STDBYCTRL_XTLSDEN_Msk ) + +#define RCC_STDBYCTRL_XTLDRV_Pos ( 3U ) +#define RCC_STDBYCTRL_XTLDRV_Msk ( 0x7UL << RCC_STDBYCTRL_XTLDRV_Pos ) +#define RCC_STDBYCTRL_XTLDRV ( RCC_STDBYCTRL_XTLDRV_Msk ) +#define RCC_STDBYCTRL_XTLDRV_0 ( 0x1UL << RCC_STDBYCTRL_XTLDRV_Pos ) +#define RCC_STDBYCTRL_XTLDRV_1 ( 0x2UL << RCC_STDBYCTRL_XTLDRV_Pos ) +#define RCC_STDBYCTRL_XTLDRV_2 ( 0x4UL << RCC_STDBYCTRL_XTLDRV_Pos ) + +#define RCC_STDBYCTRL_XTLBYP_Pos ( 2U ) +#define RCC_STDBYCTRL_XTLBYP_Msk ( 0x1UL << RCC_STDBYCTRL_XTLBYP_Pos ) +#define RCC_STDBYCTRL_XTLBYP ( RCC_STDBYCTRL_XTLBYP_Msk ) + +#define RCC_STDBYCTRL_XTLRDY_Pos ( 1U ) +#define RCC_STDBYCTRL_XTLRDY_Msk ( 0x1UL << RCC_STDBYCTRL_XTLRDY_Pos ) +#define RCC_STDBYCTRL_XTLRDY ( RCC_STDBYCTRL_XTLRDY_Msk ) + +#define RCC_STDBYCTRL_XTLEN_Pos ( 0U ) +#define RCC_STDBYCTRL_XTLEN_Msk ( 0x1UL << RCC_STDBYCTRL_XTLEN_Pos ) +#define RCC_STDBYCTRL_XTLEN ( RCC_STDBYCTRL_XTLEN_Msk ) + + +/*************** Bits definition for GPIO_MD **********************/ + +#define GPIO_MD_MD_15_Pos ( 30U ) +#define GPIO_MD_MD_15_Msk ( 0x3UL << GPIO_MD_MD_15_Pos ) +#define GPIO_MD_MD_15 ( GPIO_MD_MD_15_Msk ) +#define GPIO_MD_MD_15_0 ( 0x1UL << GPIO_MD_MD_15_Pos ) +#define GPIO_MD_MD_15_1 ( 0x2UL << GPIO_MD_MD_15_Pos ) + +#define GPIO_MD_MD_14_Pos ( 28U ) +#define GPIO_MD_MD_14_Msk ( 0x3UL << GPIO_MD_MD_14_Pos ) +#define GPIO_MD_MD_14 ( GPIO_MD_MD_14_Msk ) +#define GPIO_MD_MD_14_0 ( 0x1UL << GPIO_MD_MD_14_Pos ) +#define GPIO_MD_MD_14_1 ( 0x2UL << GPIO_MD_MD_14_Pos ) + +#define GPIO_MD_MD_13_Pos ( 26U ) +#define GPIO_MD_MD_13_Msk ( 0x3UL << GPIO_MD_MD_13_Pos ) +#define GPIO_MD_MD_13 ( GPIO_MD_MD_13_Msk ) +#define GPIO_MD_MD_13_0 ( 0x1UL << GPIO_MD_MD_13_Pos ) +#define GPIO_MD_MD_13_1 ( 0x2UL << GPIO_MD_MD_13_Pos ) + +#define GPIO_MD_MD_12_Pos ( 24U ) +#define GPIO_MD_MD_12_Msk ( 0x3UL << GPIO_MD_MD_12_Pos ) +#define GPIO_MD_MD_12 ( GPIO_MD_MD_12_Msk ) +#define GPIO_MD_MD_12_0 ( 0x1UL << GPIO_MD_MD_12_Pos ) +#define GPIO_MD_MD_12_1 ( 0x2UL << GPIO_MD_MD_12_Pos ) + +#define GPIO_MD_MD_11_Pos ( 22U ) +#define GPIO_MD_MD_11_Msk ( 0x3UL << GPIO_MD_MD_11_Pos ) +#define GPIO_MD_MD_11 ( GPIO_MD_MD_11_Msk ) +#define GPIO_MD_MD_11_0 ( 0x1UL << GPIO_MD_MD_11_Pos ) +#define GPIO_MD_MD_11_1 ( 0x2UL << GPIO_MD_MD_11_Pos ) + +#define GPIO_MD_MD_10_Pos ( 20U ) +#define GPIO_MD_MD_10_Msk ( 0x3UL << GPIO_MD_MD_10_Pos ) +#define GPIO_MD_MD_10 ( GPIO_MD_MD_10_Msk ) +#define GPIO_MD_MD_10_0 ( 0x1UL << GPIO_MD_MD_10_Pos ) +#define GPIO_MD_MD_10_1 ( 0x2UL << GPIO_MD_MD_10_Pos ) + +#define GPIO_MD_MD_9_Pos ( 18U ) +#define GPIO_MD_MD_9_Msk ( 0x3UL << GPIO_MD_MD_9_Pos ) +#define GPIO_MD_MD_9 ( GPIO_MD_MD_9_Msk ) +#define GPIO_MD_MD_9_0 ( 0x1UL << GPIO_MD_MD_9_Pos ) +#define GPIO_MD_MD_9_1 ( 0x2UL << GPIO_MD_MD_9_Pos ) + +#define GPIO_MD_MD_8_Pos ( 16U ) +#define GPIO_MD_MD_8_Msk ( 0x3UL << GPIO_MD_MD_8_Pos ) +#define GPIO_MD_MD_8 ( GPIO_MD_MD_8_Msk ) +#define GPIO_MD_MD_8_0 ( 0x1UL << GPIO_MD_MD_8_Pos ) +#define GPIO_MD_MD_8_1 ( 0x2UL << GPIO_MD_MD_8_Pos ) + +#define GPIO_MD_MD_7_Pos ( 14U ) +#define GPIO_MD_MD_7_Msk ( 0x3UL << GPIO_MD_MD_7_Pos ) +#define GPIO_MD_MD_7 ( GPIO_MD_MD_7_Msk ) +#define GPIO_MD_MD_7_0 ( 0x1UL << GPIO_MD_MD_7_Pos ) +#define GPIO_MD_MD_7_1 ( 0x2UL << GPIO_MD_MD_7_Pos ) + +#define GPIO_MD_MD_6_Pos ( 12U ) +#define GPIO_MD_MD_6_Msk ( 0x3UL << GPIO_MD_MD_6_Pos ) +#define GPIO_MD_MD_6 ( GPIO_MD_MD_6_Msk ) +#define GPIO_MD_MD_6_0 ( 0x1UL << GPIO_MD_MD_6_Pos ) +#define GPIO_MD_MD_6_1 ( 0x2UL << GPIO_MD_MD_6_Pos ) + +#define GPIO_MD_MD_5_Pos ( 10U ) +#define GPIO_MD_MD_5_Msk ( 0x3UL << GPIO_MD_MD_5_Pos ) +#define GPIO_MD_MD_5 ( GPIO_MD_MD_5_Msk ) +#define GPIO_MD_MD_5_0 ( 0x1UL << GPIO_MD_MD_5_Pos ) +#define GPIO_MD_MD_5_1 ( 0x2UL << GPIO_MD_MD_5_Pos ) + +#define GPIO_MD_MD_4_Pos ( 8U ) +#define GPIO_MD_MD_4_Msk ( 0x3UL << GPIO_MD_MD_4_Pos ) +#define GPIO_MD_MD_4 ( GPIO_MD_MD_4_Msk ) +#define GPIO_MD_MD_4_0 ( 0x1UL << GPIO_MD_MD_4_Pos ) +#define GPIO_MD_MD_4_1 ( 0x2UL << GPIO_MD_MD_4_Pos ) + +#define GPIO_MD_MD_3_Pos ( 6U ) +#define GPIO_MD_MD_3_Msk ( 0x3UL << GPIO_MD_MD_3_Pos ) +#define GPIO_MD_MD_3 ( GPIO_MD_MD_3_Msk ) +#define GPIO_MD_MD_3_0 ( 0x1UL << GPIO_MD_MD_3_Pos ) +#define GPIO_MD_MD_3_1 ( 0x2UL << GPIO_MD_MD_3_Pos ) + +#define GPIO_MD_MD_2_Pos ( 4U ) +#define GPIO_MD_MD_2_Msk ( 0x3UL << GPIO_MD_MD_2_Pos ) +#define GPIO_MD_MD_2 ( GPIO_MD_MD_2_Msk ) +#define GPIO_MD_MD_2_0 ( 0x1UL << GPIO_MD_MD_2_Pos ) +#define GPIO_MD_MD_2_1 ( 0x2UL << GPIO_MD_MD_2_Pos ) + +#define GPIO_MD_MD_1_Pos ( 2U ) +#define GPIO_MD_MD_1_Msk ( 0x3UL << GPIO_MD_MD_1_Pos ) +#define GPIO_MD_MD_1 ( GPIO_MD_MD_1_Msk ) +#define GPIO_MD_MD_1_0 ( 0x1UL << GPIO_MD_MD_1_Pos ) +#define GPIO_MD_MD_1_1 ( 0x2UL << GPIO_MD_MD_1_Pos ) + +#define GPIO_MD_MD_0_Pos ( 0U ) +#define GPIO_MD_MD_0_Msk ( 0x3UL << GPIO_MD_MD_0_Pos ) +#define GPIO_MD_MD_0 ( GPIO_MD_MD_0_Msk ) +#define GPIO_MD_MD_0_0 ( 0x1UL << GPIO_MD_MD_0_Pos ) +#define GPIO_MD_MD_0_1 ( 0x2UL << GPIO_MD_MD_0_Pos ) + + +/*************** Bits definition for GPIO_OTYP **********************/ + +#define GPIO_OTYP_OTYP15_Pos ( 15U ) +#define GPIO_OTYP_OTYP15_Msk ( 0x1UL << GPIO_OTYP_OTYP15_Pos ) +#define GPIO_OTYP_OTYP15 ( GPIO_OTYP_OTYP15_Msk ) + + +#define GPIO_OTYP_OTYP14_Pos ( 14U ) +#define GPIO_OTYP_OTYP14_Msk ( 0x1UL << GPIO_OTYP_OTYP14_Pos ) +#define GPIO_OTYP_OTYP14 ( GPIO_OTYP_OTYP14_Msk ) + + +#define GPIO_OTYP_OTYP13_Pos ( 13U ) +#define GPIO_OTYP_OTYP13_Msk ( 0x1UL << GPIO_OTYP_OTYP13_Pos ) +#define GPIO_OTYP_OTYP13 ( GPIO_OTYP_OTYP13_Msk ) + + +#define GPIO_OTYP_OTYP12_Pos ( 12U ) +#define GPIO_OTYP_OTYP12_Msk ( 0x1UL << GPIO_OTYP_OTYP12_Pos ) +#define GPIO_OTYP_OTYP12 ( GPIO_OTYP_OTYP12_Msk ) + + +#define GPIO_OTYP_OTYP11_Pos ( 11U ) +#define GPIO_OTYP_OTYP11_Msk ( 0x1UL << GPIO_OTYP_OTYP11_Pos ) +#define GPIO_OTYP_OTYP11 ( GPIO_OTYP_OTYP11_Msk ) + + +#define GPIO_OTYP_OTYP10_Pos ( 10U ) +#define GPIO_OTYP_OTYP10_Msk ( 0x1UL << GPIO_OTYP_OTYP10_Pos ) +#define GPIO_OTYP_OTYP10 ( GPIO_OTYP_OTYP10_Msk ) + + +#define GPIO_OTYP_OTYP9_Pos ( 9U ) +#define GPIO_OTYP_OTYP9_Msk ( 0x1UL << GPIO_OTYP_OTYP9_Pos ) +#define GPIO_OTYP_OTYP9 ( GPIO_OTYP_OTYP9_Msk ) + + +#define GPIO_OTYP_OTYP8_Pos ( 8U ) +#define GPIO_OTYP_OTYP8_Msk ( 0x1UL << GPIO_OTYP_OTYP8_Pos ) +#define GPIO_OTYP_OTYP8 ( GPIO_OTYP_OTYP8_Msk ) + + +#define GPIO_OTYP_OTYP7_Pos ( 7U ) +#define GPIO_OTYP_OTYP7_Msk ( 0x1UL << GPIO_OTYP_OTYP7_Pos ) +#define GPIO_OTYP_OTYP7 ( GPIO_OTYP_OTYP7_Msk ) + + +#define GPIO_OTYP_OTYP6_Pos ( 6U ) +#define GPIO_OTYP_OTYP6_Msk ( 0x1UL << GPIO_OTYP_OTYP6_Pos ) +#define GPIO_OTYP_OTYP6 ( GPIO_OTYP_OTYP6_Msk ) + + +#define GPIO_OTYP_OTYP5_Pos ( 5U ) +#define GPIO_OTYP_OTYP5_Msk ( 0x1UL << GPIO_OTYP_OTYP5_Pos ) +#define GPIO_OTYP_OTYP5 ( GPIO_OTYP_OTYP5_Msk ) + + +#define GPIO_OTYP_OTYP4_Pos ( 4U ) +#define GPIO_OTYP_OTYP4_Msk ( 0x1UL << GPIO_OTYP_OTYP4_Pos ) +#define GPIO_OTYP_OTYP4 ( GPIO_OTYP_OTYP4_Msk ) + + +#define GPIO_OTYP_OTYP3_Pos ( 3U ) +#define GPIO_OTYP_OTYP3_Msk ( 0x1UL << GPIO_OTYP_OTYP3_Pos ) +#define GPIO_OTYP_OTYP3 ( GPIO_OTYP_OTYP3_Msk ) + + +#define GPIO_OTYP_OTYP2_Pos ( 2U ) +#define GPIO_OTYP_OTYP2_Msk ( 0x1UL << GPIO_OTYP_OTYP2_Pos ) +#define GPIO_OTYP_OTYP2 ( GPIO_OTYP_OTYP2_Msk ) + + +#define GPIO_OTYP_OTYP1_Pos ( 1U ) +#define GPIO_OTYP_OTYP1_Msk ( 0x1UL << GPIO_OTYP_OTYP1_Pos ) +#define GPIO_OTYP_OTYP1 ( GPIO_OTYP_OTYP1_Msk ) + + +#define GPIO_OTYP_OTYP0_Pos ( 0U ) +#define GPIO_OTYP_OTYP0_Msk ( 0x1UL << GPIO_OTYP_OTYP0_Pos ) +#define GPIO_OTYP_OTYP0 ( GPIO_OTYP_OTYP0_Msk ) + + + +/*************** Bits definition for GPIO_PUPD **********************/ + +#define GPIO_PUPD_PUPD_15_Pos ( 30U ) +#define GPIO_PUPD_PUPD_15_Msk ( 0x3UL << GPIO_PUPD_PUPD_15_Pos ) +#define GPIO_PUPD_PUPD_15 ( GPIO_PUPD_PUPD_15_Msk ) +#define GPIO_PUPD_PUPD_15_0 ( 0x1UL << GPIO_PUPD_PUPD_15_Pos ) +#define GPIO_PUPD_PUPD_15_1 ( 0x2UL << GPIO_PUPD_PUPD_15_Pos ) + +#define GPIO_PUPD_PUPD_14_Pos ( 28U ) +#define GPIO_PUPD_PUPD_14_Msk ( 0x3UL << GPIO_PUPD_PUPD_14_Pos ) +#define GPIO_PUPD_PUPD_14 ( GPIO_PUPD_PUPD_14_Msk ) +#define GPIO_PUPD_PUPD_14_0 ( 0x1UL << GPIO_PUPD_PUPD_14_Pos ) +#define GPIO_PUPD_PUPD_14_1 ( 0x2UL << GPIO_PUPD_PUPD_14_Pos ) + +#define GPIO_PUPD_PUPD_13_Pos ( 26U ) +#define GPIO_PUPD_PUPD_13_Msk ( 0x3UL << GPIO_PUPD_PUPD_13_Pos ) +#define GPIO_PUPD_PUPD_13 ( GPIO_PUPD_PUPD_13_Msk ) +#define GPIO_PUPD_PUPD_13_0 ( 0x1UL << GPIO_PUPD_PUPD_13_Pos ) +#define GPIO_PUPD_PUPD_13_1 ( 0x2UL << GPIO_PUPD_PUPD_13_Pos ) + +#define GPIO_PUPD_PUPD_12_Pos ( 24U ) +#define GPIO_PUPD_PUPD_12_Msk ( 0x3UL << GPIO_PUPD_PUPD_12_Pos ) +#define GPIO_PUPD_PUPD_12 ( GPIO_PUPD_PUPD_12_Msk ) +#define GPIO_PUPD_PUPD_12_0 ( 0x1UL << GPIO_PUPD_PUPD_12_Pos ) +#define GPIO_PUPD_PUPD_12_1 ( 0x2UL << GPIO_PUPD_PUPD_12_Pos ) + +#define GPIO_PUPD_PUPD_11_Pos ( 22U ) +#define GPIO_PUPD_PUPD_11_Msk ( 0x3UL << GPIO_PUPD_PUPD_11_Pos ) +#define GPIO_PUPD_PUPD_11 ( GPIO_PUPD_PUPD_11_Msk ) +#define GPIO_PUPD_PUPD_11_0 ( 0x1UL << GPIO_PUPD_PUPD_11_Pos ) +#define GPIO_PUPD_PUPD_11_1 ( 0x2UL << GPIO_PUPD_PUPD_11_Pos ) + +#define GPIO_PUPD_PUPD_10_Pos ( 20U ) +#define GPIO_PUPD_PUPD_10_Msk ( 0x3UL << GPIO_PUPD_PUPD_10_Pos ) +#define GPIO_PUPD_PUPD_10 ( GPIO_PUPD_PUPD_10_Msk ) +#define GPIO_PUPD_PUPD_10_0 ( 0x1UL << GPIO_PUPD_PUPD_10_Pos ) +#define GPIO_PUPD_PUPD_10_1 ( 0x2UL << GPIO_PUPD_PUPD_10_Pos ) + +#define GPIO_PUPD_PUPD_9_Pos ( 18U ) +#define GPIO_PUPD_PUPD_9_Msk ( 0x3UL << GPIO_PUPD_PUPD_9_Pos ) +#define GPIO_PUPD_PUPD_9 ( GPIO_PUPD_PUPD_9_Msk ) +#define GPIO_PUPD_PUPD_9_0 ( 0x1UL << GPIO_PUPD_PUPD_9_Pos ) +#define GPIO_PUPD_PUPD_9_1 ( 0x2UL << GPIO_PUPD_PUPD_9_Pos ) + +#define GPIO_PUPD_PUPD_8_Pos ( 16U ) +#define GPIO_PUPD_PUPD_8_Msk ( 0x3UL << GPIO_PUPD_PUPD_8_Pos ) +#define GPIO_PUPD_PUPD_8 ( GPIO_PUPD_PUPD_8_Msk ) +#define GPIO_PUPD_PUPD_8_0 ( 0x1UL << GPIO_PUPD_PUPD_8_Pos ) +#define GPIO_PUPD_PUPD_8_1 ( 0x2UL << GPIO_PUPD_PUPD_8_Pos ) + +#define GPIO_PUPD_PUPD_7_Pos ( 14U ) +#define GPIO_PUPD_PUPD_7_Msk ( 0x3UL << GPIO_PUPD_PUPD_7_Pos ) +#define GPIO_PUPD_PUPD_7 ( GPIO_PUPD_PUPD_7_Msk ) +#define GPIO_PUPD_PUPD_7_0 ( 0x1UL << GPIO_PUPD_PUPD_7_Pos ) +#define GPIO_PUPD_PUPD_7_1 ( 0x2UL << GPIO_PUPD_PUPD_7_Pos ) + +#define GPIO_PUPD_PUPD_6_Pos ( 12U ) +#define GPIO_PUPD_PUPD_6_Msk ( 0x3UL << GPIO_PUPD_PUPD_6_Pos ) +#define GPIO_PUPD_PUPD_6 ( GPIO_PUPD_PUPD_6_Msk ) +#define GPIO_PUPD_PUPD_6_0 ( 0x1UL << GPIO_PUPD_PUPD_6_Pos ) +#define GPIO_PUPD_PUPD_6_1 ( 0x2UL << GPIO_PUPD_PUPD_6_Pos ) + +#define GPIO_PUPD_PUPD_5_Pos ( 10U ) +#define GPIO_PUPD_PUPD_5_Msk ( 0x3UL << GPIO_PUPD_PUPD_5_Pos ) +#define GPIO_PUPD_PUPD_5 ( GPIO_PUPD_PUPD_5_Msk ) +#define GPIO_PUPD_PUPD_5_0 ( 0x1UL << GPIO_PUPD_PUPD_5_Pos ) +#define GPIO_PUPD_PUPD_5_1 ( 0x2UL << GPIO_PUPD_PUPD_5_Pos ) + +#define GPIO_PUPD_PUPD_4_Pos ( 8U ) +#define GPIO_PUPD_PUPD_4_Msk ( 0x3UL << GPIO_PUPD_PUPD_4_Pos ) +#define GPIO_PUPD_PUPD_4 ( GPIO_PUPD_PUPD_4_Msk ) +#define GPIO_PUPD_PUPD_4_0 ( 0x1UL << GPIO_PUPD_PUPD_4_Pos ) +#define GPIO_PUPD_PUPD_4_1 ( 0x2UL << GPIO_PUPD_PUPD_4_Pos ) + +#define GPIO_PUPD_PUPD_3_Pos ( 6U ) +#define GPIO_PUPD_PUPD_3_Msk ( 0x3UL << GPIO_PUPD_PUPD_3_Pos ) +#define GPIO_PUPD_PUPD_3 ( GPIO_PUPD_PUPD_3_Msk ) +#define GPIO_PUPD_PUPD_3_0 ( 0x1UL << GPIO_PUPD_PUPD_3_Pos ) +#define GPIO_PUPD_PUPD_3_1 ( 0x2UL << GPIO_PUPD_PUPD_3_Pos ) + +#define GPIO_PUPD_PUPD_2_Pos ( 4U ) +#define GPIO_PUPD_PUPD_2_Msk ( 0x3UL << GPIO_PUPD_PUPD_2_Pos ) +#define GPIO_PUPD_PUPD_2 ( GPIO_PUPD_PUPD_2_Msk ) +#define GPIO_PUPD_PUPD_2_0 ( 0x1UL << GPIO_PUPD_PUPD_2_Pos ) +#define GPIO_PUPD_PUPD_2_1 ( 0x2UL << GPIO_PUPD_PUPD_2_Pos ) + +#define GPIO_PUPD_PUPD_1_Pos ( 2U ) +#define GPIO_PUPD_PUPD_1_Msk ( 0x3UL << GPIO_PUPD_PUPD_1_Pos ) +#define GPIO_PUPD_PUPD_1 ( GPIO_PUPD_PUPD_1_Msk ) +#define GPIO_PUPD_PUPD_1_0 ( 0x1UL << GPIO_PUPD_PUPD_1_Pos ) +#define GPIO_PUPD_PUPD_1_1 ( 0x2UL << GPIO_PUPD_PUPD_1_Pos ) + +#define GPIO_PUPD_PUPD_0_Pos ( 0U ) +#define GPIO_PUPD_PUPD_0_Msk ( 0x3UL << GPIO_PUPD_PUPD_0_Pos ) +#define GPIO_PUPD_PUPD_0 ( GPIO_PUPD_PUPD_0_Msk ) +#define GPIO_PUPD_PUPD_0_0 ( 0x1UL << GPIO_PUPD_PUPD_0_Pos ) +#define GPIO_PUPD_PUPD_0_1 ( 0x2UL << GPIO_PUPD_PUPD_0_Pos ) + + +/*************** Bits definition for GPIO_IDATA **********************/ + +#define GPIO_IDATA_GPIO_IDATA15_Pos ( 15U ) +#define GPIO_IDATA_GPIO_IDATA15_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA15_Pos ) +#define GPIO_IDATA_GPIO_IDATA15 ( GPIO_IDATA_GPIO_IDATA15_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA14_Pos ( 14U ) +#define GPIO_IDATA_GPIO_IDATA14_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA14_Pos ) +#define GPIO_IDATA_GPIO_IDATA14 ( GPIO_IDATA_GPIO_IDATA14_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA13_Pos ( 13U ) +#define GPIO_IDATA_GPIO_IDATA13_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA13_Pos ) +#define GPIO_IDATA_GPIO_IDATA13 ( GPIO_IDATA_GPIO_IDATA13_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA12_Pos ( 12U ) +#define GPIO_IDATA_GPIO_IDATA12_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA12_Pos ) +#define GPIO_IDATA_GPIO_IDATA12 ( GPIO_IDATA_GPIO_IDATA12_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA11_Pos ( 11U ) +#define GPIO_IDATA_GPIO_IDATA11_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA11_Pos ) +#define GPIO_IDATA_GPIO_IDATA11 ( GPIO_IDATA_GPIO_IDATA11_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA10_Pos ( 10U ) +#define GPIO_IDATA_GPIO_IDATA10_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA10_Pos ) +#define GPIO_IDATA_GPIO_IDATA10 ( GPIO_IDATA_GPIO_IDATA10_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA9_Pos ( 9U ) +#define GPIO_IDATA_GPIO_IDATA9_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA9_Pos ) +#define GPIO_IDATA_GPIO_IDATA9 ( GPIO_IDATA_GPIO_IDATA9_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA8_Pos ( 8U ) +#define GPIO_IDATA_GPIO_IDATA8_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA8_Pos ) +#define GPIO_IDATA_GPIO_IDATA8 ( GPIO_IDATA_GPIO_IDATA8_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA7_Pos ( 7U ) +#define GPIO_IDATA_GPIO_IDATA7_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA7_Pos ) +#define GPIO_IDATA_GPIO_IDATA7 ( GPIO_IDATA_GPIO_IDATA7_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA6_Pos ( 6U ) +#define GPIO_IDATA_GPIO_IDATA6_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA6_Pos ) +#define GPIO_IDATA_GPIO_IDATA6 ( GPIO_IDATA_GPIO_IDATA6_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA5_Pos ( 5U ) +#define GPIO_IDATA_GPIO_IDATA5_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA5_Pos ) +#define GPIO_IDATA_GPIO_IDATA5 ( GPIO_IDATA_GPIO_IDATA5_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA4_Pos ( 4U ) +#define GPIO_IDATA_GPIO_IDATA4_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA4_Pos ) +#define GPIO_IDATA_GPIO_IDATA4 ( GPIO_IDATA_GPIO_IDATA4_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA3_Pos ( 3U ) +#define GPIO_IDATA_GPIO_IDATA3_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA3_Pos ) +#define GPIO_IDATA_GPIO_IDATA3 ( GPIO_IDATA_GPIO_IDATA3_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA2_Pos ( 2U ) +#define GPIO_IDATA_GPIO_IDATA2_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA2_Pos ) +#define GPIO_IDATA_GPIO_IDATA2 ( GPIO_IDATA_GPIO_IDATA2_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA1_Pos ( 1U ) +#define GPIO_IDATA_GPIO_IDATA1_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA1_Pos ) +#define GPIO_IDATA_GPIO_IDATA1 ( GPIO_IDATA_GPIO_IDATA1_Msk ) + + +#define GPIO_IDATA_GPIO_IDATA0_Pos ( 0U ) +#define GPIO_IDATA_GPIO_IDATA0_Msk ( 0x1UL << GPIO_IDATA_GPIO_IDATA0_Pos ) +#define GPIO_IDATA_GPIO_IDATA0 ( GPIO_IDATA_GPIO_IDATA0_Msk ) + + + +/*************** Bits definition for GPIO_ODATA **********************/ + +#define GPIO_ODATA_GPIO_ODATA15_Pos ( 15U ) +#define GPIO_ODATA_GPIO_ODATA15_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA15_Pos ) +#define GPIO_ODATA_GPIO_ODATA15 ( GPIO_ODATA_GPIO_ODATA15_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA14_Pos ( 14U ) +#define GPIO_ODATA_GPIO_ODATA14_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA14_Pos ) +#define GPIO_ODATA_GPIO_ODATA14 ( GPIO_ODATA_GPIO_ODATA14_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA13_Pos ( 13U ) +#define GPIO_ODATA_GPIO_ODATA13_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA13_Pos ) +#define GPIO_ODATA_GPIO_ODATA13 ( GPIO_ODATA_GPIO_ODATA13_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA12_Pos ( 12U ) +#define GPIO_ODATA_GPIO_ODATA12_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA12_Pos ) +#define GPIO_ODATA_GPIO_ODATA12 ( GPIO_ODATA_GPIO_ODATA12_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA11_Pos ( 11U ) +#define GPIO_ODATA_GPIO_ODATA11_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA11_Pos ) +#define GPIO_ODATA_GPIO_ODATA11 ( GPIO_ODATA_GPIO_ODATA11_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA10_Pos ( 10U ) +#define GPIO_ODATA_GPIO_ODATA10_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA10_Pos ) +#define GPIO_ODATA_GPIO_ODATA10 ( GPIO_ODATA_GPIO_ODATA10_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA9_Pos ( 9U ) +#define GPIO_ODATA_GPIO_ODATA9_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA9_Pos ) +#define GPIO_ODATA_GPIO_ODATA9 ( GPIO_ODATA_GPIO_ODATA9_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA8_Pos ( 8U ) +#define GPIO_ODATA_GPIO_ODATA8_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA8_Pos ) +#define GPIO_ODATA_GPIO_ODATA8 ( GPIO_ODATA_GPIO_ODATA8_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA7_Pos ( 7U ) +#define GPIO_ODATA_GPIO_ODATA7_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA7_Pos ) +#define GPIO_ODATA_GPIO_ODATA7 ( GPIO_ODATA_GPIO_ODATA7_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA6_Pos ( 6U ) +#define GPIO_ODATA_GPIO_ODATA6_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA6_Pos ) +#define GPIO_ODATA_GPIO_ODATA6 ( GPIO_ODATA_GPIO_ODATA6_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA5_Pos ( 5U ) +#define GPIO_ODATA_GPIO_ODATA5_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA5_Pos ) +#define GPIO_ODATA_GPIO_ODATA5 ( GPIO_ODATA_GPIO_ODATA5_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA4_Pos ( 4U ) +#define GPIO_ODATA_GPIO_ODATA4_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA4_Pos ) +#define GPIO_ODATA_GPIO_ODATA4 ( GPIO_ODATA_GPIO_ODATA4_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA3_Pos ( 3U ) +#define GPIO_ODATA_GPIO_ODATA3_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA3_Pos ) +#define GPIO_ODATA_GPIO_ODATA3 ( GPIO_ODATA_GPIO_ODATA3_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA2_Pos ( 2U ) +#define GPIO_ODATA_GPIO_ODATA2_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA2_Pos ) +#define GPIO_ODATA_GPIO_ODATA2 ( GPIO_ODATA_GPIO_ODATA2_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA1_Pos ( 1U ) +#define GPIO_ODATA_GPIO_ODATA1_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA1_Pos ) +#define GPIO_ODATA_GPIO_ODATA1 ( GPIO_ODATA_GPIO_ODATA1_Msk ) + + +#define GPIO_ODATA_GPIO_ODATA0_Pos ( 0U ) +#define GPIO_ODATA_GPIO_ODATA0_Msk ( 0x1UL << GPIO_ODATA_GPIO_ODATA0_Pos ) +#define GPIO_ODATA_GPIO_ODATA0 ( GPIO_ODATA_GPIO_ODATA0_Msk ) + + + +/*************** Bits definition for GPIO_BSC **********************/ + +#define GPIO_BSC_GPIO_CLR15_Pos ( 31U ) +#define GPIO_BSC_GPIO_CLR15_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR15_Pos ) +#define GPIO_BSC_GPIO_CLR15 ( GPIO_BSC_GPIO_CLR15_Msk ) + + +#define GPIO_BSC_GPIO_CLR14_Pos ( 30U ) +#define GPIO_BSC_GPIO_CLR14_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR14_Pos ) +#define GPIO_BSC_GPIO_CLR14 ( GPIO_BSC_GPIO_CLR14_Msk ) + + +#define GPIO_BSC_GPIO_CLR13_Pos ( 29U ) +#define GPIO_BSC_GPIO_CLR13_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR13_Pos ) +#define GPIO_BSC_GPIO_CLR13 ( GPIO_BSC_GPIO_CLR13_Msk ) + + +#define GPIO_BSC_GPIO_CLR12_Pos ( 28U ) +#define GPIO_BSC_GPIO_CLR12_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR12_Pos ) +#define GPIO_BSC_GPIO_CLR12 ( GPIO_BSC_GPIO_CLR12_Msk ) + + +#define GPIO_BSC_GPIO_CLR11_Pos ( 27U ) +#define GPIO_BSC_GPIO_CLR11_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR11_Pos ) +#define GPIO_BSC_GPIO_CLR11 ( GPIO_BSC_GPIO_CLR11_Msk ) + + +#define GPIO_BSC_GPIO_CLR10_Pos ( 26U ) +#define GPIO_BSC_GPIO_CLR10_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR10_Pos ) +#define GPIO_BSC_GPIO_CLR10 ( GPIO_BSC_GPIO_CLR10_Msk ) + + +#define GPIO_BSC_GPIO_CLR9_Pos ( 25U ) +#define GPIO_BSC_GPIO_CLR9_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR9_Pos ) +#define GPIO_BSC_GPIO_CLR9 ( GPIO_BSC_GPIO_CLR9_Msk ) + + +#define GPIO_BSC_GPIO_CLR8_Pos ( 24U ) +#define GPIO_BSC_GPIO_CLR8_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR8_Pos ) +#define GPIO_BSC_GPIO_CLR8 ( GPIO_BSC_GPIO_CLR8_Msk ) + + +#define GPIO_BSC_GPIO_CLR7_Pos ( 23U ) +#define GPIO_BSC_GPIO_CLR7_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR7_Pos ) +#define GPIO_BSC_GPIO_CLR7 ( GPIO_BSC_GPIO_CLR7_Msk ) + + +#define GPIO_BSC_GPIO_CLR6_Pos ( 22U ) +#define GPIO_BSC_GPIO_CLR6_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR6_Pos ) +#define GPIO_BSC_GPIO_CLR6 ( GPIO_BSC_GPIO_CLR6_Msk ) + + +#define GPIO_BSC_GPIO_CLR5_Pos ( 21U ) +#define GPIO_BSC_GPIO_CLR5_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR5_Pos ) +#define GPIO_BSC_GPIO_CLR5 ( GPIO_BSC_GPIO_CLR5_Msk ) + + +#define GPIO_BSC_GPIO_CLR4_Pos ( 20U ) +#define GPIO_BSC_GPIO_CLR4_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR4_Pos ) +#define GPIO_BSC_GPIO_CLR4 ( GPIO_BSC_GPIO_CLR4_Msk ) + + +#define GPIO_BSC_GPIO_CLR3_Pos ( 19U ) +#define GPIO_BSC_GPIO_CLR3_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR3_Pos ) +#define GPIO_BSC_GPIO_CLR3 ( GPIO_BSC_GPIO_CLR3_Msk ) + + +#define GPIO_BSC_GPIO_CLR2_Pos ( 18U ) +#define GPIO_BSC_GPIO_CLR2_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR2_Pos ) +#define GPIO_BSC_GPIO_CLR2 ( GPIO_BSC_GPIO_CLR2_Msk ) + + +#define GPIO_BSC_GPIO_CLR1_Pos ( 17U ) +#define GPIO_BSC_GPIO_CLR1_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR1_Pos ) +#define GPIO_BSC_GPIO_CLR1 ( GPIO_BSC_GPIO_CLR1_Msk ) + + +#define GPIO_BSC_GPIO_CLR0_Pos ( 16U ) +#define GPIO_BSC_GPIO_CLR0_Msk ( 0x1UL << GPIO_BSC_GPIO_CLR0_Pos ) +#define GPIO_BSC_GPIO_CLR0 ( GPIO_BSC_GPIO_CLR0_Msk ) + + +#define GPIO_BSC_GPIO_SET15_Pos ( 15U ) +#define GPIO_BSC_GPIO_SET15_Msk ( 0x1UL << GPIO_BSC_GPIO_SET15_Pos ) +#define GPIO_BSC_GPIO_SET15 ( GPIO_BSC_GPIO_SET15_Msk ) + + +#define GPIO_BSC_GPIO_SET14_Pos ( 14U ) +#define GPIO_BSC_GPIO_SET14_Msk ( 0x1UL << GPIO_BSC_GPIO_SET14_Pos ) +#define GPIO_BSC_GPIO_SET14 ( GPIO_BSC_GPIO_SET14_Msk ) + + +#define GPIO_BSC_GPIO_SET13_Pos ( 13U ) +#define GPIO_BSC_GPIO_SET13_Msk ( 0x1UL << GPIO_BSC_GPIO_SET13_Pos ) +#define GPIO_BSC_GPIO_SET13 ( GPIO_BSC_GPIO_SET13_Msk ) + + +#define GPIO_BSC_GPIO_SET12_Pos ( 12U ) +#define GPIO_BSC_GPIO_SET12_Msk ( 0x1UL << GPIO_BSC_GPIO_SET12_Pos ) +#define GPIO_BSC_GPIO_SET12 ( GPIO_BSC_GPIO_SET12_Msk ) + + +#define GPIO_BSC_GPIO_SET11_Pos ( 11U ) +#define GPIO_BSC_GPIO_SET11_Msk ( 0x1UL << GPIO_BSC_GPIO_SET11_Pos ) +#define GPIO_BSC_GPIO_SET11 ( GPIO_BSC_GPIO_SET11_Msk ) + + +#define GPIO_BSC_GPIO_SET10_Pos ( 10U ) +#define GPIO_BSC_GPIO_SET10_Msk ( 0x1UL << GPIO_BSC_GPIO_SET10_Pos ) +#define GPIO_BSC_GPIO_SET10 ( GPIO_BSC_GPIO_SET10_Msk ) + + +#define GPIO_BSC_GPIO_SET9_Pos ( 9U ) +#define GPIO_BSC_GPIO_SET9_Msk ( 0x1UL << GPIO_BSC_GPIO_SET9_Pos ) +#define GPIO_BSC_GPIO_SET9 ( GPIO_BSC_GPIO_SET9_Msk ) + + +#define GPIO_BSC_GPIO_SET8_Pos ( 8U ) +#define GPIO_BSC_GPIO_SET8_Msk ( 0x1UL << GPIO_BSC_GPIO_SET8_Pos ) +#define GPIO_BSC_GPIO_SET8 ( GPIO_BSC_GPIO_SET8_Msk ) + + +#define GPIO_BSC_GPIO_SET7_Pos ( 7U ) +#define GPIO_BSC_GPIO_SET7_Msk ( 0x1UL << GPIO_BSC_GPIO_SET7_Pos ) +#define GPIO_BSC_GPIO_SET7 ( GPIO_BSC_GPIO_SET7_Msk ) + + +#define GPIO_BSC_GPIO_SET6_Pos ( 6U ) +#define GPIO_BSC_GPIO_SET6_Msk ( 0x1UL << GPIO_BSC_GPIO_SET6_Pos ) +#define GPIO_BSC_GPIO_SET6 ( GPIO_BSC_GPIO_SET6_Msk ) + + +#define GPIO_BSC_GPIO_SET5_Pos ( 5U ) +#define GPIO_BSC_GPIO_SET5_Msk ( 0x1UL << GPIO_BSC_GPIO_SET5_Pos ) +#define GPIO_BSC_GPIO_SET5 ( GPIO_BSC_GPIO_SET5_Msk ) + + +#define GPIO_BSC_GPIO_SET4_Pos ( 4U ) +#define GPIO_BSC_GPIO_SET4_Msk ( 0x1UL << GPIO_BSC_GPIO_SET4_Pos ) +#define GPIO_BSC_GPIO_SET4 ( GPIO_BSC_GPIO_SET4_Msk ) + + +#define GPIO_BSC_GPIO_SET3_Pos ( 3U ) +#define GPIO_BSC_GPIO_SET3_Msk ( 0x1UL << GPIO_BSC_GPIO_SET3_Pos ) +#define GPIO_BSC_GPIO_SET3 ( GPIO_BSC_GPIO_SET3_Msk ) + + +#define GPIO_BSC_GPIO_SET2_Pos ( 2U ) +#define GPIO_BSC_GPIO_SET2_Msk ( 0x1UL << GPIO_BSC_GPIO_SET2_Pos ) +#define GPIO_BSC_GPIO_SET2 ( GPIO_BSC_GPIO_SET2_Msk ) + + +#define GPIO_BSC_GPIO_SET1_Pos ( 1U ) +#define GPIO_BSC_GPIO_SET1_Msk ( 0x1UL << GPIO_BSC_GPIO_SET1_Pos ) +#define GPIO_BSC_GPIO_SET1 ( GPIO_BSC_GPIO_SET1_Msk ) + + +#define GPIO_BSC_GPIO_SET0_Pos ( 0U ) +#define GPIO_BSC_GPIO_SET0_Msk ( 0x1UL << GPIO_BSC_GPIO_SET0_Pos ) +#define GPIO_BSC_GPIO_SET0 ( GPIO_BSC_GPIO_SET0_Msk ) + + + +/*************** Bits definition for GPIO_AF0 **********************/ + +#define GPIO_AF0_GPIO_AFSEL0_7_Pos ( 28U ) +#define GPIO_AF0_GPIO_AFSEL0_7_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_7_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_7 ( GPIO_AF0_GPIO_AFSEL0_7_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_7_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_7_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_7_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_7_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_7_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_7_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_7_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_7_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_6_Pos ( 24U ) +#define GPIO_AF0_GPIO_AFSEL0_6_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_6_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_6 ( GPIO_AF0_GPIO_AFSEL0_6_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_6_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_6_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_6_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_6_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_6_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_6_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_6_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_6_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_5_Pos ( 20U ) +#define GPIO_AF0_GPIO_AFSEL0_5_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_5_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_5 ( GPIO_AF0_GPIO_AFSEL0_5_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_5_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_5_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_5_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_5_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_5_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_5_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_5_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_5_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_4_Pos ( 16U ) +#define GPIO_AF0_GPIO_AFSEL0_4_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_4_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_4 ( GPIO_AF0_GPIO_AFSEL0_4_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_4_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_4_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_4_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_4_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_4_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_4_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_4_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_4_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_3_Pos ( 12U ) +#define GPIO_AF0_GPIO_AFSEL0_3_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_3_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_3 ( GPIO_AF0_GPIO_AFSEL0_3_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_3_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_3_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_3_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_3_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_3_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_3_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_3_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_3_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_2_Pos ( 8U ) +#define GPIO_AF0_GPIO_AFSEL0_2_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_2_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_2 ( GPIO_AF0_GPIO_AFSEL0_2_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_2_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_2_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_2_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_2_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_2_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_2_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_2_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_2_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_1_Pos ( 4U ) +#define GPIO_AF0_GPIO_AFSEL0_1_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_1_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_1 ( GPIO_AF0_GPIO_AFSEL0_1_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_1_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_1_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_1_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_1_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_1_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_1_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_1_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_1_Pos ) + +#define GPIO_AF0_GPIO_AFSEL0_0_Pos ( 0U ) +#define GPIO_AF0_GPIO_AFSEL0_0_Msk ( 0xfUL << GPIO_AF0_GPIO_AFSEL0_0_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_0 ( GPIO_AF0_GPIO_AFSEL0_0_Msk ) +#define GPIO_AF0_GPIO_AFSEL0_0_0 ( 0x1UL << GPIO_AF0_GPIO_AFSEL0_0_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_0_1 ( 0x2UL << GPIO_AF0_GPIO_AFSEL0_0_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_0_2 ( 0x4UL << GPIO_AF0_GPIO_AFSEL0_0_Pos ) +#define GPIO_AF0_GPIO_AFSEL0_0_3 ( 0x8UL << GPIO_AF0_GPIO_AFSEL0_0_Pos ) + + +/*************** Bits definition for GPIO_AF1 **********************/ + +#define GPIO_AF1_GPIO_AFSEL1_15_Pos ( 28U ) +#define GPIO_AF1_GPIO_AFSEL1_15_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_15_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_15 ( GPIO_AF1_GPIO_AFSEL1_15_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_15_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_15_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_15_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_15_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_15_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_15_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_15_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_15_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_14_Pos ( 24U ) +#define GPIO_AF1_GPIO_AFSEL1_14_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_14_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_14 ( GPIO_AF1_GPIO_AFSEL1_14_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_14_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_14_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_14_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_14_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_14_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_14_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_14_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_14_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_13_Pos ( 20U ) +#define GPIO_AF1_GPIO_AFSEL1_13_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_13_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_13 ( GPIO_AF1_GPIO_AFSEL1_13_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_13_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_13_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_13_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_13_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_13_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_13_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_13_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_13_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_12_Pos ( 16U ) +#define GPIO_AF1_GPIO_AFSEL1_12_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_12_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_12 ( GPIO_AF1_GPIO_AFSEL1_12_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_12_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_12_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_12_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_12_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_12_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_12_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_12_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_12_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_11_Pos ( 12U ) +#define GPIO_AF1_GPIO_AFSEL1_11_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_11_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_11 ( GPIO_AF1_GPIO_AFSEL1_11_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_11_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_11_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_11_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_11_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_11_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_11_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_11_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_11_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_10_Pos ( 8U ) +#define GPIO_AF1_GPIO_AFSEL1_10_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_10_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_10 ( GPIO_AF1_GPIO_AFSEL1_10_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_10_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_10_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_10_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_10_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_10_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_10_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_10_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_10_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_9_Pos ( 4U ) +#define GPIO_AF1_GPIO_AFSEL1_9_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_9_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_9 ( GPIO_AF1_GPIO_AFSEL1_9_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_9_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_9_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_9_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_9_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_9_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_9_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_9_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_9_Pos ) + +#define GPIO_AF1_GPIO_AFSEL1_8_Pos ( 0U ) +#define GPIO_AF1_GPIO_AFSEL1_8_Msk ( 0xfUL << GPIO_AF1_GPIO_AFSEL1_8_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_8 ( GPIO_AF1_GPIO_AFSEL1_8_Msk ) +#define GPIO_AF1_GPIO_AFSEL1_8_0 ( 0x1UL << GPIO_AF1_GPIO_AFSEL1_8_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_8_1 ( 0x2UL << GPIO_AF1_GPIO_AFSEL1_8_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_8_2 ( 0x4UL << GPIO_AF1_GPIO_AFSEL1_8_Pos ) +#define GPIO_AF1_GPIO_AFSEL1_8_3 ( 0x8UL << GPIO_AF1_GPIO_AFSEL1_8_Pos ) + + +/*************** Bits definition for GPIO_DS0 **********************/ + +#define GPIO_DS0_GPIO_DS0_7_Pos ( 28U ) +#define GPIO_DS0_GPIO_DS0_7_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_7_Pos ) +#define GPIO_DS0_GPIO_DS0_7 ( GPIO_DS0_GPIO_DS0_7_Msk ) +#define GPIO_DS0_GPIO_DS0_7_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_7_Pos ) +#define GPIO_DS0_GPIO_DS0_7_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_7_Pos ) +#define GPIO_DS0_GPIO_DS0_7_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_7_Pos ) +#define GPIO_DS0_GPIO_DS0_7_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_7_Pos ) + +#define GPIO_DS0_GPIO_DS0_6_Pos ( 24U ) +#define GPIO_DS0_GPIO_DS0_6_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_6_Pos ) +#define GPIO_DS0_GPIO_DS0_6 ( GPIO_DS0_GPIO_DS0_6_Msk ) +#define GPIO_DS0_GPIO_DS0_6_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_6_Pos ) +#define GPIO_DS0_GPIO_DS0_6_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_6_Pos ) +#define GPIO_DS0_GPIO_DS0_6_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_6_Pos ) +#define GPIO_DS0_GPIO_DS0_6_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_6_Pos ) + +#define GPIO_DS0_GPIO_DS0_5_Pos ( 20U ) +#define GPIO_DS0_GPIO_DS0_5_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_5_Pos ) +#define GPIO_DS0_GPIO_DS0_5 ( GPIO_DS0_GPIO_DS0_5_Msk ) +#define GPIO_DS0_GPIO_DS0_5_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_5_Pos ) +#define GPIO_DS0_GPIO_DS0_5_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_5_Pos ) +#define GPIO_DS0_GPIO_DS0_5_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_5_Pos ) +#define GPIO_DS0_GPIO_DS0_5_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_5_Pos ) + +#define GPIO_DS0_GPIO_DS0_4_Pos ( 16U ) +#define GPIO_DS0_GPIO_DS0_4_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_4_Pos ) +#define GPIO_DS0_GPIO_DS0_4 ( GPIO_DS0_GPIO_DS0_4_Msk ) +#define GPIO_DS0_GPIO_DS0_4_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_4_Pos ) +#define GPIO_DS0_GPIO_DS0_4_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_4_Pos ) +#define GPIO_DS0_GPIO_DS0_4_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_4_Pos ) +#define GPIO_DS0_GPIO_DS0_4_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_4_Pos ) + +#define GPIO_DS0_GPIO_DS0_3_Pos ( 12U ) +#define GPIO_DS0_GPIO_DS0_3_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_3_Pos ) +#define GPIO_DS0_GPIO_DS0_3 ( GPIO_DS0_GPIO_DS0_3_Msk ) +#define GPIO_DS0_GPIO_DS0_3_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_3_Pos ) +#define GPIO_DS0_GPIO_DS0_3_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_3_Pos ) +#define GPIO_DS0_GPIO_DS0_3_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_3_Pos ) +#define GPIO_DS0_GPIO_DS0_3_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_3_Pos ) + +#define GPIO_DS0_GPIO_DS0_2_Pos ( 8U ) +#define GPIO_DS0_GPIO_DS0_2_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_2_Pos ) +#define GPIO_DS0_GPIO_DS0_2 ( GPIO_DS0_GPIO_DS0_2_Msk ) +#define GPIO_DS0_GPIO_DS0_2_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_2_Pos ) +#define GPIO_DS0_GPIO_DS0_2_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_2_Pos ) +#define GPIO_DS0_GPIO_DS0_2_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_2_Pos ) +#define GPIO_DS0_GPIO_DS0_2_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_2_Pos ) + +#define GPIO_DS0_GPIO_DS0_1_Pos ( 4U ) +#define GPIO_DS0_GPIO_DS0_1_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_1_Pos ) +#define GPIO_DS0_GPIO_DS0_1 ( GPIO_DS0_GPIO_DS0_1_Msk ) +#define GPIO_DS0_GPIO_DS0_1_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_1_Pos ) +#define GPIO_DS0_GPIO_DS0_1_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_1_Pos ) +#define GPIO_DS0_GPIO_DS0_1_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_1_Pos ) +#define GPIO_DS0_GPIO_DS0_1_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_1_Pos ) + +#define GPIO_DS0_GPIO_DS0_0_Pos ( 0U ) +#define GPIO_DS0_GPIO_DS0_0_Msk ( 0xfUL << GPIO_DS0_GPIO_DS0_0_Pos ) +#define GPIO_DS0_GPIO_DS0_0 ( GPIO_DS0_GPIO_DS0_0_Msk ) +#define GPIO_DS0_GPIO_DS0_0_0 ( 0x1UL << GPIO_DS0_GPIO_DS0_0_Pos ) +#define GPIO_DS0_GPIO_DS0_0_1 ( 0x2UL << GPIO_DS0_GPIO_DS0_0_Pos ) +#define GPIO_DS0_GPIO_DS0_0_2 ( 0x4UL << GPIO_DS0_GPIO_DS0_0_Pos ) +#define GPIO_DS0_GPIO_DS0_0_3 ( 0x8UL << GPIO_DS0_GPIO_DS0_0_Pos ) + + +/*************** Bits definition for GPIO_DS1 **********************/ + +#define GPIO_DS1_GPIO_DS1_15_Pos ( 28U ) +#define GPIO_DS1_GPIO_DS1_15_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_15_Pos ) +#define GPIO_DS1_GPIO_DS1_15 ( GPIO_DS1_GPIO_DS1_15_Msk ) +#define GPIO_DS1_GPIO_DS1_15_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_15_Pos ) +#define GPIO_DS1_GPIO_DS1_15_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_15_Pos ) +#define GPIO_DS1_GPIO_DS1_15_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_15_Pos ) +#define GPIO_DS1_GPIO_DS1_15_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_15_Pos ) + +#define GPIO_DS1_GPIO_DS1_14_Pos ( 24U ) +#define GPIO_DS1_GPIO_DS1_14_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_14_Pos ) +#define GPIO_DS1_GPIO_DS1_14 ( GPIO_DS1_GPIO_DS1_14_Msk ) +#define GPIO_DS1_GPIO_DS1_14_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_14_Pos ) +#define GPIO_DS1_GPIO_DS1_14_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_14_Pos ) +#define GPIO_DS1_GPIO_DS1_14_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_14_Pos ) +#define GPIO_DS1_GPIO_DS1_14_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_14_Pos ) + +#define GPIO_DS1_GPIO_DS1_13_Pos ( 20U ) +#define GPIO_DS1_GPIO_DS1_13_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_13_Pos ) +#define GPIO_DS1_GPIO_DS1_13 ( GPIO_DS1_GPIO_DS1_13_Msk ) +#define GPIO_DS1_GPIO_DS1_13_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_13_Pos ) +#define GPIO_DS1_GPIO_DS1_13_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_13_Pos ) +#define GPIO_DS1_GPIO_DS1_13_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_13_Pos ) +#define GPIO_DS1_GPIO_DS1_13_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_13_Pos ) + +#define GPIO_DS1_GPIO_DS1_12_Pos ( 16U ) +#define GPIO_DS1_GPIO_DS1_12_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_12_Pos ) +#define GPIO_DS1_GPIO_DS1_12 ( GPIO_DS1_GPIO_DS1_12_Msk ) +#define GPIO_DS1_GPIO_DS1_12_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_12_Pos ) +#define GPIO_DS1_GPIO_DS1_12_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_12_Pos ) +#define GPIO_DS1_GPIO_DS1_12_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_12_Pos ) +#define GPIO_DS1_GPIO_DS1_12_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_12_Pos ) + +#define GPIO_DS1_GPIO_DS1_11_Pos ( 12U ) +#define GPIO_DS1_GPIO_DS1_11_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_11_Pos ) +#define GPIO_DS1_GPIO_DS1_11 ( GPIO_DS1_GPIO_DS1_11_Msk ) +#define GPIO_DS1_GPIO_DS1_11_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_11_Pos ) +#define GPIO_DS1_GPIO_DS1_11_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_11_Pos ) +#define GPIO_DS1_GPIO_DS1_11_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_11_Pos ) +#define GPIO_DS1_GPIO_DS1_11_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_11_Pos ) + +#define GPIO_DS1_GPIO_DS1_10_Pos ( 8U ) +#define GPIO_DS1_GPIO_DS1_10_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_10_Pos ) +#define GPIO_DS1_GPIO_DS1_10 ( GPIO_DS1_GPIO_DS1_10_Msk ) +#define GPIO_DS1_GPIO_DS1_10_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_10_Pos ) +#define GPIO_DS1_GPIO_DS1_10_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_10_Pos ) +#define GPIO_DS1_GPIO_DS1_10_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_10_Pos ) +#define GPIO_DS1_GPIO_DS1_10_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_10_Pos ) + +#define GPIO_DS1_GPIO_DS1_9_Pos ( 4U ) +#define GPIO_DS1_GPIO_DS1_9_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_9_Pos ) +#define GPIO_DS1_GPIO_DS1_9 ( GPIO_DS1_GPIO_DS1_9_Msk ) +#define GPIO_DS1_GPIO_DS1_9_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_9_Pos ) +#define GPIO_DS1_GPIO_DS1_9_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_9_Pos ) +#define GPIO_DS1_GPIO_DS1_9_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_9_Pos ) +#define GPIO_DS1_GPIO_DS1_9_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_9_Pos ) + +#define GPIO_DS1_GPIO_DS1_8_Pos ( 0U ) +#define GPIO_DS1_GPIO_DS1_8_Msk ( 0xfUL << GPIO_DS1_GPIO_DS1_8_Pos ) +#define GPIO_DS1_GPIO_DS1_8 ( GPIO_DS1_GPIO_DS1_8_Msk ) +#define GPIO_DS1_GPIO_DS1_8_0 ( 0x1UL << GPIO_DS1_GPIO_DS1_8_Pos ) +#define GPIO_DS1_GPIO_DS1_8_1 ( 0x2UL << GPIO_DS1_GPIO_DS1_8_Pos ) +#define GPIO_DS1_GPIO_DS1_8_2 ( 0x4UL << GPIO_DS1_GPIO_DS1_8_Pos ) +#define GPIO_DS1_GPIO_DS1_8_3 ( 0x8UL << GPIO_DS1_GPIO_DS1_8_Pos ) + + +/*************** Bits definition for GPIO_SMIT **********************/ + +#define GPIO_SMIT_GPIO_SMTEN15_Pos ( 15U ) +#define GPIO_SMIT_GPIO_SMTEN15_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN15_Pos ) +#define GPIO_SMIT_GPIO_SMTEN15 ( GPIO_SMIT_GPIO_SMTEN15_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN14_Pos ( 14U ) +#define GPIO_SMIT_GPIO_SMTEN14_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN14_Pos ) +#define GPIO_SMIT_GPIO_SMTEN14 ( GPIO_SMIT_GPIO_SMTEN14_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN13_Pos ( 13U ) +#define GPIO_SMIT_GPIO_SMTEN13_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN13_Pos ) +#define GPIO_SMIT_GPIO_SMTEN13 ( GPIO_SMIT_GPIO_SMTEN13_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN12_Pos ( 12U ) +#define GPIO_SMIT_GPIO_SMTEN12_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN12_Pos ) +#define GPIO_SMIT_GPIO_SMTEN12 ( GPIO_SMIT_GPIO_SMTEN12_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN11_Pos ( 11U ) +#define GPIO_SMIT_GPIO_SMTEN11_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN11_Pos ) +#define GPIO_SMIT_GPIO_SMTEN11 ( GPIO_SMIT_GPIO_SMTEN11_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN10_Pos ( 10U ) +#define GPIO_SMIT_GPIO_SMTEN10_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN10_Pos ) +#define GPIO_SMIT_GPIO_SMTEN10 ( GPIO_SMIT_GPIO_SMTEN10_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN9_Pos ( 9U ) +#define GPIO_SMIT_GPIO_SMTEN9_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN9_Pos ) +#define GPIO_SMIT_GPIO_SMTEN9 ( GPIO_SMIT_GPIO_SMTEN9_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN8_Pos ( 8U ) +#define GPIO_SMIT_GPIO_SMTEN8_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN8_Pos ) +#define GPIO_SMIT_GPIO_SMTEN8 ( GPIO_SMIT_GPIO_SMTEN8_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN7_Pos ( 7U ) +#define GPIO_SMIT_GPIO_SMTEN7_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN7_Pos ) +#define GPIO_SMIT_GPIO_SMTEN7 ( GPIO_SMIT_GPIO_SMTEN7_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN6_Pos ( 6U ) +#define GPIO_SMIT_GPIO_SMTEN6_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN6_Pos ) +#define GPIO_SMIT_GPIO_SMTEN6 ( GPIO_SMIT_GPIO_SMTEN6_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN5_Pos ( 5U ) +#define GPIO_SMIT_GPIO_SMTEN5_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN5_Pos ) +#define GPIO_SMIT_GPIO_SMTEN5 ( GPIO_SMIT_GPIO_SMTEN5_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN4_Pos ( 4U ) +#define GPIO_SMIT_GPIO_SMTEN4_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN4_Pos ) +#define GPIO_SMIT_GPIO_SMTEN4 ( GPIO_SMIT_GPIO_SMTEN4_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN3_Pos ( 3U ) +#define GPIO_SMIT_GPIO_SMTEN3_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN3_Pos ) +#define GPIO_SMIT_GPIO_SMTEN3 ( GPIO_SMIT_GPIO_SMTEN3_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN2_Pos ( 2U ) +#define GPIO_SMIT_GPIO_SMTEN2_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN2_Pos ) +#define GPIO_SMIT_GPIO_SMTEN2 ( GPIO_SMIT_GPIO_SMTEN2_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN1_Pos ( 1U ) +#define GPIO_SMIT_GPIO_SMTEN1_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN1_Pos ) +#define GPIO_SMIT_GPIO_SMTEN1 ( GPIO_SMIT_GPIO_SMTEN1_Msk ) + + +#define GPIO_SMIT_GPIO_SMTEN0_Pos ( 0U ) +#define GPIO_SMIT_GPIO_SMTEN0_Msk ( 0x1UL << GPIO_SMIT_GPIO_SMTEN0_Pos ) +#define GPIO_SMIT_GPIO_SMTEN0 ( GPIO_SMIT_GPIO_SMTEN0_Msk ) + + + +/*************** Bits definition for GPIO_LOCK **********************/ + +#define GPIO_LOCK_LOCK_KEY_Pos ( 16U ) +#define GPIO_LOCK_LOCK_KEY_Msk ( 0x1UL << GPIO_LOCK_LOCK_KEY_Pos ) +#define GPIO_LOCK_LOCK_KEY ( GPIO_LOCK_LOCK_KEY_Msk ) + +#define GPIO_LOCK_LOCK_EN15_Pos ( 15U ) +#define GPIO_LOCK_LOCK_EN15_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN15_Pos ) +#define GPIO_LOCK_LOCK_EN15 ( GPIO_LOCK_LOCK_EN15_Msk ) + + +#define GPIO_LOCK_LOCK_EN14_Pos ( 14U ) +#define GPIO_LOCK_LOCK_EN14_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN14_Pos ) +#define GPIO_LOCK_LOCK_EN14 ( GPIO_LOCK_LOCK_EN14_Msk ) + + +#define GPIO_LOCK_LOCK_EN13_Pos ( 13U ) +#define GPIO_LOCK_LOCK_EN13_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN13_Pos ) +#define GPIO_LOCK_LOCK_EN13 ( GPIO_LOCK_LOCK_EN13_Msk ) + + +#define GPIO_LOCK_LOCK_EN12_Pos ( 12U ) +#define GPIO_LOCK_LOCK_EN12_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN12_Pos ) +#define GPIO_LOCK_LOCK_EN12 ( GPIO_LOCK_LOCK_EN12_Msk ) + + +#define GPIO_LOCK_LOCK_EN11_Pos ( 11U ) +#define GPIO_LOCK_LOCK_EN11_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN11_Pos ) +#define GPIO_LOCK_LOCK_EN11 ( GPIO_LOCK_LOCK_EN11_Msk ) + + +#define GPIO_LOCK_LOCK_EN10_Pos ( 10U ) +#define GPIO_LOCK_LOCK_EN10_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN10_Pos ) +#define GPIO_LOCK_LOCK_EN10 ( GPIO_LOCK_LOCK_EN10_Msk ) + + +#define GPIO_LOCK_LOCK_EN9_Pos ( 9U ) +#define GPIO_LOCK_LOCK_EN9_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN9_Pos ) +#define GPIO_LOCK_LOCK_EN9 ( GPIO_LOCK_LOCK_EN9_Msk ) + + +#define GPIO_LOCK_LOCK_EN8_Pos ( 8U ) +#define GPIO_LOCK_LOCK_EN8_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN8_Pos ) +#define GPIO_LOCK_LOCK_EN8 ( GPIO_LOCK_LOCK_EN8_Msk ) + + +#define GPIO_LOCK_LOCK_EN7_Pos ( 7U ) +#define GPIO_LOCK_LOCK_EN7_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN7_Pos ) +#define GPIO_LOCK_LOCK_EN7 ( GPIO_LOCK_LOCK_EN7_Msk ) + + +#define GPIO_LOCK_LOCK_EN6_Pos ( 6U ) +#define GPIO_LOCK_LOCK_EN6_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN6_Pos ) +#define GPIO_LOCK_LOCK_EN6 ( GPIO_LOCK_LOCK_EN6_Msk ) + + +#define GPIO_LOCK_LOCK_EN5_Pos ( 5U ) +#define GPIO_LOCK_LOCK_EN5_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN5_Pos ) +#define GPIO_LOCK_LOCK_EN5 ( GPIO_LOCK_LOCK_EN5_Msk ) + + +#define GPIO_LOCK_LOCK_EN4_Pos ( 4U ) +#define GPIO_LOCK_LOCK_EN4_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN4_Pos ) +#define GPIO_LOCK_LOCK_EN4 ( GPIO_LOCK_LOCK_EN4_Msk ) + + +#define GPIO_LOCK_LOCK_EN3_Pos ( 3U ) +#define GPIO_LOCK_LOCK_EN3_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN3_Pos ) +#define GPIO_LOCK_LOCK_EN3 ( GPIO_LOCK_LOCK_EN3_Msk ) + + +#define GPIO_LOCK_LOCK_EN2_Pos ( 2U ) +#define GPIO_LOCK_LOCK_EN2_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN2_Pos ) +#define GPIO_LOCK_LOCK_EN2 ( GPIO_LOCK_LOCK_EN2_Msk ) + + +#define GPIO_LOCK_LOCK_EN1_Pos ( 1U ) +#define GPIO_LOCK_LOCK_EN1_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN1_Pos ) +#define GPIO_LOCK_LOCK_EN1 ( GPIO_LOCK_LOCK_EN1_Msk ) + + +#define GPIO_LOCK_LOCK_EN0_Pos ( 0U ) +#define GPIO_LOCK_LOCK_EN0_Msk ( 0x1UL << GPIO_LOCK_LOCK_EN0_Pos ) +#define GPIO_LOCK_LOCK_EN0 ( GPIO_LOCK_LOCK_EN0_Msk ) + + + +/*************** Bits definition for GPIO_AIEN **********************/ + +#define GPIO_AIEN_GPIO_AIEN15_Pos ( 15U ) +#define GPIO_AIEN_GPIO_AIEN15_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN15_Pos ) +#define GPIO_AIEN_GPIO_AIEN15 ( GPIO_AIEN_GPIO_AIEN15_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN14_Pos ( 14U ) +#define GPIO_AIEN_GPIO_AIEN14_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN14_Pos ) +#define GPIO_AIEN_GPIO_AIEN14 ( GPIO_AIEN_GPIO_AIEN14_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN13_Pos ( 13U ) +#define GPIO_AIEN_GPIO_AIEN13_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN13_Pos ) +#define GPIO_AIEN_GPIO_AIEN13 ( GPIO_AIEN_GPIO_AIEN13_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN12_Pos ( 12U ) +#define GPIO_AIEN_GPIO_AIEN12_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN12_Pos ) +#define GPIO_AIEN_GPIO_AIEN12 ( GPIO_AIEN_GPIO_AIEN12_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN11_Pos ( 11U ) +#define GPIO_AIEN_GPIO_AIEN11_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN11_Pos ) +#define GPIO_AIEN_GPIO_AIEN11 ( GPIO_AIEN_GPIO_AIEN11_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN10_Pos ( 10U ) +#define GPIO_AIEN_GPIO_AIEN10_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN10_Pos ) +#define GPIO_AIEN_GPIO_AIEN10 ( GPIO_AIEN_GPIO_AIEN10_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN9_Pos ( 9U ) +#define GPIO_AIEN_GPIO_AIEN9_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN9_Pos ) +#define GPIO_AIEN_GPIO_AIEN9 ( GPIO_AIEN_GPIO_AIEN9_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN8_Pos ( 8U ) +#define GPIO_AIEN_GPIO_AIEN8_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN8_Pos ) +#define GPIO_AIEN_GPIO_AIEN8 ( GPIO_AIEN_GPIO_AIEN8_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN7_Pos ( 7U ) +#define GPIO_AIEN_GPIO_AIEN7_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN7_Pos ) +#define GPIO_AIEN_GPIO_AIEN7 ( GPIO_AIEN_GPIO_AIEN7_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN6_Pos ( 6U ) +#define GPIO_AIEN_GPIO_AIEN6_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN6_Pos ) +#define GPIO_AIEN_GPIO_AIEN6 ( GPIO_AIEN_GPIO_AIEN6_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN5_Pos ( 5U ) +#define GPIO_AIEN_GPIO_AIEN5_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN5_Pos ) +#define GPIO_AIEN_GPIO_AIEN5 ( GPIO_AIEN_GPIO_AIEN5_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN4_Pos ( 4U ) +#define GPIO_AIEN_GPIO_AIEN4_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN4_Pos ) +#define GPIO_AIEN_GPIO_AIEN4 ( GPIO_AIEN_GPIO_AIEN4_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN3_Pos ( 3U ) +#define GPIO_AIEN_GPIO_AIEN3_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN3_Pos ) +#define GPIO_AIEN_GPIO_AIEN3 ( GPIO_AIEN_GPIO_AIEN3_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN2_Pos ( 2U ) +#define GPIO_AIEN_GPIO_AIEN2_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN2_Pos ) +#define GPIO_AIEN_GPIO_AIEN2 ( GPIO_AIEN_GPIO_AIEN2_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN1_Pos ( 1U ) +#define GPIO_AIEN_GPIO_AIEN1_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN1_Pos ) +#define GPIO_AIEN_GPIO_AIEN1 ( GPIO_AIEN_GPIO_AIEN1_Msk ) + + +#define GPIO_AIEN_GPIO_AIEN0_Pos ( 0U ) +#define GPIO_AIEN_GPIO_AIEN0_Msk ( 0x1UL << GPIO_AIEN_GPIO_AIEN0_Pos ) +#define GPIO_AIEN_GPIO_AIEN0 ( GPIO_AIEN_GPIO_AIEN0_Msk ) + + +/*************** Bits definition for EXTI_IENR1 **********************/ + +#define EXTI_IENR1_INTEN31_Pos ( 31U ) +#define EXTI_IENR1_INTEN31_Msk ( 0x1UL << EXTI_IENR1_INTEN31_Pos ) +#define EXTI_IENR1_INTEN31 ( EXTI_IENR1_INTEN31_Msk ) + + +#define EXTI_IENR1_INTEN30_Pos ( 30U ) +#define EXTI_IENR1_INTEN30_Msk ( 0x1UL << EXTI_IENR1_INTEN30_Pos ) +#define EXTI_IENR1_INTEN30 ( EXTI_IENR1_INTEN30_Msk ) + + +#define EXTI_IENR1_INTEN29_Pos ( 29U ) +#define EXTI_IENR1_INTEN29_Msk ( 0x1UL << EXTI_IENR1_INTEN29_Pos ) +#define EXTI_IENR1_INTEN29 ( EXTI_IENR1_INTEN29_Msk ) + + +#define EXTI_IENR1_INTEN28_Pos ( 28U ) +#define EXTI_IENR1_INTEN28_Msk ( 0x1UL << EXTI_IENR1_INTEN28_Pos ) +#define EXTI_IENR1_INTEN28 ( EXTI_IENR1_INTEN28_Msk ) + + +#define EXTI_IENR1_INTEN27_Pos ( 27U ) +#define EXTI_IENR1_INTEN27_Msk ( 0x1UL << EXTI_IENR1_INTEN27_Pos ) +#define EXTI_IENR1_INTEN27 ( EXTI_IENR1_INTEN27_Msk ) + + +#define EXTI_IENR1_INTEN26_Pos ( 26U ) +#define EXTI_IENR1_INTEN26_Msk ( 0x1UL << EXTI_IENR1_INTEN26_Pos ) +#define EXTI_IENR1_INTEN26 ( EXTI_IENR1_INTEN26_Msk ) + + +#define EXTI_IENR1_INTEN25_Pos ( 25U ) +#define EXTI_IENR1_INTEN25_Msk ( 0x1UL << EXTI_IENR1_INTEN25_Pos ) +#define EXTI_IENR1_INTEN25 ( EXTI_IENR1_INTEN25_Msk ) + + +#define EXTI_IENR1_INTEN24_Pos ( 24U ) +#define EXTI_IENR1_INTEN24_Msk ( 0x1UL << EXTI_IENR1_INTEN24_Pos ) +#define EXTI_IENR1_INTEN24 ( EXTI_IENR1_INTEN24_Msk ) + + +#define EXTI_IENR1_INTEN23_Pos ( 23U ) +#define EXTI_IENR1_INTEN23_Msk ( 0x1UL << EXTI_IENR1_INTEN23_Pos ) +#define EXTI_IENR1_INTEN23 ( EXTI_IENR1_INTEN23_Msk ) + + +#define EXTI_IENR1_INTEN22_Pos ( 22U ) +#define EXTI_IENR1_INTEN22_Msk ( 0x1UL << EXTI_IENR1_INTEN22_Pos ) +#define EXTI_IENR1_INTEN22 ( EXTI_IENR1_INTEN22_Msk ) + + +#define EXTI_IENR1_INTEN21_Pos ( 21U ) +#define EXTI_IENR1_INTEN21_Msk ( 0x1UL << EXTI_IENR1_INTEN21_Pos ) +#define EXTI_IENR1_INTEN21 ( EXTI_IENR1_INTEN21_Msk ) + + +#define EXTI_IENR1_INTEN20_Pos ( 20U ) +#define EXTI_IENR1_INTEN20_Msk ( 0x1UL << EXTI_IENR1_INTEN20_Pos ) +#define EXTI_IENR1_INTEN20 ( EXTI_IENR1_INTEN20_Msk ) + + +#define EXTI_IENR1_INTEN19_Pos ( 19U ) +#define EXTI_IENR1_INTEN19_Msk ( 0x1UL << EXTI_IENR1_INTEN19_Pos ) +#define EXTI_IENR1_INTEN19 ( EXTI_IENR1_INTEN19_Msk ) + + +#define EXTI_IENR1_INTEN18_Pos ( 18U ) +#define EXTI_IENR1_INTEN18_Msk ( 0x1UL << EXTI_IENR1_INTEN18_Pos ) +#define EXTI_IENR1_INTEN18 ( EXTI_IENR1_INTEN18_Msk ) + + +#define EXTI_IENR1_INTEN17_Pos ( 17U ) +#define EXTI_IENR1_INTEN17_Msk ( 0x1UL << EXTI_IENR1_INTEN17_Pos ) +#define EXTI_IENR1_INTEN17 ( EXTI_IENR1_INTEN17_Msk ) + + +#define EXTI_IENR1_INTEN16_Pos ( 16U ) +#define EXTI_IENR1_INTEN16_Msk ( 0x1UL << EXTI_IENR1_INTEN16_Pos ) +#define EXTI_IENR1_INTEN16 ( EXTI_IENR1_INTEN16_Msk ) + + +#define EXTI_IENR1_INTEN15_Pos ( 15U ) +#define EXTI_IENR1_INTEN15_Msk ( 0x1UL << EXTI_IENR1_INTEN15_Pos ) +#define EXTI_IENR1_INTEN15 ( EXTI_IENR1_INTEN15_Msk ) + + +#define EXTI_IENR1_INTEN14_Pos ( 14U ) +#define EXTI_IENR1_INTEN14_Msk ( 0x1UL << EXTI_IENR1_INTEN14_Pos ) +#define EXTI_IENR1_INTEN14 ( EXTI_IENR1_INTEN14_Msk ) + + +#define EXTI_IENR1_INTEN13_Pos ( 13U ) +#define EXTI_IENR1_INTEN13_Msk ( 0x1UL << EXTI_IENR1_INTEN13_Pos ) +#define EXTI_IENR1_INTEN13 ( EXTI_IENR1_INTEN13_Msk ) + + +#define EXTI_IENR1_INTEN12_Pos ( 12U ) +#define EXTI_IENR1_INTEN12_Msk ( 0x1UL << EXTI_IENR1_INTEN12_Pos ) +#define EXTI_IENR1_INTEN12 ( EXTI_IENR1_INTEN12_Msk ) + + +#define EXTI_IENR1_INTEN11_Pos ( 11U ) +#define EXTI_IENR1_INTEN11_Msk ( 0x1UL << EXTI_IENR1_INTEN11_Pos ) +#define EXTI_IENR1_INTEN11 ( EXTI_IENR1_INTEN11_Msk ) + + +#define EXTI_IENR1_INTEN10_Pos ( 10U ) +#define EXTI_IENR1_INTEN10_Msk ( 0x1UL << EXTI_IENR1_INTEN10_Pos ) +#define EXTI_IENR1_INTEN10 ( EXTI_IENR1_INTEN10_Msk ) + + +#define EXTI_IENR1_INTEN9_Pos ( 9U ) +#define EXTI_IENR1_INTEN9_Msk ( 0x1UL << EXTI_IENR1_INTEN9_Pos ) +#define EXTI_IENR1_INTEN9 ( EXTI_IENR1_INTEN9_Msk ) + + +#define EXTI_IENR1_INTEN8_Pos ( 8U ) +#define EXTI_IENR1_INTEN8_Msk ( 0x1UL << EXTI_IENR1_INTEN8_Pos ) +#define EXTI_IENR1_INTEN8 ( EXTI_IENR1_INTEN8_Msk ) + + +#define EXTI_IENR1_INTEN7_Pos ( 7U ) +#define EXTI_IENR1_INTEN7_Msk ( 0x1UL << EXTI_IENR1_INTEN7_Pos ) +#define EXTI_IENR1_INTEN7 ( EXTI_IENR1_INTEN7_Msk ) + + +#define EXTI_IENR1_INTEN6_Pos ( 6U ) +#define EXTI_IENR1_INTEN6_Msk ( 0x1UL << EXTI_IENR1_INTEN6_Pos ) +#define EXTI_IENR1_INTEN6 ( EXTI_IENR1_INTEN6_Msk ) + + +#define EXTI_IENR1_INTEN5_Pos ( 5U ) +#define EXTI_IENR1_INTEN5_Msk ( 0x1UL << EXTI_IENR1_INTEN5_Pos ) +#define EXTI_IENR1_INTEN5 ( EXTI_IENR1_INTEN5_Msk ) + + +#define EXTI_IENR1_INTEN4_Pos ( 4U ) +#define EXTI_IENR1_INTEN4_Msk ( 0x1UL << EXTI_IENR1_INTEN4_Pos ) +#define EXTI_IENR1_INTEN4 ( EXTI_IENR1_INTEN4_Msk ) + + +#define EXTI_IENR1_INTEN3_Pos ( 3U ) +#define EXTI_IENR1_INTEN3_Msk ( 0x1UL << EXTI_IENR1_INTEN3_Pos ) +#define EXTI_IENR1_INTEN3 ( EXTI_IENR1_INTEN3_Msk ) + + +#define EXTI_IENR1_INTEN2_Pos ( 2U ) +#define EXTI_IENR1_INTEN2_Msk ( 0x1UL << EXTI_IENR1_INTEN2_Pos ) +#define EXTI_IENR1_INTEN2 ( EXTI_IENR1_INTEN2_Msk ) + + +#define EXTI_IENR1_INTEN1_Pos ( 1U ) +#define EXTI_IENR1_INTEN1_Msk ( 0x1UL << EXTI_IENR1_INTEN1_Pos ) +#define EXTI_IENR1_INTEN1 ( EXTI_IENR1_INTEN1_Msk ) + + +#define EXTI_IENR1_INTEN0_Pos ( 0U ) +#define EXTI_IENR1_INTEN0_Msk ( 0x1UL << EXTI_IENR1_INTEN0_Pos ) +#define EXTI_IENR1_INTEN0 ( EXTI_IENR1_INTEN0_Msk ) + + + +/*************** Bits definition for EXTI_IENR2 **********************/ + +#define EXTI_IENR2_INTEN34_Pos ( 2U ) +#define EXTI_IENR2_INTEN34_Msk ( 0x1UL << EXTI_IENR2_INTEN34_Pos ) +#define EXTI_IENR2_INTEN34 ( EXTI_IENR2_INTEN34_Msk ) + + +#define EXTI_IENR2_INTEN33_Pos ( 1U ) +#define EXTI_IENR2_INTEN33_Msk ( 0x1UL << EXTI_IENR2_INTEN33_Pos ) +#define EXTI_IENR2_INTEN33 ( EXTI_IENR2_INTEN33_Msk ) + + +#define EXTI_IENR2_INTEN32_Pos ( 0U ) +#define EXTI_IENR2_INTEN32_Msk ( 0x1UL << EXTI_IENR2_INTEN32_Pos ) +#define EXTI_IENR2_INTEN32 ( EXTI_IENR2_INTEN32_Msk ) + + + +/*************** Bits definition for EXTI_EENR1 **********************/ + +#define EXTI_EENR1_EVEN31_Pos ( 31U ) +#define EXTI_EENR1_EVEN31_Msk ( 0x1UL << EXTI_EENR1_EVEN31_Pos ) +#define EXTI_EENR1_EVEN31 ( EXTI_EENR1_EVEN31_Msk ) + + +#define EXTI_EENR1_EVEN30_Pos ( 30U ) +#define EXTI_EENR1_EVEN30_Msk ( 0x1UL << EXTI_EENR1_EVEN30_Pos ) +#define EXTI_EENR1_EVEN30 ( EXTI_EENR1_EVEN30_Msk ) + + +#define EXTI_EENR1_EVEN29_Pos ( 29U ) +#define EXTI_EENR1_EVEN29_Msk ( 0x1UL << EXTI_EENR1_EVEN29_Pos ) +#define EXTI_EENR1_EVEN29 ( EXTI_EENR1_EVEN29_Msk ) + + +#define EXTI_EENR1_EVEN28_Pos ( 28U ) +#define EXTI_EENR1_EVEN28_Msk ( 0x1UL << EXTI_EENR1_EVEN28_Pos ) +#define EXTI_EENR1_EVEN28 ( EXTI_EENR1_EVEN28_Msk ) + + +#define EXTI_EENR1_EVEN27_Pos ( 27U ) +#define EXTI_EENR1_EVEN27_Msk ( 0x1UL << EXTI_EENR1_EVEN27_Pos ) +#define EXTI_EENR1_EVEN27 ( EXTI_EENR1_EVEN27_Msk ) + + +#define EXTI_EENR1_EVEN26_Pos ( 26U ) +#define EXTI_EENR1_EVEN26_Msk ( 0x1UL << EXTI_EENR1_EVEN26_Pos ) +#define EXTI_EENR1_EVEN26 ( EXTI_EENR1_EVEN26_Msk ) + + +#define EXTI_EENR1_EVEN25_Pos ( 25U ) +#define EXTI_EENR1_EVEN25_Msk ( 0x1UL << EXTI_EENR1_EVEN25_Pos ) +#define EXTI_EENR1_EVEN25 ( EXTI_EENR1_EVEN25_Msk ) + + +#define EXTI_EENR1_EVEN24_Pos ( 24U ) +#define EXTI_EENR1_EVEN24_Msk ( 0x1UL << EXTI_EENR1_EVEN24_Pos ) +#define EXTI_EENR1_EVEN24 ( EXTI_EENR1_EVEN24_Msk ) + + +#define EXTI_EENR1_EVEN23_Pos ( 23U ) +#define EXTI_EENR1_EVEN23_Msk ( 0x1UL << EXTI_EENR1_EVEN23_Pos ) +#define EXTI_EENR1_EVEN23 ( EXTI_EENR1_EVEN23_Msk ) + + +#define EXTI_EENR1_EVEN22_Pos ( 22U ) +#define EXTI_EENR1_EVEN22_Msk ( 0x1UL << EXTI_EENR1_EVEN22_Pos ) +#define EXTI_EENR1_EVEN22 ( EXTI_EENR1_EVEN22_Msk ) + + +#define EXTI_EENR1_EVEN21_Pos ( 21U ) +#define EXTI_EENR1_EVEN21_Msk ( 0x1UL << EXTI_EENR1_EVEN21_Pos ) +#define EXTI_EENR1_EVEN21 ( EXTI_EENR1_EVEN21_Msk ) + + +#define EXTI_EENR1_EVEN20_Pos ( 20U ) +#define EXTI_EENR1_EVEN20_Msk ( 0x1UL << EXTI_EENR1_EVEN20_Pos ) +#define EXTI_EENR1_EVEN20 ( EXTI_EENR1_EVEN20_Msk ) + + +#define EXTI_EENR1_EVEN19_Pos ( 19U ) +#define EXTI_EENR1_EVEN19_Msk ( 0x1UL << EXTI_EENR1_EVEN19_Pos ) +#define EXTI_EENR1_EVEN19 ( EXTI_EENR1_EVEN19_Msk ) + + +#define EXTI_EENR1_EVEN18_Pos ( 18U ) +#define EXTI_EENR1_EVEN18_Msk ( 0x1UL << EXTI_EENR1_EVEN18_Pos ) +#define EXTI_EENR1_EVEN18 ( EXTI_EENR1_EVEN18_Msk ) + + +#define EXTI_EENR1_EVEN17_Pos ( 17U ) +#define EXTI_EENR1_EVEN17_Msk ( 0x1UL << EXTI_EENR1_EVEN17_Pos ) +#define EXTI_EENR1_EVEN17 ( EXTI_EENR1_EVEN17_Msk ) + + +#define EXTI_EENR1_EVEN16_Pos ( 16U ) +#define EXTI_EENR1_EVEN16_Msk ( 0x1UL << EXTI_EENR1_EVEN16_Pos ) +#define EXTI_EENR1_EVEN16 ( EXTI_EENR1_EVEN16_Msk ) + + +#define EXTI_EENR1_EVEN15_Pos ( 15U ) +#define EXTI_EENR1_EVEN15_Msk ( 0x1UL << EXTI_EENR1_EVEN15_Pos ) +#define EXTI_EENR1_EVEN15 ( EXTI_EENR1_EVEN15_Msk ) + + +#define EXTI_EENR1_EVEN14_Pos ( 14U ) +#define EXTI_EENR1_EVEN14_Msk ( 0x1UL << EXTI_EENR1_EVEN14_Pos ) +#define EXTI_EENR1_EVEN14 ( EXTI_EENR1_EVEN14_Msk ) + + +#define EXTI_EENR1_EVEN13_Pos ( 13U ) +#define EXTI_EENR1_EVEN13_Msk ( 0x1UL << EXTI_EENR1_EVEN13_Pos ) +#define EXTI_EENR1_EVEN13 ( EXTI_EENR1_EVEN13_Msk ) + + +#define EXTI_EENR1_EVEN12_Pos ( 12U ) +#define EXTI_EENR1_EVEN12_Msk ( 0x1UL << EXTI_EENR1_EVEN12_Pos ) +#define EXTI_EENR1_EVEN12 ( EXTI_EENR1_EVEN12_Msk ) + + +#define EXTI_EENR1_EVEN11_Pos ( 11U ) +#define EXTI_EENR1_EVEN11_Msk ( 0x1UL << EXTI_EENR1_EVEN11_Pos ) +#define EXTI_EENR1_EVEN11 ( EXTI_EENR1_EVEN11_Msk ) + + +#define EXTI_EENR1_EVEN10_Pos ( 10U ) +#define EXTI_EENR1_EVEN10_Msk ( 0x1UL << EXTI_EENR1_EVEN10_Pos ) +#define EXTI_EENR1_EVEN10 ( EXTI_EENR1_EVEN10_Msk ) + + +#define EXTI_EENR1_EVEN9_Pos ( 9U ) +#define EXTI_EENR1_EVEN9_Msk ( 0x1UL << EXTI_EENR1_EVEN9_Pos ) +#define EXTI_EENR1_EVEN9 ( EXTI_EENR1_EVEN9_Msk ) + + +#define EXTI_EENR1_EVEN8_Pos ( 8U ) +#define EXTI_EENR1_EVEN8_Msk ( 0x1UL << EXTI_EENR1_EVEN8_Pos ) +#define EXTI_EENR1_EVEN8 ( EXTI_EENR1_EVEN8_Msk ) + + +#define EXTI_EENR1_EVEN7_Pos ( 7U ) +#define EXTI_EENR1_EVEN7_Msk ( 0x1UL << EXTI_EENR1_EVEN7_Pos ) +#define EXTI_EENR1_EVEN7 ( EXTI_EENR1_EVEN7_Msk ) + + +#define EXTI_EENR1_EVEN6_Pos ( 6U ) +#define EXTI_EENR1_EVEN6_Msk ( 0x1UL << EXTI_EENR1_EVEN6_Pos ) +#define EXTI_EENR1_EVEN6 ( EXTI_EENR1_EVEN6_Msk ) + + +#define EXTI_EENR1_EVEN5_Pos ( 5U ) +#define EXTI_EENR1_EVEN5_Msk ( 0x1UL << EXTI_EENR1_EVEN5_Pos ) +#define EXTI_EENR1_EVEN5 ( EXTI_EENR1_EVEN5_Msk ) + + +#define EXTI_EENR1_EVEN4_Pos ( 4U ) +#define EXTI_EENR1_EVEN4_Msk ( 0x1UL << EXTI_EENR1_EVEN4_Pos ) +#define EXTI_EENR1_EVEN4 ( EXTI_EENR1_EVEN4_Msk ) + + +#define EXTI_EENR1_EVEN3_Pos ( 3U ) +#define EXTI_EENR1_EVEN3_Msk ( 0x1UL << EXTI_EENR1_EVEN3_Pos ) +#define EXTI_EENR1_EVEN3 ( EXTI_EENR1_EVEN3_Msk ) + + +#define EXTI_EENR1_EVEN2_Pos ( 2U ) +#define EXTI_EENR1_EVEN2_Msk ( 0x1UL << EXTI_EENR1_EVEN2_Pos ) +#define EXTI_EENR1_EVEN2 ( EXTI_EENR1_EVEN2_Msk ) + + +#define EXTI_EENR1_EVEN1_Pos ( 1U ) +#define EXTI_EENR1_EVEN1_Msk ( 0x1UL << EXTI_EENR1_EVEN1_Pos ) +#define EXTI_EENR1_EVEN1 ( EXTI_EENR1_EVEN1_Msk ) + + +#define EXTI_EENR1_EVEN0_Pos ( 0U ) +#define EXTI_EENR1_EVEN0_Msk ( 0x1UL << EXTI_EENR1_EVEN0_Pos ) +#define EXTI_EENR1_EVEN0 ( EXTI_EENR1_EVEN0_Msk ) + + + +/*************** Bits definition for EXTI_EENR2 **********************/ + +#define EXTI_EENR2_EVEN34_Pos ( 2U ) +#define EXTI_EENR2_EVEN34_Msk ( 0x1UL << EXTI_EENR2_EVEN34_Pos ) +#define EXTI_EENR2_EVEN34 ( EXTI_EENR2_EVEN34_Msk ) + + +#define EXTI_EENR2_EVEN33_Pos ( 1U ) +#define EXTI_EENR2_EVEN33_Msk ( 0x1UL << EXTI_EENR2_EVEN33_Pos ) +#define EXTI_EENR2_EVEN33 ( EXTI_EENR2_EVEN33_Msk ) + + +#define EXTI_EENR2_EVEN32_Pos ( 0U ) +#define EXTI_EENR2_EVEN32_Msk ( 0x1UL << EXTI_EENR2_EVEN32_Pos ) +#define EXTI_EENR2_EVEN32 ( EXTI_EENR2_EVEN32_Msk ) + + + +/*************** Bits definition for EXTI_RTENR1 **********************/ + +#define EXTI_RTENR1_RTEN31_Pos ( 31U ) +#define EXTI_RTENR1_RTEN31_Msk ( 0x1UL << EXTI_RTENR1_RTEN31_Pos ) +#define EXTI_RTENR1_RTEN31 ( EXTI_RTENR1_RTEN31_Msk ) + + +#define EXTI_RTENR1_RTEN30_Pos ( 30U ) +#define EXTI_RTENR1_RTEN30_Msk ( 0x1UL << EXTI_RTENR1_RTEN30_Pos ) +#define EXTI_RTENR1_RTEN30 ( EXTI_RTENR1_RTEN30_Msk ) + + +#define EXTI_RTENR1_RTEN29_Pos ( 29U ) +#define EXTI_RTENR1_RTEN29_Msk ( 0x1UL << EXTI_RTENR1_RTEN29_Pos ) +#define EXTI_RTENR1_RTEN29 ( EXTI_RTENR1_RTEN29_Msk ) + + +#define EXTI_RTENR1_RTEN28_Pos ( 28U ) +#define EXTI_RTENR1_RTEN28_Msk ( 0x1UL << EXTI_RTENR1_RTEN28_Pos ) +#define EXTI_RTENR1_RTEN28 ( EXTI_RTENR1_RTEN28_Msk ) + + +#define EXTI_RTENR1_RTEN27_Pos ( 27U ) +#define EXTI_RTENR1_RTEN27_Msk ( 0x1UL << EXTI_RTENR1_RTEN27_Pos ) +#define EXTI_RTENR1_RTEN27 ( EXTI_RTENR1_RTEN27_Msk ) + + +#define EXTI_RTENR1_RTEN26_Pos ( 26U ) +#define EXTI_RTENR1_RTEN26_Msk ( 0x1UL << EXTI_RTENR1_RTEN26_Pos ) +#define EXTI_RTENR1_RTEN26 ( EXTI_RTENR1_RTEN26_Msk ) + + +#define EXTI_RTENR1_RTEN25_Pos ( 25U ) +#define EXTI_RTENR1_RTEN25_Msk ( 0x1UL << EXTI_RTENR1_RTEN25_Pos ) +#define EXTI_RTENR1_RTEN25 ( EXTI_RTENR1_RTEN25_Msk ) + + +#define EXTI_RTENR1_RTEN24_Pos ( 24U ) +#define EXTI_RTENR1_RTEN24_Msk ( 0x1UL << EXTI_RTENR1_RTEN24_Pos ) +#define EXTI_RTENR1_RTEN24 ( EXTI_RTENR1_RTEN24_Msk ) + + +#define EXTI_RTENR1_RTEN23_Pos ( 23U ) +#define EXTI_RTENR1_RTEN23_Msk ( 0x1UL << EXTI_RTENR1_RTEN23_Pos ) +#define EXTI_RTENR1_RTEN23 ( EXTI_RTENR1_RTEN23_Msk ) + + +#define EXTI_RTENR1_RTEN22_Pos ( 22U ) +#define EXTI_RTENR1_RTEN22_Msk ( 0x1UL << EXTI_RTENR1_RTEN22_Pos ) +#define EXTI_RTENR1_RTEN22 ( EXTI_RTENR1_RTEN22_Msk ) + + +#define EXTI_RTENR1_RTEN21_Pos ( 21U ) +#define EXTI_RTENR1_RTEN21_Msk ( 0x1UL << EXTI_RTENR1_RTEN21_Pos ) +#define EXTI_RTENR1_RTEN21 ( EXTI_RTENR1_RTEN21_Msk ) + + +#define EXTI_RTENR1_RTEN20_Pos ( 20U ) +#define EXTI_RTENR1_RTEN20_Msk ( 0x1UL << EXTI_RTENR1_RTEN20_Pos ) +#define EXTI_RTENR1_RTEN20 ( EXTI_RTENR1_RTEN20_Msk ) + + +#define EXTI_RTENR1_RTEN19_Pos ( 19U ) +#define EXTI_RTENR1_RTEN19_Msk ( 0x1UL << EXTI_RTENR1_RTEN19_Pos ) +#define EXTI_RTENR1_RTEN19 ( EXTI_RTENR1_RTEN19_Msk ) + + +#define EXTI_RTENR1_RTEN18_Pos ( 18U ) +#define EXTI_RTENR1_RTEN18_Msk ( 0x1UL << EXTI_RTENR1_RTEN18_Pos ) +#define EXTI_RTENR1_RTEN18 ( EXTI_RTENR1_RTEN18_Msk ) + + +#define EXTI_RTENR1_RTEN17_Pos ( 17U ) +#define EXTI_RTENR1_RTEN17_Msk ( 0x1UL << EXTI_RTENR1_RTEN17_Pos ) +#define EXTI_RTENR1_RTEN17 ( EXTI_RTENR1_RTEN17_Msk ) + + +#define EXTI_RTENR1_RTEN16_Pos ( 16U ) +#define EXTI_RTENR1_RTEN16_Msk ( 0x1UL << EXTI_RTENR1_RTEN16_Pos ) +#define EXTI_RTENR1_RTEN16 ( EXTI_RTENR1_RTEN16_Msk ) + + +#define EXTI_RTENR1_RTEN15_Pos ( 15U ) +#define EXTI_RTENR1_RTEN15_Msk ( 0x1UL << EXTI_RTENR1_RTEN15_Pos ) +#define EXTI_RTENR1_RTEN15 ( EXTI_RTENR1_RTEN15_Msk ) + + +#define EXTI_RTENR1_RTEN14_Pos ( 14U ) +#define EXTI_RTENR1_RTEN14_Msk ( 0x1UL << EXTI_RTENR1_RTEN14_Pos ) +#define EXTI_RTENR1_RTEN14 ( EXTI_RTENR1_RTEN14_Msk ) + + +#define EXTI_RTENR1_RTEN13_Pos ( 13U ) +#define EXTI_RTENR1_RTEN13_Msk ( 0x1UL << EXTI_RTENR1_RTEN13_Pos ) +#define EXTI_RTENR1_RTEN13 ( EXTI_RTENR1_RTEN13_Msk ) + + +#define EXTI_RTENR1_RTEN12_Pos ( 12U ) +#define EXTI_RTENR1_RTEN12_Msk ( 0x1UL << EXTI_RTENR1_RTEN12_Pos ) +#define EXTI_RTENR1_RTEN12 ( EXTI_RTENR1_RTEN12_Msk ) + + +#define EXTI_RTENR1_RTEN11_Pos ( 11U ) +#define EXTI_RTENR1_RTEN11_Msk ( 0x1UL << EXTI_RTENR1_RTEN11_Pos ) +#define EXTI_RTENR1_RTEN11 ( EXTI_RTENR1_RTEN11_Msk ) + + +#define EXTI_RTENR1_RTEN10_Pos ( 10U ) +#define EXTI_RTENR1_RTEN10_Msk ( 0x1UL << EXTI_RTENR1_RTEN10_Pos ) +#define EXTI_RTENR1_RTEN10 ( EXTI_RTENR1_RTEN10_Msk ) + + +#define EXTI_RTENR1_RTEN9_Pos ( 9U ) +#define EXTI_RTENR1_RTEN9_Msk ( 0x1UL << EXTI_RTENR1_RTEN9_Pos ) +#define EXTI_RTENR1_RTEN9 ( EXTI_RTENR1_RTEN9_Msk ) + + +#define EXTI_RTENR1_RTEN8_Pos ( 8U ) +#define EXTI_RTENR1_RTEN8_Msk ( 0x1UL << EXTI_RTENR1_RTEN8_Pos ) +#define EXTI_RTENR1_RTEN8 ( EXTI_RTENR1_RTEN8_Msk ) + + +#define EXTI_RTENR1_RTEN7_Pos ( 7U ) +#define EXTI_RTENR1_RTEN7_Msk ( 0x1UL << EXTI_RTENR1_RTEN7_Pos ) +#define EXTI_RTENR1_RTEN7 ( EXTI_RTENR1_RTEN7_Msk ) + + +#define EXTI_RTENR1_RTEN6_Pos ( 6U ) +#define EXTI_RTENR1_RTEN6_Msk ( 0x1UL << EXTI_RTENR1_RTEN6_Pos ) +#define EXTI_RTENR1_RTEN6 ( EXTI_RTENR1_RTEN6_Msk ) + + +#define EXTI_RTENR1_RTEN5_Pos ( 5U ) +#define EXTI_RTENR1_RTEN5_Msk ( 0x1UL << EXTI_RTENR1_RTEN5_Pos ) +#define EXTI_RTENR1_RTEN5 ( EXTI_RTENR1_RTEN5_Msk ) + + +#define EXTI_RTENR1_RTEN4_Pos ( 4U ) +#define EXTI_RTENR1_RTEN4_Msk ( 0x1UL << EXTI_RTENR1_RTEN4_Pos ) +#define EXTI_RTENR1_RTEN4 ( EXTI_RTENR1_RTEN4_Msk ) + + +#define EXTI_RTENR1_RTEN3_Pos ( 3U ) +#define EXTI_RTENR1_RTEN3_Msk ( 0x1UL << EXTI_RTENR1_RTEN3_Pos ) +#define EXTI_RTENR1_RTEN3 ( EXTI_RTENR1_RTEN3_Msk ) + + +#define EXTI_RTENR1_RTEN2_Pos ( 2U ) +#define EXTI_RTENR1_RTEN2_Msk ( 0x1UL << EXTI_RTENR1_RTEN2_Pos ) +#define EXTI_RTENR1_RTEN2 ( EXTI_RTENR1_RTEN2_Msk ) + + +#define EXTI_RTENR1_RTEN1_Pos ( 1U ) +#define EXTI_RTENR1_RTEN1_Msk ( 0x1UL << EXTI_RTENR1_RTEN1_Pos ) +#define EXTI_RTENR1_RTEN1 ( EXTI_RTENR1_RTEN1_Msk ) + + +#define EXTI_RTENR1_RTEN0_Pos ( 0U ) +#define EXTI_RTENR1_RTEN0_Msk ( 0x1UL << EXTI_RTENR1_RTEN0_Pos ) +#define EXTI_RTENR1_RTEN0 ( EXTI_RTENR1_RTEN0_Msk ) + + + +/*************** Bits definition for EXTI_RTENR2 **********************/ + +#define EXTI_RTENR2_RTEN34_Pos ( 2U ) +#define EXTI_RTENR2_RTEN34_Msk ( 0x1UL << EXTI_RTENR2_RTEN34_Pos ) +#define EXTI_RTENR2_RTEN34 ( EXTI_RTENR2_RTEN34_Msk ) + + +#define EXTI_RTENR2_RTEN33_Pos ( 1U ) +#define EXTI_RTENR2_RTEN33_Msk ( 0x1UL << EXTI_RTENR2_RTEN33_Pos ) +#define EXTI_RTENR2_RTEN33 ( EXTI_RTENR2_RTEN33_Msk ) + + +#define EXTI_RTENR2_RTEN32_Pos ( 0U ) +#define EXTI_RTENR2_RTEN32_Msk ( 0x1UL << EXTI_RTENR2_RTEN32_Pos ) +#define EXTI_RTENR2_RTEN32 ( EXTI_RTENR2_RTEN32_Msk ) + + + +/*************** Bits definition for EXTI_FTENR1 **********************/ + +#define EXTI_FTENR1_FTEN31_Pos ( 31U ) +#define EXTI_FTENR1_FTEN31_Msk ( 0x1UL << EXTI_FTENR1_FTEN31_Pos ) +#define EXTI_FTENR1_FTEN31 ( EXTI_FTENR1_FTEN31_Msk ) + + +#define EXTI_FTENR1_FTEN30_Pos ( 30U ) +#define EXTI_FTENR1_FTEN30_Msk ( 0x1UL << EXTI_FTENR1_FTEN30_Pos ) +#define EXTI_FTENR1_FTEN30 ( EXTI_FTENR1_FTEN30_Msk ) + + +#define EXTI_FTENR1_FTEN29_Pos ( 29U ) +#define EXTI_FTENR1_FTEN29_Msk ( 0x1UL << EXTI_FTENR1_FTEN29_Pos ) +#define EXTI_FTENR1_FTEN29 ( EXTI_FTENR1_FTEN29_Msk ) + + +#define EXTI_FTENR1_FTEN28_Pos ( 28U ) +#define EXTI_FTENR1_FTEN28_Msk ( 0x1UL << EXTI_FTENR1_FTEN28_Pos ) +#define EXTI_FTENR1_FTEN28 ( EXTI_FTENR1_FTEN28_Msk ) + + +#define EXTI_FTENR1_FTEN27_Pos ( 27U ) +#define EXTI_FTENR1_FTEN27_Msk ( 0x1UL << EXTI_FTENR1_FTEN27_Pos ) +#define EXTI_FTENR1_FTEN27 ( EXTI_FTENR1_FTEN27_Msk ) + + +#define EXTI_FTENR1_FTEN26_Pos ( 26U ) +#define EXTI_FTENR1_FTEN26_Msk ( 0x1UL << EXTI_FTENR1_FTEN26_Pos ) +#define EXTI_FTENR1_FTEN26 ( EXTI_FTENR1_FTEN26_Msk ) + + +#define EXTI_FTENR1_FTEN25_Pos ( 25U ) +#define EXTI_FTENR1_FTEN25_Msk ( 0x1UL << EXTI_FTENR1_FTEN25_Pos ) +#define EXTI_FTENR1_FTEN25 ( EXTI_FTENR1_FTEN25_Msk ) + + +#define EXTI_FTENR1_FTEN24_Pos ( 24U ) +#define EXTI_FTENR1_FTEN24_Msk ( 0x1UL << EXTI_FTENR1_FTEN24_Pos ) +#define EXTI_FTENR1_FTEN24 ( EXTI_FTENR1_FTEN24_Msk ) + + +#define EXTI_FTENR1_FTEN23_Pos ( 23U ) +#define EXTI_FTENR1_FTEN23_Msk ( 0x1UL << EXTI_FTENR1_FTEN23_Pos ) +#define EXTI_FTENR1_FTEN23 ( EXTI_FTENR1_FTEN23_Msk ) + + +#define EXTI_FTENR1_FTEN22_Pos ( 22U ) +#define EXTI_FTENR1_FTEN22_Msk ( 0x1UL << EXTI_FTENR1_FTEN22_Pos ) +#define EXTI_FTENR1_FTEN22 ( EXTI_FTENR1_FTEN22_Msk ) + + +#define EXTI_FTENR1_FTEN21_Pos ( 21U ) +#define EXTI_FTENR1_FTEN21_Msk ( 0x1UL << EXTI_FTENR1_FTEN21_Pos ) +#define EXTI_FTENR1_FTEN21 ( EXTI_FTENR1_FTEN21_Msk ) + + +#define EXTI_FTENR1_FTEN20_Pos ( 20U ) +#define EXTI_FTENR1_FTEN20_Msk ( 0x1UL << EXTI_FTENR1_FTEN20_Pos ) +#define EXTI_FTENR1_FTEN20 ( EXTI_FTENR1_FTEN20_Msk ) + + +#define EXTI_FTENR1_FTEN19_Pos ( 19U ) +#define EXTI_FTENR1_FTEN19_Msk ( 0x1UL << EXTI_FTENR1_FTEN19_Pos ) +#define EXTI_FTENR1_FTEN19 ( EXTI_FTENR1_FTEN19_Msk ) + + +#define EXTI_FTENR1_FTEN18_Pos ( 18U ) +#define EXTI_FTENR1_FTEN18_Msk ( 0x1UL << EXTI_FTENR1_FTEN18_Pos ) +#define EXTI_FTENR1_FTEN18 ( EXTI_FTENR1_FTEN18_Msk ) + + +#define EXTI_FTENR1_FTEN17_Pos ( 17U ) +#define EXTI_FTENR1_FTEN17_Msk ( 0x1UL << EXTI_FTENR1_FTEN17_Pos ) +#define EXTI_FTENR1_FTEN17 ( EXTI_FTENR1_FTEN17_Msk ) + + +#define EXTI_FTENR1_FTEN16_Pos ( 16U ) +#define EXTI_FTENR1_FTEN16_Msk ( 0x1UL << EXTI_FTENR1_FTEN16_Pos ) +#define EXTI_FTENR1_FTEN16 ( EXTI_FTENR1_FTEN16_Msk ) + + +#define EXTI_FTENR1_FTEN15_Pos ( 15U ) +#define EXTI_FTENR1_FTEN15_Msk ( 0x1UL << EXTI_FTENR1_FTEN15_Pos ) +#define EXTI_FTENR1_FTEN15 ( EXTI_FTENR1_FTEN15_Msk ) + + +#define EXTI_FTENR1_FTEN14_Pos ( 14U ) +#define EXTI_FTENR1_FTEN14_Msk ( 0x1UL << EXTI_FTENR1_FTEN14_Pos ) +#define EXTI_FTENR1_FTEN14 ( EXTI_FTENR1_FTEN14_Msk ) + + +#define EXTI_FTENR1_FTEN13_Pos ( 13U ) +#define EXTI_FTENR1_FTEN13_Msk ( 0x1UL << EXTI_FTENR1_FTEN13_Pos ) +#define EXTI_FTENR1_FTEN13 ( EXTI_FTENR1_FTEN13_Msk ) + + +#define EXTI_FTENR1_FTEN12_Pos ( 12U ) +#define EXTI_FTENR1_FTEN12_Msk ( 0x1UL << EXTI_FTENR1_FTEN12_Pos ) +#define EXTI_FTENR1_FTEN12 ( EXTI_FTENR1_FTEN12_Msk ) + + +#define EXTI_FTENR1_FTEN11_Pos ( 11U ) +#define EXTI_FTENR1_FTEN11_Msk ( 0x1UL << EXTI_FTENR1_FTEN11_Pos ) +#define EXTI_FTENR1_FTEN11 ( EXTI_FTENR1_FTEN11_Msk ) + + +#define EXTI_FTENR1_FTEN10_Pos ( 10U ) +#define EXTI_FTENR1_FTEN10_Msk ( 0x1UL << EXTI_FTENR1_FTEN10_Pos ) +#define EXTI_FTENR1_FTEN10 ( EXTI_FTENR1_FTEN10_Msk ) + + +#define EXTI_FTENR1_FTEN9_Pos ( 9U ) +#define EXTI_FTENR1_FTEN9_Msk ( 0x1UL << EXTI_FTENR1_FTEN9_Pos ) +#define EXTI_FTENR1_FTEN9 ( EXTI_FTENR1_FTEN9_Msk ) + + +#define EXTI_FTENR1_FTEN8_Pos ( 8U ) +#define EXTI_FTENR1_FTEN8_Msk ( 0x1UL << EXTI_FTENR1_FTEN8_Pos ) +#define EXTI_FTENR1_FTEN8 ( EXTI_FTENR1_FTEN8_Msk ) + + +#define EXTI_FTENR1_FTEN7_Pos ( 7U ) +#define EXTI_FTENR1_FTEN7_Msk ( 0x1UL << EXTI_FTENR1_FTEN7_Pos ) +#define EXTI_FTENR1_FTEN7 ( EXTI_FTENR1_FTEN7_Msk ) + + +#define EXTI_FTENR1_FTEN6_Pos ( 6U ) +#define EXTI_FTENR1_FTEN6_Msk ( 0x1UL << EXTI_FTENR1_FTEN6_Pos ) +#define EXTI_FTENR1_FTEN6 ( EXTI_FTENR1_FTEN6_Msk ) + + +#define EXTI_FTENR1_FTEN5_Pos ( 5U ) +#define EXTI_FTENR1_FTEN5_Msk ( 0x1UL << EXTI_FTENR1_FTEN5_Pos ) +#define EXTI_FTENR1_FTEN5 ( EXTI_FTENR1_FTEN5_Msk ) + + +#define EXTI_FTENR1_FTEN4_Pos ( 4U ) +#define EXTI_FTENR1_FTEN4_Msk ( 0x1UL << EXTI_FTENR1_FTEN4_Pos ) +#define EXTI_FTENR1_FTEN4 ( EXTI_FTENR1_FTEN4_Msk ) + + +#define EXTI_FTENR1_FTEN3_Pos ( 3U ) +#define EXTI_FTENR1_FTEN3_Msk ( 0x1UL << EXTI_FTENR1_FTEN3_Pos ) +#define EXTI_FTENR1_FTEN3 ( EXTI_FTENR1_FTEN3_Msk ) + + +#define EXTI_FTENR1_FTEN2_Pos ( 2U ) +#define EXTI_FTENR1_FTEN2_Msk ( 0x1UL << EXTI_FTENR1_FTEN2_Pos ) +#define EXTI_FTENR1_FTEN2 ( EXTI_FTENR1_FTEN2_Msk ) + + +#define EXTI_FTENR1_FTEN1_Pos ( 1U ) +#define EXTI_FTENR1_FTEN1_Msk ( 0x1UL << EXTI_FTENR1_FTEN1_Pos ) +#define EXTI_FTENR1_FTEN1 ( EXTI_FTENR1_FTEN1_Msk ) + + +#define EXTI_FTENR1_FTEN0_Pos ( 0U ) +#define EXTI_FTENR1_FTEN0_Msk ( 0x1UL << EXTI_FTENR1_FTEN0_Pos ) +#define EXTI_FTENR1_FTEN0 ( EXTI_FTENR1_FTEN0_Msk ) + + + +/*************** Bits definition for EXTI_FTENR2 **********************/ + +#define EXTI_FTENR2_FTEN34_Pos ( 2U ) +#define EXTI_FTENR2_FTEN34_Msk ( 0x1UL << EXTI_FTENR2_FTEN34_Pos ) +#define EXTI_FTENR2_FTEN34 ( EXTI_FTENR2_FTEN34_Msk ) + + +#define EXTI_FTENR2_FTEN33_Pos ( 1U ) +#define EXTI_FTENR2_FTEN33_Msk ( 0x1UL << EXTI_FTENR2_FTEN33_Pos ) +#define EXTI_FTENR2_FTEN33 ( EXTI_FTENR2_FTEN33_Msk ) + + +#define EXTI_FTENR2_FTEN32_Pos ( 0U ) +#define EXTI_FTENR2_FTEN32_Msk ( 0x1UL << EXTI_FTENR2_FTEN32_Pos ) +#define EXTI_FTENR2_FTEN32 ( EXTI_FTENR2_FTEN32_Msk ) + + + +/*************** Bits definition for EXTI_SWIER1 **********************/ + +#define EXTI_SWIER1_SWIE31_Pos ( 31U ) +#define EXTI_SWIER1_SWIE31_Msk ( 0x1UL << EXTI_SWIER1_SWIE31_Pos ) +#define EXTI_SWIER1_SWIE31 ( EXTI_SWIER1_SWIE31_Msk ) + + +#define EXTI_SWIER1_SWIE30_Pos ( 30U ) +#define EXTI_SWIER1_SWIE30_Msk ( 0x1UL << EXTI_SWIER1_SWIE30_Pos ) +#define EXTI_SWIER1_SWIE30 ( EXTI_SWIER1_SWIE30_Msk ) + + +#define EXTI_SWIER1_SWIE29_Pos ( 29U ) +#define EXTI_SWIER1_SWIE29_Msk ( 0x1UL << EXTI_SWIER1_SWIE29_Pos ) +#define EXTI_SWIER1_SWIE29 ( EXTI_SWIER1_SWIE29_Msk ) + + +#define EXTI_SWIER1_SWIE28_Pos ( 28U ) +#define EXTI_SWIER1_SWIE28_Msk ( 0x1UL << EXTI_SWIER1_SWIE28_Pos ) +#define EXTI_SWIER1_SWIE28 ( EXTI_SWIER1_SWIE28_Msk ) + + +#define EXTI_SWIER1_SWIE27_Pos ( 27U ) +#define EXTI_SWIER1_SWIE27_Msk ( 0x1UL << EXTI_SWIER1_SWIE27_Pos ) +#define EXTI_SWIER1_SWIE27 ( EXTI_SWIER1_SWIE27_Msk ) + + +#define EXTI_SWIER1_SWIE26_Pos ( 26U ) +#define EXTI_SWIER1_SWIE26_Msk ( 0x1UL << EXTI_SWIER1_SWIE26_Pos ) +#define EXTI_SWIER1_SWIE26 ( EXTI_SWIER1_SWIE26_Msk ) + + +#define EXTI_SWIER1_SWIE25_Pos ( 25U ) +#define EXTI_SWIER1_SWIE25_Msk ( 0x1UL << EXTI_SWIER1_SWIE25_Pos ) +#define EXTI_SWIER1_SWIE25 ( EXTI_SWIER1_SWIE25_Msk ) + + +#define EXTI_SWIER1_SWIE24_Pos ( 24U ) +#define EXTI_SWIER1_SWIE24_Msk ( 0x1UL << EXTI_SWIER1_SWIE24_Pos ) +#define EXTI_SWIER1_SWIE24 ( EXTI_SWIER1_SWIE24_Msk ) + + +#define EXTI_SWIER1_SWIE23_Pos ( 23U ) +#define EXTI_SWIER1_SWIE23_Msk ( 0x1UL << EXTI_SWIER1_SWIE23_Pos ) +#define EXTI_SWIER1_SWIE23 ( EXTI_SWIER1_SWIE23_Msk ) + + +#define EXTI_SWIER1_SWIE22_Pos ( 22U ) +#define EXTI_SWIER1_SWIE22_Msk ( 0x1UL << EXTI_SWIER1_SWIE22_Pos ) +#define EXTI_SWIER1_SWIE22 ( EXTI_SWIER1_SWIE22_Msk ) + + +#define EXTI_SWIER1_SWIE21_Pos ( 21U ) +#define EXTI_SWIER1_SWIE21_Msk ( 0x1UL << EXTI_SWIER1_SWIE21_Pos ) +#define EXTI_SWIER1_SWIE21 ( EXTI_SWIER1_SWIE21_Msk ) + + +#define EXTI_SWIER1_SWIE20_Pos ( 20U ) +#define EXTI_SWIER1_SWIE20_Msk ( 0x1UL << EXTI_SWIER1_SWIE20_Pos ) +#define EXTI_SWIER1_SWIE20 ( EXTI_SWIER1_SWIE20_Msk ) + + +#define EXTI_SWIER1_SWIE19_Pos ( 19U ) +#define EXTI_SWIER1_SWIE19_Msk ( 0x1UL << EXTI_SWIER1_SWIE19_Pos ) +#define EXTI_SWIER1_SWIE19 ( EXTI_SWIER1_SWIE19_Msk ) + + +#define EXTI_SWIER1_SWIE18_Pos ( 18U ) +#define EXTI_SWIER1_SWIE18_Msk ( 0x1UL << EXTI_SWIER1_SWIE18_Pos ) +#define EXTI_SWIER1_SWIE18 ( EXTI_SWIER1_SWIE18_Msk ) + + +#define EXTI_SWIER1_SWIE17_Pos ( 17U ) +#define EXTI_SWIER1_SWIE17_Msk ( 0x1UL << EXTI_SWIER1_SWIE17_Pos ) +#define EXTI_SWIER1_SWIE17 ( EXTI_SWIER1_SWIE17_Msk ) + + +#define EXTI_SWIER1_SWIE16_Pos ( 16U ) +#define EXTI_SWIER1_SWIE16_Msk ( 0x1UL << EXTI_SWIER1_SWIE16_Pos ) +#define EXTI_SWIER1_SWIE16 ( EXTI_SWIER1_SWIE16_Msk ) + + +#define EXTI_SWIER1_SWIE15_Pos ( 15U ) +#define EXTI_SWIER1_SWIE15_Msk ( 0x1UL << EXTI_SWIER1_SWIE15_Pos ) +#define EXTI_SWIER1_SWIE15 ( EXTI_SWIER1_SWIE15_Msk ) + + +#define EXTI_SWIER1_SWIE14_Pos ( 14U ) +#define EXTI_SWIER1_SWIE14_Msk ( 0x1UL << EXTI_SWIER1_SWIE14_Pos ) +#define EXTI_SWIER1_SWIE14 ( EXTI_SWIER1_SWIE14_Msk ) + + +#define EXTI_SWIER1_SWIE13_Pos ( 13U ) +#define EXTI_SWIER1_SWIE13_Msk ( 0x1UL << EXTI_SWIER1_SWIE13_Pos ) +#define EXTI_SWIER1_SWIE13 ( EXTI_SWIER1_SWIE13_Msk ) + + +#define EXTI_SWIER1_SWIE12_Pos ( 12U ) +#define EXTI_SWIER1_SWIE12_Msk ( 0x1UL << EXTI_SWIER1_SWIE12_Pos ) +#define EXTI_SWIER1_SWIE12 ( EXTI_SWIER1_SWIE12_Msk ) + + +#define EXTI_SWIER1_SWIE11_Pos ( 11U ) +#define EXTI_SWIER1_SWIE11_Msk ( 0x1UL << EXTI_SWIER1_SWIE11_Pos ) +#define EXTI_SWIER1_SWIE11 ( EXTI_SWIER1_SWIE11_Msk ) + + +#define EXTI_SWIER1_SWIE10_Pos ( 10U ) +#define EXTI_SWIER1_SWIE10_Msk ( 0x1UL << EXTI_SWIER1_SWIE10_Pos ) +#define EXTI_SWIER1_SWIE10 ( EXTI_SWIER1_SWIE10_Msk ) + + +#define EXTI_SWIER1_SWIE9_Pos ( 9U ) +#define EXTI_SWIER1_SWIE9_Msk ( 0x1UL << EXTI_SWIER1_SWIE9_Pos ) +#define EXTI_SWIER1_SWIE9 ( EXTI_SWIER1_SWIE9_Msk ) + + +#define EXTI_SWIER1_SWIE8_Pos ( 8U ) +#define EXTI_SWIER1_SWIE8_Msk ( 0x1UL << EXTI_SWIER1_SWIE8_Pos ) +#define EXTI_SWIER1_SWIE8 ( EXTI_SWIER1_SWIE8_Msk ) + + +#define EXTI_SWIER1_SWIE7_Pos ( 7U ) +#define EXTI_SWIER1_SWIE7_Msk ( 0x1UL << EXTI_SWIER1_SWIE7_Pos ) +#define EXTI_SWIER1_SWIE7 ( EXTI_SWIER1_SWIE7_Msk ) + + +#define EXTI_SWIER1_SWIE6_Pos ( 6U ) +#define EXTI_SWIER1_SWIE6_Msk ( 0x1UL << EXTI_SWIER1_SWIE6_Pos ) +#define EXTI_SWIER1_SWIE6 ( EXTI_SWIER1_SWIE6_Msk ) + + +#define EXTI_SWIER1_SWIE5_Pos ( 5U ) +#define EXTI_SWIER1_SWIE5_Msk ( 0x1UL << EXTI_SWIER1_SWIE5_Pos ) +#define EXTI_SWIER1_SWIE5 ( EXTI_SWIER1_SWIE5_Msk ) + + +#define EXTI_SWIER1_SWIE4_Pos ( 4U ) +#define EXTI_SWIER1_SWIE4_Msk ( 0x1UL << EXTI_SWIER1_SWIE4_Pos ) +#define EXTI_SWIER1_SWIE4 ( EXTI_SWIER1_SWIE4_Msk ) + + +#define EXTI_SWIER1_SWIE3_Pos ( 3U ) +#define EXTI_SWIER1_SWIE3_Msk ( 0x1UL << EXTI_SWIER1_SWIE3_Pos ) +#define EXTI_SWIER1_SWIE3 ( EXTI_SWIER1_SWIE3_Msk ) + + +#define EXTI_SWIER1_SWIE2_Pos ( 2U ) +#define EXTI_SWIER1_SWIE2_Msk ( 0x1UL << EXTI_SWIER1_SWIE2_Pos ) +#define EXTI_SWIER1_SWIE2 ( EXTI_SWIER1_SWIE2_Msk ) + + +#define EXTI_SWIER1_SWIE1_Pos ( 1U ) +#define EXTI_SWIER1_SWIE1_Msk ( 0x1UL << EXTI_SWIER1_SWIE1_Pos ) +#define EXTI_SWIER1_SWIE1 ( EXTI_SWIER1_SWIE1_Msk ) + + +#define EXTI_SWIER1_SWIE0_Pos ( 0U ) +#define EXTI_SWIER1_SWIE0_Msk ( 0x1UL << EXTI_SWIER1_SWIE0_Pos ) +#define EXTI_SWIER1_SWIE0 ( EXTI_SWIER1_SWIE0_Msk ) + + + +/*************** Bits definition for EXTI_SWIER2 **********************/ + +#define EXTI_SWIER2_SWIE34_Pos ( 2U ) +#define EXTI_SWIER2_SWIE34_Msk ( 0x1UL << EXTI_SWIER2_SWIE34_Pos ) +#define EXTI_SWIER2_SWIE34 ( EXTI_SWIER2_SWIE34_Msk ) + + +#define EXTI_SWIER2_SWIE33_Pos ( 1U ) +#define EXTI_SWIER2_SWIE33_Msk ( 0x1UL << EXTI_SWIER2_SWIE33_Pos ) +#define EXTI_SWIER2_SWIE33 ( EXTI_SWIER2_SWIE33_Msk ) + + +#define EXTI_SWIER2_SWIE32_Pos ( 0U ) +#define EXTI_SWIER2_SWIE32_Msk ( 0x1UL << EXTI_SWIER2_SWIE32_Pos ) +#define EXTI_SWIER2_SWIE32 ( EXTI_SWIER2_SWIE32_Msk ) + + + +/*************** Bits definition for EXTI_PDR1 **********************/ + +#define EXTI_PDR1_PD31_Pos ( 31U ) +#define EXTI_PDR1_PD31_Msk ( 0x1UL << EXTI_PDR1_PD31_Pos ) +#define EXTI_PDR1_PD31 ( EXTI_PDR1_PD31_Msk ) + + +#define EXTI_PDR1_PD30_Pos ( 30U ) +#define EXTI_PDR1_PD30_Msk ( 0x1UL << EXTI_PDR1_PD30_Pos ) +#define EXTI_PDR1_PD30 ( EXTI_PDR1_PD30_Msk ) + + +#define EXTI_PDR1_PD29_Pos ( 29U ) +#define EXTI_PDR1_PD29_Msk ( 0x1UL << EXTI_PDR1_PD29_Pos ) +#define EXTI_PDR1_PD29 ( EXTI_PDR1_PD29_Msk ) + + +#define EXTI_PDR1_PD28_Pos ( 28U ) +#define EXTI_PDR1_PD28_Msk ( 0x1UL << EXTI_PDR1_PD28_Pos ) +#define EXTI_PDR1_PD28 ( EXTI_PDR1_PD28_Msk ) + + +#define EXTI_PDR1_PD27_Pos ( 27U ) +#define EXTI_PDR1_PD27_Msk ( 0x1UL << EXTI_PDR1_PD27_Pos ) +#define EXTI_PDR1_PD27 ( EXTI_PDR1_PD27_Msk ) + + +#define EXTI_PDR1_PD26_Pos ( 26U ) +#define EXTI_PDR1_PD26_Msk ( 0x1UL << EXTI_PDR1_PD26_Pos ) +#define EXTI_PDR1_PD26 ( EXTI_PDR1_PD26_Msk ) + + +#define EXTI_PDR1_PD25_Pos ( 25U ) +#define EXTI_PDR1_PD25_Msk ( 0x1UL << EXTI_PDR1_PD25_Pos ) +#define EXTI_PDR1_PD25 ( EXTI_PDR1_PD25_Msk ) + + +#define EXTI_PDR1_PD24_Pos ( 24U ) +#define EXTI_PDR1_PD24_Msk ( 0x1UL << EXTI_PDR1_PD24_Pos ) +#define EXTI_PDR1_PD24 ( EXTI_PDR1_PD24_Msk ) + + +#define EXTI_PDR1_PD23_Pos ( 23U ) +#define EXTI_PDR1_PD23_Msk ( 0x1UL << EXTI_PDR1_PD23_Pos ) +#define EXTI_PDR1_PD23 ( EXTI_PDR1_PD23_Msk ) + + +#define EXTI_PDR1_PD22_Pos ( 22U ) +#define EXTI_PDR1_PD22_Msk ( 0x1UL << EXTI_PDR1_PD22_Pos ) +#define EXTI_PDR1_PD22 ( EXTI_PDR1_PD22_Msk ) + + +#define EXTI_PDR1_PD21_Pos ( 21U ) +#define EXTI_PDR1_PD21_Msk ( 0x1UL << EXTI_PDR1_PD21_Pos ) +#define EXTI_PDR1_PD21 ( EXTI_PDR1_PD21_Msk ) + + +#define EXTI_PDR1_PD20_Pos ( 20U ) +#define EXTI_PDR1_PD20_Msk ( 0x1UL << EXTI_PDR1_PD20_Pos ) +#define EXTI_PDR1_PD20 ( EXTI_PDR1_PD20_Msk ) + + +#define EXTI_PDR1_PD19_Pos ( 19U ) +#define EXTI_PDR1_PD19_Msk ( 0x1UL << EXTI_PDR1_PD19_Pos ) +#define EXTI_PDR1_PD19 ( EXTI_PDR1_PD19_Msk ) + + +#define EXTI_PDR1_PD18_Pos ( 18U ) +#define EXTI_PDR1_PD18_Msk ( 0x1UL << EXTI_PDR1_PD18_Pos ) +#define EXTI_PDR1_PD18 ( EXTI_PDR1_PD18_Msk ) + + +#define EXTI_PDR1_PD17_Pos ( 17U ) +#define EXTI_PDR1_PD17_Msk ( 0x1UL << EXTI_PDR1_PD17_Pos ) +#define EXTI_PDR1_PD17 ( EXTI_PDR1_PD17_Msk ) + + +#define EXTI_PDR1_PD16_Pos ( 16U ) +#define EXTI_PDR1_PD16_Msk ( 0x1UL << EXTI_PDR1_PD16_Pos ) +#define EXTI_PDR1_PD16 ( EXTI_PDR1_PD16_Msk ) + + +#define EXTI_PDR1_PD15_Pos ( 15U ) +#define EXTI_PDR1_PD15_Msk ( 0x1UL << EXTI_PDR1_PD15_Pos ) +#define EXTI_PDR1_PD15 ( EXTI_PDR1_PD15_Msk ) + + +#define EXTI_PDR1_PD14_Pos ( 14U ) +#define EXTI_PDR1_PD14_Msk ( 0x1UL << EXTI_PDR1_PD14_Pos ) +#define EXTI_PDR1_PD14 ( EXTI_PDR1_PD14_Msk ) + + +#define EXTI_PDR1_PD13_Pos ( 13U ) +#define EXTI_PDR1_PD13_Msk ( 0x1UL << EXTI_PDR1_PD13_Pos ) +#define EXTI_PDR1_PD13 ( EXTI_PDR1_PD13_Msk ) + + +#define EXTI_PDR1_PD12_Pos ( 12U ) +#define EXTI_PDR1_PD12_Msk ( 0x1UL << EXTI_PDR1_PD12_Pos ) +#define EXTI_PDR1_PD12 ( EXTI_PDR1_PD12_Msk ) + + +#define EXTI_PDR1_PD11_Pos ( 11U ) +#define EXTI_PDR1_PD11_Msk ( 0x1UL << EXTI_PDR1_PD11_Pos ) +#define EXTI_PDR1_PD11 ( EXTI_PDR1_PD11_Msk ) + + +#define EXTI_PDR1_PD10_Pos ( 10U ) +#define EXTI_PDR1_PD10_Msk ( 0x1UL << EXTI_PDR1_PD10_Pos ) +#define EXTI_PDR1_PD10 ( EXTI_PDR1_PD10_Msk ) + + +#define EXTI_PDR1_PD9_Pos ( 9U ) +#define EXTI_PDR1_PD9_Msk ( 0x1UL << EXTI_PDR1_PD9_Pos ) +#define EXTI_PDR1_PD9 ( EXTI_PDR1_PD9_Msk ) + + +#define EXTI_PDR1_PD8_Pos ( 8U ) +#define EXTI_PDR1_PD8_Msk ( 0x1UL << EXTI_PDR1_PD8_Pos ) +#define EXTI_PDR1_PD8 ( EXTI_PDR1_PD8_Msk ) + + +#define EXTI_PDR1_PD7_Pos ( 7U ) +#define EXTI_PDR1_PD7_Msk ( 0x1UL << EXTI_PDR1_PD7_Pos ) +#define EXTI_PDR1_PD7 ( EXTI_PDR1_PD7_Msk ) + + +#define EXTI_PDR1_PD6_Pos ( 6U ) +#define EXTI_PDR1_PD6_Msk ( 0x1UL << EXTI_PDR1_PD6_Pos ) +#define EXTI_PDR1_PD6 ( EXTI_PDR1_PD6_Msk ) + + +#define EXTI_PDR1_PD5_Pos ( 5U ) +#define EXTI_PDR1_PD5_Msk ( 0x1UL << EXTI_PDR1_PD5_Pos ) +#define EXTI_PDR1_PD5 ( EXTI_PDR1_PD5_Msk ) + + +#define EXTI_PDR1_PD4_Pos ( 4U ) +#define EXTI_PDR1_PD4_Msk ( 0x1UL << EXTI_PDR1_PD4_Pos ) +#define EXTI_PDR1_PD4 ( EXTI_PDR1_PD4_Msk ) + + +#define EXTI_PDR1_PD3_Pos ( 3U ) +#define EXTI_PDR1_PD3_Msk ( 0x1UL << EXTI_PDR1_PD3_Pos ) +#define EXTI_PDR1_PD3 ( EXTI_PDR1_PD3_Msk ) + + +#define EXTI_PDR1_PD2_Pos ( 2U ) +#define EXTI_PDR1_PD2_Msk ( 0x1UL << EXTI_PDR1_PD2_Pos ) +#define EXTI_PDR1_PD2 ( EXTI_PDR1_PD2_Msk ) + + +#define EXTI_PDR1_PD1_Pos ( 1U ) +#define EXTI_PDR1_PD1_Msk ( 0x1UL << EXTI_PDR1_PD1_Pos ) +#define EXTI_PDR1_PD1 ( EXTI_PDR1_PD1_Msk ) + + +#define EXTI_PDR1_PD0_Pos ( 0U ) +#define EXTI_PDR1_PD0_Msk ( 0x1UL << EXTI_PDR1_PD0_Pos ) +#define EXTI_PDR1_PD0 ( EXTI_PDR1_PD0_Msk ) + + + +/*************** Bits definition for EXTI_PDR2 **********************/ + +#define EXTI_PDR2_PD34_Pos ( 2U ) +#define EXTI_PDR2_PD34_Msk ( 0x1UL << EXTI_PDR2_PD34_Pos ) +#define EXTI_PDR2_PD34 ( EXTI_PDR2_PD34_Msk ) + + +#define EXTI_PDR2_PD33_Pos ( 1U ) +#define EXTI_PDR2_PD33_Msk ( 0x1UL << EXTI_PDR2_PD33_Pos ) +#define EXTI_PDR2_PD33 ( EXTI_PDR2_PD33_Msk ) + + +#define EXTI_PDR2_PD32_Pos ( 0U ) +#define EXTI_PDR2_PD32_Msk ( 0x1UL << EXTI_PDR2_PD32_Pos ) +#define EXTI_PDR2_PD32 ( EXTI_PDR2_PD32_Msk ) + + + +/*************** Bits definition for EXTI_CR1 **********************/ + +#define EXTI_CR1_EXTI_5_Pos ( 25U ) +#define EXTI_CR1_EXTI_5_Msk ( 0x1FUL << EXTI_CR1_EXTI_5_Pos ) +#define EXTI_CR1_EXTI_5 ( EXTI_CR1_EXTI_5_Msk ) +#define EXTI_CR1_EXTI_5_0 ( 0x01UL << EXTI_CR1_EXTI_5_Pos ) +#define EXTI_CR1_EXTI_5_1 ( 0x02UL << EXTI_CR1_EXTI_5_Pos ) +#define EXTI_CR1_EXTI_5_2 ( 0x04UL << EXTI_CR1_EXTI_5_Pos ) +#define EXTI_CR1_EXTI_5_3 ( 0x08UL << EXTI_CR1_EXTI_5_Pos ) +#define EXTI_CR1_EXTI_5_4 ( 0x10UL << EXTI_CR1_EXTI_5_Pos ) + +#define EXTI_CR1_EXTI_4_Pos ( 20U ) +#define EXTI_CR1_EXTI_4_Msk ( 0x1FUL << EXTI_CR1_EXTI_4_Pos ) +#define EXTI_CR1_EXTI_4 ( EXTI_CR1_EXTI_4_Msk ) +#define EXTI_CR1_EXTI_4_0 ( 0x01UL << EXTI_CR1_EXTI_4_Pos ) +#define EXTI_CR1_EXTI_4_1 ( 0x02UL << EXTI_CR1_EXTI_4_Pos ) +#define EXTI_CR1_EXTI_4_2 ( 0x04UL << EXTI_CR1_EXTI_4_Pos ) +#define EXTI_CR1_EXTI_4_3 ( 0x08UL << EXTI_CR1_EXTI_4_Pos ) +#define EXTI_CR1_EXTI_4_4 ( 0x10UL << EXTI_CR1_EXTI_4_Pos ) + +#define EXTI_CR1_EXTI_3_Pos ( 15U ) +#define EXTI_CR1_EXTI_3_Msk ( 0x1FUL << EXTI_CR1_EXTI_3_Pos ) +#define EXTI_CR1_EXTI_3 ( EXTI_CR1_EXTI_3_Msk ) +#define EXTI_CR1_EXTI_3_0 ( 0x01UL << EXTI_CR1_EXTI_3_Pos ) +#define EXTI_CR1_EXTI_3_1 ( 0x02UL << EXTI_CR1_EXTI_3_Pos ) +#define EXTI_CR1_EXTI_3_2 ( 0x04UL << EXTI_CR1_EXTI_3_Pos ) +#define EXTI_CR1_EXTI_3_3 ( 0x08UL << EXTI_CR1_EXTI_3_Pos ) +#define EXTI_CR1_EXTI_3_4 ( 0x10UL << EXTI_CR1_EXTI_3_Pos ) + +#define EXTI_CR1_EXTI_2_Pos ( 10U ) +#define EXTI_CR1_EXTI_2_Msk ( 0x1FUL << EXTI_CR1_EXTI_2_Pos ) +#define EXTI_CR1_EXTI_2 ( EXTI_CR1_EXTI_2_Msk ) +#define EXTI_CR1_EXTI_2_0 ( 0x01UL << EXTI_CR1_EXTI_2_Pos ) +#define EXTI_CR1_EXTI_2_1 ( 0x02UL << EXTI_CR1_EXTI_2_Pos ) +#define EXTI_CR1_EXTI_2_2 ( 0x04UL << EXTI_CR1_EXTI_2_Pos ) +#define EXTI_CR1_EXTI_2_3 ( 0x08UL << EXTI_CR1_EXTI_2_Pos ) +#define EXTI_CR1_EXTI_2_4 ( 0x10UL << EXTI_CR1_EXTI_2_Pos ) + +#define EXTI_CR1_EXTI_1_Pos ( 5U ) +#define EXTI_CR1_EXTI_1_Msk ( 0x1FUL << EXTI_CR1_EXTI_1_Pos ) +#define EXTI_CR1_EXTI_1 ( EXTI_CR1_EXTI_1_Msk ) +#define EXTI_CR1_EXTI_1_0 ( 0x01UL << EXTI_CR1_EXTI_1_Pos ) +#define EXTI_CR1_EXTI_1_1 ( 0x02UL << EXTI_CR1_EXTI_1_Pos ) +#define EXTI_CR1_EXTI_1_2 ( 0x04UL << EXTI_CR1_EXTI_1_Pos ) +#define EXTI_CR1_EXTI_1_3 ( 0x08UL << EXTI_CR1_EXTI_1_Pos ) +#define EXTI_CR1_EXTI_1_4 ( 0x10UL << EXTI_CR1_EXTI_1_Pos ) + +#define EXTI_CR1_EXTI_0_Pos ( 0U ) +#define EXTI_CR1_EXTI_0_Msk ( 0x1FUL << EXTI_CR1_EXTI_0_Pos ) +#define EXTI_CR1_EXTI_0 ( EXTI_CR1_EXTI_0_Msk ) +#define EXTI_CR1_EXTI_0_0 ( 0x01UL << EXTI_CR1_EXTI_0_Pos ) +#define EXTI_CR1_EXTI_0_1 ( 0x02UL << EXTI_CR1_EXTI_0_Pos ) +#define EXTI_CR1_EXTI_0_2 ( 0x04UL << EXTI_CR1_EXTI_0_Pos ) +#define EXTI_CR1_EXTI_0_3 ( 0x08UL << EXTI_CR1_EXTI_0_Pos ) +#define EXTI_CR1_EXTI_0_4 ( 0x10UL << EXTI_CR1_EXTI_0_Pos ) + +/*************** Bits definition for EXTI_CR2 **********************/ + +#define EXTI_CR2_EXTI_11_Pos ( 25U ) +#define EXTI_CR2_EXTI_11_Msk ( 0x1FUL << EXTI_CR2_EXTI_11_Pos ) +#define EXTI_CR2_EXTI_11 ( EXTI_CR2_EXTI_11_Msk ) +#define EXTI_CR2_EXTI_11_0 ( 0x01UL << EXTI_CR2_EXTI_11_Pos ) +#define EXTI_CR2_EXTI_11_1 ( 0x02UL << EXTI_CR2_EXTI_11_Pos ) +#define EXTI_CR2_EXTI_11_2 ( 0x04UL << EXTI_CR2_EXTI_11_Pos ) +#define EXTI_CR2_EXTI_11_3 ( 0x08UL << EXTI_CR2_EXTI_11_Pos ) +#define EXTI_CR2_EXTI_11_4 ( 0x10UL << EXTI_CR2_EXTI_11_Pos ) + +#define EXTI_CR2_EXTI_10_Pos ( 20U ) +#define EXTI_CR2_EXTI_10_Msk ( 0x1FUL << EXTI_CR2_EXTI_10_Pos ) +#define EXTI_CR2_EXTI_10 ( EXTI_CR2_EXTI_10_Msk ) +#define EXTI_CR2_EXTI_10_0 ( 0x01UL << EXTI_CR2_EXTI_10_Pos ) +#define EXTI_CR2_EXTI_10_1 ( 0x02UL << EXTI_CR2_EXTI_10_Pos ) +#define EXTI_CR2_EXTI_10_2 ( 0x04UL << EXTI_CR2_EXTI_10_Pos ) +#define EXTI_CR2_EXTI_10_3 ( 0x08UL << EXTI_CR2_EXTI_10_Pos ) +#define EXTI_CR2_EXTI_10_4 ( 0x10UL << EXTI_CR2_EXTI_10_Pos ) + +#define EXTI_CR2_EXTI_9_Pos ( 15U ) +#define EXTI_CR2_EXTI_9_Msk ( 0x1FUL << EXTI_CR2_EXTI_9_Pos ) +#define EXTI_CR2_EXTI_9 ( EXTI_CR2_EXTI_9_Msk ) +#define EXTI_CR2_EXTI_9_0 ( 0x01UL << EXTI_CR2_EXTI_9_Pos ) +#define EXTI_CR2_EXTI_9_1 ( 0x02UL << EXTI_CR2_EXTI_9_Pos ) +#define EXTI_CR2_EXTI_9_2 ( 0x04UL << EXTI_CR2_EXTI_9_Pos ) +#define EXTI_CR2_EXTI_9_3 ( 0x08UL << EXTI_CR2_EXTI_9_Pos ) +#define EXTI_CR2_EXTI_9_4 ( 0x10UL << EXTI_CR2_EXTI_9_Pos ) + +#define EXTI_CR2_EXTI_8_Pos ( 10U ) +#define EXTI_CR2_EXTI_8_Msk ( 0x1FUL << EXTI_CR2_EXTI_8_Pos ) +#define EXTI_CR2_EXTI_8 ( EXTI_CR2_EXTI_8_Msk ) +#define EXTI_CR2_EXTI_8_0 ( 0x01UL << EXTI_CR2_EXTI_8_Pos ) +#define EXTI_CR2_EXTI_8_1 ( 0x02UL << EXTI_CR2_EXTI_8_Pos ) +#define EXTI_CR2_EXTI_8_2 ( 0x04UL << EXTI_CR2_EXTI_8_Pos ) +#define EXTI_CR2_EXTI_8_3 ( 0x08UL << EXTI_CR2_EXTI_8_Pos ) +#define EXTI_CR2_EXTI_8_4 ( 0x10UL << EXTI_CR2_EXTI_8_Pos ) + +#define EXTI_CR2_EXTI_7_Pos ( 5U ) +#define EXTI_CR2_EXTI_7_Msk ( 0x1FUL << EXTI_CR2_EXTI_7_Pos ) +#define EXTI_CR2_EXTI_7 ( EXTI_CR2_EXTI_7_Msk ) +#define EXTI_CR2_EXTI_7_0 ( 0x01UL << EXTI_CR2_EXTI_7_Pos ) +#define EXTI_CR2_EXTI_7_1 ( 0x02UL << EXTI_CR2_EXTI_7_Pos ) +#define EXTI_CR2_EXTI_7_2 ( 0x04UL << EXTI_CR2_EXTI_7_Pos ) +#define EXTI_CR2_EXTI_7_3 ( 0x08UL << EXTI_CR2_EXTI_7_Pos ) +#define EXTI_CR2_EXTI_7_4 ( 0x10UL << EXTI_CR2_EXTI_7_Pos ) + +#define EXTI_CR2_EXTI_6_Pos ( 0U ) +#define EXTI_CR2_EXTI_6_Msk ( 0x1FUL << EXTI_CR2_EXTI_6_Pos ) +#define EXTI_CR2_EXTI_6 ( EXTI_CR2_EXTI_6_Msk ) +#define EXTI_CR2_EXTI_6_0 ( 0x01UL << EXTI_CR2_EXTI_6_Pos ) +#define EXTI_CR2_EXTI_6_1 ( 0x02UL << EXTI_CR2_EXTI_6_Pos ) +#define EXTI_CR2_EXTI_6_2 ( 0x04UL << EXTI_CR2_EXTI_6_Pos ) +#define EXTI_CR2_EXTI_6_3 ( 0x08UL << EXTI_CR2_EXTI_6_Pos ) +#define EXTI_CR2_EXTI_6_4 ( 0x10UL << EXTI_CR2_EXTI_6_Pos ) + +/*************** Bits definition for EXTI_CR3 **********************/ + +#define EXTI_CR3_EXTI_15_Pos ( 15U ) +#define EXTI_CR3_EXTI_15_Msk ( 0x1FUL << EXTI_CR3_EXTI_15_Pos ) +#define EXTI_CR3_EXTI_15 ( EXTI_CR3_EXTI_15_Msk ) +#define EXTI_CR3_EXTI_15_0 ( 0x01UL << EXTI_CR3_EXTI_15_Pos ) +#define EXTI_CR3_EXTI_15_1 ( 0x02UL << EXTI_CR3_EXTI_15_Pos ) +#define EXTI_CR3_EXTI_15_2 ( 0x04UL << EXTI_CR3_EXTI_15_Pos ) +#define EXTI_CR3_EXTI_15_3 ( 0x08UL << EXTI_CR3_EXTI_15_Pos ) +#define EXTI_CR3_EXTI_15_4 ( 0x10UL << EXTI_CR3_EXTI_15_Pos ) + +#define EXTI_CR3_EXTI_14_Pos ( 10U ) +#define EXTI_CR3_EXTI_14_Msk ( 0x1FUL << EXTI_CR3_EXTI_14_Pos ) +#define EXTI_CR3_EXTI_14 ( EXTI_CR3_EXTI_14_Msk ) +#define EXTI_CR3_EXTI_14_0 ( 0x01UL << EXTI_CR3_EXTI_14_Pos ) +#define EXTI_CR3_EXTI_14_1 ( 0x02UL << EXTI_CR3_EXTI_14_Pos ) +#define EXTI_CR3_EXTI_14_2 ( 0x04UL << EXTI_CR3_EXTI_14_Pos ) +#define EXTI_CR3_EXTI_14_3 ( 0x08UL << EXTI_CR3_EXTI_14_Pos ) +#define EXTI_CR3_EXTI_14_4 ( 0x10UL << EXTI_CR3_EXTI_14_Pos ) + +#define EXTI_CR3_EXTI_13_Pos ( 5U ) +#define EXTI_CR3_EXTI_13_Msk ( 0x1FUL << EXTI_CR3_EXTI_13_Pos ) +#define EXTI_CR3_EXTI_13 ( EXTI_CR3_EXTI_13_Msk ) +#define EXTI_CR3_EXTI_13_0 ( 0x01UL << EXTI_CR3_EXTI_13_Pos ) +#define EXTI_CR3_EXTI_13_1 ( 0x02UL << EXTI_CR3_EXTI_13_Pos ) +#define EXTI_CR3_EXTI_13_2 ( 0x04UL << EXTI_CR3_EXTI_13_Pos ) +#define EXTI_CR3_EXTI_13_3 ( 0x08UL << EXTI_CR3_EXTI_13_Pos ) +#define EXTI_CR3_EXTI_13_4 ( 0x10UL << EXTI_CR3_EXTI_13_Pos ) + +#define EXTI_CR3_EXTI_12_Pos ( 0U ) +#define EXTI_CR3_EXTI_12_Msk ( 0x1FUL << EXTI_CR3_EXTI_12_Pos ) +#define EXTI_CR3_EXTI_12 ( EXTI_CR3_EXTI_12_Msk ) +#define EXTI_CR3_EXTI_12_0 ( 0x01UL << EXTI_CR3_EXTI_12_Pos ) +#define EXTI_CR3_EXTI_12_1 ( 0x02UL << EXTI_CR3_EXTI_12_Pos ) +#define EXTI_CR3_EXTI_12_2 ( 0x04UL << EXTI_CR3_EXTI_12_Pos ) +#define EXTI_CR3_EXTI_12_3 ( 0x08UL << EXTI_CR3_EXTI_12_Pos ) +#define EXTI_CR3_EXTI_12_4 ( 0x10UL << EXTI_CR3_EXTI_12_Pos ) + +/*************** Bits definition for DMA_IntStatus **********************/ + +#define DMA_INTSTATUS_INTSTATUS7_Pos ( 7U ) +#define DMA_INTSTATUS_INTSTATUS7_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS7_Pos ) +#define DMA_INTSTATUS_INTSTATUS7 ( DMA_INTSTATUS_INTSTATUS7_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS6_Pos ( 6U ) +#define DMA_INTSTATUS_INTSTATUS6_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS6_Pos ) +#define DMA_INTSTATUS_INTSTATUS6 ( DMA_INTSTATUS_INTSTATUS6_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS5_Pos ( 5U ) +#define DMA_INTSTATUS_INTSTATUS5_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS5_Pos ) +#define DMA_INTSTATUS_INTSTATUS5 ( DMA_INTSTATUS_INTSTATUS5_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS4_Pos ( 4U ) +#define DMA_INTSTATUS_INTSTATUS4_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS4_Pos ) +#define DMA_INTSTATUS_INTSTATUS4 ( DMA_INTSTATUS_INTSTATUS4_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS3_Pos ( 3U ) +#define DMA_INTSTATUS_INTSTATUS3_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS3_Pos ) +#define DMA_INTSTATUS_INTSTATUS3 ( DMA_INTSTATUS_INTSTATUS3_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS2_Pos ( 2U ) +#define DMA_INTSTATUS_INTSTATUS2_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS2_Pos ) +#define DMA_INTSTATUS_INTSTATUS2 ( DMA_INTSTATUS_INTSTATUS2_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS1_Pos ( 1U ) +#define DMA_INTSTATUS_INTSTATUS1_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS1_Pos ) +#define DMA_INTSTATUS_INTSTATUS1 ( DMA_INTSTATUS_INTSTATUS1_Msk ) + + +#define DMA_INTSTATUS_INTSTATUS0_Pos ( 0U ) +#define DMA_INTSTATUS_INTSTATUS0_Msk ( 0x1UL << DMA_INTSTATUS_INTSTATUS0_Pos ) +#define DMA_INTSTATUS_INTSTATUS0 ( DMA_INTSTATUS_INTSTATUS0_Msk ) + + + +/*************** Bits definition for DMA_IntTCStatus **********************/ + +#define DMA_INTTCSTATUS_INTHFTCSTATUS7_Pos ( 15U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS7_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS7_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS7 ( DMA_INTTCSTATUS_INTHFTCSTATUS7_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS6_Pos ( 14U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS6_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS6_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS6 ( DMA_INTTCSTATUS_INTHFTCSTATUS6_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS5_Pos ( 13U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS5_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS5_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS5 ( DMA_INTTCSTATUS_INTHFTCSTATUS5_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS4_Pos ( 12U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS4_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS4_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS4 ( DMA_INTTCSTATUS_INTHFTCSTATUS4_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS3_Pos ( 11U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS3_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS3_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS3 ( DMA_INTTCSTATUS_INTHFTCSTATUS3_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS2_Pos ( 10U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS2_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS2_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS2 ( DMA_INTTCSTATUS_INTHFTCSTATUS2_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS1_Pos ( 9U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS1_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS1_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS1 ( DMA_INTTCSTATUS_INTHFTCSTATUS1_Msk ) + + +#define DMA_INTTCSTATUS_INTHFTCSTATUS0_Pos ( 8U ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS0_Msk ( 0x1UL << DMA_INTTCSTATUS_INTHFTCSTATUS0_Pos ) +#define DMA_INTTCSTATUS_INTHFTCSTATUS0 ( DMA_INTTCSTATUS_INTHFTCSTATUS0_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS7_Pos ( 7U ) +#define DMA_INTTCSTATUS_INTTCSTATUS7_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS7_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS7 ( DMA_INTTCSTATUS_INTTCSTATUS7_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS6_Pos ( 6U ) +#define DMA_INTTCSTATUS_INTTCSTATUS6_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS6_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS6 ( DMA_INTTCSTATUS_INTTCSTATUS6_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS5_Pos ( 5U ) +#define DMA_INTTCSTATUS_INTTCSTATUS5_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS5_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS5 ( DMA_INTTCSTATUS_INTTCSTATUS5_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS4_Pos ( 4U ) +#define DMA_INTTCSTATUS_INTTCSTATUS4_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS4_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS4 ( DMA_INTTCSTATUS_INTTCSTATUS4_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS3_Pos ( 3U ) +#define DMA_INTTCSTATUS_INTTCSTATUS3_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS3_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS3 ( DMA_INTTCSTATUS_INTTCSTATUS3_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS2_Pos ( 2U ) +#define DMA_INTTCSTATUS_INTTCSTATUS2_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS2_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS2 ( DMA_INTTCSTATUS_INTTCSTATUS2_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS1_Pos ( 1U ) +#define DMA_INTTCSTATUS_INTTCSTATUS1_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS1_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS1 ( DMA_INTTCSTATUS_INTTCSTATUS1_Msk ) + + +#define DMA_INTTCSTATUS_INTTCSTATUS0_Pos ( 0U ) +#define DMA_INTTCSTATUS_INTTCSTATUS0_Msk ( 0x1UL << DMA_INTTCSTATUS_INTTCSTATUS0_Pos ) +#define DMA_INTTCSTATUS_INTTCSTATUS0 ( DMA_INTTCSTATUS_INTTCSTATUS0_Msk ) + + + +/*************** Bits definition for DMA_IntTCClr **********************/ + +#define DMA_INTTCCLR_INTHFTCCLR7_Pos ( 15U ) +#define DMA_INTTCCLR_INTHFTCCLR7_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR7_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR7 ( DMA_INTTCCLR_INTHFTCCLR7_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR6_Pos ( 14U ) +#define DMA_INTTCCLR_INTHFTCCLR6_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR6_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR6 ( DMA_INTTCCLR_INTHFTCCLR6_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR5_Pos ( 13U ) +#define DMA_INTTCCLR_INTHFTCCLR5_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR5_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR5 ( DMA_INTTCCLR_INTHFTCCLR5_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR4_Pos ( 12U ) +#define DMA_INTTCCLR_INTHFTCCLR4_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR4_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR4 ( DMA_INTTCCLR_INTHFTCCLR4_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR3_Pos ( 11U ) +#define DMA_INTTCCLR_INTHFTCCLR3_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR3_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR3 ( DMA_INTTCCLR_INTHFTCCLR3_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR2_Pos ( 10U ) +#define DMA_INTTCCLR_INTHFTCCLR2_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR2_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR2 ( DMA_INTTCCLR_INTHFTCCLR2_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR1_Pos ( 9U ) +#define DMA_INTTCCLR_INTHFTCCLR1_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR1_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR1 ( DMA_INTTCCLR_INTHFTCCLR1_Msk ) + + +#define DMA_INTTCCLR_INTHFTCCLR0_Pos ( 8U ) +#define DMA_INTTCCLR_INTHFTCCLR0_Msk ( 0x1UL << DMA_INTTCCLR_INTHFTCCLR0_Pos ) +#define DMA_INTTCCLR_INTHFTCCLR0 ( DMA_INTTCCLR_INTHFTCCLR0_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR7_Pos ( 7U ) +#define DMA_INTTCCLR_INTTCCLR7_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR7_Pos ) +#define DMA_INTTCCLR_INTTCCLR7 ( DMA_INTTCCLR_INTTCCLR7_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR6_Pos ( 6U ) +#define DMA_INTTCCLR_INTTCCLR6_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR6_Pos ) +#define DMA_INTTCCLR_INTTCCLR6 ( DMA_INTTCCLR_INTTCCLR6_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR5_Pos ( 5U ) +#define DMA_INTTCCLR_INTTCCLR5_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR5_Pos ) +#define DMA_INTTCCLR_INTTCCLR5 ( DMA_INTTCCLR_INTTCCLR5_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR4_Pos ( 4U ) +#define DMA_INTTCCLR_INTTCCLR4_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR4_Pos ) +#define DMA_INTTCCLR_INTTCCLR4 ( DMA_INTTCCLR_INTTCCLR4_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR3_Pos ( 3U ) +#define DMA_INTTCCLR_INTTCCLR3_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR3_Pos ) +#define DMA_INTTCCLR_INTTCCLR3 ( DMA_INTTCCLR_INTTCCLR3_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR2_Pos ( 2U ) +#define DMA_INTTCCLR_INTTCCLR2_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR2_Pos ) +#define DMA_INTTCCLR_INTTCCLR2 ( DMA_INTTCCLR_INTTCCLR2_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR1_Pos ( 1U ) +#define DMA_INTTCCLR_INTTCCLR1_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR1_Pos ) +#define DMA_INTTCCLR_INTTCCLR1 ( DMA_INTTCCLR_INTTCCLR1_Msk ) + + +#define DMA_INTTCCLR_INTTCCLR0_Pos ( 0U ) +#define DMA_INTTCCLR_INTTCCLR0_Msk ( 0x1UL << DMA_INTTCCLR_INTTCCLR0_Pos ) +#define DMA_INTTCCLR_INTTCCLR0 ( DMA_INTTCCLR_INTTCCLR0_Msk ) + + + +/*************** Bits definition for DMA_IntErrStatus **********************/ + +#define DMA_INTERRSTATUS_INTERRSTATUS7_Pos ( 7U ) +#define DMA_INTERRSTATUS_INTERRSTATUS7_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS7_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS7 ( DMA_INTERRSTATUS_INTERRSTATUS7_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS6_Pos ( 6U ) +#define DMA_INTERRSTATUS_INTERRSTATUS6_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS6_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS6 ( DMA_INTERRSTATUS_INTERRSTATUS6_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS5_Pos ( 5U ) +#define DMA_INTERRSTATUS_INTERRSTATUS5_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS5_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS5 ( DMA_INTERRSTATUS_INTERRSTATUS5_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS4_Pos ( 4U ) +#define DMA_INTERRSTATUS_INTERRSTATUS4_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS4_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS4 ( DMA_INTERRSTATUS_INTERRSTATUS4_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS3_Pos ( 3U ) +#define DMA_INTERRSTATUS_INTERRSTATUS3_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS3_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS3 ( DMA_INTERRSTATUS_INTERRSTATUS3_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS2_Pos ( 2U ) +#define DMA_INTERRSTATUS_INTERRSTATUS2_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS2_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS2 ( DMA_INTERRSTATUS_INTERRSTATUS2_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS1_Pos ( 1U ) +#define DMA_INTERRSTATUS_INTERRSTATUS1_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS1_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS1 ( DMA_INTERRSTATUS_INTERRSTATUS1_Msk ) + + +#define DMA_INTERRSTATUS_INTERRSTATUS0_Pos ( 0U ) +#define DMA_INTERRSTATUS_INTERRSTATUS0_Msk ( 0x1UL << DMA_INTERRSTATUS_INTERRSTATUS0_Pos ) +#define DMA_INTERRSTATUS_INTERRSTATUS0 ( DMA_INTERRSTATUS_INTERRSTATUS0_Msk ) + + + +/*************** Bits definition for DMA_IntErrClr **********************/ + +#define DMA_INTERRCLR_INTERRCLR7_Pos ( 7U ) +#define DMA_INTERRCLR_INTERRCLR7_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR7_Pos ) +#define DMA_INTERRCLR_INTERRCLR7 ( DMA_INTERRCLR_INTERRCLR7_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR6_Pos ( 6U ) +#define DMA_INTERRCLR_INTERRCLR6_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR6_Pos ) +#define DMA_INTERRCLR_INTERRCLR6 ( DMA_INTERRCLR_INTERRCLR6_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR5_Pos ( 5U ) +#define DMA_INTERRCLR_INTERRCLR5_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR5_Pos ) +#define DMA_INTERRCLR_INTERRCLR5 ( DMA_INTERRCLR_INTERRCLR5_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR4_Pos ( 4U ) +#define DMA_INTERRCLR_INTERRCLR4_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR4_Pos ) +#define DMA_INTERRCLR_INTERRCLR4 ( DMA_INTERRCLR_INTERRCLR4_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR3_Pos ( 3U ) +#define DMA_INTERRCLR_INTERRCLR3_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR3_Pos ) +#define DMA_INTERRCLR_INTERRCLR3 ( DMA_INTERRCLR_INTERRCLR3_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR2_Pos ( 2U ) +#define DMA_INTERRCLR_INTERRCLR2_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR2_Pos ) +#define DMA_INTERRCLR_INTERRCLR2 ( DMA_INTERRCLR_INTERRCLR2_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR1_Pos ( 1U ) +#define DMA_INTERRCLR_INTERRCLR1_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR1_Pos ) +#define DMA_INTERRCLR_INTERRCLR1 ( DMA_INTERRCLR_INTERRCLR1_Msk ) + + +#define DMA_INTERRCLR_INTERRCLR0_Pos ( 0U ) +#define DMA_INTERRCLR_INTERRCLR0_Msk ( 0x1UL << DMA_INTERRCLR_INTERRCLR0_Pos ) +#define DMA_INTERRCLR_INTERRCLR0 ( DMA_INTERRCLR_INTERRCLR0_Msk ) + + + +/*************** Bits definition for DMA_RawIntTCStatus **********************/ + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS7_Pos ( 15U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS7_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS7_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS7 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS7_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS6_Pos ( 14U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS6_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS6_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS6 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS6_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS5_Pos ( 13U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS5_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS5_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS5 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS5_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS4_Pos ( 12U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS4_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS4_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS4 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS4_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS3_Pos ( 11U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS3_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS3_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS3 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS3_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS2_Pos ( 10U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS2_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS2_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS2 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS2_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS1_Pos ( 9U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS1_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS1_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS1 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS1_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS0_Pos ( 8U ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS0_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS0_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS0 ( DMA_RAWINTTCSTATUS_RAWINTHFTCSTATUS0_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS7_Pos ( 7U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS7_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS7_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS7 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS7_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS6_Pos ( 6U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS6_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS6_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS6 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS6_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS5_Pos ( 5U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS5_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS5_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS5 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS5_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS4_Pos ( 4U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS4_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS4_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS4 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS4_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS3_Pos ( 3U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS3_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS3_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS3 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS3_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS2_Pos ( 2U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS2_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS2_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS2 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS2_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS1_Pos ( 1U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS1_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS1_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS1 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS1_Msk ) + + +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS0_Pos ( 0U ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS0_Msk ( 0x1UL << DMA_RAWINTTCSTATUS_RAWINTTCSTATUS0_Pos ) +#define DMA_RAWINTTCSTATUS_RAWINTTCSTATUS0 ( DMA_RAWINTTCSTATUS_RAWINTTCSTATUS0_Msk ) + + + +/*************** Bits definition for DMA_RawIntErrStatus **********************/ + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS7_Pos ( 7U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS7_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS7_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS7 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS7_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS6_Pos ( 6U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS6_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS6_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS6 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS6_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS5_Pos ( 5U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS5_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS5_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS5 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS5_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS4_Pos ( 4U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS4_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS4_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS4 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS4_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS3_Pos ( 3U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS3_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS3_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS3 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS3_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS2_Pos ( 2U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS2_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS2_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS2 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS2_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS1_Pos ( 1U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS1_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS1_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS1 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS1_Msk ) + + +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS0_Pos ( 0U ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS0_Msk ( 0x1UL << DMA_RAWINTERRSTATUS_RAWINTERRSTATUS0_Pos ) +#define DMA_RAWINTERRSTATUS_RAWINTERRSTATUS0 ( DMA_RAWINTERRSTATUS_RAWINTERRSTATUS0_Msk ) + + + +/*************** Bits definition for DMA_EnChStatus **********************/ + +#define DMA_ENCHSTATUS_ENCHSTAT7_Pos ( 7U ) +#define DMA_ENCHSTATUS_ENCHSTAT7_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT7_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT7 ( DMA_ENCHSTATUS_ENCHSTAT7_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT6_Pos ( 6U ) +#define DMA_ENCHSTATUS_ENCHSTAT6_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT6_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT6 ( DMA_ENCHSTATUS_ENCHSTAT6_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT5_Pos ( 5U ) +#define DMA_ENCHSTATUS_ENCHSTAT5_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT5_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT5 ( DMA_ENCHSTATUS_ENCHSTAT5_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT4_Pos ( 4U ) +#define DMA_ENCHSTATUS_ENCHSTAT4_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT4_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT4 ( DMA_ENCHSTATUS_ENCHSTAT4_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT3_Pos ( 3U ) +#define DMA_ENCHSTATUS_ENCHSTAT3_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT3_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT3 ( DMA_ENCHSTATUS_ENCHSTAT3_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT2_Pos ( 2U ) +#define DMA_ENCHSTATUS_ENCHSTAT2_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT2_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT2 ( DMA_ENCHSTATUS_ENCHSTAT2_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT1_Pos ( 1U ) +#define DMA_ENCHSTATUS_ENCHSTAT1_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT1_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT1 ( DMA_ENCHSTATUS_ENCHSTAT1_Msk ) + + +#define DMA_ENCHSTATUS_ENCHSTAT0_Pos ( 0U ) +#define DMA_ENCHSTATUS_ENCHSTAT0_Msk ( 0x1UL << DMA_ENCHSTATUS_ENCHSTAT0_Pos ) +#define DMA_ENCHSTATUS_ENCHSTAT0 ( DMA_ENCHSTATUS_ENCHSTAT0_Msk ) + + + +/*************** Bits definition for DMA_Config **********************/ + +#define DMA_CONFIG_M2ENDIAN_Pos ( 2U ) +#define DMA_CONFIG_M2ENDIAN_Msk ( 0x1UL << DMA_CONFIG_M2ENDIAN_Pos ) +#define DMA_CONFIG_M2ENDIAN ( DMA_CONFIG_M2ENDIAN_Msk ) + +#define DMA_CONFIG_M1ENDIAN_Pos ( 1U ) +#define DMA_CONFIG_M1ENDIAN_Msk ( 0x1UL << DMA_CONFIG_M1ENDIAN_Pos ) +#define DMA_CONFIG_M1ENDIAN ( DMA_CONFIG_M1ENDIAN_Msk ) + +#define DMA_CONFIG_EN_Pos ( 0U ) +#define DMA_CONFIG_EN_Msk ( 0x1UL << DMA_CONFIG_EN_Pos ) +#define DMA_CONFIG_EN ( DMA_CONFIG_EN_Msk ) + + +/*************** Bits definition for DMA_SyncLo **********************/ + +#define DMA_SYNCLO_SYNCLO_Pos ( 0U ) +#define DMA_SYNCLO_SYNCLO_Msk ( 0xffffffffUL << DMA_SYNCLO_SYNCLO_Pos ) +#define DMA_SYNCLO_SYNCLO ( DMA_SYNCLO_SYNCLO_Msk ) + + +/*************** Bits definition for DMA_SyncHi **********************/ + +#define DMA_SYNCHI_SYNCHI_Pos ( 0U ) +#define DMA_SYNCHI_SYNCHI_Msk ( 0xffffffffUL << DMA_SYNCHI_SYNCHI_Pos ) +#define DMA_SYNCHI_SYNCHI ( DMA_SYNCHI_SYNCHI_Msk ) + + +/*************** Bits definition for DMA_CxSrcAddr **********************/ + +#define DMA_CXSRCADDR_DMA_CXSRCADDR_Pos ( 0U ) +#define DMA_CXSRCADDR_DMA_CXSRCADDR_Msk ( 0xffffffffUL << DMA_CXSRCADDR_DMA_CXSRCADDR_Pos ) +#define DMA_CXSRCADDR_DMA_CXSRCADDR ( DMA_CXSRCADDR_DMA_CXSRCADDR_Msk ) + + +/*************** Bits definition for DMA_CxDestAddr **********************/ + +#define DMA_CXDESTADDR_DMA_CXDESTADDR_Pos ( 0U ) +#define DMA_CXDESTADDR_DMA_CXDESTADDR_Msk ( 0xffffffffUL << DMA_CXDESTADDR_DMA_CXDESTADDR_Pos ) +#define DMA_CXDESTADDR_DMA_CXDESTADDR ( DMA_CXDESTADDR_DMA_CXDESTADDR_Msk ) + + +/*************** Bits definition for DMA_CxLLI **********************/ + +#define DMA_CXLLI_LLI_Pos ( 2U ) +#define DMA_CXLLI_LLI_Msk ( 0x3fffffffUL << DMA_CXLLI_LLI_Pos ) +#define DMA_CXLLI_LLI ( DMA_CXLLI_LLI_Msk ) + +#define DMA_CXLLI_LM_Pos ( 0U ) +#define DMA_CXLLI_LM_Msk ( 0x1UL << DMA_CXLLI_LM_Pos ) +#define DMA_CXLLI_LM ( DMA_CXLLI_LM_Msk ) + + +/*************** Bits definition for DMA_CxCtrl **********************/ + +#define DMA_CXCTRL_RITEN_Pos ( 31U ) +#define DMA_CXCTRL_RITEN_Msk ( 0x1UL << DMA_CXCTRL_RITEN_Pos ) +#define DMA_CXCTRL_RITEN ( DMA_CXCTRL_RITEN_Msk ) + +#define DMA_CXCTRL_DIORDD_Pos ( 28U ) +#define DMA_CXCTRL_DIORDD_Msk ( 0x3UL << DMA_CXCTRL_DIORDD_Pos ) +#define DMA_CXCTRL_DIORDD ( DMA_CXCTRL_DIORDD_Msk ) +#define DMA_CXCTRL_DIORDD_0 ( 0x1UL << DMA_CXCTRL_DIORDD_Pos ) +#define DMA_CXCTRL_DIORDD_1 ( 0x2UL << DMA_CXCTRL_DIORDD_Pos ) + +#define DMA_CXCTRL_SIORSD_Pos ( 26U ) +#define DMA_CXCTRL_SIORSD_Msk ( 0x3UL << DMA_CXCTRL_SIORSD_Pos ) +#define DMA_CXCTRL_SIORSD ( DMA_CXCTRL_SIORSD_Msk ) +#define DMA_CXCTRL_SIORSD_0 ( 0x1UL << DMA_CXCTRL_SIORSD_Pos ) +#define DMA_CXCTRL_SIORSD_1 ( 0x2UL << DMA_CXCTRL_SIORSD_Pos ) + +#define DMA_CXCTRL_DWIDTH_Pos ( 24U ) +#define DMA_CXCTRL_DWIDTH_Msk ( 0x3UL << DMA_CXCTRL_DWIDTH_Pos ) +#define DMA_CXCTRL_DWIDTH ( DMA_CXCTRL_DWIDTH_Msk ) +#define DMA_CXCTRL_DWIDTH_0 ( 0x1UL << DMA_CXCTRL_DWIDTH_Pos ) +#define DMA_CXCTRL_DWIDTH_1 ( 0x2UL << DMA_CXCTRL_DWIDTH_Pos ) + +#define DMA_CXCTRL_SWIDTH_Pos ( 22U ) +#define DMA_CXCTRL_SWIDTH_Msk ( 0x3UL << DMA_CXCTRL_SWIDTH_Pos ) +#define DMA_CXCTRL_SWIDTH ( DMA_CXCTRL_SWIDTH_Msk ) +#define DMA_CXCTRL_SWIDTH_0 ( 0x1UL << DMA_CXCTRL_SWIDTH_Pos ) +#define DMA_CXCTRL_SWIDTH_1 ( 0x2UL << DMA_CXCTRL_SWIDTH_Pos ) + +#define DMA_CXCTRL_DBSIZE_Pos ( 19U ) +#define DMA_CXCTRL_DBSIZE_Msk ( 0x7UL << DMA_CXCTRL_DBSIZE_Pos ) +#define DMA_CXCTRL_DBSIZE ( DMA_CXCTRL_DBSIZE_Msk ) +#define DMA_CXCTRL_DBSIZE_0 ( 0x1UL << DMA_CXCTRL_DBSIZE_Pos ) +#define DMA_CXCTRL_DBSIZE_1 ( 0x2UL << DMA_CXCTRL_DBSIZE_Pos ) +#define DMA_CXCTRL_DBSIZE_2 ( 0x4UL << DMA_CXCTRL_DBSIZE_Pos ) + +#define DMA_CXCTRL_SBSIZE_Pos ( 16U ) +#define DMA_CXCTRL_SBSIZE_Msk ( 0x7UL << DMA_CXCTRL_SBSIZE_Pos ) +#define DMA_CXCTRL_SBSIZE ( DMA_CXCTRL_SBSIZE_Msk ) +#define DMA_CXCTRL_SBSIZE_0 ( 0x1UL << DMA_CXCTRL_SBSIZE_Pos ) +#define DMA_CXCTRL_SBSIZE_1 ( 0x2UL << DMA_CXCTRL_SBSIZE_Pos ) +#define DMA_CXCTRL_SBSIZE_2 ( 0x4UL << DMA_CXCTRL_SBSIZE_Pos ) + +#define DMA_CXCTRL_TRANSFERSIZE_Pos ( 0U ) +#define DMA_CXCTRL_TRANSFERSIZE_Msk ( 0xffffUL << DMA_CXCTRL_TRANSFERSIZE_Pos ) +#define DMA_CXCTRL_TRANSFERSIZE ( DMA_CXCTRL_TRANSFERSIZE_Msk ) + + +/*************** Bits definition for DMA_CxConfig **********************/ + +#define DMA_CXCONFIG_SRCPERIPH_Pos ( 24U ) +#define DMA_CXCONFIG_SRCPERIPH_Msk ( 0xffUL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH ( DMA_CXCONFIG_SRCPERIPH_Msk ) +#define DMA_CXCONFIG_SRCPERIPH_0 ( 0x1UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_1 ( 0x2UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_2 ( 0x4UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_3 ( 0x8UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_4 ( 0x10UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_5 ( 0x20UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_6 ( 0x40UL << DMA_CXCONFIG_SRCPERIPH_Pos ) +#define DMA_CXCONFIG_SRCPERIPH_7 ( 0x80UL << DMA_CXCONFIG_SRCPERIPH_Pos ) + +#define DMA_CXCONFIG_DESTPERIPH_Pos ( 16U ) +#define DMA_CXCONFIG_DESTPERIPH_Msk ( 0xffUL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH ( DMA_CXCONFIG_DESTPERIPH_Msk ) +#define DMA_CXCONFIG_DESTPERIPH_0 ( 0x1UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_1 ( 0x2UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_2 ( 0x4UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_3 ( 0x8UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_4 ( 0x10UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_5 ( 0x20UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_6 ( 0x40UL << DMA_CXCONFIG_DESTPERIPH_Pos ) +#define DMA_CXCONFIG_DESTPERIPH_7 ( 0x80UL << DMA_CXCONFIG_DESTPERIPH_Pos ) + +#define DMA_CXCONFIG_LOCK_Pos ( 11U ) +#define DMA_CXCONFIG_LOCK_Msk ( 0x1UL << DMA_CXCONFIG_LOCK_Pos ) +#define DMA_CXCONFIG_LOCK ( DMA_CXCONFIG_LOCK_Msk ) + +#define DMA_CXCONFIG_D_Pos ( 10U ) +#define DMA_CXCONFIG_D_Msk ( 0x1UL << DMA_CXCONFIG_D_Pos ) +#define DMA_CXCONFIG_D ( DMA_CXCONFIG_D_Msk ) + +#define DMA_CXCONFIG_S_Pos ( 9U ) +#define DMA_CXCONFIG_S_Msk ( 0x1UL << DMA_CXCONFIG_S_Pos ) +#define DMA_CXCONFIG_S ( DMA_CXCONFIG_S_Msk ) + +#define DMA_CXCONFIG_HALT_Pos ( 8U ) +#define DMA_CXCONFIG_HALT_Msk ( 0x1UL << DMA_CXCONFIG_HALT_Pos ) +#define DMA_CXCONFIG_HALT ( DMA_CXCONFIG_HALT_Msk ) + +#define DMA_CXCONFIG_ACTIVE_Pos ( 7U ) +#define DMA_CXCONFIG_ACTIVE_Msk ( 0x1UL << DMA_CXCONFIG_ACTIVE_Pos ) +#define DMA_CXCONFIG_ACTIVE ( DMA_CXCONFIG_ACTIVE_Msk ) + +#define DMA_CXCONFIG_IHFTC_Pos ( 6U ) +#define DMA_CXCONFIG_IHFTC_Msk ( 0x1UL << DMA_CXCONFIG_IHFTC_Pos ) +#define DMA_CXCONFIG_IHFTC ( DMA_CXCONFIG_IHFTC_Msk ) + +#define DMA_CXCONFIG_ITC_Pos ( 5U ) +#define DMA_CXCONFIG_ITC_Msk ( 0x1UL << DMA_CXCONFIG_ITC_Pos ) +#define DMA_CXCONFIG_ITC ( DMA_CXCONFIG_ITC_Msk ) + +#define DMA_CXCONFIG_IE_Pos ( 4U ) +#define DMA_CXCONFIG_IE_Msk ( 0x1UL << DMA_CXCONFIG_IE_Pos ) +#define DMA_CXCONFIG_IE ( DMA_CXCONFIG_IE_Msk ) + +#define DMA_CXCONFIG_FLOWCTRL_Pos ( 1U ) +#define DMA_CXCONFIG_FLOWCTRL_Msk ( 0x7UL << DMA_CXCONFIG_FLOWCTRL_Pos ) +#define DMA_CXCONFIG_FLOWCTRL ( DMA_CXCONFIG_FLOWCTRL_Msk ) +#define DMA_CXCONFIG_FLOWCTRL_0 ( 0x1UL << DMA_CXCONFIG_FLOWCTRL_Pos ) +#define DMA_CXCONFIG_FLOWCTRL_1 ( 0x2UL << DMA_CXCONFIG_FLOWCTRL_Pos ) +#define DMA_CXCONFIG_FLOWCTRL_2 ( 0x4UL << DMA_CXCONFIG_FLOWCTRL_Pos ) + +#define DMA_CXCONFIG_EN_Pos ( 0U ) +#define DMA_CXCONFIG_EN_Msk ( 0x1UL << DMA_CXCONFIG_EN_Pos ) +#define DMA_CXCONFIG_EN ( DMA_CXCONFIG_EN_Msk ) + + +/*************** Bits definition for USART_DR **********************/ + +#define USART_DR_OE_Pos ( 12U ) +#define USART_DR_OE_Msk ( 0x1UL << USART_DR_OE_Pos ) +#define USART_DR_OE ( USART_DR_OE_Msk ) + +#define USART_DR_BE_Pos ( 11U ) +#define USART_DR_BE_Msk ( 0x1UL << USART_DR_BE_Pos ) +#define USART_DR_BE ( USART_DR_BE_Msk ) + +#define USART_DR_PE_Pos ( 10U ) +#define USART_DR_PE_Msk ( 0x1UL << USART_DR_PE_Pos ) +#define USART_DR_PE ( USART_DR_PE_Msk ) + +#define USART_DR_FE_Pos ( 9U ) +#define USART_DR_FE_Msk ( 0x1UL << USART_DR_FE_Pos ) +#define USART_DR_FE ( USART_DR_FE_Msk ) + +#define USART_DR_DATA_Pos ( 0U ) +#define USART_DR_DATA_Msk ( 0x1ffUL << USART_DR_DATA_Pos ) +#define USART_DR_DATA ( USART_DR_DATA_Msk ) + + +/*************** Bits definition for USART_FR **********************/ + +#define USART_FR_BUSY_Pos ( 9U ) +#define USART_FR_BUSY_Msk ( 0x1UL << USART_FR_BUSY_Pos ) +#define USART_FR_BUSY ( USART_FR_BUSY_Msk ) + +#define USART_FR_CTS_Pos ( 8U ) +#define USART_FR_CTS_Msk ( 0x1UL << USART_FR_CTS_Pos ) +#define USART_FR_CTS ( USART_FR_CTS_Msk ) + +#define USART_FR_TXFE_Pos ( 7U ) +#define USART_FR_TXFE_Msk ( 0x1UL << USART_FR_TXFE_Pos ) +#define USART_FR_TXFE ( USART_FR_TXFE_Msk ) + +#define USART_FR_RXFF_Pos ( 6U ) +#define USART_FR_RXFF_Msk ( 0x1UL << USART_FR_RXFF_Pos ) +#define USART_FR_RXFF ( USART_FR_RXFF_Msk ) + +#define USART_FR_TXFF_Pos ( 5U ) +#define USART_FR_TXFF_Msk ( 0x1UL << USART_FR_TXFF_Pos ) +#define USART_FR_TXFF ( USART_FR_TXFF_Msk ) + +#define USART_FR_RXFE_Pos ( 4U ) +#define USART_FR_RXFE_Msk ( 0x1UL << USART_FR_RXFE_Pos ) +#define USART_FR_RXFE ( USART_FR_RXFE_Msk ) + +#define USART_FR_OE_Pos ( 3U ) +#define USART_FR_OE_Msk ( 0x1UL << USART_FR_OE_Pos ) +#define USART_FR_OE ( USART_FR_OE_Msk ) + +#define USART_FR_BE_Pos ( 2U ) +#define USART_FR_BE_Msk ( 0x1UL << USART_FR_BE_Pos ) +#define USART_FR_BE ( USART_FR_BE_Msk ) + +#define USART_FR_PE_Pos ( 1U ) +#define USART_FR_PE_Msk ( 0x1UL << USART_FR_PE_Pos ) +#define USART_FR_PE ( USART_FR_PE_Msk ) + +#define USART_FR_FE_Pos ( 0U ) +#define USART_FR_FE_Msk ( 0x1UL << USART_FR_FE_Pos ) +#define USART_FR_FE ( USART_FR_FE_Msk ) + + +/*************** Bits definition for USART_BRR **********************/ + +#define USART_BRR_IBAUD_Pos ( 6U ) +#define USART_BRR_IBAUD_Msk ( 0xffffUL << USART_BRR_IBAUD_Pos ) +#define USART_BRR_IBAUD ( USART_BRR_IBAUD_Msk ) + +#define USART_BRR_FBAUD_Pos ( 0U ) +#define USART_BRR_FBAUD_Msk ( 0x3fUL << USART_BRR_FBAUD_Pos ) +#define USART_BRR_FBAUD ( USART_BRR_FBAUD_Msk ) +#define USART_BRR_FBAUD_0 ( 0x1UL << USART_BRR_FBAUD_Pos ) +#define USART_BRR_FBAUD_1 ( 0x2UL << USART_BRR_FBAUD_Pos ) +#define USART_BRR_FBAUD_2 ( 0x4UL << USART_BRR_FBAUD_Pos ) +#define USART_BRR_FBAUD_3 ( 0x8UL << USART_BRR_FBAUD_Pos ) +#define USART_BRR_FBAUD_4 ( 0x10UL << USART_BRR_FBAUD_Pos ) +#define USART_BRR_FBAUD_5 ( 0x20UL << USART_BRR_FBAUD_Pos ) + + +/*************** Bits definition for USART_IE **********************/ + +#define USART_IE_TCI_Pos ( 15U ) +#define USART_IE_TCI_Msk ( 0x1UL << USART_IE_TCI_Pos ) +#define USART_IE_TCI ( USART_IE_TCI_Msk ) + +#define USART_IE_ABRI_Pos ( 14U ) +#define USART_IE_ABRI_Msk ( 0x1UL << USART_IE_ABRI_Pos ) +#define USART_IE_ABRI ( USART_IE_ABRI_Msk ) + +#define USART_IE_IDLEI_Pos ( 13U ) +#define USART_IE_IDLEI_Msk ( 0x1UL << USART_IE_IDLEI_Pos ) +#define USART_IE_IDLEI ( USART_IE_IDLEI_Msk ) + +#define USART_IE_BCNTI_Pos ( 12U ) +#define USART_IE_BCNTI_Msk ( 0x1UL << USART_IE_BCNTI_Pos ) +#define USART_IE_BCNTI ( USART_IE_BCNTI_Msk ) + +#define USART_IE_LBDI_Pos ( 11U ) +#define USART_IE_LBDI_Msk ( 0x1UL << USART_IE_LBDI_Pos ) +#define USART_IE_LBDI ( USART_IE_LBDI_Msk ) + +#define USART_IE_OEI_Pos ( 10U ) +#define USART_IE_OEI_Msk ( 0x1UL << USART_IE_OEI_Pos ) +#define USART_IE_OEI ( USART_IE_OEI_Msk ) + +#define USART_IE_BEI_Pos ( 9U ) +#define USART_IE_BEI_Msk ( 0x1UL << USART_IE_BEI_Pos ) +#define USART_IE_BEI ( USART_IE_BEI_Msk ) + +#define USART_IE_PEI_Pos ( 8U ) +#define USART_IE_PEI_Msk ( 0x1UL << USART_IE_PEI_Pos ) +#define USART_IE_PEI ( USART_IE_PEI_Msk ) + +#define USART_IE_FEI_Pos ( 7U ) +#define USART_IE_FEI_Msk ( 0x1UL << USART_IE_FEI_Pos ) +#define USART_IE_FEI ( USART_IE_FEI_Msk ) + +#define USART_IE_TXI_Pos ( 5U ) +#define USART_IE_TXI_Msk ( 0x1UL << USART_IE_TXI_Pos ) +#define USART_IE_TXI ( USART_IE_TXI_Msk ) + +#define USART_IE_RXI_Pos ( 4U ) +#define USART_IE_RXI_Msk ( 0x1UL << USART_IE_RXI_Pos ) +#define USART_IE_RXI ( USART_IE_RXI_Msk ) + + +/*************** Bits definition for USART_ISR **********************/ + +#define USART_ISR_TCI_Pos ( 15U ) +#define USART_ISR_TCI_Msk ( 0x1UL << USART_ISR_TCI_Pos ) +#define USART_ISR_TCI ( USART_ISR_TCI_Msk ) + +#define USART_ISR_ABRI_Pos ( 14U ) +#define USART_ISR_ABRI_Msk ( 0x1UL << USART_ISR_ABRI_Pos ) +#define USART_ISR_ABRI ( USART_ISR_ABRI_Msk ) + +#define USART_ISR_IDLEI_Pos ( 13U ) +#define USART_ISR_IDLEI_Msk ( 0x1UL << USART_ISR_IDLEI_Pos ) +#define USART_ISR_IDLEI ( USART_ISR_IDLEI_Msk ) + +#define USART_ISR_BCNTI_Pos ( 12U ) +#define USART_ISR_BCNTI_Msk ( 0x1UL << USART_ISR_BCNTI_Pos ) +#define USART_ISR_BCNTI ( USART_ISR_BCNTI_Msk ) + +#define USART_ISR_LBDI_Pos ( 11U ) +#define USART_ISR_LBDI_Msk ( 0x1UL << USART_ISR_LBDI_Pos ) +#define USART_ISR_LBDI ( USART_ISR_LBDI_Msk ) + +#define USART_ISR_OEI_Pos ( 10U ) +#define USART_ISR_OEI_Msk ( 0x1UL << USART_ISR_OEI_Pos ) +#define USART_ISR_OEI ( USART_ISR_OEI_Msk ) + +#define USART_ISR_BEI_Pos ( 9U ) +#define USART_ISR_BEI_Msk ( 0x1UL << USART_ISR_BEI_Pos ) +#define USART_ISR_BEI ( USART_ISR_BEI_Msk ) + +#define USART_ISR_PEI_Pos ( 8U ) +#define USART_ISR_PEI_Msk ( 0x1UL << USART_ISR_PEI_Pos ) +#define USART_ISR_PEI ( USART_ISR_PEI_Msk ) + +#define USART_ISR_FEI_Pos ( 7U ) +#define USART_ISR_FEI_Msk ( 0x1UL << USART_ISR_FEI_Pos ) +#define USART_ISR_FEI ( USART_ISR_FEI_Msk ) + +#define USART_ISR_TXI_Pos ( 5U ) +#define USART_ISR_TXI_Msk ( 0x1UL << USART_ISR_TXI_Pos ) +#define USART_ISR_TXI ( USART_ISR_TXI_Msk ) + +#define USART_ISR_RXI_Pos ( 4U ) +#define USART_ISR_RXI_Msk ( 0x1UL << USART_ISR_RXI_Pos ) +#define USART_ISR_RXI ( USART_ISR_RXI_Msk ) + + +/*************** Bits definition for USART_CR1 **********************/ + +#define USART_CR1_CTSEN_Pos ( 15U ) +#define USART_CR1_CTSEN_Msk ( 0x1UL << USART_CR1_CTSEN_Pos ) +#define USART_CR1_CTSEN ( USART_CR1_CTSEN_Msk ) + +#define USART_CR1_RTSEN_Pos ( 14U ) +#define USART_CR1_RTSEN_Msk ( 0x1UL << USART_CR1_RTSEN_Pos ) +#define USART_CR1_RTSEN ( USART_CR1_RTSEN_Msk ) + +#define USART_CR1_RTS_Pos ( 11U ) +#define USART_CR1_RTS_Msk ( 0x1UL << USART_CR1_RTS_Pos ) +#define USART_CR1_RTS ( USART_CR1_RTS_Msk ) + +#define USART_CR1_RXE_Pos ( 9U ) +#define USART_CR1_RXE_Msk ( 0x1UL << USART_CR1_RXE_Pos ) +#define USART_CR1_RXE ( USART_CR1_RXE_Msk ) + +#define USART_CR1_TXE_Pos ( 8U ) +#define USART_CR1_TXE_Msk ( 0x1UL << USART_CR1_TXE_Pos ) +#define USART_CR1_TXE ( USART_CR1_TXE_Msk ) + +#define USART_CR1_DMAONERR_Pos ( 5U ) +#define USART_CR1_DMAONERR_Msk ( 0x1UL << USART_CR1_DMAONERR_Pos ) +#define USART_CR1_DMAONERR ( USART_CR1_DMAONERR_Msk ) + +#define USART_CR1_TXDMAE_Pos ( 4U ) +#define USART_CR1_TXDMAE_Msk ( 0x1UL << USART_CR1_TXDMAE_Pos ) +#define USART_CR1_TXDMAE ( USART_CR1_TXDMAE_Msk ) + +#define USART_CR1_RXDMAE_Pos ( 3U ) +#define USART_CR1_RXDMAE_Msk ( 0x1UL << USART_CR1_RXDMAE_Pos ) +#define USART_CR1_RXDMAE ( USART_CR1_RXDMAE_Msk ) + +#define USART_CR1_SIRLP_Pos ( 2U ) +#define USART_CR1_SIRLP_Msk ( 0x1UL << USART_CR1_SIRLP_Pos ) +#define USART_CR1_SIRLP ( USART_CR1_SIRLP_Msk ) + +#define USART_CR1_SIREN_Pos ( 1U ) +#define USART_CR1_SIREN_Msk ( 0x1UL << USART_CR1_SIREN_Pos ) +#define USART_CR1_SIREN ( USART_CR1_SIREN_Msk ) + +#define USART_CR1_USARTEN_Pos ( 0U ) +#define USART_CR1_USARTEN_Msk ( 0x1UL << USART_CR1_USARTEN_Pos ) +#define USART_CR1_USARTEN ( USART_CR1_USARTEN_Msk ) + + +/*************** Bits definition for USART_CR2 **********************/ + +#define USART_CR2_ADDM7_Pos ( 18U ) +#define USART_CR2_ADDM7_Msk ( 0x1UL << USART_CR2_ADDM7_Pos ) +#define USART_CR2_ADDM7 ( USART_CR2_ADDM7_Msk ) + +#define USART_CR2_ADDR_Pos ( 11U ) +#define USART_CR2_ADDR_Msk ( 0x7fUL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR ( USART_CR2_ADDR_Msk ) +#define USART_CR2_ADDR_0 ( 0x1UL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR_1 ( 0x2UL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR_2 ( 0x4UL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR_3 ( 0x8UL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR_4 ( 0x10UL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR_5 ( 0x20UL << USART_CR2_ADDR_Pos ) +#define USART_CR2_ADDR_6 ( 0x40UL << USART_CR2_ADDR_Pos ) + +#define USART_CR2_CPOL_Pos ( 10U ) +#define USART_CR2_CPOL_Msk ( 0x1UL << USART_CR2_CPOL_Pos ) +#define USART_CR2_CPOL ( USART_CR2_CPOL_Msk ) + +#define USART_CR2_CPHA_Pos ( 9U ) +#define USART_CR2_CPHA_Msk ( 0x1UL << USART_CR2_CPHA_Pos ) +#define USART_CR2_CPHA ( USART_CR2_CPHA_Msk ) + +#define USART_CR2_LBCL_Pos ( 8U ) +#define USART_CR2_LBCL_Msk ( 0x1UL << USART_CR2_LBCL_Pos ) +#define USART_CR2_LBCL ( USART_CR2_LBCL_Msk ) + +#define USART_CR2_CLKEN_Pos ( 7U ) +#define USART_CR2_CLKEN_Msk ( 0x1UL << USART_CR2_CLKEN_Pos ) +#define USART_CR2_CLKEN ( USART_CR2_CLKEN_Msk ) + +#define USART_CR2_NACK_Pos ( 6U ) +#define USART_CR2_NACK_Msk ( 0x1UL << USART_CR2_NACK_Pos ) +#define USART_CR2_NACK ( USART_CR2_NACK_Msk ) + +#define USART_CR2_SCEN_Pos ( 5U ) +#define USART_CR2_SCEN_Msk ( 0x1UL << USART_CR2_SCEN_Pos ) +#define USART_CR2_SCEN ( USART_CR2_SCEN_Msk ) + +#define USART_CR2_ABREN_Pos ( 4U ) +#define USART_CR2_ABREN_Msk ( 0x1UL << USART_CR2_ABREN_Pos ) +#define USART_CR2_ABREN ( USART_CR2_ABREN_Msk ) + +#define USART_CR2_WAKE_Pos ( 3U ) +#define USART_CR2_WAKE_Msk ( 0x1UL << USART_CR2_WAKE_Pos ) +#define USART_CR2_WAKE ( USART_CR2_WAKE_Msk ) + +#define USART_CR2_RWU_Pos ( 2U ) +#define USART_CR2_RWU_Msk ( 0x1UL << USART_CR2_RWU_Pos ) +#define USART_CR2_RWU ( USART_CR2_RWU_Msk ) + +#define USART_CR2_HDSEL_Pos ( 0U ) +#define USART_CR2_HDSEL_Msk ( 0x1UL << USART_CR2_HDSEL_Pos ) +#define USART_CR2_HDSEL ( USART_CR2_HDSEL_Msk ) + + +/*************** Bits definition for USART_CR3 **********************/ + +#define USART_CR3_RXIFLSEL_Pos ( 13U ) +#define USART_CR3_RXIFLSEL_Msk ( 0x7UL << USART_CR3_RXIFLSEL_Pos ) +#define USART_CR3_RXIFLSEL ( USART_CR3_RXIFLSEL_Msk ) +#define USART_CR3_RXIFLSEL_0 ( 0x1UL << USART_CR3_RXIFLSEL_Pos ) +#define USART_CR3_RXIFLSEL_1 ( 0x2UL << USART_CR3_RXIFLSEL_Pos ) +#define USART_CR3_RXIFLSEL_2 ( 0x4UL << USART_CR3_RXIFLSEL_Pos ) + +#define USART_CR3_TXIFLSEL_Pos ( 10U ) +#define USART_CR3_TXIFLSEL_Msk ( 0x7UL << USART_CR3_TXIFLSEL_Pos ) +#define USART_CR3_TXIFLSEL ( USART_CR3_TXIFLSEL_Msk ) +#define USART_CR3_TXIFLSEL_0 ( 0x1UL << USART_CR3_TXIFLSEL_Pos ) +#define USART_CR3_TXIFLSEL_1 ( 0x2UL << USART_CR3_TXIFLSEL_Pos ) +#define USART_CR3_TXIFLSEL_2 ( 0x4UL << USART_CR3_TXIFLSEL_Pos ) + +#define USART_CR3_SPS_Pos ( 9U ) +#define USART_CR3_SPS_Msk ( 0x1UL << USART_CR3_SPS_Pos ) +#define USART_CR3_SPS ( USART_CR3_SPS_Msk ) + +#define USART_CR3_WLEN_Pos ( 6U ) +#define USART_CR3_WLEN_Msk ( 0x7UL << USART_CR3_WLEN_Pos ) +#define USART_CR3_WLEN ( USART_CR3_WLEN_Msk ) +#define USART_CR3_WLEN_0 ( 0x1UL << USART_CR3_WLEN_Pos ) +#define USART_CR3_WLEN_1 ( 0x2UL << USART_CR3_WLEN_Pos ) +#define USART_CR3_WLEN_2 ( 0x4UL << USART_CR3_WLEN_Pos ) + +#define USART_CR3_FEN_Pos ( 5U ) +#define USART_CR3_FEN_Msk ( 0x1UL << USART_CR3_FEN_Pos ) +#define USART_CR3_FEN ( USART_CR3_FEN_Msk ) + +#define USART_CR3_STP2_Pos ( 3U ) +#define USART_CR3_STP2_Msk ( 0x1UL << USART_CR3_STP2_Pos ) +#define USART_CR3_STP2 ( USART_CR3_STP2_Msk ) + +#define USART_CR3_EPS_Pos ( 2U ) +#define USART_CR3_EPS_Msk ( 0x1UL << USART_CR3_EPS_Pos ) +#define USART_CR3_EPS ( USART_CR3_EPS_Msk ) + +#define USART_CR3_PEN_Pos ( 1U ) +#define USART_CR3_PEN_Msk ( 0x1UL << USART_CR3_PEN_Pos ) +#define USART_CR3_PEN ( USART_CR3_PEN_Msk ) + +#define USART_CR3_BRK_Pos ( 0U ) +#define USART_CR3_BRK_Msk ( 0x1UL << USART_CR3_BRK_Pos ) +#define USART_CR3_BRK ( USART_CR3_BRK_Msk ) + + +/*************** Bits definition for USART_GTPR **********************/ + +#define USART_GTPR_GT_Pos ( 8U ) +#define USART_GTPR_GT_Msk ( 0xfUL << USART_GTPR_GT_Pos ) +#define USART_GTPR_GT ( USART_GTPR_GT_Msk ) +#define USART_GTPR_GT_0 ( 0x1UL << USART_GTPR_GT_Pos ) +#define USART_GTPR_GT_1 ( 0x2UL << USART_GTPR_GT_Pos ) +#define USART_GTPR_GT_2 ( 0x4UL << USART_GTPR_GT_Pos ) +#define USART_GTPR_GT_3 ( 0x8UL << USART_GTPR_GT_Pos ) + +#define USART_GTPR_PSC_Pos ( 0U ) +#define USART_GTPR_PSC_Msk ( 0xffUL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC ( USART_GTPR_PSC_Msk ) +#define USART_GTPR_PSC_0 ( 0x1UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_1 ( 0x2UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_2 ( 0x4UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_3 ( 0x8UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_4 ( 0x10UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_5 ( 0x20UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_6 ( 0x40UL << USART_GTPR_PSC_Pos ) +#define USART_GTPR_PSC_7 ( 0x80UL << USART_GTPR_PSC_Pos ) + + +/*************** Bits definition for USART_BCNT **********************/ + +#define USART_BCNT_DEM_Pos ( 27U ) +#define USART_BCNT_DEM_Msk ( 0x1UL << USART_BCNT_DEM_Pos ) +#define USART_BCNT_DEM ( USART_BCNT_DEM_Msk ) + +#define USART_BCNT_DEP_Pos ( 26U ) +#define USART_BCNT_DEP_Msk ( 0x1UL << USART_BCNT_DEP_Pos ) +#define USART_BCNT_DEP ( USART_BCNT_DEP_Msk ) + +#define USART_BCNT_AUTO_START_EN_Pos ( 25U ) +#define USART_BCNT_AUTO_START_EN_Msk ( 0x1UL << USART_BCNT_AUTO_START_EN_Pos ) +#define USART_BCNT_AUTO_START_EN ( USART_BCNT_AUTO_START_EN_Msk ) + +#define USART_BCNT_BCNTSTART_Pos ( 24U ) +#define USART_BCNT_BCNTSTART_Msk ( 0x1UL << USART_BCNT_BCNTSTART_Pos ) +#define USART_BCNT_BCNTSTART ( USART_BCNT_BCNTSTART_Msk ) + +#define USART_BCNT_BCNTVALUE_Pos ( 0U ) +#define USART_BCNT_BCNTVALUE_Msk ( 0xffffffUL << USART_BCNT_BCNTVALUE_Pos ) +#define USART_BCNT_BCNTVALUE ( USART_BCNT_BCNTVALUE_Msk ) + +#define USART_BCNT_DEAT_Pos ( 4U ) +#define USART_BCNT_DEAT_Msk ( 0xFUL << USART_BCNT_DEAT_Pos ) +#define USART_BCNT_DEAT ( USART_BCNT_DEAT_Msk ) + +#define USART_BCNT_DEDT_Pos ( 0U ) +#define USART_BCNT_DEDT_Msk ( 0xFUL << USART_BCNT_DEDT_Pos ) +#define USART_BCNT_DEDT ( USART_BCNT_DEDT_Msk ) + + +/*************** Bits definition for SPI_TX_RX_DAT **********************/ + +#define SPI_TX_RX_DAT_DAT_Pos ( 0U ) +#define SPI_TX_RX_DAT_DAT_Msk ( 0xffUL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT ( SPI_TX_RX_DAT_DAT_Msk ) +#define SPI_TX_RX_DAT_DAT_0 ( 0x1UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_1 ( 0x2UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_2 ( 0x4UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_3 ( 0x8UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_4 ( 0x10UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_5 ( 0x20UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_6 ( 0x40UL << SPI_TX_RX_DAT_DAT_Pos ) +#define SPI_TX_RX_DAT_DAT_7 ( 0x80UL << SPI_TX_RX_DAT_DAT_Pos ) + + +/*************** Bits definition for SPI_BAUD **********************/ + +#define SPI_BAUD_DIV2_Pos ( 8U ) +#define SPI_BAUD_DIV2_Msk ( 0xffUL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2 ( SPI_BAUD_DIV2_Msk ) +#define SPI_BAUD_DIV2_0 ( 0x1UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_1 ( 0x2UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_2 ( 0x4UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_3 ( 0x8UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_4 ( 0x10UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_5 ( 0x20UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_6 ( 0x40UL << SPI_BAUD_DIV2_Pos ) +#define SPI_BAUD_DIV2_7 ( 0x80UL << SPI_BAUD_DIV2_Pos ) + +#define SPI_BAUD_DIV1_Pos ( 0U ) +#define SPI_BAUD_DIV1_Msk ( 0xffUL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1 ( SPI_BAUD_DIV1_Msk ) +#define SPI_BAUD_DIV1_0 ( 0x1UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_1 ( 0x2UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_2 ( 0x4UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_3 ( 0x8UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_4 ( 0x10UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_5 ( 0x20UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_6 ( 0x40UL << SPI_BAUD_DIV1_Pos ) +#define SPI_BAUD_DIV1_7 ( 0x80UL << SPI_BAUD_DIV1_Pos ) + + +/*************** Bits definition for SPI_CTL **********************/ + +#define SPI_CTL_SWCS_EN_Pos ( 21U ) +#define SPI_CTL_SWCS_EN_Msk ( 0x1UL << SPI_CTL_SWCS_EN_Pos ) +#define SPI_CTL_SWCS_EN ( SPI_CTL_SWCS_EN_Msk ) + +#define SPI_CTL_SWCS_Pos ( 20U ) +#define SPI_CTL_SWCS_Msk ( 0x1UL << SPI_CTL_SWCS_Pos ) +#define SPI_CTL_SWCS ( SPI_CTL_SWCS_Msk ) + +#define SPI_CTL_CS_TIME_Pos ( 11U ) +#define SPI_CTL_CS_TIME_Msk ( 0xffUL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME ( SPI_CTL_CS_TIME_Msk ) +#define SPI_CTL_CS_TIME_0 ( 0x1UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_1 ( 0x2UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_2 ( 0x4UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_3 ( 0x8UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_4 ( 0x10UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_5 ( 0x20UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_6 ( 0x40UL << SPI_CTL_CS_TIME_Pos ) +#define SPI_CTL_CS_TIME_7 ( 0x80UL << SPI_CTL_CS_TIME_Pos ) + +#define SPI_CTL_CS_FILTER_Pos ( 10U ) +#define SPI_CTL_CS_FILTER_Msk ( 0x1UL << SPI_CTL_CS_FILTER_Pos ) +#define SPI_CTL_CS_FILTER ( SPI_CTL_CS_FILTER_Msk ) + +#define SPI_CTL_CS_RST_Pos ( 9U ) +#define SPI_CTL_CS_RST_Msk ( 0x1UL << SPI_CTL_CS_RST_Pos ) +#define SPI_CTL_CS_RST ( SPI_CTL_CS_RST_Msk ) + +#define SPI_CTL_SLAVE_EN_Pos ( 8U ) +#define SPI_CTL_SLAVE_EN_Msk ( 0x1UL << SPI_CTL_SLAVE_EN_Pos ) +#define SPI_CTL_SLAVE_EN ( SPI_CTL_SLAVE_EN_Msk ) + +#define SPI_CTL_IO_MODE_Pos ( 7U ) +#define SPI_CTL_IO_MODE_Msk ( 0x1UL << SPI_CTL_IO_MODE_Pos ) +#define SPI_CTL_IO_MODE ( SPI_CTL_IO_MODE_Msk ) + +#define SPI_CTL_X_MODE_Pos ( 5U ) +#define SPI_CTL_X_MODE_Msk ( 0x3UL << SPI_CTL_X_MODE_Pos ) +#define SPI_CTL_X_MODE ( SPI_CTL_X_MODE_Msk ) +#define SPI_CTL_X_MODE_0 ( 0x1UL << SPI_CTL_X_MODE_Pos ) +#define SPI_CTL_X_MODE_1 ( 0x2UL << SPI_CTL_X_MODE_Pos ) + +#define SPI_CTL_LSB_FIRST_Pos ( 4U ) +#define SPI_CTL_LSB_FIRST_Msk ( 0x1UL << SPI_CTL_LSB_FIRST_Pos ) +#define SPI_CTL_LSB_FIRST ( SPI_CTL_LSB_FIRST_Msk ) + +#define SPI_CTL_CPOL_Pos ( 3U ) +#define SPI_CTL_CPOL_Msk ( 0x1UL << SPI_CTL_CPOL_Pos ) +#define SPI_CTL_CPOL ( SPI_CTL_CPOL_Msk ) + +#define SPI_CTL_CPHA_Pos ( 2U ) +#define SPI_CTL_CPHA_Msk ( 0x1UL << SPI_CTL_CPHA_Pos ) +#define SPI_CTL_CPHA ( SPI_CTL_CPHA_Msk ) + +#define SPI_CTL_SFILTER_Pos ( 1U ) +#define SPI_CTL_SFILTER_Msk ( 0x1UL << SPI_CTL_SFILTER_Pos ) +#define SPI_CTL_SFILTER ( SPI_CTL_SFILTER_Msk ) + +#define SPI_CTL_MST_MODE_Pos ( 0U ) +#define SPI_CTL_MST_MODE_Msk ( 0x1UL << SPI_CTL_MST_MODE_Pos ) +#define SPI_CTL_MST_MODE ( SPI_CTL_MST_MODE_Msk ) + + +/*************** Bits definition for SPI_TX_CTL **********************/ + +#define SPI_TX_CTL_DUMMY_Pos ( 8U ) +#define SPI_TX_CTL_DUMMY_Msk ( 0xffUL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY ( SPI_TX_CTL_DUMMY_Msk ) +#define SPI_TX_CTL_DUMMY_0 ( 0x1UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_1 ( 0x2UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_2 ( 0x4UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_3 ( 0x8UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_4 ( 0x10UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_5 ( 0x20UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_6 ( 0x40UL << SPI_TX_CTL_DUMMY_Pos ) +#define SPI_TX_CTL_DUMMY_7 ( 0x80UL << SPI_TX_CTL_DUMMY_Pos ) + +#define SPI_TX_CTL_DMA_LEVEL_Pos ( 4U ) +#define SPI_TX_CTL_DMA_LEVEL_Msk ( 0xfUL << SPI_TX_CTL_DMA_LEVEL_Pos ) +#define SPI_TX_CTL_DMA_LEVEL ( SPI_TX_CTL_DMA_LEVEL_Msk ) +#define SPI_TX_CTL_DMA_LEVEL_0 ( 0x1UL << SPI_TX_CTL_DMA_LEVEL_Pos ) +#define SPI_TX_CTL_DMA_LEVEL_1 ( 0x2UL << SPI_TX_CTL_DMA_LEVEL_Pos ) +#define SPI_TX_CTL_DMA_LEVEL_2 ( 0x4UL << SPI_TX_CTL_DMA_LEVEL_Pos ) +#define SPI_TX_CTL_DMA_LEVEL_3 ( 0x8UL << SPI_TX_CTL_DMA_LEVEL_Pos ) + +#define SPI_TX_CTL_DMA_REQ_EN_Pos ( 3U ) +#define SPI_TX_CTL_DMA_REQ_EN_Msk ( 0x1UL << SPI_TX_CTL_DMA_REQ_EN_Pos ) +#define SPI_TX_CTL_DMA_REQ_EN ( SPI_TX_CTL_DMA_REQ_EN_Msk ) + +#define SPI_TX_CTL_MODE_Pos ( 2U ) +#define SPI_TX_CTL_MODE_Msk ( 0x1UL << SPI_TX_CTL_MODE_Pos ) +#define SPI_TX_CTL_MODE ( SPI_TX_CTL_MODE_Msk ) + +#define SPI_TX_CTL_FIFO_RESET_Pos ( 1U ) +#define SPI_TX_CTL_FIFO_RESET_Msk ( 0x1UL << SPI_TX_CTL_FIFO_RESET_Pos ) +#define SPI_TX_CTL_FIFO_RESET ( SPI_TX_CTL_FIFO_RESET_Msk ) + +#define SPI_TX_CTL_EN_Pos ( 0U ) +#define SPI_TX_CTL_EN_Msk ( 0x1UL << SPI_TX_CTL_EN_Pos ) +#define SPI_TX_CTL_EN ( SPI_TX_CTL_EN_Msk ) + + +/*************** Bits definition for SPI_RX_CTL **********************/ + +#define SPI_RX_CTL_SSHIFT_Pos ( 8U ) +#define SPI_RX_CTL_SSHIFT_Msk ( 0x3UL << SPI_RX_CTL_SSHIFT_Pos ) +#define SPI_RX_CTL_SSHIFT ( SPI_RX_CTL_SSHIFT_Msk ) +#define SPI_RX_CTL_SSHIFT_0 ( 0x1UL << SPI_RX_CTL_SSHIFT_Pos ) +#define SPI_RX_CTL_SSHIFT_1 ( 0x2UL << SPI_RX_CTL_SSHIFT_Pos ) + +#define SPI_RX_CTL_DMA_LEVEL_Pos ( 4U ) +#define SPI_RX_CTL_DMA_LEVEL_Msk ( 0xfUL << SPI_RX_CTL_DMA_LEVEL_Pos ) +#define SPI_RX_CTL_DMA_LEVEL ( SPI_RX_CTL_DMA_LEVEL_Msk ) +#define SPI_RX_CTL_DMA_LEVEL_0 ( 0x1UL << SPI_RX_CTL_DMA_LEVEL_Pos ) +#define SPI_RX_CTL_DMA_LEVEL_1 ( 0x2UL << SPI_RX_CTL_DMA_LEVEL_Pos ) +#define SPI_RX_CTL_DMA_LEVEL_2 ( 0x4UL << SPI_RX_CTL_DMA_LEVEL_Pos ) +#define SPI_RX_CTL_DMA_LEVEL_3 ( 0x8UL << SPI_RX_CTL_DMA_LEVEL_Pos ) + +#define SPI_RX_CTL_DMA_REQ_EN_Pos ( 3U ) +#define SPI_RX_CTL_DMA_REQ_EN_Msk ( 0x1UL << SPI_RX_CTL_DMA_REQ_EN_Pos ) +#define SPI_RX_CTL_DMA_REQ_EN ( SPI_RX_CTL_DMA_REQ_EN_Msk ) + +#define SPI_RX_CTL_FIFO_RESET_Pos ( 1U ) +#define SPI_RX_CTL_FIFO_RESET_Msk ( 0x1UL << SPI_RX_CTL_FIFO_RESET_Pos ) +#define SPI_RX_CTL_FIFO_RESET ( SPI_RX_CTL_FIFO_RESET_Msk ) + +#define SPI_RX_CTL_EN_Pos ( 0U ) +#define SPI_RX_CTL_EN_Msk ( 0x1UL << SPI_RX_CTL_EN_Pos ) +#define SPI_RX_CTL_EN ( SPI_RX_CTL_EN_Msk ) + + +/*************** Bits definition for SPI_IE **********************/ + +#define SPI_IE_RX_BATCH_DONE_EN_Pos ( 15U ) +#define SPI_IE_RX_BATCH_DONE_EN_Msk ( 0x1UL << SPI_IE_RX_BATCH_DONE_EN_Pos ) +#define SPI_IE_RX_BATCH_DONE_EN ( SPI_IE_RX_BATCH_DONE_EN_Msk ) + +#define SPI_IE_TX_BATCH_DONE_EN_Pos ( 14U ) +#define SPI_IE_TX_BATCH_DONE_EN_Msk ( 0x1UL << SPI_IE_TX_BATCH_DONE_EN_Pos ) +#define SPI_IE_TX_BATCH_DONE_EN ( SPI_IE_TX_BATCH_DONE_EN_Msk ) + +#define SPI_IE_RX_FIFO_FULL_OVERFLOW_EN_Pos ( 13U ) +#define SPI_IE_RX_FIFO_FULL_OVERFLOW_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_FULL_OVERFLOW_EN_Pos ) +#define SPI_IE_RX_FIFO_FULL_OVERFLOW_EN ( SPI_IE_RX_FIFO_FULL_OVERFLOW_EN_Msk ) + +#define SPI_IE_RX_FIFO_EMPTY_OVERFLOW_EN_Pos ( 12U ) +#define SPI_IE_RX_FIFO_EMPTY_OVERFLOW_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_EMPTY_OVERFLOW_EN_Pos ) +#define SPI_IE_RX_FIFO_EMPTY_OVERFLOW_EN ( SPI_IE_RX_FIFO_EMPTY_OVERFLOW_EN_Msk ) + +#define SPI_IE_RX_FIFO_NOT_EMPTY_EN_Pos ( 11U ) +#define SPI_IE_RX_FIFO_NOT_EMPTY_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_NOT_EMPTY_EN_Pos ) +#define SPI_IE_RX_FIFO_NOT_EMPTY_EN ( SPI_IE_RX_FIFO_NOT_EMPTY_EN_Msk ) + +#define SPI_IE_CS_POS_EN_Pos ( 10U ) +#define SPI_IE_CS_POS_EN_Msk ( 0x1UL << SPI_IE_CS_POS_EN_Pos ) +#define SPI_IE_CS_POS_EN ( SPI_IE_CS_POS_EN_Msk ) + +#define SPI_IE_RX_FIFO_HALF_FULL_EN_Pos ( 9U ) +#define SPI_IE_RX_FIFO_HALF_FULL_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_HALF_FULL_EN_Pos ) +#define SPI_IE_RX_FIFO_HALF_FULL_EN ( SPI_IE_RX_FIFO_HALF_FULL_EN_Msk ) + +#define SPI_IE_RX_FIFO_HALF_EMPTY_EN_Pos ( 8U ) +#define SPI_IE_RX_FIFO_HALF_EMPTY_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_HALF_EMPTY_EN_Pos ) +#define SPI_IE_RX_FIFO_HALF_EMPTY_EN ( SPI_IE_RX_FIFO_HALF_EMPTY_EN_Msk ) + +#define SPI_IE_TX_FIFO_HALF_FULL_EN_Pos ( 7U ) +#define SPI_IE_TX_FIFO_HALF_FULL_EN_Msk ( 0x1UL << SPI_IE_TX_FIFO_HALF_FULL_EN_Pos ) +#define SPI_IE_TX_FIFO_HALF_FULL_EN ( SPI_IE_TX_FIFO_HALF_FULL_EN_Msk ) + +#define SPI_IE_TX_FIFO_HALF_EMPTY_EN_Pos ( 6U ) +#define SPI_IE_TX_FIFO_HALF_EMPTY_EN_Msk ( 0x1UL << SPI_IE_TX_FIFO_HALF_EMPTY_EN_Pos ) +#define SPI_IE_TX_FIFO_HALF_EMPTY_EN ( SPI_IE_TX_FIFO_HALF_EMPTY_EN_Msk ) + +#define SPI_IE_RX_FIFO_FULL_EN_Pos ( 5U ) +#define SPI_IE_RX_FIFO_FULL_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_FULL_EN_Pos ) +#define SPI_IE_RX_FIFO_FULL_EN ( SPI_IE_RX_FIFO_FULL_EN_Msk ) + +#define SPI_IE_RX_FIFO_EMPTY_EN_Pos ( 4U ) +#define SPI_IE_RX_FIFO_EMPTY_EN_Msk ( 0x1UL << SPI_IE_RX_FIFO_EMPTY_EN_Pos ) +#define SPI_IE_RX_FIFO_EMPTY_EN ( SPI_IE_RX_FIFO_EMPTY_EN_Msk ) + +#define SPI_IE_TX_FIFO_FULL_EN_Pos ( 3U ) +#define SPI_IE_TX_FIFO_FULL_EN_Msk ( 0x1UL << SPI_IE_TX_FIFO_FULL_EN_Pos ) +#define SPI_IE_TX_FIFO_FULL_EN ( SPI_IE_TX_FIFO_FULL_EN_Msk ) + +#define SPI_IE_TX_FIFO_EMPTY_EN_Pos ( 2U ) +#define SPI_IE_TX_FIFO_EMPTY_EN_Msk ( 0x1UL << SPI_IE_TX_FIFO_EMPTY_EN_Pos ) +#define SPI_IE_TX_FIFO_EMPTY_EN ( SPI_IE_TX_FIFO_EMPTY_EN_Msk ) + +#define SPI_IE_BATCH_DONE_EN_Pos ( 1U ) +#define SPI_IE_BATCH_DONE_EN_Msk ( 0x1UL << SPI_IE_BATCH_DONE_EN_Pos ) +#define SPI_IE_BATCH_DONE_EN ( SPI_IE_BATCH_DONE_EN_Msk ) + + +/*************** Bits definition for SPI_STATUS **********************/ + +#define SPI_STATUS_RX_BATCH_DONE_Pos ( 15U ) +#define SPI_STATUS_RX_BATCH_DONE_Msk ( 0x1UL << SPI_STATUS_RX_BATCH_DONE_Pos ) +#define SPI_STATUS_RX_BATCH_DONE ( SPI_STATUS_RX_BATCH_DONE_Msk ) + +#define SPI_STATUS_TX_BATCH_DONE_Pos ( 14U ) +#define SPI_STATUS_TX_BATCH_DONE_Msk ( 0x1UL << SPI_STATUS_TX_BATCH_DONE_Pos ) +#define SPI_STATUS_TX_BATCH_DONE ( SPI_STATUS_TX_BATCH_DONE_Msk ) + +#define SPI_STATUS_RX_FIFO_FULL_OVERFLOW_Pos ( 13U ) +#define SPI_STATUS_RX_FIFO_FULL_OVERFLOW_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_FULL_OVERFLOW_Pos ) +#define SPI_STATUS_RX_FIFO_FULL_OVERFLOW ( SPI_STATUS_RX_FIFO_FULL_OVERFLOW_Msk ) + +#define SPI_STATUS_RX_FIFO_EMPTY_OVERFLOW_Pos ( 12U ) +#define SPI_STATUS_RX_FIFO_EMPTY_OVERFLOW_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_EMPTY_OVERFLOW_Pos ) +#define SPI_STATUS_RX_FIFO_EMPTY_OVERFLOW ( SPI_STATUS_RX_FIFO_EMPTY_OVERFLOW_Msk ) + +#define SPI_STATUS_RX_FIFO_NOT_EMPTY_Pos ( 11U ) +#define SPI_STATUS_RX_FIFO_NOT_EMPTY_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_NOT_EMPTY_Pos ) +#define SPI_STATUS_RX_FIFO_NOT_EMPTY ( SPI_STATUS_RX_FIFO_NOT_EMPTY_Msk ) + +#define SPI_STATUS_CS_POS_FLG_Pos ( 10U ) +#define SPI_STATUS_CS_POS_FLG_Msk ( 0x1UL << SPI_STATUS_CS_POS_FLG_Pos ) +#define SPI_STATUS_CS_POS_FLG ( SPI_STATUS_CS_POS_FLG_Msk ) + +#define SPI_STATUS_RX_FIFO_HALF_FULL_Pos ( 9U ) +#define SPI_STATUS_RX_FIFO_HALF_FULL_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_HALF_FULL_Pos ) +#define SPI_STATUS_RX_FIFO_HALF_FULL ( SPI_STATUS_RX_FIFO_HALF_FULL_Msk ) + +#define SPI_STATUS_RX_FIFO_HALF_EMPTY_Pos ( 8U ) +#define SPI_STATUS_RX_FIFO_HALF_EMPTY_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_HALF_EMPTY_Pos ) +#define SPI_STATUS_RX_FIFO_HALF_EMPTY ( SPI_STATUS_RX_FIFO_HALF_EMPTY_Msk ) + +#define SPI_STATUS_TX_FIFO_HALF_FULL_Pos ( 7U ) +#define SPI_STATUS_TX_FIFO_HALF_FULL_Msk ( 0x1UL << SPI_STATUS_TX_FIFO_HALF_FULL_Pos ) +#define SPI_STATUS_TX_FIFO_HALF_FULL ( SPI_STATUS_TX_FIFO_HALF_FULL_Msk ) + +#define SPI_STATUS_TX_FIFO_HALF_EMPTY_Pos ( 6U ) +#define SPI_STATUS_TX_FIFO_HALF_EMPTY_Msk ( 0x1UL << SPI_STATUS_TX_FIFO_HALF_EMPTY_Pos ) +#define SPI_STATUS_TX_FIFO_HALF_EMPTY ( SPI_STATUS_TX_FIFO_HALF_EMPTY_Msk ) + +#define SPI_STATUS_RX_FIFO_FULL_Pos ( 5U ) +#define SPI_STATUS_RX_FIFO_FULL_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_FULL_Pos ) +#define SPI_STATUS_RX_FIFO_FULL ( SPI_STATUS_RX_FIFO_FULL_Msk ) + +#define SPI_STATUS_RX_FIFO_EMPTY_Pos ( 4U ) +#define SPI_STATUS_RX_FIFO_EMPTY_Msk ( 0x1UL << SPI_STATUS_RX_FIFO_EMPTY_Pos ) +#define SPI_STATUS_RX_FIFO_EMPTY ( SPI_STATUS_RX_FIFO_EMPTY_Msk ) + +#define SPI_STATUS_TX_FIFO_FULL_Pos ( 3U ) +#define SPI_STATUS_TX_FIFO_FULL_Msk ( 0x1UL << SPI_STATUS_TX_FIFO_FULL_Pos ) +#define SPI_STATUS_TX_FIFO_FULL ( SPI_STATUS_TX_FIFO_FULL_Msk ) + +#define SPI_STATUS_TX_FIFO_EMPTY_Pos ( 2U ) +#define SPI_STATUS_TX_FIFO_EMPTY_Msk ( 0x1UL << SPI_STATUS_TX_FIFO_EMPTY_Pos ) +#define SPI_STATUS_TX_FIFO_EMPTY ( SPI_STATUS_TX_FIFO_EMPTY_Msk ) + +#define SPI_STATUS_BATCH_DONE_Pos ( 1U ) +#define SPI_STATUS_BATCH_DONE_Msk ( 0x1UL << SPI_STATUS_BATCH_DONE_Pos ) +#define SPI_STATUS_BATCH_DONE ( SPI_STATUS_BATCH_DONE_Msk ) + +#define SPI_STATUS_TX_BUSY_Pos ( 0U ) +#define SPI_STATUS_TX_BUSY_Msk ( 0x1UL << SPI_STATUS_TX_BUSY_Pos ) +#define SPI_STATUS_TX_BUSY ( SPI_STATUS_TX_BUSY_Msk ) + + +/*************** Bits definition for SPI_TXDelay **********************/ + +#define SPI_TXDELAY_SPI_TDY_Pos ( 0U ) +#define SPI_TXDELAY_SPI_TDY_Msk ( 0xffffffffUL << SPI_TXDELAY_SPI_TDY_Pos ) +#define SPI_TXDELAY_SPI_TDY ( SPI_TXDELAY_SPI_TDY_Msk ) + + +/*************** Bits definition for SPI_BATCH **********************/ + +#define SPI_BATCH_BATCH_NUMBER_Pos ( 0U ) +#define SPI_BATCH_BATCH_NUMBER_Msk ( 0xffffffffUL << SPI_BATCH_BATCH_NUMBER_Pos ) +#define SPI_BATCH_BATCH_NUMBER ( SPI_BATCH_BATCH_NUMBER_Msk ) + + +/*************** Bits definition for SPI_CS **********************/ + +#define SPI_CS_Pos ( 0U ) +#define SPI_CS_Msk ( 0x1FUL << SPI_CS_Pos ) +#define SPI_CS ( SPI_CS_Msk ) +#define SPI_CS_CS0 ( 0x1UL << SPI_CS_Pos ) +#define SPI_CS_CS1 ( 0x2UL << SPI_CS_Pos ) +#define SPI_CS_CS2 ( 0x4UL << SPI_CS_Pos ) +#define SPI_CS_CS3 ( 0x8UL << SPI_CS_Pos ) +#define SPI_CS_CS4 ( 0x10UL << SPI_CS_Pos ) + +#define SPI_CSMAP_EN_Pos (8) +#define SPI_CSMAP_EN_Msk (0x1UL << SPI_CSMAP_EN_Pos) +#define SPI_CSMAP_EN (SPI_CSMAP_EN_Msk) + +/*************** Bits definition for SPI_OUT_EN **********************/ + +#define SPI_OUT_EN_SPI_HOLD_EN_Pos ( 3U ) +#define SPI_OUT_EN_SPI_HOLD_EN_Msk ( 0x1UL << SPI_OUT_EN_SPI_HOLD_EN_Pos ) +#define SPI_OUT_EN_SPI_HOLD_EN ( SPI_OUT_EN_SPI_HOLD_EN_Msk ) + +#define SPI_OUT_EN_SPI_WP_EN_Pos ( 2U ) +#define SPI_OUT_EN_SPI_WP_EN_Msk ( 0x1UL << SPI_OUT_EN_SPI_WP_EN_Pos ) +#define SPI_OUT_EN_SPI_WP_EN ( SPI_OUT_EN_SPI_WP_EN_Msk ) + +#define SPI_OUT_EN_SPI_MISO_EN_Pos ( 1U ) +#define SPI_OUT_EN_SPI_MISO_EN_Msk ( 0x1UL << SPI_OUT_EN_SPI_MISO_EN_Pos ) +#define SPI_OUT_EN_SPI_MISO_EN ( SPI_OUT_EN_SPI_MISO_EN_Msk ) + + +/*************** Bits definition for SPI_MEMO_ACC **********************/ + +#define SPI_MEMO_ACC_DATA_MODE_Pos ( 25U ) +#define SPI_MEMO_ACC_DATA_MODE_Msk ( 0x3UL << SPI_MEMO_ACC_DATA_MODE_Pos ) +#define SPI_MEMO_ACC_DATA_MODE ( SPI_MEMO_ACC_DATA_MODE_Msk ) +#define SPI_MEMO_ACC_DATA_MODE_0 ( 0x1UL << SPI_MEMO_ACC_DATA_MODE_Pos ) +#define SPI_MEMO_ACC_DATA_MODE_1 ( 0x2UL << SPI_MEMO_ACC_DATA_MODE_Pos ) + +#define SPI_MEMO_ACC_ALTER_BYTE_MODE_Pos ( 23U ) +#define SPI_MEMO_ACC_ALTER_BYTE_MODE_Msk ( 0x3UL << SPI_MEMO_ACC_ALTER_BYTE_MODE_Pos ) +#define SPI_MEMO_ACC_ALTER_BYTE_MODE ( SPI_MEMO_ACC_ALTER_BYTE_MODE_Msk ) +#define SPI_MEMO_ACC_ALTER_BYTE_MODE_0 ( 0x1UL << SPI_MEMO_ACC_ALTER_BYTE_MODE_Pos ) +#define SPI_MEMO_ACC_ALTER_BYTE_MODE_1 ( 0x2UL << SPI_MEMO_ACC_ALTER_BYTE_MODE_Pos ) + +#define SPI_MEMO_ACC_ADDR_MODE_Pos ( 21U ) +#define SPI_MEMO_ACC_ADDR_MODE_Msk ( 0x3UL << SPI_MEMO_ACC_ADDR_MODE_Pos ) +#define SPI_MEMO_ACC_ADDR_MODE ( SPI_MEMO_ACC_ADDR_MODE_Msk ) +#define SPI_MEMO_ACC_ADDR_MODE_0 ( 0x1UL << SPI_MEMO_ACC_ADDR_MODE_Pos ) +#define SPI_MEMO_ACC_ADDR_MODE_1 ( 0x2UL << SPI_MEMO_ACC_ADDR_MODE_Pos ) + +#define SPI_MEMO_ACC_INSTR_MODE_Pos ( 19U ) +#define SPI_MEMO_ACC_INSTR_MODE_Msk ( 0x3UL << SPI_MEMO_ACC_INSTR_MODE_Pos ) +#define SPI_MEMO_ACC_INSTR_MODE ( SPI_MEMO_ACC_INSTR_MODE_Msk ) +#define SPI_MEMO_ACC_INSTR_MODE_0 ( 0x1UL << SPI_MEMO_ACC_INSTR_MODE_Pos ) +#define SPI_MEMO_ACC_INSTR_MODE_1 ( 0x2UL << SPI_MEMO_ACC_INSTR_MODE_Pos ) + +#define SPI_MEMO_ACC_ADDR_WIDTH_Pos ( 17U ) +#define SPI_MEMO_ACC_ADDR_WIDTH_Msk ( 0x3UL << SPI_MEMO_ACC_ADDR_WIDTH_Pos ) +#define SPI_MEMO_ACC_ADDR_WIDTH ( SPI_MEMO_ACC_ADDR_WIDTH_Msk ) +#define SPI_MEMO_ACC_ADDR_WIDTH_0 ( 0x1UL << SPI_MEMO_ACC_ADDR_WIDTH_Pos ) +#define SPI_MEMO_ACC_ADDR_WIDTH_1 ( 0x2UL << SPI_MEMO_ACC_ADDR_WIDTH_Pos ) + +#define SPI_MEMO_ACC_DUMMY_BYTE_SIZE_Pos ( 12U ) +#define SPI_MEMO_ACC_DUMMY_BYTE_SIZE_Msk ( 0x3UL << SPI_MEMO_ACC_DUMMY_BYTE_SIZE_Pos ) +#define SPI_MEMO_ACC_DUMMY_BYTE_SIZE ( SPI_MEMO_ACC_DUMMY_BYTE_SIZE_Msk ) +#define SPI_MEMO_ACC_DUMMY_BYTE_SIZE_0 ( 0x1UL << SPI_MEMO_ACC_DUMMY_BYTE_SIZE_Pos ) +#define SPI_MEMO_ACC_DUMMY_BYTE_SIZE_1 ( 0x2UL << SPI_MEMO_ACC_DUMMY_BYTE_SIZE_Pos ) + +#define SPI_MEMO_ACC_RD_DB_EN_Pos ( 11U ) +#define SPI_MEMO_ACC_RD_DB_EN_Msk ( 0x1UL << SPI_MEMO_ACC_RD_DB_EN_Pos ) +#define SPI_MEMO_ACC_RD_DB_EN ( SPI_MEMO_ACC_RD_DB_EN_Msk ) + +#define SPI_MEMO_ACC_WR_DB_EN_Pos ( 10U ) +#define SPI_MEMO_ACC_WR_DB_EN_Msk ( 0x1UL << SPI_MEMO_ACC_WR_DB_EN_Pos ) +#define SPI_MEMO_ACC_WR_DB_EN ( SPI_MEMO_ACC_WR_DB_EN_Msk ) + +#define SPI_MEMO_ACC_ALTER_BYTE_SIZE_Pos ( 7U ) +#define SPI_MEMO_ACC_ALTER_BYTE_SIZE_Msk ( 0x3UL << SPI_MEMO_ACC_ALTER_BYTE_SIZE_Pos ) +#define SPI_MEMO_ACC_ALTER_BYTE_SIZE ( SPI_MEMO_ACC_ALTER_BYTE_SIZE_Msk ) +#define SPI_MEMO_ACC_ALTER_BYTE_SIZE_0 ( 0x1UL << SPI_MEMO_ACC_ALTER_BYTE_SIZE_Pos ) +#define SPI_MEMO_ACC_ALTER_BYTE_SIZE_1 ( 0x2UL << SPI_MEMO_ACC_ALTER_BYTE_SIZE_Pos ) + +#define SPI_MEMO_ACC_RD_AB_EN_Pos ( 6U ) +#define SPI_MEMO_ACC_RD_AB_EN_Msk ( 0x1UL << SPI_MEMO_ACC_RD_AB_EN_Pos ) +#define SPI_MEMO_ACC_RD_AB_EN ( SPI_MEMO_ACC_RD_AB_EN_Msk ) + +#define SPI_MEMO_ACC_WR_AB_EN_Pos ( 5U ) +#define SPI_MEMO_ACC_WR_AB_EN_Msk ( 0x1UL << SPI_MEMO_ACC_WR_AB_EN_Pos ) +#define SPI_MEMO_ACC_WR_AB_EN ( SPI_MEMO_ACC_WR_AB_EN_Msk ) + +#define SPI_MEMO_ACC_DISABLE_CMD_Pos ( 4U ) +#define SPI_MEMO_ACC_DISABLE_CMD_Msk ( 0x1UL << SPI_MEMO_ACC_DISABLE_CMD_Pos ) +#define SPI_MEMO_ACC_DISABLE_CMD ( SPI_MEMO_ACC_DISABLE_CMD_Msk ) + +#define SPI_MEMO_ACC_CON_MODE_EN_Pos ( 3U ) +#define SPI_MEMO_ACC_CON_MODE_EN_Msk ( 0x1UL << SPI_MEMO_ACC_CON_MODE_EN_Pos ) +#define SPI_MEMO_ACC_CON_MODE_EN ( SPI_MEMO_ACC_CON_MODE_EN_Msk ) + +#define SPI_MEMO_ACC_CON_CS_WAIT_EN_Pos ( 1U ) +#define SPI_MEMO_ACC_CON_CS_WAIT_EN_Msk ( 0x1UL << SPI_MEMO_ACC_CON_CS_WAIT_EN_Pos ) +#define SPI_MEMO_ACC_CON_CS_WAIT_EN ( SPI_MEMO_ACC_CON_CS_WAIT_EN_Msk ) + +#define SPI_MEMO_ACC_SPI_ACC_EN_Pos ( 0U ) +#define SPI_MEMO_ACC_SPI_ACC_EN_Msk ( 0x1UL << SPI_MEMO_ACC_SPI_ACC_EN_Pos ) +#define SPI_MEMO_ACC_SPI_ACC_EN ( SPI_MEMO_ACC_SPI_ACC_EN_Msk ) + + +/*************** Bits definition for SPI_CMD **********************/ + +#define SPI_CMD_WR_CMD_Pos ( 8U ) +#define SPI_CMD_WR_CMD_Msk ( 0xffUL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD ( SPI_CMD_WR_CMD_Msk ) +#define SPI_CMD_WR_CMD_0 ( 0x1UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_1 ( 0x2UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_2 ( 0x4UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_3 ( 0x8UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_4 ( 0x10UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_5 ( 0x20UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_6 ( 0x40UL << SPI_CMD_WR_CMD_Pos ) +#define SPI_CMD_WR_CMD_7 ( 0x80UL << SPI_CMD_WR_CMD_Pos ) + +#define SPI_CMD_RD_CMD_Pos ( 0U ) +#define SPI_CMD_RD_CMD_Msk ( 0xffUL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD ( SPI_CMD_RD_CMD_Msk ) +#define SPI_CMD_RD_CMD_0 ( 0x1UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_1 ( 0x2UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_2 ( 0x4UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_3 ( 0x8UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_4 ( 0x10UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_5 ( 0x20UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_6 ( 0x40UL << SPI_CMD_RD_CMD_Pos ) +#define SPI_CMD_RD_CMD_7 ( 0x80UL << SPI_CMD_RD_CMD_Pos ) + + +/*************** Bits definition for SPI_ALTER_BYTE **********************/ + +#define SPI_ALTER_BYTE_ALTER_BYTE_Pos ( 0U ) +#define SPI_ALTER_BYTE_ALTER_BYTE_Msk ( 0xffffffffUL << SPI_ALTER_BYTE_ALTER_BYTE_Pos ) +#define SPI_ALTER_BYTE_ALTER_BYTE ( SPI_ALTER_BYTE_ALTER_BYTE_Msk ) + + +/*************** Bits definition for SPI_CS_WAIT_VAL **********************/ + +#define SPI_CS_WAIT_VAL_CON_CS_WAIT_VAL_Pos ( 0U ) +#define SPI_CS_WAIT_VAL_CON_CS_WAIT_VAL_Msk ( 0xffffUL << SPI_CS_WAIT_VAL_CON_CS_WAIT_VAL_Pos ) +#define SPI_CS_WAIT_VAL_CON_CS_WAIT_VAL ( SPI_CS_WAIT_VAL_CON_CS_WAIT_VAL_Msk ) + + +/*************** Bits definition for I2C_SLAVE_ADDR1 **********************/ + +#define I2C_SLAVE_ADDR1_ADDR17_Pos ( 7U ) +#define I2C_SLAVE_ADDR1_ADDR17_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR17_Pos ) +#define I2C_SLAVE_ADDR1_ADDR17 ( I2C_SLAVE_ADDR1_ADDR17_Msk ) + + +#define I2C_SLAVE_ADDR1_ADDR16_Pos ( 6U ) +#define I2C_SLAVE_ADDR1_ADDR16_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR16_Pos ) +#define I2C_SLAVE_ADDR1_ADDR16 ( I2C_SLAVE_ADDR1_ADDR16_Msk ) + + +#define I2C_SLAVE_ADDR1_ADDR15_Pos ( 5U ) +#define I2C_SLAVE_ADDR1_ADDR15_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR15_Pos ) +#define I2C_SLAVE_ADDR1_ADDR15 ( I2C_SLAVE_ADDR1_ADDR15_Msk ) + + +#define I2C_SLAVE_ADDR1_ADDR14_Pos ( 4U ) +#define I2C_SLAVE_ADDR1_ADDR14_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR14_Pos ) +#define I2C_SLAVE_ADDR1_ADDR14 ( I2C_SLAVE_ADDR1_ADDR14_Msk ) + + +#define I2C_SLAVE_ADDR1_ADDR13_Pos ( 3U ) +#define I2C_SLAVE_ADDR1_ADDR13_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR13_Pos ) +#define I2C_SLAVE_ADDR1_ADDR13 ( I2C_SLAVE_ADDR1_ADDR13_Msk ) + + +#define I2C_SLAVE_ADDR1_ADDR12_Pos ( 2U ) +#define I2C_SLAVE_ADDR1_ADDR12_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR12_Pos ) +#define I2C_SLAVE_ADDR1_ADDR12 ( I2C_SLAVE_ADDR1_ADDR12_Msk ) + + +#define I2C_SLAVE_ADDR1_ADDR11_Pos ( 1U ) +#define I2C_SLAVE_ADDR1_ADDR11_Msk ( 0x1UL << I2C_SLAVE_ADDR1_ADDR11_Pos ) +#define I2C_SLAVE_ADDR1_ADDR11 ( I2C_SLAVE_ADDR1_ADDR11_Msk ) + + + +/*************** Bits definition for I2C_CLK_DIV **********************/ + +#define I2C_CLK_DIV_I2C_CLK_DIV_Pos ( 0U ) +#define I2C_CLK_DIV_I2C_CLK_DIV_Msk ( 0xfffUL << I2C_CLK_DIV_I2C_CLK_DIV_Pos ) +#define I2C_CLK_DIV_I2C_CLK_DIV ( I2C_CLK_DIV_I2C_CLK_DIV_Msk ) + + +/*************** Bits definition for I2C_CR **********************/ + +#define I2C_CR_SU_HD_FIXEN_Pos ( 24U ) +#define I2C_CR_SU_HD_FIXEN_Msk ( 0x1UL << I2C_CR_SU_HD_FIXEN_Pos ) +#define I2C_CR_SU_HD_FIXEN ( I2C_CR_SU_HD_FIXEN_Msk ) + +#define I2C_CR_MARLO_SEL_Pos ( 23U ) +#define I2C_CR_MARLO_SEL_Msk ( 0x1UL << I2C_CR_MARLO_SEL_Pos ) +#define I2C_CR_MARLO_SEL ( I2C_CR_MARLO_SEL_Msk ) + +#define I2C_CR_TX_RX_FLAG_INTEN_Pos ( 22U ) +#define I2C_CR_TX_RX_FLAG_INTEN_Msk ( 0x1UL << I2C_CR_TX_RX_FLAG_INTEN_Pos ) +#define I2C_CR_TX_RX_FLAG_INTEN ( I2C_CR_TX_RX_FLAG_INTEN_Msk ) + +#define I2C_CR_NACKF_INTEN_Pos ( 21U ) +#define I2C_CR_NACKF_INTEN_Msk ( 0x1UL << I2C_CR_NACKF_INTEN_Pos ) +#define I2C_CR_NACKF_INTEN ( I2C_CR_NACKF_INTEN_Msk ) + +#define I2C_CR_STOPF_INTEN_Pos ( 20U ) +#define I2C_CR_STOPF_INTEN_Msk ( 0x1UL << I2C_CR_STOPF_INTEN_Pos ) +#define I2C_CR_STOPF_INTEN ( I2C_CR_STOPF_INTEN_Msk ) + +#define I2C_CR_RX_ADDR3_INTEN_Pos ( 19U ) +#define I2C_CR_RX_ADDR3_INTEN_Msk ( 0x1UL << I2C_CR_RX_ADDR3_INTEN_Pos ) +#define I2C_CR_RX_ADDR3_INTEN ( I2C_CR_RX_ADDR3_INTEN_Msk ) + +#define I2C_CR_DMA_EN_Pos ( 18U ) +#define I2C_CR_DMA_EN_Msk ( 0x1UL << I2C_CR_DMA_EN_Pos ) +#define I2C_CR_DMA_EN ( I2C_CR_DMA_EN_Msk ) + +#define I2C_CR_TXE_SEL_Pos ( 17U ) +#define I2C_CR_TXE_SEL_Msk ( 0x1UL << I2C_CR_TXE_SEL_Pos ) +#define I2C_CR_TXE_SEL ( I2C_CR_TXE_SEL_Msk ) + +#define I2C_CR_MARLO_INTEN_Pos ( 16U ) +#define I2C_CR_MARLO_INTEN_Msk ( 0x1UL << I2C_CR_MARLO_INTEN_Pos ) +#define I2C_CR_MARLO_INTEN ( I2C_CR_MARLO_INTEN_Msk ) + +#define I2C_CR_TX_AUTO_EN_Pos ( 15U ) +#define I2C_CR_TX_AUTO_EN_Msk ( 0x1UL << I2C_CR_TX_AUTO_EN_Pos ) +#define I2C_CR_TX_AUTO_EN ( I2C_CR_TX_AUTO_EN_Msk ) + +#define I2C_CR_OD_MODE_Pos ( 14U ) +#define I2C_CR_OD_MODE_Msk ( 0x1UL << I2C_CR_OD_MODE_Pos ) +#define I2C_CR_OD_MODE ( I2C_CR_OD_MODE_Msk ) + +#define I2C_CR_DETR_INT_EN_Pos ( 13U ) +#define I2C_CR_DETR_INT_EN_Msk ( 0x1UL << I2C_CR_DETR_INT_EN_Pos ) +#define I2C_CR_DETR_INT_EN ( I2C_CR_DETR_INT_EN_Msk ) + +#define I2C_CR_RX_ADDR2_INT_EN_Pos ( 12U ) +#define I2C_CR_RX_ADDR2_INT_EN_Msk ( 0x1UL << I2C_CR_RX_ADDR2_INT_EN_Pos ) +#define I2C_CR_RX_ADDR2_INT_EN ( I2C_CR_RX_ADDR2_INT_EN_Msk ) + +#define I2C_CR_OVR_INT_EN_Pos ( 11U ) +#define I2C_CR_OVR_INT_EN_Msk ( 0x1UL << I2C_CR_OVR_INT_EN_Pos ) +#define I2C_CR_OVR_INT_EN ( I2C_CR_OVR_INT_EN_Msk ) + +#define I2C_CR_RXNE_INT_EN_Pos ( 10U ) +#define I2C_CR_RXNE_INT_EN_Msk ( 0x1UL << I2C_CR_RXNE_INT_EN_Pos ) +#define I2C_CR_RXNE_INT_EN ( I2C_CR_RXNE_INT_EN_Msk ) + +#define I2C_CR_TXE_INT_EN_Pos ( 9U ) +#define I2C_CR_TXE_INT_EN_Msk ( 0x1UL << I2C_CR_TXE_INT_EN_Pos ) +#define I2C_CR_TXE_INT_EN ( I2C_CR_TXE_INT_EN_Msk ) + +#define I2C_CR_RX_ADDR1_INT_EN_Pos ( 8U ) +#define I2C_CR_RX_ADDR1_INT_EN_Msk ( 0x1UL << I2C_CR_RX_ADDR1_INT_EN_Pos ) +#define I2C_CR_RX_ADDR1_INT_EN ( I2C_CR_RX_ADDR1_INT_EN_Msk ) + +#define I2C_CR_MTF_INT_EN_Pos ( 7U ) +#define I2C_CR_MTF_INT_EN_Msk ( 0x1UL << I2C_CR_MTF_INT_EN_Pos ) +#define I2C_CR_MTF_INT_EN ( I2C_CR_MTF_INT_EN_Msk ) + +#define I2C_CR_TACK_Pos ( 6U ) +#define I2C_CR_TACK_Msk ( 0x1UL << I2C_CR_TACK_Pos ) +#define I2C_CR_TACK ( I2C_CR_TACK_Msk ) + +#define I2C_CR_STOP_Pos ( 5U ) +#define I2C_CR_STOP_Msk ( 0x1UL << I2C_CR_STOP_Pos ) +#define I2C_CR_STOP ( I2C_CR_STOP_Msk ) + +#define I2C_CR_START_Pos ( 4U ) +#define I2C_CR_START_Msk ( 0x1UL << I2C_CR_START_Pos ) +#define I2C_CR_START ( I2C_CR_START_Msk ) + +#define I2C_CR_TX_Pos ( 3U ) +#define I2C_CR_TX_Msk ( 0x1UL << I2C_CR_TX_Pos ) +#define I2C_CR_TX ( I2C_CR_TX_Msk ) + +#define I2C_CR_MASTER_Pos ( 2U ) +#define I2C_CR_MASTER_Msk ( 0x1UL << I2C_CR_MASTER_Pos ) +#define I2C_CR_MASTER ( I2C_CR_MASTER_Msk ) + +#define I2C_CR_NOSTRETCH_Pos ( 1U ) +#define I2C_CR_NOSTRETCH_Msk ( 0x1UL << I2C_CR_NOSTRETCH_Pos ) +#define I2C_CR_NOSTRETCH ( I2C_CR_NOSTRETCH_Msk ) + +#define I2C_CR_MEN_Pos ( 0U ) +#define I2C_CR_MEN_Msk ( 0x1UL << I2C_CR_MEN_Pos ) +#define I2C_CR_MEN ( I2C_CR_MEN_Msk ) + + +/*************** Bits definition for I2C_SR **********************/ + +#define I2C_SR_NACKF_Pos ( 17U ) +#define I2C_SR_NACKF_Msk ( 0x1UL << I2C_SR_NACKF_Pos ) +#define I2C_SR_NACKF ( I2C_SR_NACKF_Msk ) + +#define I2C_SR_TIMEOUTBF_Pos ( 16U ) +#define I2C_SR_TIMEOUTBF_Msk ( 0x1UL << I2C_SR_TIMEOUTBF_Pos ) +#define I2C_SR_TIMEOUTBF ( I2C_SR_TIMEOUTBF_Msk ) + +#define I2C_SR_TIMEOUTAF_Pos ( 15U ) +#define I2C_SR_TIMEOUTAF_Msk ( 0x1UL << I2C_SR_TIMEOUTAF_Pos ) +#define I2C_SR_TIMEOUTAF ( I2C_SR_TIMEOUTAF_Msk ) + +#define I2C_SR_RX_ADDR3_Pos ( 14U ) +#define I2C_SR_RX_ADDR3_Msk ( 0x1UL << I2C_SR_RX_ADDR3_Pos ) +#define I2C_SR_RX_ADDR3 ( I2C_SR_RX_ADDR3_Msk ) + +#define I2C_SR_DETR_Pos ( 13U ) +#define I2C_SR_DETR_Msk ( 0x1UL << I2C_SR_DETR_Pos ) +#define I2C_SR_DETR ( I2C_SR_DETR_Msk ) + +#define I2C_SR_RX_ADDR2_Pos ( 12U ) +#define I2C_SR_RX_ADDR2_Msk ( 0x1UL << I2C_SR_RX_ADDR2_Pos ) +#define I2C_SR_RX_ADDR2 ( I2C_SR_RX_ADDR2_Msk ) + +#define I2C_SR_OVR_Pos ( 11U ) +#define I2C_SR_OVR_Msk ( 0x1UL << I2C_SR_OVR_Pos ) +#define I2C_SR_OVR ( I2C_SR_OVR_Msk ) + +#define I2C_SR_RXNE_Pos ( 10U ) +#define I2C_SR_RXNE_Msk ( 0x1UL << I2C_SR_RXNE_Pos ) +#define I2C_SR_RXNE ( I2C_SR_RXNE_Msk ) + +#define I2C_SR_TXE_Pos ( 9U ) +#define I2C_SR_TXE_Msk ( 0x1UL << I2C_SR_TXE_Pos ) +#define I2C_SR_TXE ( I2C_SR_TXE_Msk ) + +#define I2C_SR_RX_ADDR1_Pos ( 8U ) +#define I2C_SR_RX_ADDR1_Msk ( 0x1UL << I2C_SR_RX_ADDR1_Pos ) +#define I2C_SR_RX_ADDR1 ( I2C_SR_RX_ADDR1_Msk ) + +#define I2C_SR_MTF_Pos ( 7U ) +#define I2C_SR_MTF_Msk ( 0x1UL << I2C_SR_MTF_Pos ) +#define I2C_SR_MTF ( I2C_SR_MTF_Msk ) + +#define I2C_SR_MARLO_Pos ( 6U ) +#define I2C_SR_MARLO_Msk ( 0x1UL << I2C_SR_MARLO_Pos ) +#define I2C_SR_MARLO ( I2C_SR_MARLO_Msk ) + +#define I2C_SR_TX_RX_FLAG_Pos ( 5U ) +#define I2C_SR_TX_RX_FLAG_Msk ( 0x1UL << I2C_SR_TX_RX_FLAG_Pos ) +#define I2C_SR_TX_RX_FLAG ( I2C_SR_TX_RX_FLAG_Msk ) + +#define I2C_SR_BUS_BUSY_Pos ( 4U ) +#define I2C_SR_BUS_BUSY_Msk ( 0x1UL << I2C_SR_BUS_BUSY_Pos ) +#define I2C_SR_BUS_BUSY ( I2C_SR_BUS_BUSY_Msk ) + +#define I2C_SR_SRW_Pos ( 3U ) +#define I2C_SR_SRW_Msk ( 0x1UL << I2C_SR_SRW_Pos ) +#define I2C_SR_SRW ( I2C_SR_SRW_Msk ) + +#define I2C_SR_STOPF_Pos ( 2U ) +#define I2C_SR_STOPF_Msk ( 0x1UL << I2C_SR_STOPF_Pos ) +#define I2C_SR_STOPF ( I2C_SR_STOPF_Msk ) + +#define I2C_SR_STARTF_Pos ( 1U ) +#define I2C_SR_STARTF_Msk ( 0x1UL << I2C_SR_STARTF_Pos ) +#define I2C_SR_STARTF ( I2C_SR_STARTF_Msk ) + +#define I2C_SR_RACK_Pos ( 0U ) +#define I2C_SR_RACK_Msk ( 0x1UL << I2C_SR_RACK_Pos ) +#define I2C_SR_RACK ( I2C_SR_RACK_Msk ) + + +/*************** Bits definition for I2C_DR **********************/ + +#define I2C_DR_I2CDR_Pos ( 0U ) +#define I2C_DR_I2CDR_Msk ( 0xffUL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR ( I2C_DR_I2CDR_Msk ) +#define I2C_DR_I2CDR_0 ( 0x1UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_1 ( 0x2UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_2 ( 0x4UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_3 ( 0x8UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_4 ( 0x10UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_5 ( 0x20UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_6 ( 0x40UL << I2C_DR_I2CDR_Pos ) +#define I2C_DR_I2CDR_7 ( 0x80UL << I2C_DR_I2CDR_Pos ) + + +/*************** Bits definition for I2C_SLAVE_ADDR2_3 **********************/ +#define I2C_SLAVE_ADDR3_Pos ( 9U ) +#define I2C_SLAVE_ADDR3_Msk ( 0x7fUL << I2C_SLAVE_ADDR3_Pos ) +#define I2C_SLAVE_ADDR3 ( I2C_SLAVE__ADDR3_Msk ) + + +#define I2C_SLAVE_ADDR3_EN_Pos ( 8U ) +#define I2C_SLAVE_ADDR3_EN_Msk ( 0x1UL << I2C_SLAVE_ADDR3_EN_Pos ) +#define I2C_SLAVE_ADDR3_EN ( I2C_SLAVE_ADDR3_EN_Msk ) + + +#define I2C_SLAVE_ADDR2_Pos ( 1U ) +#define I2C_SLAVE_ADDR2_Msk ( 0x7fUL << I2C_SLAVE_ADDR2_Pos ) +#define I2C_SLAVE_ADDR2 ( I2C_SLAVE_ADDR2_Msk ) + + +#define I2C_SLAVE_ADDR2_EN_Pos ( 0U ) +#define I2C_SLAVE_ADDR2_EN_Msk ( 0x1UL << I2C_SLAVE_ADDR2_EN_Pos ) +#define I2C_SLAVE_ADDR2_EN ( I2C_SLAVE_ADDR2_EN_Msk ) + + +/*************** Bits definition for I2C_DET **********************/ + +#define I2C_DET_DETCNT_Pos ( 0U ) +#define I2C_DET_DETCNT_Msk ( 0xffffUL << I2C_DET_DETCNT_Pos ) +#define I2C_DET_DETCNT ( I2C_DET_DETCNT_Msk ) + + +/*************** Bits definition for I2C_FITER **********************/ + +#define I2C_FITER_SDA_IN_DELAY_Pos ( 8U ) +#define I2C_FITER_SDA_IN_DELAY_Msk ( 0x1FUL << I2C_FITER_SDA_IN_DELAY_Pos ) +#define I2C_FITER_SDA_IN_DELAY ( I2C_FITER_SDA_IN_DELAY_Msk ) +#define I2C_FITER_SDA_IN_DELAY_0 ( 0x1UL << I2C_FITER_SDA_IN_DELAY_Pos ) +#define I2C_FITER_SDA_IN_DELAY_1 ( 0x2UL << I2C_FITER_SDA_IN_DELAY_Pos ) +#define I2C_FITER_SDA_IN_DELAY_2 ( 0x4UL << I2C_FITER_SDA_IN_DELAY_Pos ) +#define I2C_FITER_SDA_IN_DELAY_3 ( 0x8UL << I2C_FITER_SDA_IN_DELAY_Pos ) +#define I2C_FITER_SDA_IN_DELAY_4 ( 0x10UL << I2C_FITER_SDA_IN_DELAY_Pos ) + +#define I2C_FITER_SCL_FITER_Pos ( 0U ) +#define I2C_FITER_SCL_FITER_Msk ( 0x1FUL << I2C_FITER_SCL_FITER_Pos ) +#define I2C_FITER_SCL_FITER ( I2C_FITER_SCL_FITER_Msk ) +#define I2C_FITER_SCL_FITER_0 ( 0x1UL << I2C_FITER_SCL_FITER_Pos ) +#define I2C_FITER_SCL_FITER_1 ( 0x2UL << I2C_FITER_SCL_FITER_Pos ) +#define I2C_FITER_SCL_FITER_2 ( 0x4UL << I2C_FITER_SCL_FITER_Pos ) +#define I2C_FITER_SCL_FITER_3 ( 0x8UL << I2C_FITER_SCL_FITER_Pos ) +#define I2C_FITER_SCL_FITER_4 ( 0x10UL << I2C_FITER_SCL_FITER_Pos ) + + +/*************** Bits definition for I2C_Timeout **********************/ + +#define I2C_TIMEOUT_EXTEN_Pos ( 31U ) +#define I2C_TIMEOUT_EXTEN_Msk ( 0x1UL << I2C_TIMEOUT_EXTEN_Pos ) +#define I2C_TIMEOUT_EXTEN ( I2C_TIMEOUT_EXTEN_Msk ) + +#define I2C_TIMEOUTB_INTEN_Pos ( 30U ) +#define I2C_TIMEOUTB_INTEN_Msk ( 0x1UL << I2C_TIMEOUT_TOUTB_INTEN_Pos ) +#define I2C_TIMEOUTB_INTEN ( I2C_TIMEOUT_TOUTB_INTEN_Msk ) + +#define I2C_TIMEOUT_EXT_MODE_Pos ( 29U ) +#define I2C_TIMEOUT_EXT_MODE_Msk ( 0x1UL << I2C_TIMEOUT_EXT_MODE_Pos ) +#define I2C_TIMEOUT_EXT_MODE ( I2C_TIMEOUT_EXT_MODE_Msk ) + +#define I2C_TIMEOUTB_Pos ( 16U ) +#define I2C_TIMEOUTB_Msk ( 0xfffUL << I2C_TIMEOUT_TIMEOUTB_Pos ) +#define I2C_TIMEOUTB ( I2C_TIMEOUT_TIMEOUTB_Msk ) + +#define I2C_TIMOUTEN_Pos ( 15U ) +#define I2C_TIMOUTEN_Msk ( 0x1UL << I2C_TIMEOUT_TIMOUTEN_Pos ) +#define I2C_TIMOUTEN ( I2C_TIMEOUT_TIMOUTEN_Msk ) + +#define I2C_TIMEOUTA_INTEN_Pos ( 14U ) +#define I2C_TIMEOUTA_INTEN_Msk ( 0x1UL << I2C_TIMEOUT_TOUTA_INTEN_Pos ) +#define I2C_TIMEOUTA_INTEN ( I2C_TIMEOUT_TOUTA_INTEN_Msk ) + +#define I2C_TIMEOUTA_Pos ( 0U ) +#define I2C_TIMEOUTA_Msk ( 0xfffUL << I2C_TIMEOUT_TIMEOUTA_Pos ) +#define I2C_TIMEOUTA ( I2C_TIMEOUT_TIMEOUTA_Msk ) + + +/*************** Bits definition for FDCAN_RBUFx **********************/ + +#define FDCAN_RBUFX_RBUFX_Pos ( 0U ) +#define FDCAN_RBUFX_RBUFX_Msk ( 0xffffffffUL << FDCAN_RBUFX_RBUFX_Pos ) +#define FDCAN_RBUFX_RBUFX ( FDCAN_RBUFX_RBUFX_Msk ) + + +/*************** Bits definition for FDCAN_TBUFx **********************/ + +#define FDCAN_TBUFX_TBUFX_Pos ( 0U ) +#define FDCAN_TBUFX_TBUFX_Msk ( 0xffffffffUL << FDCAN_TBUFX_TBUFX_Pos ) +#define FDCAN_TBUFX_TBUFX ( FDCAN_TBUFX_TBUFX_Msk ) + + +/*************** Bits definition for FDCAN_TTSL **********************/ + +#define FDCAN_TTSL_TTS_Pos ( 0U ) +#define FDCAN_TTSL_TTS_Msk ( 0xffffffffUL << FDCAN_TTSL_TTS_Pos ) +#define FDCAN_TTSL_TTS ( FDCAN_TTSL_TTS_Msk ) + + +/*************** Bits definition for FDCAN_TTSH **********************/ + +#define FDCAN_TTSH_TTS_Pos ( 0U ) +#define FDCAN_TTSH_TTS_Msk ( 0xffffffffUL << FDCAN_TTSH_TTS_Pos ) +#define FDCAN_TTSH_TTS ( FDCAN_TTSH_TTS_Msk ) + + +/*************** Bits definition for FDCAN_CR **********************/ + +#define FDCAN_CR_SACK_Pos ( 31U ) +#define FDCAN_CR_SACK_Msk ( 0x1UL << FDCAN_CR_SACK_Pos ) +#define FDCAN_CR_SACK ( FDCAN_CR_SACK_Msk ) + +#define FDCAN_CR_ROM_Pos ( 30U ) +#define FDCAN_CR_ROM_Msk ( 0x1UL << FDCAN_CR_ROM_Pos ) +#define FDCAN_CR_ROM ( FDCAN_CR_ROM_Msk ) + +#define FDCAN_CR_ROV_Pos ( 29U ) +#define FDCAN_CR_ROV_Msk ( 0x1UL << FDCAN_CR_ROV_Pos ) +#define FDCAN_CR_ROV ( FDCAN_CR_ROV_Msk ) + +#define FDCAN_CR_RREL_Pos ( 28U ) +#define FDCAN_CR_RREL_Msk ( 0x1UL << FDCAN_CR_RREL_Pos ) +#define FDCAN_CR_RREL ( FDCAN_CR_RREL_Msk ) + +#define FDCAN_CR_RBALL_Pos ( 27U ) +#define FDCAN_CR_RBALL_Msk ( 0x1UL << FDCAN_CR_RBALL_Pos ) +#define FDCAN_CR_RBALL ( FDCAN_CR_RBALL_Msk ) + +#define FDCAN_CR_RSTAT_Pos ( 24U ) +#define FDCAN_CR_RSTAT_Msk ( 0x3UL << FDCAN_CR_RSTAT_Pos ) +#define FDCAN_CR_RSTAT ( FDCAN_CR_RSTAT_Msk ) +#define FDCAN_CR_RSTAT_0 ( 0x1UL << FDCAN_CR_RSTAT_Pos ) +#define FDCAN_CR_RSTAT_1 ( 0x2UL << FDCAN_CR_RSTAT_Pos ) + +#define FDCAN_CR_FD_ISO_Pos ( 23U ) +#define FDCAN_CR_FD_ISO_Msk ( 0x1UL << FDCAN_CR_FD_ISO_Pos ) +#define FDCAN_CR_FD_ISO ( FDCAN_CR_FD_ISO_Msk ) + +#define FDCAN_CR_TSNEXT_Pos ( 22U ) +#define FDCAN_CR_TSNEXT_Msk ( 0x1UL << FDCAN_CR_TSNEXT_Pos ) +#define FDCAN_CR_TSNEXT ( FDCAN_CR_TSNEXT_Msk ) + +#define FDCAN_CR_TSMODE_Pos ( 21U ) +#define FDCAN_CR_TSMODE_Msk ( 0x1UL << FDCAN_CR_TSMODE_Pos ) +#define FDCAN_CR_TSMODE ( FDCAN_CR_TSMODE_Msk ) + +#define FDCAN_CR_TTTBM_Pos ( 20U ) +#define FDCAN_CR_TTTBM_Msk ( 0x1UL << FDCAN_CR_TTTBM_Pos ) +#define FDCAN_CR_TTTBM ( FDCAN_CR_TTTBM_Msk ) + +#define FDCAN_CR_TSSTAT_Pos ( 16U ) +#define FDCAN_CR_TSSTAT_Msk ( 0x3UL << FDCAN_CR_TSSTAT_Pos ) +#define FDCAN_CR_TSSTAT ( FDCAN_CR_TSSTAT_Msk ) +#define FDCAN_CR_TSSTAT_0 ( 0x1UL << FDCAN_CR_TSSTAT_Pos ) +#define FDCAN_CR_TSSTAT_1 ( 0x2UL << FDCAN_CR_TSSTAT_Pos ) + +#define FDCAN_CR_TBSEL_Pos ( 15U ) +#define FDCAN_CR_TBSEL_Msk ( 0x1UL << FDCAN_CR_TBSEL_Pos ) +#define FDCAN_CR_TBSEL ( FDCAN_CR_TBSEL_Msk ) + +#define FDCAN_CR_LOM_Pos ( 14U ) +#define FDCAN_CR_LOM_Msk ( 0x1UL << FDCAN_CR_LOM_Pos ) +#define FDCAN_CR_LOM ( FDCAN_CR_LOM_Msk ) + +#define FDCAN_CR_STBY_Pos ( 13U ) +#define FDCAN_CR_STBY_Msk ( 0x1UL << FDCAN_CR_STBY_Pos ) +#define FDCAN_CR_STBY ( FDCAN_CR_STBY_Msk ) + +#define FDCAN_CR_TPE_Pos ( 12U ) +#define FDCAN_CR_TPE_Msk ( 0x1UL << FDCAN_CR_TPE_Pos ) +#define FDCAN_CR_TPE ( FDCAN_CR_TPE_Msk ) + +#define FDCAN_CR_TPA_Pos ( 11U ) +#define FDCAN_CR_TPA_Msk ( 0x1UL << FDCAN_CR_TPA_Pos ) +#define FDCAN_CR_TPA ( FDCAN_CR_TPA_Msk ) + +#define FDCAN_CR_TSONE_Pos ( 10U ) +#define FDCAN_CR_TSONE_Msk ( 0x1UL << FDCAN_CR_TSONE_Pos ) +#define FDCAN_CR_TSONE ( FDCAN_CR_TSONE_Msk ) + +#define FDCAN_CR_TSALL_Pos ( 9U ) +#define FDCAN_CR_TSALL_Msk ( 0x1UL << FDCAN_CR_TSALL_Pos ) +#define FDCAN_CR_TSALL ( FDCAN_CR_TSALL_Msk ) + +#define FDCAN_CR_TSA_Pos ( 8U ) +#define FDCAN_CR_TSA_Msk ( 0x1UL << FDCAN_CR_TSA_Pos ) +#define FDCAN_CR_TSA ( FDCAN_CR_TSA_Msk ) + +#define FDCAN_CR_RESET_Pos ( 7U ) +#define FDCAN_CR_RESET_Msk ( 0x1UL << FDCAN_CR_RESET_Pos ) +#define FDCAN_CR_RESET ( FDCAN_CR_RESET_Msk ) + +#define FDCAN_CR_LBME_Pos ( 6U ) +#define FDCAN_CR_LBME_Msk ( 0x1UL << FDCAN_CR_LBME_Pos ) +#define FDCAN_CR_LBME ( FDCAN_CR_LBME_Msk ) + +#define FDCAN_CR_LBMI_Pos ( 5U ) +#define FDCAN_CR_LBMI_Msk ( 0x1UL << FDCAN_CR_LBMI_Pos ) +#define FDCAN_CR_LBMI ( FDCAN_CR_LBMI_Msk ) + +#define FDCAN_CR_TPSS_Pos ( 4U ) +#define FDCAN_CR_TPSS_Msk ( 0x1UL << FDCAN_CR_TPSS_Pos ) +#define FDCAN_CR_TPSS ( FDCAN_CR_TPSS_Msk ) + +#define FDCAN_CR_TSSS_Pos ( 3U ) +#define FDCAN_CR_TSSS_Msk ( 0x1UL << FDCAN_CR_TSSS_Pos ) +#define FDCAN_CR_TSSS ( FDCAN_CR_TSSS_Msk ) + +#define FDCAN_CR_RACTIVE_Pos ( 2U ) +#define FDCAN_CR_RACTIVE_Msk ( 0x1UL << FDCAN_CR_RACTIVE_Pos ) +#define FDCAN_CR_RACTIVE ( FDCAN_CR_RACTIVE_Msk ) + +#define FDCAN_CR_TACTIVE_Pos ( 1U ) +#define FDCAN_CR_TACTIVE_Msk ( 0x1UL << FDCAN_CR_TACTIVE_Pos ) +#define FDCAN_CR_TACTIVE ( FDCAN_CR_TACTIVE_Msk ) + +#define FDCAN_CR_BUSOFF_Pos ( 0U ) +#define FDCAN_CR_BUSOFF_Msk ( 0x1UL << FDCAN_CR_BUSOFF_Pos ) +#define FDCAN_CR_BUSOFF ( FDCAN_CR_BUSOFF_Msk ) + + +/*************** Bits definition for FDCAN_IR **********************/ + +#define FDCAN_IR_EWARN_Pos ( 23U ) +#define FDCAN_IR_EWARN_Msk ( 0x1UL << FDCAN_IR_EWARN_Pos ) +#define FDCAN_IR_EWARN ( FDCAN_IR_EWARN_Msk ) + +#define FDCAN_IR_EPASS_Pos ( 22U ) +#define FDCAN_IR_EPASS_Msk ( 0x1UL << FDCAN_IR_EPASS_Pos ) +#define FDCAN_IR_EPASS ( FDCAN_IR_EPASS_Msk ) + +#define FDCAN_IR_EPIE_Pos ( 21U ) +#define FDCAN_IR_EPIE_Msk ( 0x1UL << FDCAN_IR_EPIE_Pos ) +#define FDCAN_IR_EPIE ( FDCAN_IR_EPIE_Msk ) + +#define FDCAN_IR_EPIF_Pos ( 20U ) +#define FDCAN_IR_EPIF_Msk ( 0x1UL << FDCAN_IR_EPIF_Pos ) +#define FDCAN_IR_EPIF ( FDCAN_IR_EPIF_Msk ) + +#define FDCAN_IR_ALIE_Pos ( 19U ) +#define FDCAN_IR_ALIE_Msk ( 0x1UL << FDCAN_IR_ALIE_Pos ) +#define FDCAN_IR_ALIE ( FDCAN_IR_ALIE_Msk ) + +#define FDCAN_IR_ALIF_Pos ( 18U ) +#define FDCAN_IR_ALIF_Msk ( 0x1UL << FDCAN_IR_ALIF_Pos ) +#define FDCAN_IR_ALIF ( FDCAN_IR_ALIF_Msk ) + +#define FDCAN_IR_BEIE_Pos ( 17U ) +#define FDCAN_IR_BEIE_Msk ( 0x1UL << FDCAN_IR_BEIE_Pos ) +#define FDCAN_IR_BEIE ( FDCAN_IR_BEIE_Msk ) + +#define FDCAN_IR_BEIF_Pos ( 16U ) +#define FDCAN_IR_BEIF_Msk ( 0x1UL << FDCAN_IR_BEIF_Pos ) +#define FDCAN_IR_BEIF ( FDCAN_IR_BEIF_Msk ) + +#define FDCAN_IR_RIF_Pos ( 15U ) +#define FDCAN_IR_RIF_Msk ( 0x1UL << FDCAN_IR_RIF_Pos ) +#define FDCAN_IR_RIF ( FDCAN_IR_RIF_Msk ) + +#define FDCAN_IR_ROIF_Pos ( 14U ) +#define FDCAN_IR_ROIF_Msk ( 0x1UL << FDCAN_IR_ROIF_Pos ) +#define FDCAN_IR_ROIF ( FDCAN_IR_ROIF_Msk ) + +#define FDCAN_IR_RFIF_Pos ( 13U ) +#define FDCAN_IR_RFIF_Msk ( 0x1UL << FDCAN_IR_RFIF_Pos ) +#define FDCAN_IR_RFIF ( FDCAN_IR_RFIF_Msk ) + +#define FDCAN_IR_RAFIF_Pos ( 12U ) +#define FDCAN_IR_RAFIF_Msk ( 0x1UL << FDCAN_IR_RAFIF_Pos ) +#define FDCAN_IR_RAFIF ( FDCAN_IR_RAFIF_Msk ) + +#define FDCAN_IR_TPIF_Pos ( 11U ) +#define FDCAN_IR_TPIF_Msk ( 0x1UL << FDCAN_IR_TPIF_Pos ) +#define FDCAN_IR_TPIF ( FDCAN_IR_TPIF_Msk ) + +#define FDCAN_IR_TSIF_Pos ( 10U ) +#define FDCAN_IR_TSIF_Msk ( 0x1UL << FDCAN_IR_TSIF_Pos ) +#define FDCAN_IR_TSIF ( FDCAN_IR_TSIF_Msk ) + +#define FDCAN_IR_EIF_Pos ( 9U ) +#define FDCAN_IR_EIF_Msk ( 0x1UL << FDCAN_IR_EIF_Pos ) +#define FDCAN_IR_EIF ( FDCAN_IR_EIF_Msk ) + +#define FDCAN_IR_AIF_Pos ( 8U ) +#define FDCAN_IR_AIF_Msk ( 0x1UL << FDCAN_IR_AIF_Pos ) +#define FDCAN_IR_AIF ( FDCAN_IR_AIF_Msk ) + +#define FDCAN_IR_RIE_Pos ( 7U ) +#define FDCAN_IR_RIE_Msk ( 0x1UL << FDCAN_IR_RIE_Pos ) +#define FDCAN_IR_RIE ( FDCAN_IR_RIE_Msk ) + +#define FDCAN_IR_ROIE_Pos ( 6U ) +#define FDCAN_IR_ROIE_Msk ( 0x1UL << FDCAN_IR_ROIE_Pos ) +#define FDCAN_IR_ROIE ( FDCAN_IR_ROIE_Msk ) + +#define FDCAN_IR_RFIE_Pos ( 5U ) +#define FDCAN_IR_RFIE_Msk ( 0x1UL << FDCAN_IR_RFIE_Pos ) +#define FDCAN_IR_RFIE ( FDCAN_IR_RFIE_Msk ) + +#define FDCAN_IR_RAFIE_Pos ( 4U ) +#define FDCAN_IR_RAFIE_Msk ( 0x1UL << FDCAN_IR_RAFIE_Pos ) +#define FDCAN_IR_RAFIE ( FDCAN_IR_RAFIE_Msk ) + +#define FDCAN_IR_TPIE_Pos ( 3U ) +#define FDCAN_IR_TPIE_Msk ( 0x1UL << FDCAN_IR_TPIE_Pos ) +#define FDCAN_IR_TPIE ( FDCAN_IR_TPIE_Msk ) + +#define FDCAN_IR_TSIE_Pos ( 2U ) +#define FDCAN_IR_TSIE_Msk ( 0x1UL << FDCAN_IR_TSIE_Pos ) +#define FDCAN_IR_TSIE ( FDCAN_IR_TSIE_Msk ) + +#define FDCAN_IR_EIE_Pos ( 1U ) +#define FDCAN_IR_EIE_Msk ( 0x1UL << FDCAN_IR_EIE_Pos ) +#define FDCAN_IR_EIE ( FDCAN_IR_EIE_Msk ) + +#define FDCAN_IR_TSFF_Pos ( 0U ) +#define FDCAN_IR_TSFF_Msk ( 0x1UL << FDCAN_IR_TSFF_Pos ) +#define FDCAN_IR_TSFF ( FDCAN_IR_TSFF_Msk ) + + +/*************** Bits definition for FDCAN_LIMIT **********************/ + +#define FDCAN_LIMIT_AFWL_Pos ( 4U ) +#define FDCAN_LIMIT_AFWL_Msk ( 0xfUL << FDCAN_LIMIT_AFWL_Pos ) +#define FDCAN_LIMIT_AFWL ( FDCAN_LIMIT_AFWL_Msk ) +#define FDCAN_LIMIT_AFWL_0 ( 0x1UL << FDCAN_LIMIT_AFWL_Pos ) +#define FDCAN_LIMIT_AFWL_1 ( 0x2UL << FDCAN_LIMIT_AFWL_Pos ) +#define FDCAN_LIMIT_AFWL_2 ( 0x4UL << FDCAN_LIMIT_AFWL_Pos ) +#define FDCAN_LIMIT_AFWL_3 ( 0x8UL << FDCAN_LIMIT_AFWL_Pos ) + +#define FDCAN_LIMIT_EWL_Pos ( 0U ) +#define FDCAN_LIMIT_EWL_Msk ( 0xfUL << FDCAN_LIMIT_EWL_Pos ) +#define FDCAN_LIMIT_EWL ( FDCAN_LIMIT_EWL_Msk ) +#define FDCAN_LIMIT_EWL_0 ( 0x1UL << FDCAN_LIMIT_EWL_Pos ) +#define FDCAN_LIMIT_EWL_1 ( 0x2UL << FDCAN_LIMIT_EWL_Pos ) +#define FDCAN_LIMIT_EWL_2 ( 0x4UL << FDCAN_LIMIT_EWL_Pos ) +#define FDCAN_LIMIT_EWL_3 ( 0x8UL << FDCAN_LIMIT_EWL_Pos ) + + +/*************** Bits definition for FDCAN_SBTR **********************/ + +#define FDCAN_SBTR_S_PRESC_Pos ( 24U ) +#define FDCAN_SBTR_S_PRESC_Msk ( 0xffUL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC ( FDCAN_SBTR_S_PRESC_Msk ) +#define FDCAN_SBTR_S_PRESC_0 ( 0x1UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_1 ( 0x2UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_2 ( 0x4UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_3 ( 0x8UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_4 ( 0x10UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_5 ( 0x20UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_6 ( 0x40UL << FDCAN_SBTR_S_PRESC_Pos ) +#define FDCAN_SBTR_S_PRESC_7 ( 0x80UL << FDCAN_SBTR_S_PRESC_Pos ) + +#define FDCAN_SBTR_S_SJW_Pos ( 16U ) +#define FDCAN_SBTR_S_SJW_Msk ( 0x7fUL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW ( FDCAN_SBTR_S_SJW_Msk ) +#define FDCAN_SBTR_S_SJW_0 ( 0x1UL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW_1 ( 0x2UL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW_2 ( 0x4UL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW_3 ( 0x8UL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW_4 ( 0x10UL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW_5 ( 0x20UL << FDCAN_SBTR_S_SJW_Pos ) +#define FDCAN_SBTR_S_SJW_6 ( 0x40UL << FDCAN_SBTR_S_SJW_Pos ) + +#define FDCAN_SBTR_S_SEG_2_Pos ( 8U ) +#define FDCAN_SBTR_S_SEG_2_Msk ( 0x7fUL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2 ( FDCAN_SBTR_S_SEG_2_Msk ) +#define FDCAN_SBTR_S_SEG_2_0 ( 0x1UL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2_1 ( 0x2UL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2_2 ( 0x4UL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2_3 ( 0x8UL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2_4 ( 0x10UL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2_5 ( 0x20UL << FDCAN_SBTR_S_SEG_2_Pos ) +#define FDCAN_SBTR_S_SEG_2_6 ( 0x40UL << FDCAN_SBTR_S_SEG_2_Pos ) + +#define FDCAN_SBTR_S_SEG_1_Pos ( 0U ) +#define FDCAN_SBTR_S_SEG_1_Msk ( 0xffUL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1 ( FDCAN_SBTR_S_SEG_1_Msk ) +#define FDCAN_SBTR_S_SEG_1_0 ( 0x1UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_1 ( 0x2UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_2 ( 0x4UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_3 ( 0x8UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_4 ( 0x10UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_5 ( 0x20UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_6 ( 0x40UL << FDCAN_SBTR_S_SEG_1_Pos ) +#define FDCAN_SBTR_S_SEG_1_7 ( 0x80UL << FDCAN_SBTR_S_SEG_1_Pos ) + + +/*************** Bits definition for FDCAN_FBTR **********************/ + +#define FDCAN_FBTR_F_PRESC_Pos ( 24U ) +#define FDCAN_FBTR_F_PRESC_Msk ( 0xffUL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC ( FDCAN_FBTR_F_PRESC_Msk ) +#define FDCAN_FBTR_F_PRESC_0 ( 0x1UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_1 ( 0x2UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_2 ( 0x4UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_3 ( 0x8UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_4 ( 0x10UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_5 ( 0x20UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_6 ( 0x40UL << FDCAN_FBTR_F_PRESC_Pos ) +#define FDCAN_FBTR_F_PRESC_7 ( 0x80UL << FDCAN_FBTR_F_PRESC_Pos ) + +#define FDCAN_FBTR_F_SJW_Pos ( 16U ) +#define FDCAN_FBTR_F_SJW_Msk ( 0xfUL << FDCAN_FBTR_F_SJW_Pos ) +#define FDCAN_FBTR_F_SJW ( FDCAN_FBTR_F_SJW_Msk ) +#define FDCAN_FBTR_F_SJW_0 ( 0x1UL << FDCAN_FBTR_F_SJW_Pos ) +#define FDCAN_FBTR_F_SJW_1 ( 0x2UL << FDCAN_FBTR_F_SJW_Pos ) +#define FDCAN_FBTR_F_SJW_2 ( 0x4UL << FDCAN_FBTR_F_SJW_Pos ) +#define FDCAN_FBTR_F_SJW_3 ( 0x8UL << FDCAN_FBTR_F_SJW_Pos ) + +#define FDCAN_FBTR_F_SEG_2_Pos ( 8U ) +#define FDCAN_FBTR_F_SEG_2_Msk ( 0xfUL << FDCAN_FBTR_F_SEG_2_Pos ) +#define FDCAN_FBTR_F_SEG_2 ( FDCAN_FBTR_F_SEG_2_Msk ) +#define FDCAN_FBTR_F_SEG_2_0 ( 0x1UL << FDCAN_FBTR_F_SEG_2_Pos ) +#define FDCAN_FBTR_F_SEG_2_1 ( 0x2UL << FDCAN_FBTR_F_SEG_2_Pos ) +#define FDCAN_FBTR_F_SEG_2_2 ( 0x4UL << FDCAN_FBTR_F_SEG_2_Pos ) +#define FDCAN_FBTR_F_SEG_2_3 ( 0x8UL << FDCAN_FBTR_F_SEG_2_Pos ) + +#define FDCAN_FBTR_F_SEG_1_Pos ( 0U ) +#define FDCAN_FBTR_F_SEG_1_Msk ( 0x1fUL << FDCAN_FBTR_F_SEG_1_Pos ) +#define FDCAN_FBTR_F_SEG_1 ( FDCAN_FBTR_F_SEG_1_Msk ) +#define FDCAN_FBTR_F_SEG_1_0 ( 0x1UL << FDCAN_FBTR_F_SEG_1_Pos ) +#define FDCAN_FBTR_F_SEG_1_1 ( 0x2UL << FDCAN_FBTR_F_SEG_1_Pos ) +#define FDCAN_FBTR_F_SEG_1_2 ( 0x4UL << FDCAN_FBTR_F_SEG_1_Pos ) +#define FDCAN_FBTR_F_SEG_1_3 ( 0x8UL << FDCAN_FBTR_F_SEG_1_Pos ) +#define FDCAN_FBTR_F_SEG_1_4 ( 0x10UL << FDCAN_FBTR_F_SEG_1_Pos ) + + +/*************** Bits definition for FDCAN_TDC **********************/ + +#define FDCAN_TDC_TDCEN_Pos ( 7U ) +#define FDCAN_TDC_TDCEN_Msk ( 0x1UL << FDCAN_TDC_TDCEN_Pos ) +#define FDCAN_TDC_TDCEN ( FDCAN_TDC_TDCEN_Msk ) + +#define FDCAN_TDC_SSPOFF_Pos ( 0U ) +#define FDCAN_TDC_SSPOFF_Msk ( 0x7fUL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF ( FDCAN_TDC_SSPOFF_Msk ) +#define FDCAN_TDC_SSPOFF_0 ( 0x1UL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF_1 ( 0x2UL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF_2 ( 0x4UL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF_3 ( 0x8UL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF_4 ( 0x10UL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF_5 ( 0x20UL << FDCAN_TDC_SSPOFF_Pos ) +#define FDCAN_TDC_SSPOFF_6 ( 0x40UL << FDCAN_TDC_SSPOFF_Pos ) + + +/*************** Bits definition for FDCAN_ECC **********************/ + +#define FDCAN_ECC_TECNT_Pos ( 24U ) +#define FDCAN_ECC_TECNT_Msk ( 0xffUL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT ( FDCAN_ECC_TECNT_Msk ) +#define FDCAN_ECC_TECNT_0 ( 0x1UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_1 ( 0x2UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_2 ( 0x4UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_3 ( 0x8UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_4 ( 0x10UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_5 ( 0x20UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_6 ( 0x40UL << FDCAN_ECC_TECNT_Pos ) +#define FDCAN_ECC_TECNT_7 ( 0x80UL << FDCAN_ECC_TECNT_Pos ) + +#define FDCAN_ECC_RECNT_Pos ( 16U ) +#define FDCAN_ECC_RECNT_Msk ( 0xffUL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT ( FDCAN_ECC_RECNT_Msk ) +#define FDCAN_ECC_RECNT_0 ( 0x1UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_1 ( 0x2UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_2 ( 0x4UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_3 ( 0x8UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_4 ( 0x10UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_5 ( 0x20UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_6 ( 0x40UL << FDCAN_ECC_RECNT_Pos ) +#define FDCAN_ECC_RECNT_7 ( 0x80UL << FDCAN_ECC_RECNT_Pos ) + +#define FDCAN_ECC_KOER_Pos ( 5U ) +#define FDCAN_ECC_KOER_Msk ( 0x7UL << FDCAN_ECC_KOER_Pos ) +#define FDCAN_ECC_KOER ( FDCAN_ECC_KOER_Msk ) +#define FDCAN_ECC_KOER_0 ( 0x1UL << FDCAN_ECC_KOER_Pos ) +#define FDCAN_ECC_KOER_1 ( 0x2UL << FDCAN_ECC_KOER_Pos ) +#define FDCAN_ECC_KOER_2 ( 0x4UL << FDCAN_ECC_KOER_Pos ) + +#define FDCAN_ECC_ALC_Pos ( 0U ) +#define FDCAN_ECC_ALC_Msk ( 0x1fUL << FDCAN_ECC_ALC_Pos ) +#define FDCAN_ECC_ALC ( FDCAN_ECC_ALC_Msk ) +#define FDCAN_ECC_ALC_0 ( 0x1UL << FDCAN_ECC_ALC_Pos ) +#define FDCAN_ECC_ALC_1 ( 0x2UL << FDCAN_ECC_ALC_Pos ) +#define FDCAN_ECC_ALC_2 ( 0x4UL << FDCAN_ECC_ALC_Pos ) +#define FDCAN_ECC_ALC_3 ( 0x8UL << FDCAN_ECC_ALC_Pos ) +#define FDCAN_ECC_ALC_4 ( 0x10UL << FDCAN_ECC_ALC_Pos ) + + +/*************** Bits definition for FDCAN_ACFCR **********************/ + +#define FDCAN_ACFCR_AE_Pos ( 16U ) +#define FDCAN_ACFCR_AE_Msk ( 0xffffUL << FDCAN_ACFCR_AE_Pos ) +#define FDCAN_ACFCR_AE ( FDCAN_ACFCR_AE_Msk ) + +#define FDCAN_ACFCR_SELMASK_Pos ( 5U ) +#define FDCAN_ACFCR_SELMASK_Msk ( 0x1UL << FDCAN_ACFCR_SELMASK_Pos ) +#define FDCAN_ACFCR_SELMASK ( FDCAN_ACFCR_SELMASK_Msk ) + +#define FDCAN_ACFCR_ACFADR_Pos ( 0U ) +#define FDCAN_ACFCR_ACFADR_Msk ( 0xfUL << FDCAN_ACFCR_ACFADR_Pos ) +#define FDCAN_ACFCR_ACFADR ( FDCAN_ACFCR_ACFADR_Msk ) +#define FDCAN_ACFCR_ACFADR_0 ( 0x1UL << FDCAN_ACFCR_ACFADR_Pos ) +#define FDCAN_ACFCR_ACFADR_1 ( 0x2UL << FDCAN_ACFCR_ACFADR_Pos ) +#define FDCAN_ACFCR_ACFADR_2 ( 0x4UL << FDCAN_ACFCR_ACFADR_Pos ) +#define FDCAN_ACFCR_ACFADR_3 ( 0x8UL << FDCAN_ACFCR_ACFADR_Pos ) + + +/*************** Bits definition for FDCAN_ACODR **********************/ + +#define FDCAN_ACODR_AIDEE_Pos ( 30U ) +#define FDCAN_ACODR_AIDEE_Msk ( 0x1UL << FDCAN_ACODR_AIDEE_Pos ) +#define FDCAN_ACODR_AIDEE ( FDCAN_ACODR_AIDEE_Msk ) + +#define FDCAN_ACODR_AIDE_Pos ( 29U ) +#define FDCAN_ACODR_AIDE_Msk ( 0x1UL << FDCAN_ACODR_AIDE_Pos ) +#define FDCAN_ACODR_AIDE ( FDCAN_ACODR_AIDE_Msk ) + +#define FDCAN_ACODR_ACODE_AMASK_Pos ( 0U ) +#define FDCAN_ACODR_ACODE_AMASK_Msk ( 0x1fffffffUL << FDCAN_ACODR_ACODE_AMASK_Pos ) +#define FDCAN_ACODR_ACODE_AMASK ( FDCAN_ACODR_ACODE_AMASK_Msk ) + + +/*************** Bits definition for FDCAN_TIMCFG **********************/ + +#define FDCAN_TIMCFG_TIMEPOS_Pos ( 1U ) +#define FDCAN_TIMCFG_TIMEPOS_Msk ( 0x1UL << FDCAN_TIMCFG_TIMEPOS_Pos ) +#define FDCAN_TIMCFG_TIMEPOS ( FDCAN_TIMCFG_TIMEPOS_Msk ) + +#define FDCAN_TIMCFG_TIMEEN_Pos ( 0U ) +#define FDCAN_TIMCFG_TIMEEN_Msk ( 0x1UL << FDCAN_TIMCFG_TIMEEN_Pos ) +#define FDCAN_TIMCFG_TIMEEN ( FDCAN_TIMCFG_TIMEEN_Msk ) + + +/*************** Bits definition for FDCAN_VER **********************/ + +#define FDCAN_VER_VER_Pos ( 0U ) +#define FDCAN_VER_VER_Msk ( 0xffffUL << FDCAN_VER_VER_Pos ) +#define FDCAN_VER_VER ( FDCAN_VER_VER_Msk ) + + +/*************** Bits definition for FDCAN_TTCFG **********************/ + +#define FDCAN_TTCFG_REFMSGIE_Pos ( 17U ) +#define FDCAN_TTCFG_REFMSGIE_Msk ( 0x1UL << FDCAN_TTCFG_REFMSGIE_Pos ) +#define FDCAN_TTCFG_REFMSGIE ( FDCAN_TTCFG_REFMSGIE_Msk ) + +#define FDCAN_TTCFG_REFMSGIF_Pos ( 16U ) +#define FDCAN_TTCFG_REFMSGIF_Msk ( 0x1UL << FDCAN_TTCFG_REFMSGIF_Pos ) +#define FDCAN_TTCFG_REFMSGIF ( FDCAN_TTCFG_REFMSGIF_Msk ) + +#define FDCAN_TTCFG_WTIE_Pos ( 15U ) +#define FDCAN_TTCFG_WTIE_Msk ( 0x1UL << FDCAN_TTCFG_WTIE_Pos ) +#define FDCAN_TTCFG_WTIE ( FDCAN_TTCFG_WTIE_Msk ) + +#define FDCAN_TTCFG_WTIF_Pos ( 14U ) +#define FDCAN_TTCFG_WTIF_Msk ( 0x1UL << FDCAN_TTCFG_WTIF_Pos ) +#define FDCAN_TTCFG_WTIF ( FDCAN_TTCFG_WTIF_Msk ) + +#define FDCAN_TTCFG_TEIF_Pos ( 13U ) +#define FDCAN_TTCFG_TEIF_Msk ( 0x1UL << FDCAN_TTCFG_TEIF_Pos ) +#define FDCAN_TTCFG_TEIF ( FDCAN_TTCFG_TEIF_Msk ) + +#define FDCAN_TTCFG_TTIE_Pos ( 12U ) +#define FDCAN_TTCFG_TTIE_Msk ( 0x1UL << FDCAN_TTCFG_TTIE_Pos ) +#define FDCAN_TTCFG_TTIE ( FDCAN_TTCFG_TTIE_Msk ) + +#define FDCAN_TTCFG_TTIF_Pos ( 11U ) +#define FDCAN_TTCFG_TTIF_Msk ( 0x1UL << FDCAN_TTCFG_TTIF_Pos ) +#define FDCAN_TTCFG_TTIF ( FDCAN_TTCFG_TTIF_Msk ) + +#define FDCAN_TTCFG_T_PRESC_Pos ( 9U ) +#define FDCAN_TTCFG_T_PRESC_Msk ( 0x3UL << FDCAN_TTCFG_T_PRESC_Pos ) +#define FDCAN_TTCFG_T_PRESC ( FDCAN_TTCFG_T_PRESC_Msk ) +#define FDCAN_TTCFG_T_PRESC_0 ( 0x1UL << FDCAN_TTCFG_T_PRESC_Pos ) +#define FDCAN_TTCFG_T_PRESC_1 ( 0x2UL << FDCAN_TTCFG_T_PRESC_Pos ) + +#define FDCAN_TTCFG_TTEN_Pos ( 8U ) +#define FDCAN_TTCFG_TTEN_Msk ( 0x1UL << FDCAN_TTCFG_TTEN_Pos ) +#define FDCAN_TTCFG_TTEN ( FDCAN_TTCFG_TTEN_Msk ) + +#define FDCAN_TTCFG_TBE_Pos ( 7U ) +#define FDCAN_TTCFG_TBE_Msk ( 0x1UL << FDCAN_TTCFG_TBE_Pos ) +#define FDCAN_TTCFG_TBE ( FDCAN_TTCFG_TBE_Msk ) + +#define FDCAN_TTCFG_TBF_Pos ( 6U ) +#define FDCAN_TTCFG_TBF_Msk ( 0x1UL << FDCAN_TTCFG_TBF_Pos ) +#define FDCAN_TTCFG_TBF ( FDCAN_TTCFG_TBF_Msk ) + +#define FDCAN_TTCFG_TBPTR_Pos ( 0U ) +#define FDCAN_TTCFG_TBPTR_Msk ( 0x3fUL << FDCAN_TTCFG_TBPTR_Pos ) +#define FDCAN_TTCFG_TBPTR ( FDCAN_TTCFG_TBPTR_Msk ) +#define FDCAN_TTCFG_TBPTR_0 ( 0x1UL << FDCAN_TTCFG_TBPTR_Pos ) +#define FDCAN_TTCFG_TBPTR_1 ( 0x2UL << FDCAN_TTCFG_TBPTR_Pos ) +#define FDCAN_TTCFG_TBPTR_2 ( 0x4UL << FDCAN_TTCFG_TBPTR_Pos ) +#define FDCAN_TTCFG_TBPTR_3 ( 0x8UL << FDCAN_TTCFG_TBPTR_Pos ) +#define FDCAN_TTCFG_TBPTR_4 ( 0x10UL << FDCAN_TTCFG_TBPTR_Pos ) +#define FDCAN_TTCFG_TBPTR_5 ( 0x20UL << FDCAN_TTCFG_TBPTR_Pos ) + + +/*************** Bits definition for FDCAN_REFMSG **********************/ + +#define FDCAN_REFMSG_REF_IDE_Pos ( 31U ) +#define FDCAN_REFMSG_REF_IDE_Msk ( 0x1UL << FDCAN_REFMSG_REF_IDE_Pos ) +#define FDCAN_REFMSG_REF_IDE ( FDCAN_REFMSG_REF_IDE_Msk ) + +#define FDCAN_REFMSG_REF_ID_Pos ( 0U ) +#define FDCAN_REFMSG_REF_ID_Msk ( 0x1fffffffUL << FDCAN_REFMSG_REF_ID_Pos ) +#define FDCAN_REFMSG_REF_ID ( FDCAN_REFMSG_REF_ID_Msk ) + + +/*************** Bits definition for FDCAN_TTTRIGR **********************/ + +#define FDCAN_TTTRIGR_TT_TRIG_Pos ( 16U ) +#define FDCAN_TTTRIGR_TT_TRIG_Msk ( 0xffffUL << FDCAN_TTTRIGR_TT_TRIG_Pos ) +#define FDCAN_TTTRIGR_TT_TRIG ( FDCAN_TTTRIGR_TT_TRIG_Msk ) + +#define FDCAN_TTTRIGR_TEW_Pos ( 12U ) +#define FDCAN_TTTRIGR_TEW_Msk ( 0xfUL << FDCAN_TTTRIGR_TEW_Pos ) +#define FDCAN_TTTRIGR_TEW ( FDCAN_TTTRIGR_TEW_Msk ) +#define FDCAN_TTTRIGR_TEW_0 ( 0x1UL << FDCAN_TTTRIGR_TEW_Pos ) +#define FDCAN_TTTRIGR_TEW_1 ( 0x2UL << FDCAN_TTTRIGR_TEW_Pos ) +#define FDCAN_TTTRIGR_TEW_2 ( 0x4UL << FDCAN_TTTRIGR_TEW_Pos ) +#define FDCAN_TTTRIGR_TEW_3 ( 0x8UL << FDCAN_TTTRIGR_TEW_Pos ) + +#define FDCAN_TTTRIGR_TTYPE_Pos ( 8U ) +#define FDCAN_TTTRIGR_TTYPE_Msk ( 0x7UL << FDCAN_TTTRIGR_TTYPE_Pos ) +#define FDCAN_TTTRIGR_TTYPE ( FDCAN_TTTRIGR_TTYPE_Msk ) +#define FDCAN_TTTRIGR_TTYPE_0 ( 0x1UL << FDCAN_TTTRIGR_TTYPE_Pos ) +#define FDCAN_TTTRIGR_TTYPE_1 ( 0x2UL << FDCAN_TTTRIGR_TTYPE_Pos ) +#define FDCAN_TTTRIGR_TTYPE_2 ( 0x4UL << FDCAN_TTTRIGR_TTYPE_Pos ) + +#define FDCAN_TTTRIGR_TTPTR_Pos ( 0U ) +#define FDCAN_TTTRIGR_TTPTR_Msk ( 0x3fUL << FDCAN_TTTRIGR_TTPTR_Pos ) +#define FDCAN_TTTRIGR_TTPTR ( FDCAN_TTTRIGR_TTPTR_Msk ) +#define FDCAN_TTTRIGR_TTPTR_0 ( 0x1UL << FDCAN_TTTRIGR_TTPTR_Pos ) +#define FDCAN_TTTRIGR_TTPTR_1 ( 0x2UL << FDCAN_TTTRIGR_TTPTR_Pos ) +#define FDCAN_TTTRIGR_TTPTR_2 ( 0x4UL << FDCAN_TTTRIGR_TTPTR_Pos ) +#define FDCAN_TTTRIGR_TTPTR_3 ( 0x8UL << FDCAN_TTTRIGR_TTPTR_Pos ) +#define FDCAN_TTTRIGR_TTPTR_4 ( 0x10UL << FDCAN_TTTRIGR_TTPTR_Pos ) +#define FDCAN_TTTRIGR_TTPTR_5 ( 0x20UL << FDCAN_TTTRIGR_TTPTR_Pos ) + + +/*************** Bits definition for FDCAN_WTRIGR **********************/ + +#define FDCAN_WTRIGR_TT_WTRIG_Pos ( 0U ) +#define FDCAN_WTRIGR_TT_WTRIG_Msk ( 0xffffUL << FDCAN_WTRIGR_TT_WTRIG_Pos ) +#define FDCAN_WTRIGR_TT_WTRIG ( FDCAN_WTRIGR_TT_WTRIG_Msk ) + + +/*************** Bits definition for LPUART_RXDR **********************/ + +#define LPUART_RXDR_RXDATA_Pos ( 0U ) +#define LPUART_RXDR_RXDATA_Msk ( 0xffUL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA ( LPUART_RXDR_RXDATA_Msk ) +#define LPUART_RXDR_RXDATA_0 ( 0x1UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_1 ( 0x2UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_2 ( 0x4UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_3 ( 0x8UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_4 ( 0x10UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_5 ( 0x20UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_6 ( 0x40UL << LPUART_RXDR_RXDATA_Pos ) +#define LPUART_RXDR_RXDATA_7 ( 0x80UL << LPUART_RXDR_RXDATA_Pos ) + + +/*************** Bits definition for LPUART_TXDR **********************/ + +#define LPUART_TXDR_TXDATA_Pos ( 0U ) +#define LPUART_TXDR_TXDATA_Msk ( 0xffUL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA ( LPUART_TXDR_TXDATA_Msk ) +#define LPUART_TXDR_TXDATA_0 ( 0x1UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_1 ( 0x2UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_2 ( 0x4UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_3 ( 0x8UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_4 ( 0x10UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_5 ( 0x20UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_6 ( 0x40UL << LPUART_TXDR_TXDATA_Pos ) +#define LPUART_TXDR_TXDATA_7 ( 0x80UL << LPUART_TXDR_TXDATA_Pos ) + + +/*************** Bits definition for LPUART_LCR **********************/ + +#define LPUART_LCR_BCNT_VALUE_Pos ( 16U ) +#define LPUART_LCR_BCNT_VALUE_Msk ( 0xffffUL << LPUART_LCR_BCNT_VALUE_Pos ) +#define LPUART_LCR_BCNT_VALUE ( LPUART_LCR_BCNT_VALUE_Msk ) + +#define LPUART_LCR_AUTO_START_EN_Pos ( 15U ) +#define LPUART_LCR_AUTO_START_EN_Msk ( 0x1UL << LPUART_LCR_AUTO_START_EN_Pos ) +#define LPUART_LCR_AUTO_START_EN ( LPUART_LCR_AUTO_START_EN_Msk ) + +#define LPUART_LCR_TXPOL_Pos ( 9U ) +#define LPUART_LCR_TXPOL_Msk ( 0x1UL << LPUART_LCR_TXPOL_Pos ) +#define LPUART_LCR_TXPOL ( LPUART_LCR_TXPOL_Msk ) + +#define LPUART_LCR_RXPOL_Pos ( 8U ) +#define LPUART_LCR_RXPOL_Msk ( 0x1UL << LPUART_LCR_RXPOL_Pos ) +#define LPUART_LCR_RXPOL ( LPUART_LCR_RXPOL_Msk ) + +#define LPUART_LCR_WKCK_Pos ( 7U ) +#define LPUART_LCR_WKCK_Msk ( 0x1UL << LPUART_LCR_WKCK_Pos ) +#define LPUART_LCR_WKCK ( LPUART_LCR_WKCK_Msk ) + +#define LPUART_LCR_RXWKS_Pos ( 5U ) +#define LPUART_LCR_RXWKS_Msk ( 0x3UL << LPUART_LCR_RXWKS_Pos ) +#define LPUART_LCR_RXWKS ( LPUART_LCR_RXWKS_Msk ) +#define LPUART_LCR_RXWKS_0 ( 0x1UL << LPUART_LCR_RXWKS_Pos ) +#define LPUART_LCR_RXWKS_1 ( 0x2UL << LPUART_LCR_RXWKS_Pos ) + +#define LPUART_LCR_WLEN_Pos ( 4U ) +#define LPUART_LCR_WLEN_Msk ( 0x1UL << LPUART_LCR_WLEN_Pos ) +#define LPUART_LCR_WLEN ( LPUART_LCR_WLEN_Msk ) + +#define LPUART_LCR_STP2_Pos ( 3U ) +#define LPUART_LCR_STP2_Msk ( 0x1UL << LPUART_LCR_STP2_Pos ) +#define LPUART_LCR_STP2 ( LPUART_LCR_STP2_Msk ) + +#define LPUART_LCR_EPS_Pos ( 2U ) +#define LPUART_LCR_EPS_Msk ( 0x1UL << LPUART_LCR_EPS_Pos ) +#define LPUART_LCR_EPS ( LPUART_LCR_EPS_Msk ) + +#define LPUART_LCR_SPS_Pos ( 1U ) +#define LPUART_LCR_SPS_Msk ( 0x1UL << LPUART_LCR_SPS_Pos ) +#define LPUART_LCR_SPS ( LPUART_LCR_SPS_Msk ) + +#define LPUART_LCR_PEN_Pos ( 0U ) +#define LPUART_LCR_PEN_Msk ( 0x1UL << LPUART_LCR_PEN_Pos ) +#define LPUART_LCR_PEN ( LPUART_LCR_PEN_Msk ) + + +/*************** Bits definition for LPUART_CR **********************/ + +#define LPUART_CR_DMA_EN_Pos ( 2U ) +#define LPUART_CR_DMA_EN_Msk ( 0x1UL << LPUART_CR_DMA_EN_Pos ) +#define LPUART_CR_DMA_EN ( LPUART_CR_DMA_EN_Msk ) + +#define LPUART_CR_TX_EN_Pos ( 1U ) +#define LPUART_CR_TX_EN_Msk ( 0x1UL << LPUART_CR_TX_EN_Pos ) +#define LPUART_CR_TX_EN ( LPUART_CR_TX_EN_Msk ) + +#define LPUART_CR_RX_EN_Pos ( 0U ) +#define LPUART_CR_RX_EN_Msk ( 0x1UL << LPUART_CR_RX_EN_Pos ) +#define LPUART_CR_RX_EN ( LPUART_CR_RX_EN_Msk ) + + +/*************** Bits definition for LPUART_IBAUD **********************/ + +#define LPUART_IBAUD_RXSAM_Pos ( 8U ) +#define LPUART_IBAUD_RXSAM_Msk ( 0xffUL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM ( LPUART_IBAUD_RXSAM_Msk ) +#define LPUART_IBAUD_RXSAM_0 ( 0x1UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_1 ( 0x2UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_2 ( 0x4UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_3 ( 0x8UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_4 ( 0x10UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_5 ( 0x20UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_6 ( 0x40UL << LPUART_IBAUD_RXSAM_Pos ) +#define LPUART_IBAUD_RXSAM_7 ( 0x80UL << LPUART_IBAUD_RXSAM_Pos ) + +#define LPUART_IBAUD_IBAUD_Pos ( 0U ) +#define LPUART_IBAUD_IBAUD_Msk ( 0xffUL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD ( LPUART_IBAUD_IBAUD_Msk ) +#define LPUART_IBAUD_IBAUD_0 ( 0x1UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_1 ( 0x2UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_2 ( 0x4UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_3 ( 0x8UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_4 ( 0x10UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_5 ( 0x20UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_6 ( 0x40UL << LPUART_IBAUD_IBAUD_Pos ) +#define LPUART_IBAUD_IBAUD_7 ( 0x80UL << LPUART_IBAUD_IBAUD_Pos ) + + +/*************** Bits definition for LPUART_FBAUD **********************/ + +#define LPUART_FBAUD_FBAUD_Pos ( 0U ) +#define LPUART_FBAUD_FBAUD_Msk ( 0xfffUL << LPUART_FBAUD_FBAUD_Pos ) +#define LPUART_FBAUD_FBAUD ( LPUART_FBAUD_FBAUD_Msk ) + + +/*************** Bits definition for LPUART_IE **********************/ + +#define LPUART_IE_IDLEIE_Pos ( 17U ) +#define LPUART_IE_IDLEIE_Msk ( 0x1UL << LPUART_IE_IDLEIE_Pos ) +#define LPUART_IE_IDLEIE ( LPUART_IE_IDLEIE_Msk ) + +#define LPUART_IE_BCNTIE_Pos ( 16U ) +#define LPUART_IE_BCNTIE_Msk ( 0x1UL << LPUART_IE_BCNTIE_Pos ) +#define LPUART_IE_BCNTIE ( LPUART_IE_BCNTIE_Msk ) + +#define LPUART_IE_STARTIE_Pos ( 9U ) +#define LPUART_IE_STARTIE_Msk ( 0x1UL << LPUART_IE_STARTIE_Pos ) +#define LPUART_IE_STARTIE ( LPUART_IE_STARTIE_Msk ) + +#define LPUART_IE_MATCHIE_Pos ( 8U ) +#define LPUART_IE_MATCHIE_Msk ( 0x1UL << LPUART_IE_MATCHIE_Pos ) +#define LPUART_IE_MATCHIE ( LPUART_IE_MATCHIE_Msk ) + +#define LPUART_IE_RXOVIE_Pos ( 5U ) +#define LPUART_IE_RXOVIE_Msk ( 0x1UL << LPUART_IE_RXOVIE_Pos ) +#define LPUART_IE_RXOVIE ( LPUART_IE_RXOVIE_Msk ) + +#define LPUART_IE_FEIE_Pos ( 4U ) +#define LPUART_IE_FEIE_Msk ( 0x1UL << LPUART_IE_FEIE_Pos ) +#define LPUART_IE_FEIE ( LPUART_IE_FEIE_Msk ) + +#define LPUART_IE_PEIE_Pos ( 3U ) +#define LPUART_IE_PEIE_Msk ( 0x1UL << LPUART_IE_PEIE_Pos ) +#define LPUART_IE_PEIE ( LPUART_IE_PEIE_Msk ) + +#define LPUART_IE_TXEIE_Pos ( 2U ) +#define LPUART_IE_TXEIE_Msk ( 0x1UL << LPUART_IE_TXEIE_Pos ) +#define LPUART_IE_TXEIE ( LPUART_IE_TXEIE_Msk ) + +#define LPUART_IE_TCIE_Pos ( 1U ) +#define LPUART_IE_TCIE_Msk ( 0x1UL << LPUART_IE_TCIE_Pos ) +#define LPUART_IE_TCIE ( LPUART_IE_TCIE_Msk ) + +#define LPUART_IE_RXIE_Pos ( 0U ) +#define LPUART_IE_RXIE_Msk ( 0x1UL << LPUART_IE_RXIE_Pos ) +#define LPUART_IE_RXIE ( LPUART_IE_RXIE_Msk ) + + +/*************** Bits definition for LPUART_SR **********************/ + +#define LPUART_SR_IDLEIF_Pos ( 17U ) +#define LPUART_SR_IDLEIF_Msk ( 0x1UL << LPUART_SR_IDLEIF_Pos ) +#define LPUART_SR_IDLEIF ( LPUART_SR_IDLEIF_Msk ) + +#define LPUART_SR_BCNTIF_Pos ( 16U ) +#define LPUART_SR_BCNTIF_Msk ( 0x1UL << LPUART_SR_BCNTIF_Pos ) +#define LPUART_SR_BCNTIF ( LPUART_SR_BCNTIF_Msk ) + +#define LPUART_SR_TXE_Pos ( 10U ) +#define LPUART_SR_TXE_Msk ( 0x1UL << LPUART_SR_TXE_Pos ) +#define LPUART_SR_TXE ( LPUART_SR_TXE_Msk ) + +#define LPUART_SR_STARTIF_Pos ( 9U ) +#define LPUART_SR_STARTIF_Msk ( 0x1UL << LPUART_SR_STARTIF_Pos ) +#define LPUART_SR_STARTIF ( LPUART_SR_STARTIF_Msk ) + +#define LPUART_SR_MATCHIF_Pos ( 8U ) +#define LPUART_SR_MATCHIF_Msk ( 0x1UL << LPUART_SR_MATCHIF_Pos ) +#define LPUART_SR_MATCHIF ( LPUART_SR_MATCHIF_Msk ) + +#define LPUART_SR_TXOVF_Pos ( 7U ) +#define LPUART_SR_TXOVF_Msk ( 0x1UL << LPUART_SR_TXOVF_Pos ) +#define LPUART_SR_TXOVF ( LPUART_SR_TXOVF_Msk ) + +#define LPUART_SR_RXF_Pos ( 6U ) +#define LPUART_SR_RXF_Msk ( 0x1UL << LPUART_SR_RXF_Pos ) +#define LPUART_SR_RXF ( LPUART_SR_RXF_Msk ) + +#define LPUART_SR_RXOVIF_Pos ( 5U ) +#define LPUART_SR_RXOVIF_Msk ( 0x1UL << LPUART_SR_RXOVIF_Pos ) +#define LPUART_SR_RXOVIF ( LPUART_SR_RXOVIF_Msk ) + +#define LPUART_SR_FEIF_Pos ( 4U ) +#define LPUART_SR_FEIF_Msk ( 0x1UL << LPUART_SR_FEIF_Pos ) +#define LPUART_SR_FEIF ( LPUART_SR_FEIF_Msk ) + +#define LPUART_SR_PEIF_Pos ( 3U ) +#define LPUART_SR_PEIF_Msk ( 0x1UL << LPUART_SR_PEIF_Pos ) +#define LPUART_SR_PEIF ( LPUART_SR_PEIF_Msk ) + +#define LPUART_SR_TXEIF_Pos ( 2U ) +#define LPUART_SR_TXEIF_Msk ( 0x1UL << LPUART_SR_TXEIF_Pos ) +#define LPUART_SR_TXEIF ( LPUART_SR_TXEIF_Msk ) + +#define LPUART_SR_TCIF_Pos ( 1U ) +#define LPUART_SR_TCIF_Msk ( 0x1UL << LPUART_SR_TCIF_Pos ) +#define LPUART_SR_TCIF ( LPUART_SR_TCIF_Msk ) + +#define LPUART_SR_RXIF_Pos ( 0U ) +#define LPUART_SR_RXIF_Msk ( 0x1UL << LPUART_SR_RXIF_Pos ) +#define LPUART_SR_RXIF ( LPUART_SR_RXIF_Msk ) + + +/*************** Bits definition for LPUART_ADDR **********************/ + +#define LPUART_ADDR_ADDR_Pos ( 0U ) +#define LPUART_ADDR_ADDR_Msk ( 0xffUL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR ( LPUART_ADDR_ADDR_Msk ) +#define LPUART_ADDR_ADDR_0 ( 0x1UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_1 ( 0x2UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_2 ( 0x4UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_3 ( 0x8UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_4 ( 0x10UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_5 ( 0x20UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_6 ( 0x40UL << LPUART_ADDR_ADDR_Pos ) +#define LPUART_ADDR_ADDR_7 ( 0x80UL << LPUART_ADDR_ADDR_Pos ) + + +/*************** Bits definition for I2S_TXDR **********************/ + +#define I2S_TXDR_TXDR_Pos ( 0 ) +#define I2S_TXDR_TXDR_Msk ( 0xFFFFFFFFUL << I2S_TXDR_TXDR_Pos ) +#define I2S_TXDR_TXDR ( I2S_TXDR_TXDR_Msk ) + +/*************** Bits definition for I2S_RXDR **********************/ + +#define I2S_RXDR_RXDR_Pos ( 0U ) +#define I2S_RXDR_RXDR_Msk ( 0xFFFFFFFFUL << I2S_RXDR_RXDR_Pos ) +#define I2S_RXDR_RXDR ( I2S_RXDR_RXDR_Msk ) + +/*************** Bits definition for I2S_CR **********************/ + +#define I2S_CR_TXDMAEN_Pos ( 16U ) +#define I2S_CR_TXDMAEN_Msk ( 0x1UL << I2S_CR_TXDMAEN_Pos ) +#define I2S_CR_TXDMAEN ( I2S_CR_TXDMAEN_Msk ) + +#define I2S_CR_RXDMAEN_Pos ( 15U ) +#define I2S_CR_RXDMAEN_Msk ( 0x1UL << I2S_CR_RXDMAEN_Pos ) +#define I2S_CR_RXDMAEN ( I2S_CR_RXDMAEN_Msk ) + +#define I2S_CR_STOP_Pos ( 14U ) +#define I2S_CR_STOP_Msk ( 0x1UL << I2S_CR_STOP_Pos ) +#define I2S_CR_STOP ( I2S_CR_STOP_Msk ) + +#define I2S_CR_START_Pos ( 13U ) +#define I2S_CR_START_Msk ( 0x1UL << I2S_CR_START_Pos ) +#define I2S_CR_START ( I2S_CR_START_Msk ) + +#define I2S_CR_IOSWP_Pos ( 12U ) +#define I2S_CR_IOSWP_Msk ( 0x1UL << I2S_CR_IOSWP_Pos ) +#define I2S_CR_IOSWP ( I2S_CR_IOSWP_Msk ) + +#define I2S_CR_EN_Pos ( 11U ) +#define I2S_CR_EN_Msk ( 0x1UL << I2S_CR_EN_Pos ) +#define I2S_CR_EN ( I2S_CR_EN_Msk ) + +#define I2S_CR_REN_Pos ( 10U ) +#define I2S_CR_REN_Msk ( 0x1UL << I2S_CR_REN_Pos ) +#define I2S_CR_REN ( I2S_CR_REN_Msk ) + +#define I2S_CR_TEN_Pos ( 9U ) +#define I2S_CR_TEN_Msk ( 0x1UL << I2S_CR_TEN_Pos ) +#define I2S_CR_TEN ( I2S_CR_TEN_Msk ) + +#define I2S_CR_MODE_Pos ( 8U ) +#define I2S_CR_MODE_Msk ( 0x1UL << I2S_CR_MODE_Pos ) +#define I2S_CR_MODE ( I2S_CR_MODE_Msk ) + +#define I2S_CR_PCMMODE_Pos ( 7U ) +#define I2S_CR_PCMMODE_Msk ( 0x1UL << I2S_CR_PCMMODE_Pos ) +#define I2S_CR_PCMMODE ( I2S_CR_PCMMODE_Msk ) + +#define I2S_CR_STD_Pos ( 4U ) +#define I2S_CR_STD_Msk ( 0x3UL << I2S_CR_STD_Pos ) +#define I2S_CR_STD ( I2S_CR_STD_Msk ) +#define I2S_CR_STD_0 ( 0x1UL << I2S_CR_STD_Pos ) +#define I2S_CR_STD_1 ( 0x2UL << I2S_CR_STD_Pos ) + +#define I2S_CR_CKPL_Pos ( 3U ) +#define I2S_CR_CKPL_Msk ( 0x1UL << I2S_CR_CKPL_Pos ) +#define I2S_CR_CKPL ( I2S_CR_CKPL_Msk ) + +#define I2S_CR_DLEN_Pos ( 1U ) +#define I2S_CR_DLEN_Msk ( 0x3UL << I2S_CR_DLEN_Pos ) +#define I2S_CR_DLEN ( I2S_CR_DLEN_Msk ) +#define I2S_CR_DLEN_0 ( 0x1UL << I2S_CR_DLEN_Pos ) +#define I2S_CR_DLEN_1 ( 0x2UL << I2S_CR_DLEN_Pos ) + + +#define I2S_CR_CHLEN_Pos ( 0U ) +#define I2S_CR_CHLEN_Msk ( 0x1UL << I2S_CR_CHLEN_Pos ) +#define I2S_CR_CHLEN ( I2S_CR_CHLEN_Msk ) + + +/*************** Bits definition for I2S_PR **********************/ + +#define I2S_PR_MCKOE_Pos ( 10U ) +#define I2S_PR_MCKOE_Msk ( 0x1UL << I2S_PR_MCKOE_Pos ) +#define I2S_PR_MCKOE ( I2S_PR_MCKOE_Msk ) + +#define I2S_PR_OF_Pos ( 9U ) +#define I2S_PR_OF_Msk ( 0x1UL << I2S_PR_OF_Pos ) +#define I2S_PR_OF ( I2S_PR_OF_Msk ) + +#define I2S_PR_DIV_Pos ( 0U ) +#define I2S_PR_DIV_Msk ( 0x1FFUL << I2S_PR_DIV_Pos ) +#define I2S_PR_DIV ( I2S_PR_DIV_Msk ) + + +/*************** Bits definition for I2S_DIER **********************/ + +#define I2S_DIER_SVTCIE_Pos ( 10U ) +#define I2S_DIER_SVTCIE_Msk ( 0x1UL << I2S_DIER_SVTCIE_Pos ) +#define I2S_DIER_SVTCIE ( I2S_DIER_SVTCIE_Msk ) + +#define I2S_DIER_MSUSPIE_Pos ( 9U ) +#define I2S_DIER_MSUSPIE_Msk ( 0x1UL << I2S_DIER_MSUSPIE_Pos ) +#define I2S_DIER_MSUSPIE ( I2S_DIER_MSUSPIE_Msk ) + +#define I2S_DIER_ERRIE_Pos ( 5U ) +#define I2S_DIER_ERRIE_Msk ( 0x1UL << I2S_DIER_ERRIE_Pos ) +#define I2S_DIER_ERRIE ( I2S_DIER_ERRIE_Msk ) + +#define I2S_DIER_TXEIE_Pos ( 1U ) +#define I2S_DIER_TXEIE_Msk ( 0x1UL << I2S_DIER_TXEIE_Pos ) +#define I2S_DIER_TXEIE ( I2S_DIER_TXEIE_Msk ) + +#define I2S_DIER_RXNEIE_Pos ( 0U ) +#define I2S_DIER_RXNEIE_Msk ( 0x1UL << I2S_DIER_RXNEIE_Pos ) +#define I2S_DIER_RXNEIE ( I2S_DIER_RXNEIE_Msk ) + + +/*************** Bits definition for I2S_SR **********************/ + +#define I2S_SR_SVTC_Pos ( 10U ) +#define I2S_SR_SVTC_Msk ( 0x1UL << I2S_SR_SVTC_Pos ) +#define I2S_SR_SVTC ( I2S_SR_SVTC_Msk ) + +#define I2S_SR_MSUSP_Pos ( 9U ) +#define I2S_SR_MSUSP_Msk ( 0x1UL << I2S_SR_MSUSP_Pos ) +#define I2S_SR_MSUSP ( I2S_SR_MSUSP_Msk ) + +#define I2S_SR_FE_Pos ( 5U ) +#define I2S_SR_FE_Msk ( 0x1UL << I2S_SR_FE_Pos ) +#define I2S_SR_FE ( I2S_SR_FE_Msk ) + +#define I2S_SR_OVR_Pos ( 4U ) +#define I2S_SR_OVR_Msk ( 0x1UL << I2S_SR_OVR_Pos ) +#define I2S_SR_OVR ( I2S_SR_OVR_Msk ) + +#define I2S_SR_UDR_Pos ( 3U ) +#define I2S_SR_UDR_Msk ( 0x1UL << I2S_SR_UDR_Pos ) +#define I2S_SR_UDR ( I2S_SR_UDR_Msk ) + +#define I2S_SR_CH_Pos ( 2U ) +#define I2S_SR_CH_Msk ( 0x1UL << I2S_SR_CH_Pos ) +#define I2S_SR_CH ( I2S_SR_CH_Msk ) + +#define I2S_SR_TXE_Pos ( 1U ) +#define I2S_SR_TXE_Msk ( 0x1UL << I2S_SR_TXE_Pos ) +#define I2S_SR_TXE ( I2S_SR_TXE_Msk ) + +#define I2S_SR_RXNE_Pos ( 0U ) +#define I2S_SR_RXNE_Msk ( 0x1UL << I2S_SR_RXNE_Pos ) +#define I2S_SR_RXNE ( I2S_SR_RXNE_Msk ) + + +/*************** Bits definition for I2S_RSIZE **********************/ + +#define I2S_RSIZE_RSIZE_Pos ( 0U ) +#define I2S_RSIZE_RSIZE_Msk ( 0xFFFFUL << I2S_RSIZE_RSIZE_Pos ) +#define I2S_RSIZE_RSIZE ( I2S_RSIZE_RSIZE_Msk ) + + +/*************** Bits definition for ETH_MACCR **********************/ + +#define ETH_MACCR_SARC_Pos ( 28U ) +#define ETH_MACCR_SARC_Msk ( 0x7UL << ETH_MACCR_SARC_Pos ) +#define ETH_MACCR_SARC ( ETH_MACCR_SARC_Msk ) +#define ETH_MACCR_SARC_0 ( 0x1UL << ETH_MACCR_SARC_Pos ) +#define ETH_MACCR_SARC_1 ( 0x2UL << ETH_MACCR_SARC_Pos ) +#define ETH_MACCR_SARC_2 ( 0x4UL << ETH_MACCR_SARC_Pos ) + +#define ETH_MACCR_S2KP_Pos ( 27U ) +#define ETH_MACCR_S2KP_Msk ( 0x1UL << ETH_MACCR_S2KP_Pos ) +#define ETH_MACCR_S2KP ( ETH_MACCR_S2KP_Msk ) + +#define ETH_MACCR_CSTF_Pos ( 25U ) +#define ETH_MACCR_CSTF_Msk ( 0x1UL << ETH_MACCR_CSTF_Pos ) +#define ETH_MACCR_CSTF ( ETH_MACCR_CSTF_Msk ) + +#define ETH_MACCR_WD_Pos ( 23U ) +#define ETH_MACCR_WD_Msk ( 0x1UL << ETH_MACCR_WD_Pos ) +#define ETH_MACCR_WD ( ETH_MACCR_WD_Msk ) + +#define ETH_MACCR_JD_Pos ( 22U ) +#define ETH_MACCR_JD_Msk ( 0x1UL << ETH_MACCR_JD_Pos ) +#define ETH_MACCR_JD ( ETH_MACCR_JD_Msk ) + +#define ETH_MACCR_JE_Pos ( 20U ) +#define ETH_MACCR_JE_Msk ( 0x1UL << ETH_MACCR_JE_Pos ) +#define ETH_MACCR_JE ( ETH_MACCR_JE_Msk ) + +#define ETH_MACCR_IFG_Pos ( 17U ) +#define ETH_MACCR_IFG_Msk ( 0x7UL << ETH_MACCR_IFG_Pos ) +#define ETH_MACCR_IFG ( ETH_MACCR_IFG_Msk ) +#define ETH_MACCR_IFG_0 ( 0x1UL << ETH_MACCR_IFG_Pos ) +#define ETH_MACCR_IFG_1 ( 0x2UL << ETH_MACCR_IFG_Pos ) +#define ETH_MACCR_IFG_2 ( 0x4UL << ETH_MACCR_IFG_Pos ) + +#define ETH_MACCR_CSD_Pos ( 16U ) +#define ETH_MACCR_CSD_Msk ( 0x1UL << ETH_MACCR_CSD_Pos ) +#define ETH_MACCR_CSD ( ETH_MACCR_CSD_Msk ) + +#define ETH_MACCR_FES_Pos ( 14U ) +#define ETH_MACCR_FES_Msk ( 0x1UL << ETH_MACCR_FES_Pos ) +#define ETH_MACCR_FES ( ETH_MACCR_FES_Msk ) + +#define ETH_MACCR_ROD_Pos ( 13U ) +#define ETH_MACCR_ROD_Msk ( 0x1UL << ETH_MACCR_ROD_Pos ) +#define ETH_MACCR_ROD ( ETH_MACCR_ROD_Msk ) + +#define ETH_MACCR_LM_Pos ( 12U ) +#define ETH_MACCR_LM_Msk ( 0x1UL << ETH_MACCR_LM_Pos ) +#define ETH_MACCR_LM ( ETH_MACCR_LM_Msk ) + +#define ETH_MACCR_DM_Pos ( 11U ) +#define ETH_MACCR_DM_Msk ( 0x1UL << ETH_MACCR_DM_Pos ) +#define ETH_MACCR_DM ( ETH_MACCR_DM_Msk ) + +#define ETH_MACCR_IPCO_Pos ( 10U ) +#define ETH_MACCR_IPCO_Msk ( 0x1UL << ETH_MACCR_IPCO_Pos ) +#define ETH_MACCR_IPCO ( ETH_MACCR_IPCO_Msk ) + +#define ETH_MACCR_DR_Pos ( 9U ) +#define ETH_MACCR_DR_Msk ( 0x1UL << ETH_MACCR_DR_Pos ) +#define ETH_MACCR_DR ( ETH_MACCR_DR_Msk ) + +#define ETH_MACCR_APCS_Pos ( 7U ) +#define ETH_MACCR_APCS_Msk ( 0x1UL << ETH_MACCR_APCS_Pos ) +#define ETH_MACCR_APCS ( ETH_MACCR_APCS_Msk ) + +#define ETH_MACCR_BL_Pos ( 5U ) +#define ETH_MACCR_BL_Msk ( 0x3UL << ETH_MACCR_BL_Pos ) +#define ETH_MACCR_BL ( ETH_MACCR_BL_Msk ) +#define ETH_MACCR_BL_0 ( 0x1UL << ETH_MACCR_BL_Pos ) +#define ETH_MACCR_BL_1 ( 0x2UL << ETH_MACCR_BL_Pos ) + +#define ETH_MACCR_DC_Pos ( 4U ) +#define ETH_MACCR_DC_Msk ( 0x1UL << ETH_MACCR_DC_Pos ) +#define ETH_MACCR_DC ( ETH_MACCR_DC_Msk ) + +#define ETH_MACCR_TE_Pos ( 3U ) +#define ETH_MACCR_TE_Msk ( 0x1UL << ETH_MACCR_TE_Pos ) +#define ETH_MACCR_TE ( ETH_MACCR_TE_Msk ) + +#define ETH_MACCR_RE_Pos ( 2U ) +#define ETH_MACCR_RE_Msk ( 0x1UL << ETH_MACCR_RE_Pos ) +#define ETH_MACCR_RE ( ETH_MACCR_RE_Msk ) + +#define ETH_MACCR_PRELEN_Pos ( 0U ) +#define ETH_MACCR_PRELEN_Msk ( 0x3UL << ETH_MACCR_PRELEN_Pos ) +#define ETH_MACCR_PRELEN ( ETH_MACCR_PRELEN_Msk ) +#define ETH_MACCR_PRELEN_0 ( 0x1UL << ETH_MACCR_PRELEN_Pos ) +#define ETH_MACCR_PRELEN_1 ( 0x2UL << ETH_MACCR_PRELEN_Pos ) + + +/*************** Bits definition for ETH_MACFFR **********************/ + +#define ETH_MACFFR_RA_Pos ( 31U ) +#define ETH_MACFFR_RA_Msk ( 0x1UL << ETH_MACFFR_RA_Pos ) +#define ETH_MACFFR_RA ( ETH_MACFFR_RA_Msk ) + +#define ETH_MACFFR_DNTU_Pos ( 21U ) +#define ETH_MACFFR_DNTU_Msk ( 0x1UL << ETH_MACFFR_DNTU_Pos ) +#define ETH_MACFFR_DNTU ( ETH_MACFFR_DNTU_Msk ) + +#define ETH_MACFFR_IPFE_Pos ( 20U ) +#define ETH_MACFFR_IPFE_Msk ( 0x1UL << ETH_MACFFR_IPFE_Pos ) +#define ETH_MACFFR_IPFE ( ETH_MACFFR_IPFE_Msk ) + +#define ETH_MACFFR_VTFE_Pos ( 16U ) +#define ETH_MACFFR_VTFE_Msk ( 0x1UL << ETH_MACFFR_VTFE_Pos ) +#define ETH_MACFFR_VTFE ( ETH_MACFFR_VTFE_Msk ) + +#define ETH_MACFFR_HPF_Pos ( 10U ) +#define ETH_MACFFR_HPF_Msk ( 0x1UL << ETH_MACFFR_HPF_Pos ) +#define ETH_MACFFR_HPF ( ETH_MACFFR_HPF_Msk ) + +#define ETH_MACFFR_SAF_Pos ( 9U ) +#define ETH_MACFFR_SAF_Msk ( 0x1UL << ETH_MACFFR_SAF_Pos ) +#define ETH_MACFFR_SAF ( ETH_MACFFR_SAF_Msk ) + +#define ETH_MACFFR_SAIF_Pos ( 8U ) +#define ETH_MACFFR_SAIF_Msk ( 0x1UL << ETH_MACFFR_SAIF_Pos ) +#define ETH_MACFFR_SAIF ( ETH_MACFFR_SAIF_Msk ) + +#define ETH_MACFFR_PCF_Pos ( 6U ) +#define ETH_MACFFR_PCF_Msk ( 0x3UL << ETH_MACFFR_PCF_Pos ) +#define ETH_MACFFR_PCF ( ETH_MACFFR_PCF_Msk ) +#define ETH_MACFFR_PCF_0 ( 0x1UL << ETH_MACFFR_PCF_Pos ) +#define ETH_MACFFR_PCF_1 ( 0x2UL << ETH_MACFFR_PCF_Pos ) + +#define ETH_MACFFR_DBF_Pos ( 5U ) +#define ETH_MACFFR_DBF_Msk ( 0x1UL << ETH_MACFFR_DBF_Pos ) +#define ETH_MACFFR_DBF ( ETH_MACFFR_DBF_Msk ) + +#define ETH_MACFFR_PAM_Pos ( 4U ) +#define ETH_MACFFR_PAM_Msk ( 0x1UL << ETH_MACFFR_PAM_Pos ) +#define ETH_MACFFR_PAM ( ETH_MACFFR_PAM_Msk ) + +#define ETH_MACFFR_DAIF_Pos ( 3U ) +#define ETH_MACFFR_DAIF_Msk ( 0x1UL << ETH_MACFFR_DAIF_Pos ) +#define ETH_MACFFR_DAIF ( ETH_MACFFR_DAIF_Msk ) + +#define ETH_MACFFR_HMC_Pos ( 2U ) +#define ETH_MACFFR_HMC_Msk ( 0x1UL << ETH_MACFFR_HMC_Pos ) +#define ETH_MACFFR_HMC ( ETH_MACFFR_HMC_Msk ) + +#define ETH_MACFFR_HUC_Pos ( 1U ) +#define ETH_MACFFR_HUC_Msk ( 0x1UL << ETH_MACFFR_HUC_Pos ) +#define ETH_MACFFR_HUC ( ETH_MACFFR_HUC_Msk ) + +#define ETH_MACFFR_PR_Pos ( 0U ) +#define ETH_MACFFR_PR_Msk ( 0x1UL << ETH_MACFFR_PR_Pos ) +#define ETH_MACFFR_PR ( ETH_MACFFR_PR_Msk ) + + +/*************** Bits definition for ETH_MACHTHR **********************/ + +#define ETH_MACHTHR_HTH_Pos ( 0U ) +#define ETH_MACHTHR_HTH_Msk ( 0xffffffffUL << ETH_MACHTHR_HTH_Pos ) +#define ETH_MACHTHR_HTH ( ETH_MACHTHR_HTH_Msk ) + + +/*************** Bits definition for ETH_MACHTLR **********************/ + +#define ETH_MACHTLR_HTL_Pos ( 0U ) +#define ETH_MACHTLR_HTL_Msk ( 0xffffffffUL << ETH_MACHTLR_HTL_Pos ) +#define ETH_MACHTLR_HTL ( ETH_MACHTLR_HTL_Msk ) + + +/*************** Bits definition for ETH_MACMIIAR **********************/ + +#define ETH_MACMIIAR_PA_Pos ( 11U ) +#define ETH_MACMIIAR_PA_Msk ( 0x1fUL << ETH_MACMIIAR_PA_Pos ) +#define ETH_MACMIIAR_PA ( ETH_MACMIIAR_PA_Msk ) +#define ETH_MACMIIAR_PA_0 ( 0x1UL << ETH_MACMIIAR_PA_Pos ) +#define ETH_MACMIIAR_PA_1 ( 0x2UL << ETH_MACMIIAR_PA_Pos ) +#define ETH_MACMIIAR_PA_2 ( 0x4UL << ETH_MACMIIAR_PA_Pos ) +#define ETH_MACMIIAR_PA_3 ( 0x8UL << ETH_MACMIIAR_PA_Pos ) +#define ETH_MACMIIAR_PA_4 ( 0x10UL << ETH_MACMIIAR_PA_Pos ) + +#define ETH_MACMIIAR_MR_Pos ( 6U ) +#define ETH_MACMIIAR_MR_Msk ( 0x1fUL << ETH_MACMIIAR_MR_Pos ) +#define ETH_MACMIIAR_MR ( ETH_MACMIIAR_MR_Msk ) +#define ETH_MACMIIAR_MR_0 ( 0x1UL << ETH_MACMIIAR_MR_Pos ) +#define ETH_MACMIIAR_MR_1 ( 0x2UL << ETH_MACMIIAR_MR_Pos ) +#define ETH_MACMIIAR_MR_2 ( 0x4UL << ETH_MACMIIAR_MR_Pos ) +#define ETH_MACMIIAR_MR_3 ( 0x8UL << ETH_MACMIIAR_MR_Pos ) +#define ETH_MACMIIAR_MR_4 ( 0x10UL << ETH_MACMIIAR_MR_Pos ) + +#define ETH_MACMIIAR_CR_Pos ( 2U ) +#define ETH_MACMIIAR_CR_Msk ( 0xfUL << ETH_MACMIIAR_CR_Pos ) +#define ETH_MACMIIAR_CR ( ETH_MACMIIAR_CR_Msk ) +#define ETH_MACMIIAR_CR_0 ( 0x1UL << ETH_MACMIIAR_CR_Pos ) +#define ETH_MACMIIAR_CR_1 ( 0x2UL << ETH_MACMIIAR_CR_Pos ) +#define ETH_MACMIIAR_CR_2 ( 0x4UL << ETH_MACMIIAR_CR_Pos ) +#define ETH_MACMIIAR_CR_3 ( 0x8UL << ETH_MACMIIAR_CR_Pos ) + +#define ETH_MACMIIAR_MW_Pos ( 1U ) +#define ETH_MACMIIAR_MW_Msk ( 0x1UL << ETH_MACMIIAR_MW_Pos ) +#define ETH_MACMIIAR_MW ( ETH_MACMIIAR_MW_Msk ) + +#define ETH_MACMIIAR_MB_Pos ( 0U ) +#define ETH_MACMIIAR_MB_Msk ( 0x1UL << ETH_MACMIIAR_MB_Pos ) +#define ETH_MACMIIAR_MB ( ETH_MACMIIAR_MB_Msk ) + + +/*************** Bits definition for ETH_MACMIIDR **********************/ + +#define ETH_MACMIIDR_MD_Pos ( 0U ) +#define ETH_MACMIIDR_MD_Msk ( 0xffffUL << ETH_MACMIIDR_MD_Pos ) +#define ETH_MACMIIDR_MD ( ETH_MACMIIDR_MD_Msk ) + + +/*************** Bits definition for ETH_MACFCR **********************/ + +#define ETH_MACFCR_PT_Pos ( 16U ) +#define ETH_MACFCR_PT_Msk ( 0xffffUL << ETH_MACFCR_PT_Pos ) +#define ETH_MACFCR_PT ( ETH_MACFCR_PT_Msk ) + +#define ETH_MACFCR_DZQP_Pos ( 7U ) +#define ETH_MACFCR_DZQP_Msk ( 0x1UL << ETH_MACFCR_DZQP_Pos ) +#define ETH_MACFCR_DZQP ( ETH_MACFCR_DZQP_Msk ) + +#define ETH_MACFCR_PLT_Pos ( 4U ) +#define ETH_MACFCR_PLT_Msk ( 0x3UL << ETH_MACFCR_PLT_Pos ) +#define ETH_MACFCR_PLT ( ETH_MACFCR_PLT_Msk ) +#define ETH_MACFCR_PLT_0 ( 0x1UL << ETH_MACFCR_PLT_Pos ) +#define ETH_MACFCR_PLT_1 ( 0x2UL << ETH_MACFCR_PLT_Pos ) + +#define ETH_MACFCR_UPFD_Pos ( 3U ) +#define ETH_MACFCR_UPFD_Msk ( 0x1UL << ETH_MACFCR_UPFD_Pos ) +#define ETH_MACFCR_UPFD ( ETH_MACFCR_UPFD_Msk ) + +#define ETH_MACFCR_RFCE_Pos ( 2U ) +#define ETH_MACFCR_RFCE_Msk ( 0x1UL << ETH_MACFCR_RFCE_Pos ) +#define ETH_MACFCR_RFCE ( ETH_MACFCR_RFCE_Msk ) + +#define ETH_MACFCR_TFCE_Pos ( 1U ) +#define ETH_MACFCR_TFCE_Msk ( 0x1UL << ETH_MACFCR_TFCE_Pos ) +#define ETH_MACFCR_TFCE ( ETH_MACFCR_TFCE_Msk ) + +#define ETH_MACFCR_FCB_BPA_Pos ( 0U ) +#define ETH_MACFCR_FCB_BPA_Msk ( 0x1UL << ETH_MACFCR_FCB_BPA_Pos ) +#define ETH_MACFCR_FCB_BPA ( ETH_MACFCR_FCB_BPA_Msk ) + + +/*************** Bits definition for ETH_MACVLANTR **********************/ + +#define ETH_MACVLANTR_VTHM_Pos ( 19U ) +#define ETH_MACVLANTR_VTHM_Msk ( 0x1UL << ETH_MACVLANTR_VTHM_Pos ) +#define ETH_MACVLANTR_VTHM ( ETH_MACVLANTR_VTHM_Msk ) + +#define ETH_MACVLANTR_ESVL_Pos ( 18U ) +#define ETH_MACVLANTR_ESVL_Msk ( 0x1UL << ETH_MACVLANTR_ESVL_Pos ) +#define ETH_MACVLANTR_ESVL ( ETH_MACVLANTR_ESVL_Msk ) + +#define ETH_MACVLANTR_VTIM_Pos ( 17U ) +#define ETH_MACVLANTR_VTIM_Msk ( 0x1UL << ETH_MACVLANTR_VTIM_Pos ) +#define ETH_MACVLANTR_VTIM ( ETH_MACVLANTR_VTIM_Msk ) + +#define ETH_MACVLANTR_ETV_Pos ( 16U ) +#define ETH_MACVLANTR_ETV_Msk ( 0x1UL << ETH_MACVLANTR_ETV_Pos ) +#define ETH_MACVLANTR_ETV ( ETH_MACVLANTR_ETV_Msk ) + +#define ETH_MACVLANTR_VL_Pos ( 0U ) +#define ETH_MACVLANTR_VL_Msk ( 0xffffUL << ETH_MACVLANTR_VL_Pos ) +#define ETH_MACVLANTR_VL ( ETH_MACVLANTR_VL_Msk ) + + +/*************** Bits definition for ETH_MACDBGR **********************/ + +#define ETH_MACDBGR_TFF_Pos ( 25U ) +#define ETH_MACDBGR_TFF_Msk ( 0x1UL << ETH_MACDBGR_TFF_Pos ) +#define ETH_MACDBGR_TFF ( ETH_MACDBGR_TFF_Msk ) + +#define ETH_MACDBGR_TFNE_Pos ( 24U ) +#define ETH_MACDBGR_TFNE_Msk ( 0x1UL << ETH_MACDBGR_TFNE_Pos ) +#define ETH_MACDBGR_TFNE ( ETH_MACDBGR_TFNE_Msk ) + +#define ETH_MACDBGR_TFWA_Pos ( 22U ) +#define ETH_MACDBGR_TFWA_Msk ( 0x1UL << ETH_MACDBGR_TFWA_Pos ) +#define ETH_MACDBGR_TFWA ( ETH_MACDBGR_TFWA_Msk ) + +#define ETH_MACDBGR_TFRS_Pos ( 20U ) +#define ETH_MACDBGR_TFRS_Msk ( 0x3UL << ETH_MACDBGR_TFRS_Pos ) +#define ETH_MACDBGR_TFRS ( ETH_MACDBGR_TFRS_Msk ) +#define ETH_MACDBGR_TFRS_0 ( 0x1UL << ETH_MACDBGR_TFRS_Pos ) +#define ETH_MACDBGR_TFRS_1 ( 0x2UL << ETH_MACDBGR_TFRS_Pos ) + +#define ETH_MACDBGR_MTP_Pos ( 19U ) +#define ETH_MACDBGR_MTP_Msk ( 0x1UL << ETH_MACDBGR_MTP_Pos ) +#define ETH_MACDBGR_MTP ( ETH_MACDBGR_MTP_Msk ) + +#define ETH_MACDBGR_MTFCS_Pos ( 17U ) +#define ETH_MACDBGR_MTFCS_Msk ( 0x3UL << ETH_MACDBGR_MTFCS_Pos ) +#define ETH_MACDBGR_MTFCS ( ETH_MACDBGR_MTFCS_Msk ) +#define ETH_MACDBGR_MTFCS_0 ( 0x1UL << ETH_MACDBGR_MTFCS_Pos ) +#define ETH_MACDBGR_MTFCS_1 ( 0x2UL << ETH_MACDBGR_MTFCS_Pos ) + +#define ETH_MACDBGR_MMTEA_Pos ( 16U ) +#define ETH_MACDBGR_MMTEA_Msk ( 0x1UL << ETH_MACDBGR_MMTEA_Pos ) +#define ETH_MACDBGR_MMTEA ( ETH_MACDBGR_MMTEA_Msk ) + +#define ETH_MACDBGR_RFFL_Pos ( 8U ) +#define ETH_MACDBGR_RFFL_Msk ( 0x3UL << ETH_MACDBGR_RFFL_Pos ) +#define ETH_MACDBGR_RFFL ( ETH_MACDBGR_RFFL_Msk ) +#define ETH_MACDBGR_RFFL_0 ( 0x1UL << ETH_MACDBGR_RFFL_Pos ) +#define ETH_MACDBGR_RFFL_1 ( 0x2UL << ETH_MACDBGR_RFFL_Pos ) + +#define ETH_MACDBGR_RFRCS_Pos ( 5U ) +#define ETH_MACDBGR_RFRCS_Msk ( 0x3UL << ETH_MACDBGR_RFRCS_Pos ) +#define ETH_MACDBGR_RFRCS ( ETH_MACDBGR_RFRCS_Msk ) +#define ETH_MACDBGR_RFRCS_0 ( 0x1UL << ETH_MACDBGR_RFRCS_Pos ) +#define ETH_MACDBGR_RFRCS_1 ( 0x2UL << ETH_MACDBGR_RFRCS_Pos ) + +#define ETH_MACDBGR_RFWCS_Pos ( 4U ) +#define ETH_MACDBGR_RFWCS_Msk ( 0x1UL << ETH_MACDBGR_RFWCS_Pos ) +#define ETH_MACDBGR_RFWCS ( ETH_MACDBGR_RFWCS_Msk ) + +#define ETH_MACDBGR_MRFFCS_Pos ( 1U ) +#define ETH_MACDBGR_MRFFCS_Msk ( 0x3UL << ETH_MACDBGR_MRFFCS_Pos ) +#define ETH_MACDBGR_MRFFCS ( ETH_MACDBGR_MRFFCS_Msk ) +#define ETH_MACDBGR_MRFFCS_0 ( 0x1UL << ETH_MACDBGR_MRFFCS_Pos ) +#define ETH_MACDBGR_MRFFCS_1 ( 0x2UL << ETH_MACDBGR_MRFFCS_Pos ) + +#define ETH_MACDBGR_MMRPES_Pos ( 0U ) +#define ETH_MACDBGR_MMRPES_Msk ( 0x1UL << ETH_MACDBGR_MMRPES_Pos ) +#define ETH_MACDBGR_MMRPES ( ETH_MACDBGR_MMRPES_Msk ) + + +/*************** Bits definition for ETH_MACRWUFF **********************/ + +#define ETH_MACRWUFF_MACRWUFF_Pos ( 0U ) +#define ETH_MACRWUFF_MACRWUFF_Msk ( 0xffffffffUL << ETH_MACRWUFF_MACRWUFF_Pos ) +#define ETH_MACRWUFF_MACRWUFF ( ETH_MACRWUFF_MACRWUFF_Msk ) + + +/*************** Bits definition for ETH_MACPMTCSR **********************/ + +#define ETH_MACPMTCSR_RWFFPR_Pos ( 31U ) +#define ETH_MACPMTCSR_RWFFPR_Msk ( 0x1UL << ETH_MACPMTCSR_RWFFPR_Pos ) +#define ETH_MACPMTCSR_RWFFPR ( ETH_MACPMTCSR_RWFFPR_Msk ) + +#define ETH_MACPMTCSR_RWFP_Pos ( 24U ) +#define ETH_MACPMTCSR_RWFP_Msk ( 0x3UL << ETH_MACPMTCSR_GU_Pos ) +#define ETH_MACPMTCSR_RWFP ( ETH_MACPMTCSR_GU_Msk ) +#define ETH_MACPMTCSR_RWFP_0 ( 0x1UL << ETH_MACPMTCSR_GU_Pos ) +#define ETH_MACPMTCSR_RWFP_1 ( 0x2UL << ETH_MACPMTCSR_GU_Pos ) + +#define ETH_MACPMTCSR_GU_Pos ( 9U ) +#define ETH_MACPMTCSR_GU_Msk ( 0x1UL << ETH_MACPMTCSR_GU_Pos ) +#define ETH_MACPMTCSR_GU ( ETH_MACPMTCSR_GU_Msk ) + +#define ETH_MACPMTCSR_WFR_Pos ( 6U ) +#define ETH_MACPMTCSR_WFR_Msk ( 0x1UL << ETH_MACPMTCSR_WFR_Pos ) +#define ETH_MACPMTCSR_WFR ( ETH_MACPMTCSR_WFR_Msk ) + +#define ETH_MACPMTCSR_MPR_Pos ( 5U ) +#define ETH_MACPMTCSR_MPR_Msk ( 0x1UL << ETH_MACPMTCSR_MPR_Pos ) +#define ETH_MACPMTCSR_MPR ( ETH_MACPMTCSR_MPR_Msk ) + +#define ETH_MACPMTCSR_WFE_Pos ( 2U ) +#define ETH_MACPMTCSR_WFE_Msk ( 0x1UL << ETH_MACPMTCSR_WFE_Pos ) +#define ETH_MACPMTCSR_WFE ( ETH_MACPMTCSR_WFE_Msk ) + +#define ETH_MACPMTCSR_MPE_Pos ( 1U ) +#define ETH_MACPMTCSR_MPE_Msk ( 0x1UL << ETH_MACPMTCSR_MPE_Pos ) +#define ETH_MACPMTCSR_MPE ( ETH_MACPMTCSR_MPE_Msk ) + +#define ETH_MACPMTCSR_PD_Pos ( 0U ) +#define ETH_MACPMTCSR_PD_Msk ( 0x1UL << ETH_MACPMTCSR_PD_Pos ) +#define ETH_MACPMTCSR_PD ( ETH_MACPMTCSR_PD_Msk ) + + +/*************** Bits definition for ETH_MACLPICSR **********************/ + +#define ETH_MACLPICSR_LPITXA_Pos ( 19U ) +#define ETH_MACLPICSR_LPITXA_Msk ( 0x1UL << ETH_MACLPICSR_LPITXA_Pos ) +#define ETH_MACLPICSR_LPITXA ( ETH_MACLPICSR_LPITXA_Msk ) + +#define ETH_MACLPICSR_PLSEN_Pos ( 18U ) +#define ETH_MACLPICSR_PLSEN_Msk ( 0x1UL << ETH_MACLPICSR_PLSEN_Pos ) +#define ETH_MACLPICSR_PLSEN ( ETH_MACLPICSR_PLSEN_Msk ) + +#define ETH_MACLPICSR_PLS_Pos ( 17U ) +#define ETH_MACLPICSR_PLS_Msk ( 0x1UL << ETH_MACLPICSR_PLS_Pos ) +#define ETH_MACLPICSR_PLS ( ETH_MACLPICSR_PLS_Msk ) + +#define ETH_MACLPICSR_LPIEN_Pos ( 16U ) +#define ETH_MACLPICSR_LPIEN_Msk ( 0x1UL << ETH_MACLPICSR_LPIEN_Pos ) +#define ETH_MACLPICSR_LPIEN ( ETH_MACLPICSR_LPIEN_Msk ) + +#define ETH_MACLPICSR_RLPIST_Pos ( 9U ) +#define ETH_MACLPICSR_RLPIST_Msk ( 0x1UL << ETH_MACLPICSR_RLPIST_Pos ) +#define ETH_MACLPICSR_RLPIST ( ETH_MACLPICSR_RLPIST_Msk ) + +#define ETH_MACLPICSR_TLPIST_Pos ( 8U ) +#define ETH_MACLPICSR_TLPIST_Msk ( 0x1UL << ETH_MACLPICSR_TLPIST_Pos ) +#define ETH_MACLPICSR_TLPIST ( ETH_MACLPICSR_TLPIST_Msk ) + +#define ETH_MACLPICSR_RLPIEX_Pos ( 3U ) +#define ETH_MACLPICSR_RLPIEX_Msk ( 0x1UL << ETH_MACLPICSR_RLPIEX_Pos ) +#define ETH_MACLPICSR_RLPIEX ( ETH_MACLPICSR_RLPIEX_Msk ) + +#define ETH_MACLPICSR_RLPIEN_Pos ( 2U ) +#define ETH_MACLPICSR_RLPIEN_Msk ( 0x1UL << ETH_MACLPICSR_RLPIEN_Pos ) +#define ETH_MACLPICSR_RLPIEN ( ETH_MACLPICSR_RLPIEN_Msk ) + +#define ETH_MACLPICSR_TLPIEX_Pos ( 1U ) +#define ETH_MACLPICSR_TLPIEX_Msk ( 0x1UL << ETH_MACLPICSR_TLPIEX_Pos ) +#define ETH_MACLPICSR_TLPIEX ( ETH_MACLPICSR_TLPIEX_Msk ) + +#define ETH_MACLPICSR_TLPIEN_Pos ( 0U ) +#define ETH_MACLPICSR_TLPIEN_Msk ( 0x1UL << ETH_MACLPICSR_TLPIEN_Pos ) +#define ETH_MACLPICSR_TLPIEN ( ETH_MACLPICSR_TLPIEN_Msk ) + + +/*************** Bits definition for ETH_MACLPITCR **********************/ + +#define ETH_MACLPITCR_LST_Pos ( 16U ) +#define ETH_MACLPITCR_LST_Msk ( 0x3FFUL << ETH_MACLPITCR_LST_Pos ) +#define ETH_MACLPITCR_LST ( ETH_MACLPITCR_LST_Msk ) + +#define ETH_MACLPITCR_TWT_Pos ( 0U ) +#define ETH_MACLPITCR_TWT_Msk ( 0xFFFFUL << ETH_MACLPITCR_TWT_Pos ) +#define ETH_MACLPITCR_TWT ( ETH_MACLPITCR_TWT_Msk ) + + +/*************** Bits definition for ETH_MACISR **********************/ + +#define ETH_MACISR_LPIIS_Pos ( 10U ) +#define ETH_MACISR_LPIIS_Msk ( 0x1UL << ETH_MACISR_LPIIS_Pos ) +#define ETH_MACISR_LPIIS ( ETH_MACISR_LPIIS_Msk ) + +#define ETH_MACISR_TIS_Pos ( 9U ) +#define ETH_MACISR_TIS_Msk ( 0x1UL << ETH_MACISR_TIS_Pos ) +#define ETH_MACISR_TIS ( ETH_MACISR_TIS_Msk ) + +#define ETH_MACISR_MMCTIS_Pos ( 6U ) +#define ETH_MACISR_MMCTIS_Msk ( 0x1UL << ETH_MACISR_MMCTIS_Pos ) +#define ETH_MACISR_MMCTIS ( ETH_MACISR_MMCTIS_Msk ) + +#define ETH_MACISR_MMCRIS_Pos ( 5U ) +#define ETH_MACISR_MMCRIS_Msk ( 0x1UL << ETH_MACISR_MMCRIS_Pos ) +#define ETH_MACISR_MMCRIS ( ETH_MACISR_MMCRIS_Msk ) + +#define ETH_MACISR_MMCIS_Pos ( 4U ) +#define ETH_MACISR_MMCIS_Msk ( 0x1UL << ETH_MACISR_MMCIS_Pos ) +#define ETH_MACISR_MMCIS ( ETH_MACISR_MMCIS_Msk ) + +#define ETH_MACISR_PMTS_Pos ( 3U ) +#define ETH_MACISR_PMTS_Msk ( 0x1UL << ETH_MACISR_PMTS_Pos ) +#define ETH_MACISR_PMTS ( ETH_MACISR_PMTS_Msk ) + + +/*************** Bits definition for ETH_MACIMR **********************/ + +#define ETH_MACIMR_LPIIM_Pos ( 10U ) +#define ETH_MACIMR_LPIIM_Msk ( 0x1UL << ETH_MACIMR_LPIIM_Pos ) +#define ETH_MACIMR_LPIIM ( ETH_MACIMR_LPIIM_Msk ) + +#define ETH_MACIMR_TIM_Pos ( 9U ) +#define ETH_MACIMR_TIM_Msk ( 0x1UL << ETH_MACIMR_TIM_Pos ) +#define ETH_MACIMR_TIM ( ETH_MACIMR_TIM_Msk ) + +#define ETH_MACIMR_PIM_Pos ( 3U ) +#define ETH_MACIMR_PIM_Msk ( 0x1UL << ETH_MACIMR_PIM_Pos ) +#define ETH_MACIMR_PIM ( ETH_MACIMR_PIM_Msk ) + + +/*************** Bits definition for ETH_MACA0HR **********************/ + +#define ETH_MACA0HR_AE_Pos ( 31U ) +#define ETH_MACA0HR_AE_Msk ( 0x1UL << ETH_MACA0HR_AE_Pos ) +#define ETH_MACA0HR_AE ( ETH_MACA0HR_AE_Msk ) + +#define ETH_MACA0HR_MACA0H_Pos ( 0U ) +#define ETH_MACA0HR_MACA0H_Msk ( 0xffffUL << ETH_MACA0HR_MACA0H_Pos ) +#define ETH_MACA0HR_MACA0H ( ETH_MACA0HR_MACA0H_Msk ) + + +/*************** Bits definition for ETH_MACA0LR **********************/ + +#define ETH_MACA0LR_MACA0L_Pos ( 0U ) +#define ETH_MACA0LR_MACA0L_Msk ( 0xffffffffUL << ETH_MACA0LR_MACA0L_Pos ) +#define ETH_MACA0LR_MACA0L ( ETH_MACA0LR_MACA0L_Msk ) + + +/*************** Bits definition for ETH_MACA1HR **********************/ + +#define ETH_MACA1HR_AE_Pos ( 31U ) +#define ETH_MACA1HR_AE_Msk ( 0x1UL << ETH_MACA1HR_AE_Pos ) +#define ETH_MACA1HR_AE ( ETH_MACA1HR_AE_Msk ) + +#define ETH_MACA1HR_SA_Pos ( 30U ) +#define ETH_MACA1HR_SA_Msk ( 0x1UL << ETH_MACA1HR_SA_Pos ) +#define ETH_MACA1HR_SA ( ETH_MACA1HR_SA_Msk ) + +#define ETH_MACA1HR_MBC_Pos ( 24U ) +#define ETH_MACA1HR_MBC_Msk ( 0x3fUL << ETH_MACA1HR_MBC_Pos ) +#define ETH_MACA1HR_MBC ( ETH_MACA1HR_MBC_Msk ) +#define ETH_MACA1HR_MBC_0 ( 0x1UL << ETH_MACA1HR_MBC_Pos ) +#define ETH_MACA1HR_MBC_1 ( 0x2UL << ETH_MACA1HR_MBC_Pos ) +#define ETH_MACA1HR_MBC_2 ( 0x4UL << ETH_MACA1HR_MBC_Pos ) +#define ETH_MACA1HR_MBC_3 ( 0x8UL << ETH_MACA1HR_MBC_Pos ) +#define ETH_MACA1HR_MBC_4 ( 0x10UL << ETH_MACA1HR_MBC_Pos ) +#define ETH_MACA1HR_MBC_5 ( 0x20UL << ETH_MACA1HR_MBC_Pos ) + +#define ETH_MACA1HR_MACA1H_Pos ( 0U ) +#define ETH_MACA1HR_MACA1H_Msk ( 0xffffUL << ETH_MACA1HR_MACA1H_Pos ) +#define ETH_MACA1HR_MACA1H ( ETH_MACA1HR_MACA1H_Msk ) + + +/*************** Bits definition for ETH_MACA1LR **********************/ + +#define ETH_MACA1LR_MACA1L_Pos ( 0U ) +#define ETH_MACA1LR_MACA1L_Msk ( 0xffffffffUL << ETH_MACA1LR_MACA1L_Pos ) +#define ETH_MACA1LR_MACA1L ( ETH_MACA1LR_MACA1L_Msk ) + + +/*************** Bits definition for ETH_MACA2HR **********************/ + +#define ETH_MACA2HR_AE_Pos ( 31U ) +#define ETH_MACA2HR_AE_Msk ( 0x1UL << ETH_MACA2HR_AE_Pos ) +#define ETH_MACA2HR_AE ( ETH_MACA2HR_AE_Msk ) + +#define ETH_MACA2HR_SA_Pos ( 30U ) +#define ETH_MACA2HR_SA_Msk ( 0x1UL << ETH_MACA2HR_SA_Pos ) +#define ETH_MACA2HR_SA ( ETH_MACA2HR_SA_Msk ) + +#define ETH_MACA2HR_MBC_Pos ( 24U ) +#define ETH_MACA2HR_MBC_Msk ( 0x3fUL << ETH_MACA2HR_MBC_Pos ) +#define ETH_MACA2HR_MBC ( ETH_MACA2HR_MBC_Msk ) +#define ETH_MACA2HR_MBC_0 ( 0x1UL << ETH_MACA2HR_MBC_Pos ) +#define ETH_MACA2HR_MBC_1 ( 0x2UL << ETH_MACA2HR_MBC_Pos ) +#define ETH_MACA2HR_MBC_2 ( 0x4UL << ETH_MACA2HR_MBC_Pos ) +#define ETH_MACA2HR_MBC_3 ( 0x8UL << ETH_MACA2HR_MBC_Pos ) +#define ETH_MACA2HR_MBC_4 ( 0x10UL << ETH_MACA2HR_MBC_Pos ) +#define ETH_MACA2HR_MBC_5 ( 0x20UL << ETH_MACA2HR_MBC_Pos ) + +#define ETH_MACA2HR_MACA2H_Pos ( 0U ) +#define ETH_MACA2HR_MACA2H_Msk ( 0xffffUL << ETH_MACA2HR_MACA2H_Pos ) +#define ETH_MACA2HR_MACA2H ( ETH_MACA2HR_MACA2H_Msk ) + + +/*************** Bits definition for ETH_MACA2LR **********************/ + +#define ETH_MACA2LR_MACA2L_Pos ( 0U ) +#define ETH_MACA2LR_MACA2L_Msk ( 0xffffffffUL << ETH_MACA2LR_MACA2L_Pos ) +#define ETH_MACA2LR_MACA2L ( ETH_MACA2LR_MACA2L_Msk ) + + +/*************** Bits definition for ETH_MACA3HR **********************/ + +#define ETH_MACA3HR_AE_Pos ( 31U ) +#define ETH_MACA3HR_AE_Msk ( 0x1UL << ETH_MACA3HR_AE_Pos ) +#define ETH_MACA3HR_AE ( ETH_MACA3HR_AE_Msk ) + +#define ETH_MACA3HR_SA_Pos ( 30U ) +#define ETH_MACA3HR_SA_Msk ( 0x1UL << ETH_MACA3HR_SA_Pos ) +#define ETH_MACA3HR_SA ( ETH_MACA3HR_SA_Msk ) + +#define ETH_MACA3HR_MBC_Pos ( 24U ) +#define ETH_MACA3HR_MBC_Msk ( 0x3fUL << ETH_MACA3HR_MBC_Pos ) +#define ETH_MACA3HR_MBC ( ETH_MACA3HR_MBC_Msk ) +#define ETH_MACA3HR_MBC_0 ( 0x1UL << ETH_MACA3HR_MBC_Pos ) +#define ETH_MACA3HR_MBC_1 ( 0x2UL << ETH_MACA3HR_MBC_Pos ) +#define ETH_MACA3HR_MBC_2 ( 0x4UL << ETH_MACA3HR_MBC_Pos ) +#define ETH_MACA3HR_MBC_3 ( 0x8UL << ETH_MACA3HR_MBC_Pos ) +#define ETH_MACA3HR_MBC_4 ( 0x10UL << ETH_MACA3HR_MBC_Pos ) +#define ETH_MACA3HR_MBC_5 ( 0x20UL << ETH_MACA3HR_MBC_Pos ) + +#define ETH_MACA3HR_MACA3H_Pos ( 0U ) +#define ETH_MACA3HR_MACA3H_Msk ( 0xffffUL << ETH_MACA3HR_MACA3H_Pos ) +#define ETH_MACA3HR_MACA3H ( ETH_MACA3HR_MACA3H_Msk ) + + +/*************** Bits definition for ETH_MACA3LR **********************/ + +#define ETH_MACA3LR_MACA3L_Pos ( 0U ) +#define ETH_MACA3LR_MACA3L_Msk ( 0xffffffffUL << ETH_MACA3LR_MACA3L_Pos ) +#define ETH_MACA3LR_MACA3L ( ETH_MACA3LR_MACA3L_Msk ) + + +/*************** Bits definition for ETH_MACWTR **********************/ + +#define ETH_MACWTR_PWE_Pos ( 16U ) +#define ETH_MACWTR_PWE_Msk ( 0x1UL << ETH_MACWTR_PWE_Pos ) +#define ETH_MACWTR_PWE ( ETH_MACWTR_PWE_Msk ) + +#define ETH_MACWTR_WTO_Pos ( 0U ) +#define ETH_MACWTR_WTO_Msk ( 0x3FFFUL << ETH_MACWTR_WTO_Pos ) +#define ETH_MACWTR_WTO ( ETH_MACWTR_WTO_Msk ) + + +/*************** Bits definition for ETH_MMCCR **********************/ + +#define ETH_MMCCR_UCDBC_Pos ( 8U ) +#define ETH_MMCCR_UCDBC_Msk ( 0x1UL << ETH_MMCCR_UCDBC_Pos ) +#define ETH_MMCCR_UCDBC ( ETH_MMCCR_UCDBC_Msk ) + +#define ETH_MMCCR_CNTPRSTLVL_Pos ( 5U ) +#define ETH_MMCCR_CNTPRSTLVL_Msk ( 0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos ) +#define ETH_MMCCR_CNTPRSTLVL ( ETH_MMCCR_CNTPRSTLVL_Msk ) + +#define ETH_MMCCR_CNTPRST_Pos ( 4U ) +#define ETH_MMCCR_CNTPRST_Msk ( 0x1UL << ETH_MMCCR_CNTPRST_Pos ) +#define ETH_MMCCR_CNTPRST ( ETH_MMCCR_CNTPRST_Msk ) + +#define ETH_MMCCR_CNTFREEZ_Pos ( 3U ) +#define ETH_MMCCR_CNTFREEZ_Msk ( 0x1UL << ETH_MMCCR_CNTFREEZ_Pos ) +#define ETH_MMCCR_CNTFREEZ ( ETH_MMCCR_CNTFREEZ_Msk ) + +#define ETH_MMCCR_RSTONRD_Pos ( 2U ) +#define ETH_MMCCR_RSTONRD_Msk ( 0x1UL << ETH_MMCCR_RSTONRD_Pos ) +#define ETH_MMCCR_RSTONRD ( ETH_MMCCR_RSTONRD_Msk ) + +#define ETH_MMCCR_CNTSTOPRO_Pos ( 1U ) +#define ETH_MMCCR_CNTSTOPRO_Msk ( 0x1UL << ETH_MMCCR_CNTSTOPRO_Pos ) +#define ETH_MMCCR_CNTSTOPRO ( ETH_MMCCR_CNTSTOPRO_Msk ) + +#define ETH_MMCCR_CNTRST_Pos ( 0U ) +#define ETH_MMCCR_CNTRST_Msk ( 0x1UL << ETH_MMCCR_CNTRST_Pos ) +#define ETH_MMCCR_CNTRST ( ETH_MMCCR_CNTRST_Msk ) + + +/*************** Bits definition for ETH_MMCRIR **********************/ + +#define ETH_MMCRIR_RGUFIS_Pos ( 17U ) +#define ETH_MMCRIR_RGUFIS_Msk ( 0x1UL << ETH_MMCRIR_RGUFIS_Pos ) +#define ETH_MMCRIR_RGUFIS ( ETH_MMCRIR_RGUFIS_Msk ) + +#define ETH_MMCRIR_RFAEIS_Pos ( 6U ) +#define ETH_MMCRIR_RFAEIS_Msk ( 0x1UL << ETH_MMCRIR_RFAEIS_Pos ) +#define ETH_MMCRIR_RFAEIS ( ETH_MMCRIR_RFAEIS_Msk ) + +#define ETH_MMCRIR_RFCEIS_Pos ( 5U ) +#define ETH_MMCRIR_RFCEIS_Msk ( 0x1UL << ETH_MMCRIR_RFCEIS_Pos ) +#define ETH_MMCRIR_RFCEIS ( ETH_MMCRIR_RFCEIS_Msk ) + + +/*************** Bits definition for ETH_MMCTIR **********************/ + +#define ETH_MMCTIR_TGFIS_Pos ( 21U ) +#define ETH_MMCTIR_TGFIS_Msk ( 0x1UL << ETH_MMCTIR_TGFIS_Pos ) +#define ETH_MMCTIR_TGFIS ( ETH_MMCTIR_TGFIS_Msk ) + +#define ETH_MMCTIR_TMCGFCIS_Pos ( 15U ) +#define ETH_MMCTIR_TMCGFCIS_Msk ( 0x1UL << ETH_MMCTIR_TMCGFCIS_Pos ) +#define ETH_MMCTIR_TMCGFCIS ( ETH_MMCTIR_TMCGFCIS_Msk ) + +#define ETH_MMCTIR_TSCGFCIS_Pos ( 14U ) +#define ETH_MMCTIR_TSCGFCIS_Msk ( 0x1UL << ETH_MMCTIR_TSCGFCIS_Pos ) +#define ETH_MMCTIR_TSCGFCIS ( ETH_MMCTIR_TSCGFCIS_Msk ) + + +/*************** Bits definition for ETH_MMCRIMR **********************/ + +#define ETH_MMCRIMR_RGUFIM_Pos ( 17U ) +#define ETH_MMCRIMR_RGUFIM_Msk ( 0x1UL << ETH_MMCRIMR_RGUFIM_Pos ) +#define ETH_MMCRIMR_RGUFIM ( ETH_MMCRIMR_RGUFIM_Msk ) + +#define ETH_MMCRIMR_RFAEIM_Pos ( 6U ) +#define ETH_MMCRIMR_RFAEIM_Msk ( 0x1UL << ETH_MMCRIMR_RFAEIM_Pos ) +#define ETH_MMCRIMR_RFAEIM ( ETH_MMCRIMR_RFAEIM_Msk ) + +#define ETH_MMCRIMR_RFCEIM_Pos ( 5U ) +#define ETH_MMCRIMR_RFCEIM_Msk ( 0x1UL << ETH_MMCRIMR_RFCEIM_Pos ) +#define ETH_MMCRIMR_RFCEIM ( ETH_MMCRIMR_RFCEIM_Msk ) + + +/*************** Bits definition for ETH_MMCTIMR **********************/ + +#define ETH_MMCTIMR_TGFIM_Pos ( 21U ) +#define ETH_MMCTIMR_TGFIM_Msk ( 0x1UL << ETH_MMCTIMR_TGFIM_Pos ) +#define ETH_MMCTIMR_TGFIM ( ETH_MMCTIMR_TGFIM_Msk ) + +#define ETH_MMCTIMR_TMCGFCIM_Pos ( 15U ) +#define ETH_MMCTIMR_TMCGFCIM_Msk ( 0x1UL << ETH_MMCTIMR_TMCGFCIM_Pos ) +#define ETH_MMCTIMR_TMCGFCIM ( ETH_MMCTIMR_TMCGFCIM_Msk ) + +#define ETH_MMCTIMR_TSCGFCIM_Pos ( 14U ) +#define ETH_MMCTIMR_TSCGFCIM_Msk ( 0x1UL << ETH_MMCTIMR_TSCGFCIM_Pos ) +#define ETH_MMCTIMR_TSCGFCIM ( ETH_MMCTIMR_TSCGFCIM_Msk ) + + +/*************** Bits definition for ETH_MMCTGFSCCR **********************/ + +#define ETH_MMCTGFSCCR_TGFSCC_Pos ( 0U ) +#define ETH_MMCTGFSCCR_TGFSCC_Msk ( 0xffffffffUL << ETH_MMCTGFSCCR_TGFSCC_Pos ) +#define ETH_MMCTGFSCCR_TGFSCC ( ETH_MMCTGFSCCR_TGFSCC_Msk ) + + +/*************** Bits definition for ETH_MMCTGFMCCR **********************/ + +#define ETH_MMCTGFMCCR_TGFMCC_Pos ( 0U ) +#define ETH_MMCTGFMCCR_TGFMCC_Msk ( 0xffffffffUL << ETH_MMCTGFMCCR_TGFMCC_Pos ) +#define ETH_MMCTGFMCCR_TGFMCC ( ETH_MMCTGFMCCR_TGFMCC_Msk ) + + +/*************** Bits definition for ETH_MMCTGFCR **********************/ + +#define ETH_MMCTGFCR_TGFC_Pos ( 0U ) +#define ETH_MMCTGFCR_TGFC_Msk ( 0xffffffffUL << ETH_MMCTGFCR_TGFC_Pos ) +#define ETH_MMCTGFCR_TGFC ( ETH_MMCTGFCR_TGFC_Msk ) + + +/*************** Bits definition for ETH_MMCRFCECR **********************/ + +#define ETH_MMCRFCECR_RFCEC_Pos ( 0U ) +#define ETH_MMCRFCECR_RFCEC_Msk ( 0xffffffffUL << ETH_MMCRFCECR_RFCEC_Pos ) +#define ETH_MMCRFCECR_RFCEC ( ETH_MMCRFCECR_RFCEC_Msk ) + + +/*************** Bits definition for ETH_MMCRFAECR **********************/ + +#define ETH_MMCRFAECR_RFAEC_Pos ( 0U ) +#define ETH_MMCRFAECR_RFAEC_Msk ( 0xffffffffUL << ETH_MMCRFAECR_RFAEC_Pos ) +#define ETH_MMCRFAECR_RFAEC ( ETH_MMCRFAECR_RFAEC_Msk ) + + +/*************** Bits definition for ETH_MMCRGUFCR **********************/ + +#define ETH_MMCRGUFCR_RGUFC_Pos ( 0U ) +#define ETH_MMCRGUFCR_RGUFC_Msk ( 0xffffffffUL << ETH_MMCRGUFCR_RGUFC_Pos ) +#define ETH_MMCRGUFCR_RGUFC ( ETH_MMCRGUFCR_RGUFC_Msk ) + + +/*************** Bits definition for ETH_MACL3L4C0R **********************/ + +#define ETH_MACL3L4C0R_L4DPIM0_Pos ( 21U ) +#define ETH_MACL3L4C0R_L4DPIM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos ) +#define ETH_MACL3L4C0R_L4DPIM0 ( ETH_MACL3L4C0R_L4DPIM0_Msk ) + +#define ETH_MACL3L4C0R_L4DPM0_Pos ( 20U ) +#define ETH_MACL3L4C0R_L4DPM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos ) +#define ETH_MACL3L4C0R_L4DPM0 ( ETH_MACL3L4C0R_L4DPM0_Msk ) + +#define ETH_MACL3L4C0R_L4SPIM0_Pos ( 19U ) +#define ETH_MACL3L4C0R_L4SPIM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos ) +#define ETH_MACL3L4C0R_L4SPIM0 ( ETH_MACL3L4C0R_L4SPIM0_Msk ) + +#define ETH_MACL3L4C0R_L4SPM0_Pos ( 18U ) +#define ETH_MACL3L4C0R_L4SPM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos ) +#define ETH_MACL3L4C0R_L4SPM0 ( ETH_MACL3L4C0R_L4SPM0_Msk ) + +#define ETH_MACL3L4C0R_L4PEN0_Pos ( 16U ) +#define ETH_MACL3L4C0R_L4PEN0_Msk ( 0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos ) +#define ETH_MACL3L4C0R_L4PEN0 ( ETH_MACL3L4C0R_L4PEN0_Msk ) + +#define ETH_MACL3L4C0R_L3HDBM0_Pos ( 11U ) +#define ETH_MACL3L4C0R_L3HDBM0_Msk ( 0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos ) +#define ETH_MACL3L4C0R_L3HDBM0 ( ETH_MACL3L4C0R_L3HDBM0_Msk ) +#define ETH_MACL3L4C0R_L3HDBM0_0 ( 0x01UL << ETH_MACL3L4C0R_L3HDBM0_Pos ) +#define ETH_MACL3L4C0R_L3HDBM0_1 ( 0x02UL << ETH_MACL3L4C0R_L3HDBM0_Pos ) +#define ETH_MACL3L4C0R_L3HDBM0_2 ( 0x04UL << ETH_MACL3L4C0R_L3HDBM0_Pos ) +#define ETH_MACL3L4C0R_L3HDBM0_3 ( 0x08UL << ETH_MACL3L4C0R_L3HDBM0_Pos ) +#define ETH_MACL3L4C0R_L3HDBM0_4 ( 0x10UL << ETH_MACL3L4C0R_L3HDBM0_Pos ) + +#define ETH_MACL3L4C0R_L3HSBM0_Pos ( 6U ) +#define ETH_MACL3L4C0R_L3HSBM0_Msk ( 0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos ) +#define ETH_MACL3L4C0R_L3HSBM0 ( ETH_MACL3L4C0R_L3HSBM0_Msk ) +#define ETH_MACL3L4C0R_L3HSBM0_0 ( 0x01UL << ETH_MACL3L4C0R_L3HSBM0_Pos ) +#define ETH_MACL3L4C0R_L3HSBM0_1 ( 0x02UL << ETH_MACL3L4C0R_L3HSBM0_Pos ) +#define ETH_MACL3L4C0R_L3HSBM0_2 ( 0x04UL << ETH_MACL3L4C0R_L3HSBM0_Pos ) +#define ETH_MACL3L4C0R_L3HSBM0_3 ( 0x08UL << ETH_MACL3L4C0R_L3HSBM0_Pos ) +#define ETH_MACL3L4C0R_L3HSBM0_4 ( 0x10UL << ETH_MACL3L4C0R_L3HSBM0_Pos ) + +#define ETH_MACL3L4C0R_L3DAIM0_Pos ( 5U ) +#define ETH_MACL3L4C0R_L3DAIM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos ) +#define ETH_MACL3L4C0R_L3DAIM0 ( ETH_MACL3L4C0R_L3DAIM0_Msk ) + +#define ETH_MACL3L4C0R_L3DAM0_Pos ( 4U ) +#define ETH_MACL3L4C0R_L3DAM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos ) +#define ETH_MACL3L4C0R_L3DAM0 ( ETH_MACL3L4C0R_L3DAM0_Msk ) + +#define ETH_MACL3L4C0R_L3SAIM0_Pos ( 3U ) +#define ETH_MACL3L4C0R_L3SAIM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos ) +#define ETH_MACL3L4C0R_L3SAIM0 ( ETH_MACL3L4C0R_L3SAIM0_Msk ) + +#define ETH_MACL3L4C0R_L3SAM0_Pos ( 2U ) +#define ETH_MACL3L4C0R_L3SAM0_Msk ( 0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos ) +#define ETH_MACL3L4C0R_L3SAM0 ( ETH_MACL3L4C0R_L3SAM0_Msk ) + +#define ETH_MACL3L4C0R_L3PEN0_Pos ( 0U ) +#define ETH_MACL3L4C0R_L3PEN0_Msk ( 0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos ) +#define ETH_MACL3L4C0R_L3PEN0 ( ETH_MACL3L4C0R_L3PEN0_Msk ) + + +/*************** Bits definition for ETH_MACL4A0R **********************/ + +#define ETH_MACL4A0R_L4DP0_Pos ( 16U ) +#define ETH_MACL4A0R_L4DP0_Msk ( 0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos ) +#define ETH_MACL4A0R_L4DP0 ( ETH_MACL4A0R_L4DP0_Msk ) + +#define ETH_MACL4A0R_L4SP0_Pos ( 0U ) +#define ETH_MACL4A0R_L4SP0_Msk ( 0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos ) +#define ETH_MACL4A0R_L4SP0 ( ETH_MACL4A0R_L4SP0_Msk ) + + +/*************** Bits definition for ETH_MACL3A00R **********************/ + +#define ETH_MACL3A00R_L3A00_Pos ( 0U ) +#define ETH_MACL3A00R_L3A00_Msk ( 0xFFFFFFFFUL << ETH_MACL3A00R_L3A00_Pos ) +#define ETH_MACL3A00R_L3A00 ( ETH_MACL3A00R_L3A00_Msk ) + + +/*************** Bits definition for ETH_MACL3A10R **********************/ + +#define ETH_MACL3A10R_L3A10_Pos ( 0U ) +#define ETH_MACL3A10R_L3A10_Msk ( 0xFFFFFFFFUL << ETH_MACL3A10R_L3A10_Pos ) +#define ETH_MACL3A10R_L3A10 ( ETH_MACL3A10R_L3A10_Msk ) + + +/*************** Bits definition for ETH_MACL3A20R **********************/ + +#define ETH_MACL3A20R_L3A20_Pos ( 0U ) +#define ETH_MACL3A20R_L3A20_Msk ( 0xFFFFFFFFUL << ETH_MACL3A20R_L3A20_Pos ) +#define ETH_MACL3A20R_L3A20 ( ETH_MACL3A20R_L3A20_Msk ) + + +/*************** Bits definition for ETH_MACL3A30R **********************/ + +#define ETH_MACL3A30R_L3A30_Pos ( 0U ) +#define ETH_MACL3A30R_L3A30_Msk ( 0xFFFFFFFFUL << ETH_MACL3A30R_L3A30_Pos ) +#define ETH_MACL3A30R_L3A30 ( ETH_MACL3A30R_L3A30_Msk ) + + +/*************** Bits definition for ETH_MACL3L4C1R **********************/ + +#define ETH_MACL3L4C1R_L4DPIM1_Pos ( 21U ) +#define ETH_MACL3L4C1R_L4DPIM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L4DPIM1_Pos ) +#define ETH_MACL3L4C1R_L4DPIM1 ( ETH_MACL3L4C1R_L4DPIM1_Msk ) + +#define ETH_MACL3L4C1R_L4DPM1_Pos ( 20U ) +#define ETH_MACL3L4C1R_L4DPM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L4DPM1_Pos ) +#define ETH_MACL3L4C1R_L4DPM1 ( ETH_MACL3L4C1R_L4DPM1_Msk ) + +#define ETH_MACL3L4C1R_L4SPIM1_Pos ( 19U ) +#define ETH_MACL3L4C1R_L4SPIM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L4SPIM1_Pos ) +#define ETH_MACL3L4C1R_L4SPIM1 ( ETH_MACL3L4C1R_L4SPIM1_Msk ) + +#define ETH_MACL3L4C1R_L4SPM1_Pos ( 18U ) +#define ETH_MACL3L4C1R_L4SPM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L4SPM1_Pos ) +#define ETH_MACL3L4C1R_L4SPM1 ( ETH_MACL3L4C1R_L4SPM1_Msk ) + +#define ETH_MACL3L4C1R_L4PEN1_Pos ( 16U ) +#define ETH_MACL3L4C1R_L4PEN1_Msk ( 0x1UL << ETH_MACL3L4C1R_L4PEN1_Pos ) +#define ETH_MACL3L4C1R_L4PEN1 ( ETH_MACL3L4C1R_L4PEN1_Msk ) + +#define ETH_MACL3L4C1R_L3HDBM1_Pos ( 11U ) +#define ETH_MACL3L4C1R_L3HDBM1_Msk ( 0x1FUL << ETH_MACL3L4C1R_L3HDBM1_Pos ) +#define ETH_MACL3L4C1R_L3HDBM1 ( ETH_MACL3L4C1R_L3HDBM1_Msk ) +#define ETH_MACL3L4C1R_L3HDBM1_0 ( 0x01UL << ETH_MACL3L4C1R_L3HDBM1_Pos ) +#define ETH_MACL3L4C1R_L3HDBM1_1 ( 0x02UL << ETH_MACL3L4C1R_L3HDBM1_Pos ) +#define ETH_MACL3L4C1R_L3HDBM1_2 ( 0x04UL << ETH_MACL3L4C1R_L3HDBM1_Pos ) +#define ETH_MACL3L4C1R_L3HDBM1_3 ( 0x08UL << ETH_MACL3L4C1R_L3HDBM1_Pos ) +#define ETH_MACL3L4C1R_L3HDBM1_4 ( 0x10UL << ETH_MACL3L4C1R_L3HDBM1_Pos ) + +#define ETH_MACL3L4C1R_L3HSBM1_Pos ( 6U ) +#define ETH_MACL3L4C1R_L3HSBM1_Msk ( 0x1FUL << ETH_MACL3L4C1R_L3HSBM1_Pos ) +#define ETH_MACL3L4C1R_L3HSBM1 ( ETH_MACL3L4C1R_L3HSBM1_Msk ) +#define ETH_MACL3L4C1R_L3HSBM1_0 ( 0x01UL << ETH_MACL3L4C1R_L3HSBM1_Pos ) +#define ETH_MACL3L4C1R_L3HSBM1_1 ( 0x02UL << ETH_MACL3L4C1R_L3HSBM1_Pos ) +#define ETH_MACL3L4C1R_L3HSBM1_2 ( 0x04UL << ETH_MACL3L4C1R_L3HSBM1_Pos ) +#define ETH_MACL3L4C1R_L3HSBM1_3 ( 0x08UL << ETH_MACL3L4C1R_L3HSBM1_Pos ) +#define ETH_MACL3L4C1R_L3HSBM1_4 ( 0x10UL << ETH_MACL3L4C1R_L3HSBM1_Pos ) + +#define ETH_MACL3L4C1R_L3DAIM1_Pos ( 5U ) +#define ETH_MACL3L4C1R_L3DAIM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L3DAIM1_Pos ) +#define ETH_MACL3L4C1R_L3DAIM1 ( ETH_MACL3L4C1R_L3DAIM1_Msk ) + +#define ETH_MACL3L4C1R_L3DAM1_Pos ( 4U ) +#define ETH_MACL3L4C1R_L3DAM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L3DAM1_Pos ) +#define ETH_MACL3L4C1R_L3DAM1 ( ETH_MACL3L4C1R_L3DAM1_Msk ) + +#define ETH_MACL3L4C1R_L3SAIM1_Pos ( 3U ) +#define ETH_MACL3L4C1R_L3SAIM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L3SAIM1_Pos ) +#define ETH_MACL3L4C1R_L3SAIM1 ( ETH_MACL3L4C1R_L3SAIM1_Msk ) + +#define ETH_MACL3L4C1R_L3SAM1_Pos ( 2U ) +#define ETH_MACL3L4C1R_L3SAM1_Msk ( 0x1UL << ETH_MACL3L4C1R_L3SAM1_Pos ) +#define ETH_MACL3L4C1R_L3SAM1 ( ETH_MACL3L4C1R_L3SAM1_Msk ) + +#define ETH_MACL3L4C1R_L3PEN1_Pos ( 0U ) +#define ETH_MACL3L4C1R_L3PEN1_Msk ( 0x1UL << ETH_MACL3L4C1R_L3PEN1_Pos ) +#define ETH_MACL3L4C1R_L3PEN1 ( ETH_MACL3L4C1R_L3PEN1_Msk ) + + +/*************** Bits definition for ETH_MACL4A1R **********************/ + +#define ETH_MACL4A1R_L4DP1_Pos ( 16U ) +#define ETH_MACL4A1R_L4DP1_Msk ( 0xFFFFUL << ETH_MACL4A1R_L4DP1_Pos ) +#define ETH_MACL4A1R_L4DP1 ( ETH_MACL4A1R_L4DP1_Msk ) + +#define ETH_MACL4A1R_L4SP1_Pos ( 0U ) +#define ETH_MACL4A1R_L4SP1_Msk ( 0xFFFFUL << ETH_MACL4A1R_L4SP1_Pos ) +#define ETH_MACL4A1R_L4SP1 ( ETH_MACL4A1R_L4SP1_Msk ) + + +/*************** Bits definition for ETH_MACL3A01R **********************/ + +#define ETH_MACL3A01R_L3A01_Pos ( 0U ) +#define ETH_MACL3A01R_L3A01_Msk ( 0xFFFFFFFFUL << ETH_MACL3A01R_L3A01_Pos ) +#define ETH_MACL3A01R_L3A01 ( ETH_MACL3A01R_L3A01_Msk ) + + +/*************** Bits definition for ETH_MACL3A11R **********************/ + +#define ETH_MACL3A11R_L3A11_Pos ( 0U ) +#define ETH_MACL3A11R_L3A11_Msk ( 0xFFFFFFFFUL << ETH_MACL3A11R_L3A11_Pos ) +#define ETH_MACL3A11R_L3A11 ( ETH_MACL3A11R_L3A11_Msk ) + + +/*************** Bits definition for ETH_MACL3A21R **********************/ + +#define ETH_MACL3A21R_L3A21_Pos ( 0U ) +#define ETH_MACL3A21R_L3A21_Msk ( 0xFFFFFFFFUL << ETH_MACL3A21R_L3A21_Pos ) +#define ETH_MACL3A21R_L3A21 ( ETH_MACL3A21R_L3A21_Msk ) + + +/*************** Bits definition for ETH_MACL3A31R **********************/ + +#define ETH_MACL3A31R_L3A31_Pos ( 0U ) +#define ETH_MACL3A31R_L3A31_Msk ( 0xFFFFFFFFUL << ETH_MACL3A31R_L3A31_Pos ) +#define ETH_MACL3A31R_L3A31 ( ETH_MACL3A31R_L3A31_Msk ) + + +/*************** Bits definition for ETH_MACVTIRR **********************/ + +#define ETH_MACVTIRR_CSVL_Pos ( 19U ) +#define ETH_MACVTIRR_CSVL_Msk ( 0x1UL << ETH_MACVTIRR_CSVL_Pos ) +#define ETH_MACVTIRR_CSVL ( ETH_MACVTIRR_CSVL_Msk ) + +#define ETH_MACVTIRR_VLP_Pos ( 18U ) +#define ETH_MACVTIRR_VLP_Msk ( 0x1UL << ETH_MACVTIRR_VLP_Pos ) +#define ETH_MACVTIRR_VLP ( ETH_MACVTIRR_VLP_Msk ) + +#define ETH_MACVTIRR_VLC_Pos ( 16U ) +#define ETH_MACVTIRR_VLC_Msk ( 0x3UL << ETH_MACVTIRR_VLC_Pos ) +#define ETH_MACVTIRR_VLC ( ETH_MACVTIRR_VLC_Msk ) +#define ETH_MACVTIRR_VLC_0 ( 0x1UL << ETH_MACVTIRR_VLC_Pos ) +#define ETH_MACVTIRR_VLC_1 ( 0x2UL << ETH_MACVTIRR_VLC_Pos ) + +#define ETH_MACVTIRR_VLT_Pos ( 0U ) +#define ETH_MACVTIRR_VLT_Msk ( 0xFFFFUL << ETH_MACVTIRR_VLT_Pos ) +#define ETH_MACVTIRR_VLT ( ETH_MACVTIRR_VLT_Msk ) + + +/*************** Bits definition for ETH_MACVHTR **********************/ + +#define ETH_MACVHTR_CSVL_Pos ( 0U ) +#define ETH_MACVHTR_CSVL_Msk ( 0xFFFFUL << ETH_MACVHTR_CSVL_Pos ) +#define ETH_MACVHTR_CSVL ( ETH_MACVHTR_CSVL_Msk ) + + +/*************** Bits definition for ETH_PTPTSCR **********************/ + +#define ETH_PTPTSCR_ASEN3_Pos ( 28U ) +#define ETH_PTPTSCR_ASEN3_Msk ( 0x1UL << ETH_PTPTSCR_ASEN3_Pos ) +#define ETH_PTPTSCR_ASEN3 ( ETH_PTPTSCR_ASEN3_Msk ) + +#define ETH_PTPTSCR_ASEN2_Pos ( 27U ) +#define ETH_PTPTSCR_ASEN2_Msk ( 0x1UL << ETH_PTPTSCR_ASEN2_Pos ) +#define ETH_PTPTSCR_ASEN2 ( ETH_PTPTSCR_ASEN2_Msk ) + +#define ETH_PTPTSCR_ASEN1_Pos ( 26U ) +#define ETH_PTPTSCR_ASEN1_Msk ( 0x1UL << ETH_PTPTSCR_ASEN1_Pos ) +#define ETH_PTPTSCR_ASEN1 ( ETH_PTPTSCR_ASEN1_Msk ) + +#define ETH_PTPTSCR_ASEN0_Pos ( 25U ) +#define ETH_PTPTSCR_ASEN0_Msk ( 0x1UL << ETH_PTPTSCR_ASEN0_Pos ) +#define ETH_PTPTSCR_ASEN0 ( ETH_PTPTSCR_ASEN0_Msk ) + +#define ETH_PTPTSCR_ASFC_Pos ( 24U ) +#define ETH_PTPTSCR_ASFC_Msk ( 0x1UL << ETH_PTPTSCR_ASFC_Pos ) +#define ETH_PTPTSCR_ASFC ( ETH_PTPTSCR_ASFC_Msk ) + +#define ETH_PTPTSCR_EMAFPFF_Pos ( 18U ) +#define ETH_PTPTSCR_EMAFPFF_Msk ( 0x1UL << ETH_PTPTSCR_EMAFPFF_Pos ) +#define ETH_PTPTSCR_EMAFPFF ( ETH_PTPTSCR_EMAFPFF_Msk ) + +#define ETH_PTPTSCR_SPPFTS_Pos ( 16U ) +#define ETH_PTPTSCR_SPPFTS_Msk ( 0x3UL << ETH_PTPTSCR_SPPFTS_Pos ) +#define ETH_PTPTSCR_SPPFTS ( ETH_PTPTSCR_SPPFTS_Msk ) +#define ETH_PTPTSCR_SPPFTS_0 ( 0x1UL << ETH_PTPTSCR_SPPFTS_Pos ) +#define ETH_PTPTSCR_SPPFTS_1 ( 0x2UL << ETH_PTPTSCR_SPPFTS_Pos ) + +#define ETH_PTPTSCR_ESFMRTM_Pos ( 15U ) +#define ETH_PTPTSCR_ESFMRTM_Msk ( 0x1UL << ETH_PTPTSCR_ESFMRTM_Pos ) +#define ETH_PTPTSCR_ESFMRTM ( ETH_PTPTSCR_ESFMRTM_Msk ) + +#define ETH_PTPTSCR_ETSFEM_Pos ( 14U ) +#define ETH_PTPTSCR_ETSFEM_Msk ( 0x1UL << ETH_PTPTSCR_ETSFEM_Pos ) +#define ETH_PTPTSCR_ETSFEM ( ETH_PTPTSCR_ETSFEM_Msk ) + +#define ETH_PTPTSCR_EPPFSIP4U_Pos ( 13U ) +#define ETH_PTPTSCR_EPPFSIP4U_Msk ( 0x1UL << ETH_PTPTSCR_EPPFSIP4U_Pos ) +#define ETH_PTPTSCR_EPPFSIP4U ( ETH_PTPTSCR_EPPFSIP4U_Msk ) + +#define ETH_PTPTSCR_EPPFSIP6U_Pos ( 12U ) +#define ETH_PTPTSCR_EPPFSIP6U_Msk ( 0x1UL << ETH_PTPTSCR_EPPFSIP6U_Pos ) +#define ETH_PTPTSCR_EPPFSIP6U ( ETH_PTPTSCR_EPPFSIP6U_Msk ) + +#define ETH_PTPTSCR_EPPEF_Pos ( 11U ) +#define ETH_PTPTSCR_EPPEF_Msk ( 0x1UL << ETH_PTPTSCR_EPPEF_Pos ) +#define ETH_PTPTSCR_EPPEF ( ETH_PTPTSCR_EPPEF_Msk ) + +#define ETH_PTPTSCR_TSPTPPSV2E_Pos ( 10U ) +#define ETH_PTPTSCR_TSPTPPSV2E_Msk ( 0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos ) +#define ETH_PTPTSCR_TSPTPPSV2E ( ETH_PTPTSCR_TSPTPPSV2E_Msk ) + +#define ETH_PTPTSCR_TSR_Pos ( 9U ) +#define ETH_PTPTSCR_TSR_Msk ( 0x1UL << ETH_PTPTSCR_TSR_Pos ) +#define ETH_PTPTSCR_TSR ( ETH_PTPTSCR_TSR_Msk ) + +#define ETH_PTPTSCR_TSARFE_Pos ( 8U ) +#define ETH_PTPTSCR_TSARFE_Msk ( 0x1UL << ETH_PTPTSCR_TSARFE_Pos ) +#define ETH_PTPTSCR_TSARFE ( ETH_PTPTSCR_TSARFE_Msk ) + +#define ETH_PTPTSCR_TARU_Pos ( 5U ) +#define ETH_PTPTSCR_TARU_Msk ( 0x1UL << ETH_PTPTSCR_TARU_Pos ) +#define ETH_PTPTSCR_TARU ( ETH_PTPTSCR_TARU_Msk ) + +#define ETH_PTPTSCR_TITE_Pos ( 4U ) +#define ETH_PTPTSCR_TITE_Msk ( 0x1UL << ETH_PTPTSCR_TITE_Pos ) +#define ETH_PTPTSCR_TITE ( ETH_PTPTSCR_TITE_Msk ) + +#define ETH_PTPTSCR_TU_Pos ( 3U ) +#define ETH_PTPTSCR_TU_Msk ( 0x1UL << ETH_PTPTSCR_TU_Pos ) +#define ETH_PTPTSCR_TU ( ETH_PTPTSCR_TU_Msk ) + +#define ETH_PTPTSCR_TI_Pos ( 2U ) +#define ETH_PTPTSCR_TI_Msk ( 0x1UL << ETH_PTPTSCR_TI_Pos ) +#define ETH_PTPTSCR_TI ( ETH_PTPTSCR_TI_Msk ) + +#define ETH_PTPTSCR_TFCU_Pos ( 1U ) +#define ETH_PTPTSCR_TFCU_Msk ( 0x1UL << ETH_PTPTSCR_TFCU_Pos ) +#define ETH_PTPTSCR_TFCU ( ETH_PTPTSCR_TFCU_Msk ) + +#define ETH_PTPTSCR_TE_Pos ( 0U ) +#define ETH_PTPTSCR_TE_Msk ( 0x1UL << ETH_PTPTSCR_TE_Pos ) +#define ETH_PTPTSCR_TE ( ETH_PTPTSCR_TE_Msk ) + + +/*************** Bits definition for ETH_PTPSSIR **********************/ + +#define ETH_PTPSSIR_SSIV_Pos ( 0U ) +#define ETH_PTPSSIR_SSIV_Msk ( 0xffUL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV ( ETH_PTPSSIR_SSIV_Msk ) +#define ETH_PTPSSIR_SSIV_0 ( 0x1UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_1 ( 0x2UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_2 ( 0x4UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_3 ( 0x8UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_4 ( 0x10UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_5 ( 0x20UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_6 ( 0x40UL << ETH_PTPSSIR_SSIV_Pos ) +#define ETH_PTPSSIR_SSIV_7 ( 0x80UL << ETH_PTPSSIR_SSIV_Pos ) + + +/*************** Bits definition for ETH_PTPTSHR **********************/ + +#define ETH_PTPTSHR_TS_Pos ( 0U ) +#define ETH_PTPTSHR_TS_Msk ( 0xffffffffUL << ETH_PTPTSHR_TS_Pos ) +#define ETH_PTPTSHR_TS ( ETH_PTPTSHR_TS_Msk ) + + +/*************** Bits definition for ETH_PTPTSLR **********************/ + +#define ETH_PTPTSLR_TSS_Pos ( 0U ) +#define ETH_PTPTSLR_TSS_Msk ( 0x7fffffffUL << ETH_PTPTSLR_TSS_Pos ) +#define ETH_PTPTSLR_TSS ( ETH_PTPTSLR_TSS_Msk ) + + +/*************** Bits definition for ETH_PTPTSHUR **********************/ + +#define ETH_PTPTSHUR_TSU_Pos ( 0U ) +#define ETH_PTPTSHUR_TSU_Msk ( 0xffffffffUL << ETH_PTPTSHUR_TSU_Pos ) +#define ETH_PTPTSHUR_TSU ( ETH_PTPTSHUR_TSU_Msk ) + + +/*************** Bits definition for ETH_PTPTSLUR **********************/ + +#define ETH_PTPTSLUR_AST_Pos ( 31U ) +#define ETH_PTPTSLUR_AST_Msk ( 0x1UL << ETH_PTPTSLUR_AST_Pos ) +#define ETH_PTPTSLUR_AST ( ETH_PTPTSLUR_AST_Msk ) + +#define ETH_PTPTSLUR_TSSU_Pos ( 0U ) +#define ETH_PTPTSLUR_TSSU_Msk ( 0x7fffffffUL << ETH_PTPTSLUR_TSSU_Pos ) +#define ETH_PTPTSLUR_TSSU ( ETH_PTPTSLUR_TSSU_Msk ) + + +/*************** Bits definition for ETH_PTPTSAR **********************/ + +#define ETH_PTPTSAR_TAR_Pos ( 0U ) +#define ETH_PTPTSAR_TAR_Msk ( 0xffffffffUL << ETH_PTPTSAR_TAR_Pos ) +#define ETH_PTPTSAR_TAR ( ETH_PTPTSAR_TAR_Msk ) + + +/*************** Bits definition for ETH_PTPTTHR **********************/ + +#define ETH_PTPTTHR_TTSR_Pos ( 0U ) +#define ETH_PTPTTHR_TTSR_Msk ( 0xffffffffUL << ETH_PTPTTHR_TTSR_Pos ) +#define ETH_PTPTTHR_TTSR ( ETH_PTPTTHR_TTSR_Msk ) + + +/*************** Bits definition for ETH_PTPTTLR **********************/ + +#define ETH_PTPTTLR_TTRB_Pos ( 31U ) +#define ETH_PTPTTLR_TTRB_Msk ( 0x1UL << ETH_PTPTTLR_TTRB_Pos ) +#define ETH_PTPTTLR_TTRB ( ETH_PTPTTLR_TTRB_Msk ) + +#define ETH_PTPTTLR_TTLR_Pos ( 0U ) +#define ETH_PTPTTLR_TTLR_Msk ( 0x7fffffffUL << ETH_PTPTTLR_TTLR_Pos ) +#define ETH_PTPTTLR_TTLR ( ETH_PTPTTLR_TTLR_Msk ) + + +/*************** Bits definition for ETH_PTPTSSR **********************/ + +#define ETH_PTPTSSR_ATSNS_Pos ( 25U ) +#define ETH_PTPTSSR_ATSNS_Msk ( 0x7UL << ETH_PTPTSSR_ATSNS_Pos ) +#define ETH_PTPTSSR_ATSNS ( ETH_PTPTSSR_ATSNS_Msk ) + +#define ETH_PTPTSSR_ATSTM_Pos ( 24U ) +#define ETH_PTPTSSR_ATSTM_Msk ( 0x1UL << ETH_PTPTSSR_ATSTM_Pos ) +#define ETH_PTPTSSR_ATSTM ( ETH_PTPTSSR_ATSTM_Msk ) + +#define ETH_PTPTSSR_ATSTI_Pos ( 16U ) +#define ETH_PTPTSSR_ATSTI_Msk ( 0xFUL << ETH_PTPTSSR_ATSTI_Pos ) +#define ETH_PTPTSSR_ATSTI ( ETH_PTPTSSR_ATSTI_Msk ) +#define ETH_PTPTSSR_ATSTI_0 ( 0x1UL << ETH_PTPTSSR_ATSTI_Pos ) +#define ETH_PTPTSSR_ATSTI_1 ( 0x2UL << ETH_PTPTSSR_ATSTI_Pos ) +#define ETH_PTPTSSR_ATSTI_2 ( 0x4UL << ETH_PTPTSSR_ATSTI_Pos ) +#define ETH_PTPTSSR_ATSTI_3 ( 0x8UL << ETH_PTPTSSR_ATSTI_Pos ) + +#define ETH_PTPTSSR_TTTE_Pos ( 3U ) +#define ETH_PTPTSSR_TTTE_Msk ( 0x1UL << ETH_PTPTSSR_TTTE_Pos ) +#define ETH_PTPTSSR_TTTE ( ETH_PTPTSSR_TTTE_Msk ) + +#define ETH_PTPTSSR_ATTS_Pos ( 2U ) +#define ETH_PTPTSSR_ATTS_Msk ( 0x1UL << ETH_PTPTSSR_ATTS_Pos ) +#define ETH_PTPTSSR_ATTS ( ETH_PTPTSSR_ATTS_Msk ) + +#define ETH_PTPTSSR_TTTR_Pos ( 1U ) +#define ETH_PTPTSSR_TTTR_Msk ( 0x1UL << ETH_PTPTSSR_TTTR_Pos ) +#define ETH_PTPTSSR_TTTR ( ETH_PTPTSSR_TTTR_Msk ) + +#define ETH_PTPTSSR_TSO_Pos ( 0U ) +#define ETH_PTPTSSR_TSO_Msk ( 0x1UL << ETH_PTPTSSR_TSO_Pos ) +#define ETH_PTPTSSR_TSO ( ETH_PTPTSSR_TSO_Msk ) + + +/*************** Bits definition for ETH_PTPPPSCR **********************/ + +#define ETH_PTPPPSCR_TRGTMODSEL_Pos ( 5U ) +#define ETH_PTPPPSCR_TRGTMODSEL_Msk ( 0x3UL << ETH_PTPPPSCR_TRGTMODSEL_Pos ) +#define ETH_PTPPPSCR_TRGTMODSEL ( ETH_PTPPPSCR_TRGTMODSEL_Msk ) +#define ETH_PTPPPSCR_TRGTMODSEL_0 ( 0x1UL << ETH_PTPPPSCR_TRGTMODSEL_Pos ) +#define ETH_PTPPPSCR_TRGTMODSEL_1 ( 0x2UL << ETH_PTPPPSCR_TRGTMODSEL_Pos ) + +#define ETH_PTPPPSCR_PPSEN_Pos ( 4U ) +#define ETH_PTPPPSCR_PPSEN_Msk ( 0x1UL << ETH_PTPPPSCR_PPSEN_Pos ) +#define ETH_PTPPPSCR_PPSEN ( ETH_PTPPPSCR_PPSEN_Msk ) + +#define ETH_PTPPPSCR_PPSCTRL_Pos ( 0U ) +#define ETH_PTPPPSCR_PPSCTRL_Msk ( 0xfUL << ETH_PTPPPSCR_PPSCTRL_Pos ) +#define ETH_PTPPPSCR_PPSCTRL ( ETH_PTPPPSCR_PPSCTRL_Msk ) +#define ETH_PTPPPSCR_PPSCTRL_0 ( 0x1UL << ETH_PTPPPSCR_PPSCTRL_Pos ) +#define ETH_PTPPPSCR_PPSCTRL_1 ( 0x2UL << ETH_PTPPPSCR_PPSCTRL_Pos ) +#define ETH_PTPPPSCR_PPSCTRL_2 ( 0x4UL << ETH_PTPPPSCR_PPSCTRL_Pos ) +#define ETH_PTPPPSCR_PPSCTRL_3 ( 0x8UL << ETH_PTPPPSCR_PPSCTRL_Pos ) + +#define ETH_PTPPPSCR_PPSCMD_Pos ( 0U ) +#define ETH_PTPPPSCR_PPSCMD_Msk ( 0xfUL << ETH_PTPPPSCR_PPSCMD_Pos ) +#define ETH_PTPPPSCR_PPSCMD ( ETH_PTPPPSCR_PPSCMD_Msk ) +#define ETH_PTPPPSCR_PPSCMD_0 ( 0x1UL << ETH_PTPPPSCR_PPSCMD_Pos ) +#define ETH_PTPPPSCR_PPSCMD_1 ( 0x2UL << ETH_PTPPPSCR_PPSCMD_Pos ) +#define ETH_PTPPPSCR_PPSCMD_2 ( 0x4UL << ETH_PTPPPSCR_PPSCMD_Pos ) +#define ETH_PTPPPSCR_PPSCMD_3 ( 0x8UL << ETH_PTPPPSCR_PPSCMD_Pos ) + + +/*************** Bits definition for ETH_PTPATSNR **********************/ + +#define ETH_PTPATSNR_AUSTSLO_Pos ( 0U ) +#define ETH_PTPATSNR_AUSTSLO_Msk ( 0x7fffffffUL << ETH_PTPATSNR_AUSTSLO_Pos ) +#define ETH_PTPATSNR_AUSTSLO ( ETH_PTPATSNR_AUSTSLO_Msk ) + + +/*************** Bits definition for ETH_PTPATSSR **********************/ + +#define ETH_PTPATSSR_AUSTSHI_Pos ( 0U ) +#define ETH_PTPATSSR_AUSTSHI_Msk ( 0x7fffffffUL << ETH_PTPATSSR_AUSTSHI_Pos ) +#define ETH_PTPATSSR_AUSTSHI ( ETH_PTPATSSR_AUSTSHI_Msk ) + + +/*************** Bits definition for ETH_PTPPPSIR **********************/ + +#define ETH_PTPPPSIR_PPSINT_Pos ( 0U ) +#define ETH_PTPPPSIR_PPSINT_Msk ( 0xffffffffUL << ETH_PTPPPSIR_PPSINT_Pos ) +#define ETH_PTPPPSIR_PPSINT ( ETH_PTPPPSIR_PPSINT_Msk ) + + +/*************** Bits definition for ETH_PTPPPSWR **********************/ + +#define ETH_PTPPPSWR_PPSWIDTH_Pos ( 0U ) +#define ETH_PTPPPSWR_PPSWIDTH_Msk ( 0xffffffffUL << ETH_PTPPPSWR_PPSWIDTH_Pos ) +#define ETH_PTPPPSWR_PPSWIDTH ( ETH_PTPPPSWR_PPSWIDTH_Msk ) + + +/*************** Bits definition for ETH_DMABMR **********************/ + +#define ETH_DMABMR_RIB_Pos ( 31U ) +#define ETH_DMABMR_RIB_Msk ( 0x1UL << ETH_DMABMR_RIB_Pos ) +#define ETH_DMABMR_RIB ( ETH_DMABMR_RIB_Msk ) + +#define ETH_DMABMR_TXPR_Pos ( 27U ) +#define ETH_DMABMR_TXPR_Msk ( 0x1UL << ETH_DMABMR_TXPR_Pos ) +#define ETH_DMABMR_TXPR ( ETH_DMABMR_TXPR_Msk ) + +#define ETH_DMABMR_MB_Pos ( 26U ) +#define ETH_DMABMR_MB_Msk ( 0x1UL << ETH_DMABMR_MB_Pos ) +#define ETH_DMABMR_MB ( ETH_DMABMR_MB_Msk ) + +#define ETH_DMABMR_AAB_Pos ( 25U ) +#define ETH_DMABMR_AAB_Msk ( 0x1UL << ETH_DMABMR_AAB_Pos ) +#define ETH_DMABMR_AAB ( ETH_DMABMR_AAB_Msk ) + +#define ETH_DMABMR_EPM_Pos ( 24U ) +#define ETH_DMABMR_EPM_Msk ( 0x1UL << ETH_DMABMR_EPM_Pos ) +#define ETH_DMABMR_EPM ( ETH_DMABMR_EPM_Msk ) + +#define ETH_DMABMR_USP_Pos ( 23U ) +#define ETH_DMABMR_USP_Msk ( 0x1UL << ETH_DMABMR_USP_Pos ) +#define ETH_DMABMR_USP ( ETH_DMABMR_USP_Msk ) + +#define ETH_DMABMR_RDP_Pos ( 17U ) +#define ETH_DMABMR_RDP_Msk ( 0x3fUL << ETH_DMABMR_RDP_Pos ) +#define ETH_DMABMR_RDP ( ETH_DMABMR_RDP_Msk ) +#define ETH_DMABMR_RDP_0 ( 0x1UL << ETH_DMABMR_RDP_Pos ) +#define ETH_DMABMR_RDP_1 ( 0x2UL << ETH_DMABMR_RDP_Pos ) +#define ETH_DMABMR_RDP_2 ( 0x4UL << ETH_DMABMR_RDP_Pos ) +#define ETH_DMABMR_RDP_3 ( 0x8UL << ETH_DMABMR_RDP_Pos ) +#define ETH_DMABMR_RDP_4 ( 0x10UL << ETH_DMABMR_RDP_Pos ) +#define ETH_DMABMR_RDP_5 ( 0x20UL << ETH_DMABMR_RDP_Pos ) + +#define ETH_DMABMR_FB_Pos ( 16U ) +#define ETH_DMABMR_FB_Msk ( 0x1UL << ETH_DMABMR_FB_Pos ) +#define ETH_DMABMR_FB ( ETH_DMABMR_FB_Msk ) + +#define ETH_DMABMR_PM_Pos ( 14U ) +#define ETH_DMABMR_PM_Msk ( 0x3UL << ETH_DMABMR_PM_Pos ) +#define ETH_DMABMR_PM ( ETH_DMABMR_PM_Msk ) +#define ETH_DMABMR_PM_0 ( 0x1UL << ETH_DMABMR_PM_Pos ) +#define ETH_DMABMR_PM_1 ( 0x2UL << ETH_DMABMR_PM_Pos ) + +#define ETH_DMABMR_PBL_Pos ( 8U ) +#define ETH_DMABMR_PBL_Msk ( 0x3fUL << ETH_DMABMR_PBL_Pos ) +#define ETH_DMABMR_PBL ( ETH_DMABMR_PBL_Msk ) +#define ETH_DMABMR_PBL_0 ( 0x1UL << ETH_DMABMR_PBL_Pos ) +#define ETH_DMABMR_PBL_1 ( 0x2UL << ETH_DMABMR_PBL_Pos ) +#define ETH_DMABMR_PBL_2 ( 0x4UL << ETH_DMABMR_PBL_Pos ) +#define ETH_DMABMR_PBL_3 ( 0x8UL << ETH_DMABMR_PBL_Pos ) +#define ETH_DMABMR_PBL_4 ( 0x10UL << ETH_DMABMR_PBL_Pos ) +#define ETH_DMABMR_PBL_5 ( 0x20UL << ETH_DMABMR_PBL_Pos ) + +#define ETH_DMABMR_EDFE_Pos ( 7U ) +#define ETH_DMABMR_EDFE_Msk ( 0x1UL << ETH_DMABMR_EDFE_Pos ) +#define ETH_DMABMR_EDFE ( ETH_DMABMR_EDFE_Msk ) + +#define ETH_DMABMR_DSL_Pos ( 2U ) +#define ETH_DMABMR_DSL_Msk ( 0x1fUL << ETH_DMABMR_DSL_Pos ) +#define ETH_DMABMR_DSL ( ETH_DMABMR_DSL_Msk ) +#define ETH_DMABMR_DSL_0 ( 0x1UL << ETH_DMABMR_DSL_Pos ) +#define ETH_DMABMR_DSL_1 ( 0x2UL << ETH_DMABMR_DSL_Pos ) +#define ETH_DMABMR_DSL_2 ( 0x4UL << ETH_DMABMR_DSL_Pos ) +#define ETH_DMABMR_DSL_3 ( 0x8UL << ETH_DMABMR_DSL_Pos ) +#define ETH_DMABMR_DSL_4 ( 0x10UL << ETH_DMABMR_DSL_Pos ) + +#define ETH_DMABMR_DA_Pos ( 1U ) +#define ETH_DMABMR_DA_Msk ( 0x1UL << ETH_DMABMR_DA_Pos ) +#define ETH_DMABMR_DA ( ETH_DMABMR_DA_Msk ) + +#define ETH_DMABMR_SWR_Pos ( 0U ) +#define ETH_DMABMR_SWR_Msk ( 0x1UL << ETH_DMABMR_SWR_Pos ) +#define ETH_DMABMR_SWR ( ETH_DMABMR_SWR_Msk ) + + +/*************** Bits definition for ETH_DMATPDR **********************/ + +#define ETH_DMATPDR_TPD_Pos ( 0U ) +#define ETH_DMATPDR_TPD_Msk ( 0xffffffffUL << ETH_DMATPDR_TPD_Pos ) +#define ETH_DMATPDR_TPD ( ETH_DMATPDR_TPD_Msk ) + + +/*************** Bits definition for ETH_DMARPDR **********************/ + +#define ETH_DMARPDR_RPD_Pos ( 0U ) +#define ETH_DMARPDR_RPD_Msk ( 0xffffffffUL << ETH_DMARPDR_RPD_Pos ) +#define ETH_DMARPDR_RPD ( ETH_DMARPDR_RPD_Msk ) + + +/*************** Bits definition for ETH_DMARDLAR **********************/ + +#define ETH_DMARDLAR_SRL_Pos ( 0U ) +#define ETH_DMARDLAR_SRL_Msk ( 0xffffffffUL << ETH_DMARDLAR_SRL_Pos ) +#define ETH_DMARDLAR_SRL ( ETH_DMARDLAR_SRL_Msk ) + + +/*************** Bits definition for ETH_DMATDLAR **********************/ + +#define ETH_DMATDLAR_STL_Pos ( 0U ) +#define ETH_DMATDLAR_STL_Msk ( 0xffffffffUL << ETH_DMATDLAR_STL_Pos ) +#define ETH_DMATDLAR_STL ( ETH_DMATDLAR_STL_Msk ) + + +/*************** Bits definition for ETH_DMASR **********************/ + +#define ETH_DMASR_LPIS_Pos ( 30U ) +#define ETH_DMASR_LPIS_Msk ( 0x1UL << ETH_DMASR_LPIS_Pos ) +#define ETH_DMASR_LPIS ( ETH_DMASR_LPIS_Msk ) + +#define ETH_DMASR_TSTS_Pos ( 29U ) +#define ETH_DMASR_TSTS_Msk ( 0x1UL << ETH_DMASR_TSTS_Pos ) +#define ETH_DMASR_TSTS ( ETH_DMASR_TSTS_Msk ) + +#define ETH_DMASR_PMTS_Pos ( 28U ) +#define ETH_DMASR_PMTS_Msk ( 0x1UL << ETH_DMASR_PMTS_Pos ) +#define ETH_DMASR_PMTS ( ETH_DMASR_PMTS_Msk ) + +#define ETH_DMASR_MMCS_Pos ( 27U ) +#define ETH_DMASR_MMCS_Msk ( 0x1UL << ETH_DMASR_MMCS_Pos ) +#define ETH_DMASR_MMCS ( ETH_DMASR_MMCS_Msk ) + +#define ETH_DMASR_EBS_Pos ( 23U ) +#define ETH_DMASR_EBS_Msk ( 0x7UL << ETH_DMASR_EBS_Pos ) +#define ETH_DMASR_EBS ( ETH_DMASR_EBS_Msk ) +#define ETH_DMASR_EBS_0 ( 0x1UL << ETH_DMASR_EBS_Pos ) +#define ETH_DMASR_EBS_1 ( 0x2UL << ETH_DMASR_EBS_Pos ) +#define ETH_DMASR_EBS_2 ( 0x4UL << ETH_DMASR_EBS_Pos ) + +#define ETH_DMASR_TPS_Pos ( 20U ) +#define ETH_DMASR_TPS_Msk ( 0x7UL << ETH_DMASR_TPS_Pos ) +#define ETH_DMASR_TPS ( ETH_DMASR_TPS_Msk ) +#define ETH_DMASR_TPS_0 ( 0x1UL << ETH_DMASR_TPS_Pos ) +#define ETH_DMASR_TPS_1 ( 0x2UL << ETH_DMASR_TPS_Pos ) +#define ETH_DMASR_TPS_2 ( 0x4UL << ETH_DMASR_TPS_Pos ) + +#define ETH_DMASR_RPS_Pos ( 17U ) +#define ETH_DMASR_RPS_Msk ( 0x7UL << ETH_DMASR_RPS_Pos ) +#define ETH_DMASR_RPS ( ETH_DMASR_RPS_Msk ) +#define ETH_DMASR_RPS_0 ( 0x1UL << ETH_DMASR_RPS_Pos ) +#define ETH_DMASR_RPS_1 ( 0x2UL << ETH_DMASR_RPS_Pos ) +#define ETH_DMASR_RPS_2 ( 0x4UL << ETH_DMASR_RPS_Pos ) + +#define ETH_DMASR_NIS_Pos ( 16U ) +#define ETH_DMASR_NIS_Msk ( 0x1UL << ETH_DMASR_NIS_Pos ) +#define ETH_DMASR_NIS ( ETH_DMASR_NIS_Msk ) + +#define ETH_DMASR_AIS_Pos ( 15U ) +#define ETH_DMASR_AIS_Msk ( 0x1UL << ETH_DMASR_AIS_Pos ) +#define ETH_DMASR_AIS ( ETH_DMASR_AIS_Msk ) + +#define ETH_DMASR_ERS_Pos ( 14U ) +#define ETH_DMASR_ERS_Msk ( 0x1UL << ETH_DMASR_ERS_Pos ) +#define ETH_DMASR_ERS ( ETH_DMASR_ERS_Msk ) + +#define ETH_DMASR_FBES_Pos ( 13U ) +#define ETH_DMASR_FBES_Msk ( 0x1UL << ETH_DMASR_FBES_Pos ) +#define ETH_DMASR_FBES ( ETH_DMASR_FBES_Msk ) + +#define ETH_DMASR_ETS_Pos ( 10U ) +#define ETH_DMASR_ETS_Msk ( 0x1UL << ETH_DMASR_ETS_Pos ) +#define ETH_DMASR_ETS ( ETH_DMASR_ETS_Msk ) + +#define ETH_DMASR_RWTS_Pos ( 9U ) +#define ETH_DMASR_RWTS_Msk ( 0x1UL << ETH_DMASR_RWTS_Pos ) +#define ETH_DMASR_RWTS ( ETH_DMASR_RWTS_Msk ) + +#define ETH_DMASR_RPSS_Pos ( 8U ) +#define ETH_DMASR_RPSS_Msk ( 0x1UL << ETH_DMASR_RPSS_Pos ) +#define ETH_DMASR_RPSS ( ETH_DMASR_RPSS_Msk ) + +#define ETH_DMASR_RBUS_Pos ( 7U ) +#define ETH_DMASR_RBUS_Msk ( 0x1UL << ETH_DMASR_RBUS_Pos ) +#define ETH_DMASR_RBUS ( ETH_DMASR_RBUS_Msk ) + +#define ETH_DMASR_RS_Pos ( 6U ) +#define ETH_DMASR_RS_Msk ( 0x1UL << ETH_DMASR_RS_Pos ) +#define ETH_DMASR_RS ( ETH_DMASR_RS_Msk ) + +#define ETH_DMASR_TUS_Pos ( 5U ) +#define ETH_DMASR_TUS_Msk ( 0x1UL << ETH_DMASR_TUS_Pos ) +#define ETH_DMASR_TUS ( ETH_DMASR_TUS_Msk ) + +#define ETH_DMASR_ROS_Pos ( 4U ) +#define ETH_DMASR_ROS_Msk ( 0x1UL << ETH_DMASR_ROS_Pos ) +#define ETH_DMASR_ROS ( ETH_DMASR_ROS_Msk ) + +#define ETH_DMASR_TJTS_Pos ( 3U ) +#define ETH_DMASR_TJTS_Msk ( 0x1UL << ETH_DMASR_TJTS_Pos ) +#define ETH_DMASR_TJTS ( ETH_DMASR_TJTS_Msk ) + +#define ETH_DMASR_TBUS_Pos ( 2U ) +#define ETH_DMASR_TBUS_Msk ( 0x1UL << ETH_DMASR_TBUS_Pos ) +#define ETH_DMASR_TBUS ( ETH_DMASR_TBUS_Msk ) + +#define ETH_DMASR_TPSS_Pos ( 1U ) +#define ETH_DMASR_TPSS_Msk ( 0x1UL << ETH_DMASR_TPSS_Pos ) +#define ETH_DMASR_TPSS ( ETH_DMASR_TPSS_Msk ) + +#define ETH_DMASR_TS_Pos ( 0U ) +#define ETH_DMASR_TS_Msk ( 0x1UL << ETH_DMASR_TS_Pos ) +#define ETH_DMASR_TS ( ETH_DMASR_TS_Msk ) + + +/*************** Bits definition for ETH_DMAOMR **********************/ + +#define ETH_DMAOMR_DTCEFD_Pos ( 26U ) +#define ETH_DMAOMR_DTCEFD_Msk ( 0x1UL << ETH_DMAOMR_DTCEFD_Pos ) +#define ETH_DMAOMR_DTCEFD ( ETH_DMAOMR_DTCEFD_Msk ) + +#define ETH_DMAOMR_RSF_Pos ( 25U ) +#define ETH_DMAOMR_RSF_Msk ( 0x1UL << ETH_DMAOMR_RSF_Pos ) +#define ETH_DMAOMR_RSF ( ETH_DMAOMR_RSF_Msk ) + +#define ETH_DMAOMR_DFRF_Pos ( 24U ) +#define ETH_DMAOMR_DFRF_Msk ( 0x1UL << ETH_DMAOMR_DFRF_Pos ) +#define ETH_DMAOMR_DFRF ( ETH_DMAOMR_DFRF_Msk ) + +#define ETH_DMAOMR_TSF_Pos ( 21U ) +#define ETH_DMAOMR_TSF_Msk ( 0x1UL << ETH_DMAOMR_TSF_Pos ) +#define ETH_DMAOMR_TSF ( ETH_DMAOMR_TSF_Msk ) + +#define ETH_DMAOMR_FTF_Pos ( 20U ) +#define ETH_DMAOMR_FTF_Msk ( 0x1UL << ETH_DMAOMR_FTF_Pos ) +#define ETH_DMAOMR_FTF ( ETH_DMAOMR_FTF_Msk ) + +#define ETH_DMAOMR_TTC_Pos ( 14U ) +#define ETH_DMAOMR_TTC_Msk ( 0x7UL << ETH_DMAOMR_TTC_Pos ) +#define ETH_DMAOMR_TTC ( ETH_DMAOMR_TTC_Msk ) +#define ETH_DMAOMR_TTC_0 ( 0x1UL << ETH_DMAOMR_TTC_Pos ) +#define ETH_DMAOMR_TTC_1 ( 0x2UL << ETH_DMAOMR_TTC_Pos ) +#define ETH_DMAOMR_TTC_2 ( 0x4UL << ETH_DMAOMR_TTC_Pos ) + +#define ETH_DMAOMR_ST_Pos ( 13U ) +#define ETH_DMAOMR_ST_Msk ( 0x1UL << ETH_DMAOMR_ST_Pos ) +#define ETH_DMAOMR_ST ( ETH_DMAOMR_ST_Msk ) + +#define ETH_DMAOMR_FEF_Pos ( 7U ) +#define ETH_DMAOMR_FEF_Msk ( 0x1UL << ETH_DMAOMR_FEF_Pos ) +#define ETH_DMAOMR_FEF ( ETH_DMAOMR_FEF_Msk ) + +#define ETH_DMAOMR_FUGF_Pos ( 6U ) +#define ETH_DMAOMR_FUGF_Msk ( 0x1UL << ETH_DMAOMR_FUGF_Pos ) +#define ETH_DMAOMR_FUGF ( ETH_DMAOMR_FUGF_Msk ) + +#define ETH_DMAOMR_DGF_Pos ( 5U ) +#define ETH_DMAOMR_DGF_Msk ( 0x1UL << ETH_DMAOMR_DGF_Pos ) +#define ETH_DMAOMR_DGF ( ETH_DMAOMR_DGF_Msk ) + +#define ETH_DMAOMR_RTC_Pos ( 3U ) +#define ETH_DMAOMR_RTC_Msk ( 0x3UL << ETH_DMAOMR_RTC_Pos ) +#define ETH_DMAOMR_RTC ( ETH_DMAOMR_RTC_Msk ) +#define ETH_DMAOMR_RTC_0 ( 0x1UL << ETH_DMAOMR_RTC_Pos ) +#define ETH_DMAOMR_RTC_1 ( 0x2UL << ETH_DMAOMR_RTC_Pos ) + +#define ETH_DMAOMR_OSF_Pos ( 2U ) +#define ETH_DMAOMR_OSF_Msk ( 0x1UL << ETH_DMAOMR_OSF_Pos ) +#define ETH_DMAOMR_OSF ( ETH_DMAOMR_OSF_Msk ) + +#define ETH_DMAOMR_SR_Pos ( 1U ) +#define ETH_DMAOMR_SR_Msk ( 0x1UL << ETH_DMAOMR_SR_Pos ) +#define ETH_DMAOMR_SR ( ETH_DMAOMR_SR_Msk ) + + +/*************** Bits definition for ETH_DMAIER **********************/ + +#define ETH_DMAIER_NISE_Pos ( 16U ) +#define ETH_DMAIER_NISE_Msk ( 0x1UL << ETH_DMAIER_NISE_Pos ) +#define ETH_DMAIER_NISE ( ETH_DMAIER_NISE_Msk ) + +#define ETH_DMAIER_AISE_Pos ( 15U ) +#define ETH_DMAIER_AISE_Msk ( 0x1UL << ETH_DMAIER_AISE_Pos ) +#define ETH_DMAIER_AISE ( ETH_DMAIER_AISE_Msk ) + +#define ETH_DMAIER_ERIE_Pos ( 14U ) +#define ETH_DMAIER_ERIE_Msk ( 0x1UL << ETH_DMAIER_ERIE_Pos ) +#define ETH_DMAIER_ERIE ( ETH_DMAIER_ERIE_Msk ) + +#define ETH_DMAIER_FBEIE_Pos ( 13U ) +#define ETH_DMAIER_FBEIE_Msk ( 0x1UL << ETH_DMAIER_FBEIE_Pos ) +#define ETH_DMAIER_FBEIE ( ETH_DMAIER_FBEIE_Msk ) + +#define ETH_DMAIER_ETIE_Pos ( 10U ) +#define ETH_DMAIER_ETIE_Msk ( 0x1UL << ETH_DMAIER_ETIE_Pos ) +#define ETH_DMAIER_ETIE ( ETH_DMAIER_ETIE_Msk ) + +#define ETH_DMAIER_RWTIE_Pos ( 9U ) +#define ETH_DMAIER_RWTIE_Msk ( 0x1UL << ETH_DMAIER_RWTIE_Pos ) +#define ETH_DMAIER_RWTIE ( ETH_DMAIER_RWTIE_Msk ) + +#define ETH_DMAIER_RPSIE_Pos ( 8U ) +#define ETH_DMAIER_RPSIE_Msk ( 0x1UL << ETH_DMAIER_RPSIE_Pos ) +#define ETH_DMAIER_RPSIE ( ETH_DMAIER_RPSIE_Msk ) + +#define ETH_DMAIER_RBUIE_Pos ( 7U ) +#define ETH_DMAIER_RBUIE_Msk ( 0x1UL << ETH_DMAIER_RBUIE_Pos ) +#define ETH_DMAIER_RBUIE ( ETH_DMAIER_RBUIE_Msk ) + +#define ETH_DMAIER_RIE_Pos ( 6U ) +#define ETH_DMAIER_RIE_Msk ( 0x1UL << ETH_DMAIER_RIE_Pos ) +#define ETH_DMAIER_RIE ( ETH_DMAIER_RIE_Msk ) + +#define ETH_DMAIER_TUIE_Pos ( 5U ) +#define ETH_DMAIER_TUIE_Msk ( 0x1UL << ETH_DMAIER_TUIE_Pos ) +#define ETH_DMAIER_TUIE ( ETH_DMAIER_TUIE_Msk ) + +#define ETH_DMAIER_ROIE_Pos ( 4U ) +#define ETH_DMAIER_ROIE_Msk ( 0x1UL << ETH_DMAIER_ROIE_Pos ) +#define ETH_DMAIER_ROIE ( ETH_DMAIER_ROIE_Msk ) + +#define ETH_DMAIER_TJTIE_Pos ( 3U ) +#define ETH_DMAIER_TJTIE_Msk ( 0x1UL << ETH_DMAIER_TJTIE_Pos ) +#define ETH_DMAIER_TJTIE ( ETH_DMAIER_TJTIE_Msk ) + +#define ETH_DMAIER_TBUIE_Pos ( 2U ) +#define ETH_DMAIER_TBUIE_Msk ( 0x1UL << ETH_DMAIER_TBUIE_Pos ) +#define ETH_DMAIER_TBUIE ( ETH_DMAIER_TBUIE_Msk ) + +#define ETH_DMAIER_TPSIE_Pos ( 1U ) +#define ETH_DMAIER_TPSIE_Msk ( 0x1UL << ETH_DMAIER_TPSIE_Pos ) +#define ETH_DMAIER_TPSIE ( ETH_DMAIER_TPSIE_Msk ) + +#define ETH_DMAIER_TIE_Pos ( 0U ) +#define ETH_DMAIER_TIE_Msk ( 0x1UL << ETH_DMAIER_TIE_Pos ) +#define ETH_DMAIER_TIE ( ETH_DMAIER_TIE_Msk ) + + +/*************** Bits definition for ETH_DMAMFBOCR **********************/ + +#define ETH_DMAMFBOCR_OBFOC_Pos ( 28U ) +#define ETH_DMAMFBOCR_OBFOC_Msk ( 0x1UL << ETH_DMAMFBOCR_OBFOC_Pos ) +#define ETH_DMAMFBOCR_OBFOC ( ETH_DMAMFBOCR_OBFOC_Msk ) + +#define ETH_DMAMFBOCR_OFC_Pos ( 17U ) +#define ETH_DMAMFBOCR_OFC_Msk ( 0x7ffUL << ETH_DMAMFBOCR_OFC_Pos ) +#define ETH_DMAMFBOCR_OFC ( ETH_DMAMFBOCR_OFC_Msk ) + +#define ETH_DMAMFBOCR_OBMFC_Pos ( 16U ) +#define ETH_DMAMFBOCR_OBMFC_Msk ( 0x1UL << ETH_DMAMFBOCR_OBMFC_Pos ) +#define ETH_DMAMFBOCR_OBMFC ( ETH_DMAMFBOCR_OBMFC_Msk ) + +#define ETH_DMAMFBOCR_MFC_Pos ( 0U ) +#define ETH_DMAMFBOCR_MFC_Msk ( 0xffffUL << ETH_DMAMFBOCR_MFC_Pos ) +#define ETH_DMAMFBOCR_MFC ( ETH_DMAMFBOCR_MFC_Msk ) + + +/*************** Bits definition for ETH_DMARIWTR **********************/ + +#define ETH_DMARIWTR_RIWTC_Pos ( 0U ) +#define ETH_DMARIWTR_RIWTC_Msk ( 0xffUL << ETH_DMARIWTR_RIWTC_Pos ) +#define ETH_DMARIWTR_RIWTC ( ETH_DMARIWTR_RIWTC_Msk ) + + +/*************** Bits definition for ETH_DMACHTDR **********************/ + +#define ETH_DMACHTDR_HTDAP_Pos ( 0U ) +#define ETH_DMACHTDR_HTDAP_Msk ( 0xffffffffUL << ETH_DMACHTDR_HTDAP_Pos ) +#define ETH_DMACHTDR_HTDAP ( ETH_DMACHTDR_HTDAP_Msk ) + + +/*************** Bits definition for ETH_DMACHRDR **********************/ + +#define ETH_DMACHRDR_HRDAP_Pos ( 0U ) +#define ETH_DMACHRDR_HRDAP_Msk ( 0xffffffffUL << ETH_DMACHRDR_HRDAP_Pos ) +#define ETH_DMACHRDR_HRDAP ( ETH_DMACHRDR_HRDAP_Msk ) + + +/*************** Bits definition for ETH_DMACHTBAR **********************/ + +#define ETH_DMACHTBAR_HTBAP_Pos ( 0U ) +#define ETH_DMACHTBAR_HTBAP_Msk ( 0xffffffffUL << ETH_DMACHTBAR_HTBAP_Pos ) +#define ETH_DMACHTBAR_HTBAP ( ETH_DMACHTBAR_HTBAP_Msk ) + + +/*************** Bits definition for ETH_DMACHRBAR **********************/ + +#define ETH_DMACHRBAR_HRBAP_Pos ( 0U ) +#define ETH_DMACHRBAR_HRBAP_Msk ( 0xffffffffUL << ETH_DMACHRBAR_HRBAP_Pos ) +#define ETH_DMACHRBAR_HRBAP ( ETH_DMACHRBAR_HRBAP_Msk ) + + +/*************** Bits definition for PMU_CTRL0 **********************/ + +#define PMU_CTRL0_BKPRAMREN_Pos ( 31U ) +#define PMU_CTRL0_BKPRAMREN_Msk ( 0x1UL << PMU_CTRL0_BKPRAMREN_Pos ) +#define PMU_CTRL0_BKPRAMREN ( PMU_CTRL0_BKPRAMREN_Msk ) + +#define PMU_CTRL0_BKPRAMSEN_Pos ( 30U ) +#define PMU_CTRL0_BKPRAMSEN_Msk ( 0x1UL << PMU_CTRL0_BKPRAMSEN_Pos ) +#define PMU_CTRL0_BKPRAMSEN ( PMU_CTRL0_BKPRAMSEN_Msk ) + +#define PMU_CTRL0_STOPWPT_Pos ( 16U ) +#define PMU_CTRL0_STOPWPT_Msk ( 0xfffUL << PMU_CTRL0_STOPWPT_Pos ) +#define PMU_CTRL0_STOPWPT ( PMU_CTRL0_STOPWPT_Msk ) + +#define PMU_CTRL0_LPLDO12_Pos ( 12U ) +#define PMU_CTRL0_LPLDO12_Msk ( 0x7UL << PMU_CTRL0_LPLDO12_Pos ) +#define PMU_CTRL0_LPLDO12 ( PMU_CTRL0_LPLDO12_Msk ) +#define PMU_CTRL0_LPLDO12_0 ( 0x1UL << PMU_CTRL0_LPLDO12_Pos ) +#define PMU_CTRL0_LPLDO12_1 ( 0x2UL << PMU_CTRL0_LPLDO12_Pos ) +#define PMU_CTRL0_LPLDO12_2 ( 0x4UL << PMU_CTRL0_LPLDO12_Pos ) + +#define PMU_CTRL0_MLDO12_Pos ( 8U ) +#define PMU_CTRL0_MLDO12_Msk ( 0x3UL << PMU_CTRL0_MLDO12_Pos ) +#define PMU_CTRL0_MLDO12 ( PMU_CTRL0_MLDO12_Msk ) +#define PMU_CTRL0_MLDO12_0 ( 0x1UL << PMU_CTRL0_MLDO12_Pos ) +#define PMU_CTRL0_MLDO12_1 ( 0x2UL << PMU_CTRL0_MLDO12_Pos ) + +#define PMU_CTRL0_RTCWE_Pos ( 7U ) +#define PMU_CTRL0_RTCWE_Msk ( 0x1UL << PMU_CTRL0_RTCWE_Pos ) +#define PMU_CTRL0_RTCWE ( PMU_CTRL0_RTCWE_Msk ) + +#define PMU_CTRL0_RCHDIV_Pos ( 5U ) +#define PMU_CTRL0_RCHDIV_Msk ( 0x1UL << PMU_CTRL0_RCHDIV_Pos ) +#define PMU_CTRL0_RCHDIV ( PMU_CTRL0_RCHDIV_Msk ) + +#define PMU_CTRL0_RCHPDEN_Pos ( 4U ) +#define PMU_CTRL0_RCHPDEN_Msk ( 0x1UL << PMU_CTRL0_RCHPDEN_Pos ) +#define PMU_CTRL0_RCHPDEN ( PMU_CTRL0_RCHPDEN_Msk ) + +#define PMU_CTRL0_LPMS_Pos ( 0U ) +#define PMU_CTRL0_LPMS_Msk ( 0x1UL << PMU_CTRL0_LPMS_Pos ) +#define PMU_CTRL0_LPMS ( PMU_CTRL0_LPMS_Msk ) + + +/*************** Bits definition for PMU_CTRL1 **********************/ + +#define PMU_CTRL1_LVDVALUE_Pos ( 15U ) +#define PMU_CTRL1_LVDVALUE_Msk ( 0x1UL << PMU_CTRL1_LVDVALUE_Pos ) +#define PMU_CTRL1_LVDVALUE ( PMU_CTRL1_LVDVALUE_Msk ) + +#define PMU_CTRL1_LVDFILTER_Pos ( 14U ) +#define PMU_CTRL1_LVDFILTER_Msk ( 0x1UL << PMU_CTRL1_LVDFILTER_Pos ) +#define PMU_CTRL1_LVDFILTER ( PMU_CTRL1_LVDFILTER_Msk ) + +#define PMU_CTRL1_FLTTIME_Pos ( 9U ) +#define PMU_CTRL1_FLTTIME_Msk ( 0x7UL << PMU_CTRL1_FLTTIME_Pos ) +#define PMU_CTRL1_FLTTIME ( PMU_CTRL1_FLTTIME_Msk ) +#define PMU_CTRL1_FLTTIME_0 ( 0x1UL << PMU_CTRL1_FLTTIME_Pos ) +#define PMU_CTRL1_FLTTIME_1 ( 0x2UL << PMU_CTRL1_FLTTIME_Pos ) +#define PMU_CTRL1_FLTTIME_2 ( 0x4UL << PMU_CTRL1_FLTTIME_Pos ) + +#define PMU_CTRL1_LVDFLTEN_Pos ( 8U ) +#define PMU_CTRL1_LVDFLTEN_Msk ( 0x1UL << PMU_CTRL1_LVDFLTEN_Pos ) +#define PMU_CTRL1_LVDFLTEN ( PMU_CTRL1_LVDFLTEN_Msk ) + +#define PMU_CTRL1_LVDSEL_Pos ( 1U ) +#define PMU_CTRL1_LVDSEL_Msk ( 0x7UL << PMU_CTRL1_LVDSEL_Pos ) +#define PMU_CTRL1_LVDSEL ( PMU_CTRL1_LVDSEL_Msk ) +#define PMU_CTRL1_LVDSEL_0 ( 0x1UL << PMU_CTRL1_LVDSEL_Pos ) +#define PMU_CTRL1_LVDSEL_1 ( 0x2UL << PMU_CTRL1_LVDSEL_Pos ) +#define PMU_CTRL1_LVDSEL_2 ( 0x4UL << PMU_CTRL1_LVDSEL_Pos ) + +#define PMU_CTRL1_LVDEN_Pos ( 0U ) +#define PMU_CTRL1_LVDEN_Msk ( 0x1UL << PMU_CTRL1_LVDEN_Pos ) +#define PMU_CTRL1_LVDEN ( PMU_CTRL1_LVDEN_Msk ) + + +/*************** Bits definition for PMU_CTRL2 **********************/ + +#define PMU_CTRL2_BORCFG_Pos ( 26U ) +#define PMU_CTRL2_BORCFG_Msk ( 0x3UL << PMU_CTRL2_BORCFG_Pos ) +#define PMU_CTRL2_BORCFG ( PMU_CTRL2_BORCFG_Msk ) +#define PMU_CTRL2_BORCFG_0 ( 0x1UL << PMU_CTRL2_BORCFG_Pos ) +#define PMU_CTRL2_BORCFG_1 ( 0x2UL << PMU_CTRL2_BORCFG_Pos ) + +#define PMU_CTRL2_BOREN_Pos ( 24U ) +#define PMU_CTRL2_BOREN_Msk ( 0x1UL << PMU_CTRL2_BOREN_Pos ) +#define PMU_CTRL2_BOREN ( PMU_CTRL2_BOREN_Msk ) + +#define PMU_CTRL2_BORRSTEN_Pos ( 20U ) +#define PMU_CTRL2_BORRSTEN_Msk ( 0x1UL << PMU_CTRL2_BORRSTEN_Pos ) +#define PMU_CTRL2_BORRSTEN ( PMU_CTRL2_BORRSTEN_Msk ) + +#define PMU_CTRL2_STDBYWPT_Pos ( 16U ) +#define PMU_CTRL2_STDBYWPT_Msk ( 0xfUL << PMU_CTRL2_STDBYWPT_Pos ) +#define PMU_CTRL2_STDBYWPT ( PMU_CTRL2_STDBYWPT_Msk ) +#define PMU_CTRL2_STDBYWPT_0 ( 0x1UL << PMU_CTRL2_STDBYWPT_Pos ) +#define PMU_CTRL2_STDBYWPT_1 ( 0x2UL << PMU_CTRL2_STDBYWPT_Pos ) +#define PMU_CTRL2_STDBYWPT_2 ( 0x4UL << PMU_CTRL2_STDBYWPT_Pos ) + +#define PMU_CTRL2_WUXFILEN_Pos ( 8U ) +#define PMU_CTRL2_WUXFILEN_Msk ( 0x1fUL << PMU_CTRL2_WUXFILEN_Pos ) +#define PMU_CTRL2_WUXFILEN ( PMU_CTRL2_WUXFILEN_Msk ) +#define PMU_CTRL2_WUXFILEN_0 ( 0x1UL << PMU_CTRL2_WUXFILEN_Pos ) +#define PMU_CTRL2_WUXFILEN_1 ( 0x2UL << PMU_CTRL2_WUXFILEN_Pos ) +#define PMU_CTRL2_WUXFILEN_2 ( 0x4UL << PMU_CTRL2_WUXFILEN_Pos ) +#define PMU_CTRL2_WUXFILEN_3 ( 0x8UL << PMU_CTRL2_WUXFILEN_Pos ) +#define PMU_CTRL2_WUXFILEN_4 ( 0x10UL << PMU_CTRL2_WUXFILEN_Pos ) + +#define PMU_CTRL2_EWUPX_Pos ( 0U ) +#define PMU_CTRL2_EWUPX_Msk ( 0x1fUL << PMU_CTRL2_EWUPX_Pos ) +#define PMU_CTRL2_EWUPX ( PMU_CTRL2_EWUPX_Msk ) +#define PMU_CTRL2_EWUPX_0 ( 0x1UL << PMU_CTRL2_EWUPX_Pos ) +#define PMU_CTRL2_EWUPX_1 ( 0x2UL << PMU_CTRL2_EWUPX_Pos ) +#define PMU_CTRL2_EWUPX_2 ( 0x4UL << PMU_CTRL2_EWUPX_Pos ) +#define PMU_CTRL2_EWUPX_3 ( 0x8UL << PMU_CTRL2_EWUPX_Pos ) +#define PMU_CTRL2_EWUPX_4 ( 0x10UL << PMU_CTRL2_EWUPX_Pos ) + + +/*************** Bits definition for PMU_CTRL3 **********************/ + +#define PMU_CTRL3_WUPOLX_Pos ( 0U ) +#define PMU_CTRL3_WUPOLX_Msk ( 0x1fUL << PMU_CTRL3_WUPOLX_Pos ) +#define PMU_CTRL3_WUPOLX ( PMU_CTRL3_WUPOLX_Msk ) +#define PMU_CTRL3_WUPOLX_0 ( 0x1UL << PMU_CTRL3_WUPOLX_Pos ) +#define PMU_CTRL3_WUPOLX_1 ( 0x2UL << PMU_CTRL3_WUPOLX_Pos ) +#define PMU_CTRL3_WUPOLX_2 ( 0x4UL << PMU_CTRL3_WUPOLX_Pos ) +#define PMU_CTRL3_WUPOLX_3 ( 0x8UL << PMU_CTRL3_WUPOLX_Pos ) +#define PMU_CTRL3_WUPOLX_4 ( 0x10UL << PMU_CTRL3_WUPOLX_Pos ) + + +/*************** Bits definition for PMU_ST **********************/ + +#define PMU_SR_BORN_Pos ( 16U ) +#define PMU_SR_BORN_Msk ( 0x1UL << PMU_SR_BORN_Pos ) +#define PMU_SR_BORN ( PMU_SR_BORN_Msk ) + +#define PMU_SR_BORWUF_Pos ( 15U ) +#define PMU_SR_BORWUF_Msk ( 0x1UL << PMU_SR_BORWUF_Pos ) +#define PMU_SR_BORWUF ( PMU_SR_BORWUF_Msk ) + +#define PMU_SR_IWDTWUF_Pos ( 14U ) +#define PMU_SR_IWDTWUF_Msk ( 0x1UL << PMU_SR_IWDTWUF_Pos ) +#define PMU_SR_IWDTWUF ( PMU_SR_IWDTWUF_Msk ) + +#define PMU_SR_RSTWUF_Pos ( 13U ) +#define PMU_SR_RSTWUF_Msk ( 0x1UL << PMU_SR_RSTWUF_Pos ) +#define PMU_SR_RSTWUF ( PMU_SR_RSTWUF_Msk ) + +#define PMU_SR_RTCWUF_Pos ( 12U ) +#define PMU_SR_RTCWUF_Msk ( 0x1UL << PMU_SR_RTCWUF_Pos ) +#define PMU_SR_RTCWUF ( PMU_SR_RTCWUF_Msk ) + +#define PMU_SR_SBF_Pos ( 8U ) +#define PMU_SR_SBF_Msk ( 0x1UL << PMU_SR_SBF_Pos ) +#define PMU_SR_SBF ( PMU_SR_SBF_Msk ) + +#define PMU_SR_WUPFX_Pos ( 0U ) +#define PMU_SR_WUPFX_Msk ( 0x1fUL << PMU_SR_WUPFX_Pos ) +#define PMU_SR_WUPFX ( PMU_SR_WUPFX_Msk ) +#define PMU_SR_WUPFX_0 ( 0x1UL << PMU_SR_WUPFX_Pos ) +#define PMU_SR_WUPFX_1 ( 0x2UL << PMU_SR_WUPFX_Pos ) +#define PMU_SR_WUPFX_2 ( 0x4UL << PMU_SR_WUPFX_Pos ) +#define PMU_SR_WUPFX_3 ( 0x8UL << PMU_SR_WUPFX_Pos ) +#define PMU_SR_WUPFX_4 ( 0x10UL << PMU_SR_WUPFX_Pos ) + + +/*************** Bits definition for PMU_STCLR **********************/ + +#define PMU_STCLR_CBORWUF_Pos ( 15U ) +#define PMU_STCLR_CBORWUF_Msk ( 0x1UL << PMU_STCLR_CBORWUF_Pos ) +#define PMU_STCLR_CBORWUF ( PMU_STCLR_CBORWUF_Msk ) + +#define PMU_STCLR_CIWDTWUF_Pos ( 14U ) +#define PMU_STCLR_CIWDTWUF_Msk ( 0x1UL << PMU_STCLR_CIWDTWUF_Pos ) +#define PMU_STCLR_CIWDTWUF ( PMU_STCLR_CIWDTWUF_Msk ) + +#define PMU_STCLR_CRSTWUF_Pos ( 13U ) +#define PMU_STCLR_CRSTWUF_Msk ( 0x1UL << PMU_STCLR_CRSTWUF_Pos ) +#define PMU_STCLR_CRSTWUF ( PMU_STCLR_CRSTWUF_Msk ) + +#define PMU_STCLR_CRTCWUF_Pos ( 12U ) +#define PMU_STCLR_CRTCWUF_Msk ( 0x1UL << PMU_STCLR_CRTCWUF_Pos ) +#define PMU_STCLR_CRTCWUF ( PMU_STCLR_CRTCWUF_Msk ) + +#define PMU_STCLR_CSBF_Pos ( 8U ) +#define PMU_STCLR_CSBF_Msk ( 0x1UL << PMU_STCLR_CSBF_Pos ) +#define PMU_STCLR_CSBF ( PMU_STCLR_CSBF_Msk ) + +#define PMU_STCLR_CWUFX_Pos ( 0U ) +#define PMU_STCLR_CWUFX_Msk ( 0x1fUL << PMU_STCLR_CWUFX_Pos ) +#define PMU_STCLR_CWUFX ( PMU_STCLR_CWUFX_Msk ) +#define PMU_STCLR_CWUFX_0 ( 0x1UL << PMU_STCLR_CWUFX_Pos ) +#define PMU_STCLR_CWUFX_1 ( 0x2UL << PMU_STCLR_CWUFX_Pos ) +#define PMU_STCLR_CWUFX_2 ( 0x4UL << PMU_STCLR_CWUFX_Pos ) +#define PMU_STCLR_CWUFX_3 ( 0x8UL << PMU_STCLR_CWUFX_Pos ) +#define PMU_STCLR_CWUFX_4 ( 0x10UL << PMU_STCLR_CWUFX_Pos ) + + +/*************** Bits definition for PMU_IOSEL **********************/ + +#define PMU_IOSEL_PI8VALUE_Pos ( 11U ) +#define PMU_IOSEL_PI8VALUE_Msk ( 0x1UL << PMU_IOSEL_PI8VALUE_Pos ) +#define PMU_IOSEL_PI8VALUE ( PMU_IOSEL_PI8VALUE_Msk ) + +#define PMU_IOSEL_PC15VALUE_Pos ( 10U ) +#define PMU_IOSEL_PC15VALUE_Msk ( 0x1UL << PMU_IOSEL_PC15VALUE_Pos ) +#define PMU_IOSEL_PC15VALUE ( PMU_IOSEL_PC15VALUE_Msk ) + +#define PMU_IOSEL_PC14VALUE_Pos ( 9U ) +#define PMU_IOSEL_PC14VALUE_Msk ( 0x1UL << PMU_IOSEL_PC14VALUE_Pos ) +#define PMU_IOSEL_PC14VALUE ( PMU_IOSEL_PC14VALUE_Msk ) + +#define PMU_IOSEL_PC13VALUE_Pos ( 8U ) +#define PMU_IOSEL_PC13VALUE_Msk ( 0x1UL << PMU_IOSEL_PC13VALUE_Pos ) +#define PMU_IOSEL_PC13VALUE ( PMU_IOSEL_PC13VALUE_Msk ) + +#define PMU_IOSEL_PI8SEL_Pos ( 6U ) +#define PMU_IOSEL_PI8SEL_Msk ( 0x3UL << PMU_IOSEL_PI8SEL_Pos ) +#define PMU_IOSEL_PI8SEL ( PMU_IOSEL_PI8SEL_Msk ) +#define PMU_IOSEL_PI8SEL_0 ( 0x1UL << PMU_IOSEL_PI8SEL_Pos ) +#define PMU_IOSEL_PI8SEL_1 ( 0x2UL << PMU_IOSEL_PI8SEL_Pos ) + +#define PMU_IOSEL_PC15SEL_Pos ( 4U ) +#define PMU_IOSEL_PC15SEL_Msk ( 0x3UL << PMU_IOSEL_PC15SEL_Pos ) +#define PMU_IOSEL_PC15SEL ( PMU_IOSEL_PC15SEL_Msk ) +#define PMU_IOSEL_PC15SEL_0 ( 0x1UL << PMU_IOSEL_PC15SEL_Pos ) +#define PMU_IOSEL_PC15SEL_1 ( 0x2UL << PMU_IOSEL_PC15SEL_Pos ) + +#define PMU_IOSEL_PC14SEL_Pos ( 2U ) +#define PMU_IOSEL_PC14SEL_Msk ( 0x3UL << PMU_IOSEL_PC14SEL_Pos ) +#define PMU_IOSEL_PC14SEL ( PMU_IOSEL_PC14SEL_Msk ) +#define PMU_IOSEL_PC14SEL_0 ( 0x1UL << PMU_IOSEL_PC14SEL_Pos ) +#define PMU_IOSEL_PC14SEL_1 ( 0x2UL << PMU_IOSEL_PC14SEL_Pos ) + +#define PMU_IOSEL_PC13SEL_Pos ( 0U ) +#define PMU_IOSEL_PC13SEL_Msk ( 0x3UL << PMU_IOSEL_PC13SEL_Pos ) +#define PMU_IOSEL_PC13SEL ( PMU_IOSEL_PC13SEL_Msk ) +#define PMU_IOSEL_PC13SEL_0 ( 0x1UL << PMU_IOSEL_PC13SEL_Pos ) +#define PMU_IOSEL_PC13SEL_1 ( 0x2UL << PMU_IOSEL_PC13SEL_Pos ) + + +/*************** Bits definition for PMU_TEST_ANATEST_SR **********************/ + +#define PMU_TEST_ANATEST_SR_ANATESTSEL_Pos ( 0U ) +#define PMU_TEST_ANATEST_SR_ANATESTSEL_Msk ( 0x7UL << PMU_TEST_ANATEST_SR_ANATESTSEL_Pos ) +#define PMU_TEST_ANATEST_SR_ANATESTSEL ( PMU_TEST_ANATEST_SR_ANATESTSEL_Msk ) +#define PMU_TEST_ANATEST_SR_ANATESTSEL_0 ( 0x1UL << PMU_TEST_ANATEST_SR_ANATESTSEL_Pos ) +#define PMU_TEST_ANATEST_SR_ANATESTSEL_1 ( 0x2UL << PMU_TEST_ANATEST_SR_ANATESTSEL_Pos ) +#define PMU_TEST_ANATEST_SR_ANATESTSEL_2 ( 0x4UL << PMU_TEST_ANATEST_SR_ANATESTSEL_Pos ) + + +/*************** Bits definition for PMU_TEST_LDOCAL **********************/ + +#define PMU_TEST_LDOCAL_LPLDO12TRIM_Pos ( 12U ) +#define PMU_TEST_LDOCAL_LPLDO12TRIM_Msk ( 0x7UL << PMU_TEST_LDOCAL_LPLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_LPLDO12TRIM ( PMU_TEST_LDOCAL_LPLDO12TRIM_Msk ) +#define PMU_TEST_LDOCAL_LPLDO12TRIM_0 ( 0x1UL << PMU_TEST_LDOCAL_LPLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_LPLDO12TRIM_1 ( 0x2UL << PMU_TEST_LDOCAL_LPLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_LPLDO12TRIM_2 ( 0x4UL << PMU_TEST_LDOCAL_LPLDO12TRIM_Pos ) + +#define PMU_TEST_LDOCAL_MLDO12TRIM_Pos ( 8U ) +#define PMU_TEST_LDOCAL_MLDO12TRIM_Msk ( 0xfUL << PMU_TEST_LDOCAL_MLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_MLDO12TRIM ( PMU_TEST_LDOCAL_MLDO12TRIM_Msk ) +#define PMU_TEST_LDOCAL_MLDO12TRIM_0 ( 0x1UL << PMU_TEST_LDOCAL_MLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_MLDO12TRIM_1 ( 0x2UL << PMU_TEST_LDOCAL_MLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_MLDO12TRIM_2 ( 0x4UL << PMU_TEST_LDOCAL_MLDO12TRIM_Pos ) +#define PMU_TEST_LDOCAL_MLDO12TRIM_3 ( 0x8UL << PMU_TEST_LDOCAL_MLDO12TRIM_Pos ) + +#define PMU_TEST_LDOCAL_LPBGRTRIM_Pos ( 4U ) +#define PMU_TEST_LDOCAL_LPBGRTRIM_Msk ( 0x7UL << PMU_TEST_LDOCAL_LPBGRTRIM_Pos ) +#define PMU_TEST_LDOCAL_LPBGRTRIM ( PMU_TEST_LDOCAL_LPBGRTRIM_Msk ) +#define PMU_TEST_LDOCAL_LPBGRTRIM_0 ( 0x1UL << PMU_TEST_LDOCAL_LPBGRTRIM_Pos ) +#define PMU_TEST_LDOCAL_LPBGRTRIM_1 ( 0x2UL << PMU_TEST_LDOCAL_LPBGRTRIM_Pos ) +#define PMU_TEST_LDOCAL_LPBGRTRIM_2 ( 0x4UL << PMU_TEST_LDOCAL_LPBGRTRIM_Pos ) + +#define PMU_TEST_LDOCAL_VREFTRIM_Pos ( 0U ) +#define PMU_TEST_LDOCAL_VREFTRIM_Msk ( 0x7UL << PMU_TEST_LDOCAL_VREFTRIM_Pos ) +#define PMU_TEST_LDOCAL_VREFTRIM ( PMU_TEST_LDOCAL_VREFTRIM_Msk ) +#define PMU_TEST_LDOCAL_VREFTRIM_0 ( 0x1UL << PMU_TEST_LDOCAL_VREFTRIM_Pos ) +#define PMU_TEST_LDOCAL_VREFTRIM_1 ( 0x2UL << PMU_TEST_LDOCAL_VREFTRIM_Pos ) +#define PMU_TEST_LDOCAL_VREFTRIM_2 ( 0x4UL << PMU_TEST_LDOCAL_VREFTRIM_Pos ) + + +/*************** Bits definition for PMU_TEST_LDOCR **********************/ + +#define PMU_TEST_LDOCR_TEST_LPLDO12EN_Pos ( 9U ) +#define PMU_TEST_LDOCR_TEST_LPLDO12EN_Msk ( 0x1UL << PMU_TEST_LDOCR_TEST_LPLDO12EN_Pos ) +#define PMU_TEST_LDOCR_TEST_LPLDO12EN ( PMU_TEST_LDOCR_TEST_LPLDO12EN_Msk ) + +#define PMU_TEST_LDOCR_TEST_MLDO12LV_Pos ( 4U ) +#define PMU_TEST_LDOCR_TEST_MLDO12LV_Msk ( 0x3UL << PMU_TEST_LDOCR_TEST_MLDO12LV_Pos ) +#define PMU_TEST_LDOCR_TEST_MLDO12LV ( PMU_TEST_LDOCR_TEST_MLDO12LV_Msk ) +#define PMU_TEST_LDOCR_TEST_MLDO12LV_0 ( 0x1UL << PMU_TEST_LDOCR_TEST_MLDO12LV_Pos ) +#define PMU_TEST_LDOCR_TEST_MLDO12LV_1 ( 0x2UL << PMU_TEST_LDOCR_TEST_MLDO12LV_Pos ) + +#define PMU_TEST_LDOCR_LDO_TESTEN_Pos ( 0U ) +#define PMU_TEST_LDOCR_LDO_TESTEN_Msk ( 0x1UL << PMU_TEST_LDOCR_LDO_TESTEN_Pos ) +#define PMU_TEST_LDOCR_LDO_TESTEN ( PMU_TEST_LDOCR_LDO_TESTEN_Msk ) + + +/*************** Bits definition for RTC_WP **********************/ + +#define RTC_WP_WE_Pos ( 0U ) +#define RTC_WP_WE_Msk ( 0x1UL << RTC_WP_WE_Pos ) +#define RTC_WP_WE ( RTC_WP_WE_Msk ) + + +/*************** Bits definition for RTC_IE **********************/ + +#define RTC_IE_WUTIE_Pos ( 17U ) +#define RTC_IE_WUTIE_Msk ( 0x1UL << RTC_IE_WUTIE_Pos ) +#define RTC_IE_WUTIE ( RTC_IE_WUTIE_Msk ) + +#define RTC_IE_STP2RIE_Pos ( 16U ) +#define RTC_IE_STP2RIE_Msk ( 0x1UL << RTC_IE_STP2RIE_Pos ) +#define RTC_IE_STP2RIE ( RTC_IE_STP2RIE_Msk ) + +#define RTC_IE_STP2FIE_Pos ( 15U ) +#define RTC_IE_STP2FIE_Msk ( 0x1UL << RTC_IE_STP2FIE_Pos ) +#define RTC_IE_STP2FIE ( RTC_IE_STP2FIE_Msk ) + +#define RTC_IE_STP1RIE_Pos ( 14U ) +#define RTC_IE_STP1RIE_Msk ( 0x1UL << RTC_IE_STP1RIE_Pos ) +#define RTC_IE_STP1RIE ( RTC_IE_STP1RIE_Msk ) + +#define RTC_IE_STP1FIE_Pos ( 13U ) +#define RTC_IE_STP1FIE_Msk ( 0x1UL << RTC_IE_STP1FIE_Pos ) +#define RTC_IE_STP1FIE ( RTC_IE_STP1FIE_Msk ) + +#define RTC_IE_ADJ32_IE_Pos ( 12U ) +#define RTC_IE_ADJ32_IE_Msk ( 0x1UL << RTC_IE_ADJ32_IE_Pos ) +#define RTC_IE_ADJ32_IE ( RTC_IE_ADJ32_IE_Msk ) + +#define RTC_IE_ALM_IE_Pos ( 11U ) +#define RTC_IE_ALM_IE_Msk ( 0x1UL << RTC_IE_ALM_IE_Pos ) +#define RTC_IE_ALM_IE ( RTC_IE_ALM_IE_Msk ) + +#define RTC_IE_1KHZ_IE_Pos ( 10U ) +#define RTC_IE_1KHZ_IE_Msk ( 0x1UL << RTC_IE_1KHZ_IE_Pos ) +#define RTC_IE_1KHZ_IE ( RTC_IE_1KHZ_IE_Msk ) + +#define RTC_IE_256HZ_IE_Pos ( 9U ) +#define RTC_IE_256HZ_IE_Msk ( 0x1UL << RTC_IE_256HZ_IE_Pos ) +#define RTC_IE_256HZ_IE ( RTC_IE_256HZ_IE_Msk ) + +#define RTC_IE_64HZ_IE_Pos ( 8U ) +#define RTC_IE_64HZ_IE_Msk ( 0x1UL << RTC_IE_64HZ_IE_Pos ) +#define RTC_IE_64HZ_IE ( RTC_IE_64HZ_IE_Msk ) + +#define RTC_IE_16HZ_IE_Pos ( 7U ) +#define RTC_IE_16HZ_IE_Msk ( 0x1UL << RTC_IE_16HZ_IE_Pos ) +#define RTC_IE_16HZ_IE ( RTC_IE_16HZ_IE_Msk ) + +#define RTC_IE_8HZ_IE_Pos ( 6U ) +#define RTC_IE_8HZ_IE_Msk ( 0x1UL << RTC_IE_8HZ_IE_Pos ) +#define RTC_IE_8HZ_IE ( RTC_IE_8HZ_IE_Msk ) + +#define RTC_IE_4HZ_IE_Pos ( 5U ) +#define RTC_IE_4HZ_IE_Msk ( 0x1UL << RTC_IE_4HZ_IE_Pos ) +#define RTC_IE_4HZ_IE ( RTC_IE_4HZ_IE_Msk ) + +#define RTC_IE_2HZ_IE_Pos ( 4U ) +#define RTC_IE_2HZ_IE_Msk ( 0x1UL << RTC_IE_2HZ_IE_Pos ) +#define RTC_IE_2HZ_IE ( RTC_IE_2HZ_IE_Msk ) + +#define RTC_IE_SEC_IE_Pos ( 3U ) +#define RTC_IE_SEC_IE_Msk ( 0x1UL << RTC_IE_SEC_IE_Pos ) +#define RTC_IE_SEC_IE ( RTC_IE_SEC_IE_Msk ) + +#define RTC_IE_MIN_IE_Pos ( 2U ) +#define RTC_IE_MIN_IE_Msk ( 0x1UL << RTC_IE_MIN_IE_Pos ) +#define RTC_IE_MIN_IE ( RTC_IE_MIN_IE_Msk ) + +#define RTC_IE_HOUR_IE_Pos ( 1U ) +#define RTC_IE_HOUR_IE_Msk ( 0x1UL << RTC_IE_HOUR_IE_Pos ) +#define RTC_IE_HOUR_IE ( RTC_IE_HOUR_IE_Msk ) + +#define RTC_IE_DATE_IE_Pos ( 0U ) +#define RTC_IE_DATE_IE_Msk ( 0x1UL << RTC_IE_DATE_IE_Pos ) +#define RTC_IE_DATE_IE ( RTC_IE_DATE_IE_Msk ) + + +/*************** Bits definition for RTC_SR **********************/ + +#define RTC_SR_WUTWF_Pos ( 24U ) +#define RTC_SR_WUTWF_Msk ( 0x1UL << RTC_SR_WUTWF_Pos ) +#define RTC_SR_WUTWF ( RTC_SR_WUTWF_Msk ) + +#define RTC_SR_WUTF_Pos ( 17U ) +#define RTC_SR_WUTF_Msk ( 0x1UL << RTC_SR_WUTF_Pos ) +#define RTC_SR_WUTF ( RTC_SR_WUTF_Msk ) + +#define RTC_SR_STP2RIF_Pos ( 16U ) +#define RTC_SR_STP2RIF_Msk ( 0x1UL << RTC_SR_STP2RIF_Pos ) +#define RTC_SR_STP2RIF ( RTC_SR_STP2RIF_Msk ) + +#define RTC_SR_STP2FIF_Pos ( 15U ) +#define RTC_SR_STP2FIF_Msk ( 0x1UL << RTC_SR_STP2FIF_Pos ) +#define RTC_SR_STP2FIF ( RTC_SR_STP2FIF_Msk ) + +#define RTC_SR_STP1RIF_Pos ( 14U ) +#define RTC_SR_STP1RIF_Msk ( 0x1UL << RTC_SR_STP1RIF_Pos ) +#define RTC_SR_STP1RIF ( RTC_SR_STP1RIF_Msk ) + +#define RTC_SR_STP1FIF_Pos ( 13U ) +#define RTC_SR_STP1FIF_Msk ( 0x1UL << RTC_SR_STP1FIF_Pos ) +#define RTC_SR_STP1FIF ( RTC_SR_STP1FIF_Msk ) + +#define RTC_SR_ADJ32_IF_Pos ( 12U ) +#define RTC_SR_ADJ32_IF_Msk ( 0x1UL << RTC_SR_ADJ32_IF_Pos ) +#define RTC_SR_ADJ32_IF ( RTC_SR_ADJ32_IF_Msk ) + +#define RTC_SR_ALM_IF_Pos ( 11U ) +#define RTC_SR_ALM_IF_Msk ( 0x1UL << RTC_SR_ALM_IF_Pos ) +#define RTC_SR_ALM_IF ( RTC_SR_ALM_IF_Msk ) + +#define RTC_SR_1KHZ_IF_Pos ( 10U ) +#define RTC_SR_1KHZ_IF_Msk ( 0x1UL << RTC_SR_1KHZ_IF_Pos ) +#define RTC_SR_1KHZ_IF ( RTC_SR_1KHZ_IF_Msk ) + +#define RTC_SR_256HZ_IF_Pos ( 9U ) +#define RTC_SR_256HZ_IF_Msk ( 0x1UL << RTC_SR_256HZ_IF_Pos ) +#define RTC_SR_256HZ_IF ( RTC_SR_256HZ_IF_Msk ) + +#define RTC_SR_64HZ_IF_Pos ( 8U ) +#define RTC_SR_64HZ_IF_Msk ( 0x1UL << RTC_SR_64HZ_IF_Pos ) +#define RTC_SR_64HZ_IF ( RTC_SR_64HZ_IF_Msk ) + +#define RTC_SR_16HZ_IF_Pos ( 7U ) +#define RTC_SR_16HZ_IF_Msk ( 0x1UL << RTC_SR_16HZ_IF_Pos ) +#define RTC_SR_16HZ_IF ( RTC_SR_16HZ_IF_Msk ) + +#define RTC_SR_8HZ_IF_Pos ( 6U ) +#define RTC_SR_8HZ_IF_Msk ( 0x1UL << RTC_SR_8HZ_IF_Pos ) +#define RTC_SR_8HZ_IF ( RTC_SR_8HZ_IF_Msk ) + +#define RTC_SR_4HZ_IF_Pos ( 5U ) +#define RTC_SR_4HZ_IF_Msk ( 0x1UL << RTC_SR_4HZ_IF_Pos ) +#define RTC_SR_4HZ_IF ( RTC_SR_4HZ_IF_Msk ) + +#define RTC_SR_2HZ_IF_Pos ( 4U ) +#define RTC_SR_2HZ_IF_Msk ( 0x1UL << RTC_SR_2HZ_IF_Pos ) +#define RTC_SR_2HZ_IF ( RTC_SR_2HZ_IF_Msk ) + +#define RTC_SR_SEC_IF_Pos ( 3U ) +#define RTC_SR_SEC_IF_Msk ( 0x1UL << RTC_SR_SEC_IF_Pos ) +#define RTC_SR_SEC_IF ( RTC_SR_SEC_IF_Msk ) + +#define RTC_SR_MIN_IF_Pos ( 2U ) +#define RTC_SR_MIN_IF_Msk ( 0x1UL << RTC_SR_MIN_IF_Pos ) +#define RTC_SR_MIN_IF ( RTC_SR_MIN_IF_Msk ) + +#define RTC_SR_HOUR_IF_Pos ( 1U ) +#define RTC_SR_HOUR_IF_Msk ( 0x1UL << RTC_SR_HOUR_IF_Pos ) +#define RTC_SR_HOUR_IF ( RTC_SR_HOUR_IF_Msk ) + +#define RTC_SR_DATE_IF_Pos ( 0U ) +#define RTC_SR_DATE_IF_Msk ( 0x1UL << RTC_SR_DATE_IF_Pos ) +#define RTC_SR_DATE_IF ( RTC_SR_DATE_IF_Msk ) + + +/*************** Bits definition for RTC_SEC **********************/ + +#define RTC_SEC_BCDSEC_Pos ( 0U ) +#define RTC_SEC_BCDSEC_Msk ( 0x7fUL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC ( RTC_SEC_BCDSEC_Msk ) +#define RTC_SEC_BCDSEC_0 ( 0x1UL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC_1 ( 0x2UL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC_2 ( 0x4UL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC_3 ( 0x8UL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC_4 ( 0x10UL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC_5 ( 0x20UL << RTC_SEC_BCDSEC_Pos ) +#define RTC_SEC_BCDSEC_6 ( 0x40UL << RTC_SEC_BCDSEC_Pos ) + + +/*************** Bits definition for RTC_MIN **********************/ + +#define RTC_MIN_BCDMIN_Pos ( 0U ) +#define RTC_MIN_BCDMIN_Msk ( 0x7fUL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN ( RTC_MIN_BCDMIN_Msk ) +#define RTC_MIN_BCDMIN_0 ( 0x1UL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN_1 ( 0x2UL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN_2 ( 0x4UL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN_3 ( 0x8UL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN_4 ( 0x10UL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN_5 ( 0x20UL << RTC_MIN_BCDMIN_Pos ) +#define RTC_MIN_BCDMIN_6 ( 0x40UL << RTC_MIN_BCDMIN_Pos ) + + +/*************** Bits definition for RTC_HOUR **********************/ + +#define RTC_HOUR_BCDHOUR_Pos ( 0U ) +#define RTC_HOUR_BCDHOUR_Msk ( 0x3fUL << RTC_HOUR_BCDHOUR_Pos ) +#define RTC_HOUR_BCDHOUR ( RTC_HOUR_BCDHOUR_Msk ) +#define RTC_HOUR_BCDHOUR_0 ( 0x1UL << RTC_HOUR_BCDHOUR_Pos ) +#define RTC_HOUR_BCDHOUR_1 ( 0x2UL << RTC_HOUR_BCDHOUR_Pos ) +#define RTC_HOUR_BCDHOUR_2 ( 0x4UL << RTC_HOUR_BCDHOUR_Pos ) +#define RTC_HOUR_BCDHOUR_3 ( 0x8UL << RTC_HOUR_BCDHOUR_Pos ) +#define RTC_HOUR_BCDHOUR_4 ( 0x10UL << RTC_HOUR_BCDHOUR_Pos ) +#define RTC_HOUR_BCDHOUR_5 ( 0x20UL << RTC_HOUR_BCDHOUR_Pos ) + + +/*************** Bits definition for RTC_DAY **********************/ + +#define RTC_DAY_BCDDATE_Pos ( 0U ) +#define RTC_DAY_BCDDATE_Msk ( 0x3fUL << RTC_DAY_BCDDATE_Pos ) +#define RTC_DAY_BCDDATE ( RTC_DAY_BCDDATE_Msk ) +#define RTC_DAY_BCDDATE_0 ( 0x1UL << RTC_DAY_BCDDATE_Pos ) +#define RTC_DAY_BCDDATE_1 ( 0x2UL << RTC_DAY_BCDDATE_Pos ) +#define RTC_DAY_BCDDATE_2 ( 0x4UL << RTC_DAY_BCDDATE_Pos ) +#define RTC_DAY_BCDDATE_3 ( 0x8UL << RTC_DAY_BCDDATE_Pos ) +#define RTC_DAY_BCDDATE_4 ( 0x10UL << RTC_DAY_BCDDATE_Pos ) +#define RTC_DAY_BCDDATE_5 ( 0x20UL << RTC_DAY_BCDDATE_Pos ) + + +/*************** Bits definition for RTC_WEEK **********************/ + +#define RTC_WEEK_BCDWEEK_Pos ( 0U ) +#define RTC_WEEK_BCDWEEK_Msk ( 0x7UL << RTC_WEEK_BCDWEEK_Pos ) +#define RTC_WEEK_BCDWEEK ( RTC_WEEK_BCDWEEK_Msk ) +#define RTC_WEEK_BCDWEEK_0 ( 0x1UL << RTC_WEEK_BCDWEEK_Pos ) +#define RTC_WEEK_BCDWEEK_1 ( 0x2UL << RTC_WEEK_BCDWEEK_Pos ) +#define RTC_WEEK_BCDWEEK_2 ( 0x4UL << RTC_WEEK_BCDWEEK_Pos ) + + +/*************** Bits definition for RTC_MONTH **********************/ + +#define RTC_MONTH_BCDMONTH_Pos ( 0U ) +#define RTC_MONTH_BCDMONTH_Msk ( 0x1fUL << RTC_MONTH_BCDMONTH_Pos ) +#define RTC_MONTH_BCDMONTH ( RTC_MONTH_BCDMONTH_Msk ) +#define RTC_MONTH_BCDMONTH_0 ( 0x1UL << RTC_MONTH_BCDMONTH_Pos ) +#define RTC_MONTH_BCDMONTH_1 ( 0x2UL << RTC_MONTH_BCDMONTH_Pos ) +#define RTC_MONTH_BCDMONTH_2 ( 0x4UL << RTC_MONTH_BCDMONTH_Pos ) +#define RTC_MONTH_BCDMONTH_3 ( 0x8UL << RTC_MONTH_BCDMONTH_Pos ) +#define RTC_MONTH_BCDMONTH_4 ( 0x10UL << RTC_MONTH_BCDMONTH_Pos ) + + +/*************** Bits definition for RTC_YEAR **********************/ + +#define RTC_YEAR_BCDYEAR_Pos ( 0U ) +#define RTC_YEAR_BCDYEAR_Msk ( 0xffUL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR ( RTC_YEAR_BCDYEAR_Msk ) +#define RTC_YEAR_BCDYEAR_0 ( 0x1UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_1 ( 0x2UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_2 ( 0x4UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_3 ( 0x8UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_4 ( 0x10UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_5 ( 0x20UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_6 ( 0x40UL << RTC_YEAR_BCDYEAR_Pos ) +#define RTC_YEAR_BCDYEAR_7 ( 0x80UL << RTC_YEAR_BCDYEAR_Pos ) + + +/*************** Bits definition for RTC_ALM **********************/ + +#define RTC_ALM_ALM_WDS_Pos ( 31U ) +#define RTC_ALM_ALM_WDS_Msk ( 0x1UL << RTC_ALM_ALM_WDS_Pos ) +#define RTC_ALM_ALM_WDS ( RTC_ALM_ALM_WDS_Msk ) + +#define RTC_ALM_ALMWEEK_ALMDAY_Pos ( 24U ) +#define RTC_ALM_ALMWEEK_ALMDAY_Msk ( 0x7fUL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY ( RTC_ALM_ALMWEEK_ALMDAY_Msk ) +#define RTC_ALM_ALMWEEK_ALMDAY_0 ( 0x1UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY_1 ( 0x2UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY_2 ( 0x4UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY_3 ( 0x8UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY_4 ( 0x10UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY_5 ( 0x20UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) +#define RTC_ALM_ALMWEEK_ALMDAY_6 ( 0x40UL << RTC_ALM_ALMWEEK_ALMDAY_Pos ) + +#define RTC_ALM_ALMHOUR_Pos ( 16U ) +#define RTC_ALM_ALMHOUR_Msk ( 0x3fUL << RTC_ALM_ALMHOUR_Pos ) +#define RTC_ALM_ALMHOUR ( RTC_ALM_ALMHOUR_Msk ) +#define RTC_ALM_ALMHOUR_0 ( 0x1UL << RTC_ALM_ALMHOUR_Pos ) +#define RTC_ALM_ALMHOUR_1 ( 0x2UL << RTC_ALM_ALMHOUR_Pos ) +#define RTC_ALM_ALMHOUR_2 ( 0x4UL << RTC_ALM_ALMHOUR_Pos ) +#define RTC_ALM_ALMHOUR_3 ( 0x8UL << RTC_ALM_ALMHOUR_Pos ) +#define RTC_ALM_ALMHOUR_4 ( 0x10UL << RTC_ALM_ALMHOUR_Pos ) +#define RTC_ALM_ALMHOUR_5 ( 0x20UL << RTC_ALM_ALMHOUR_Pos ) + +#define RTC_ALM_ALMMIN_Pos ( 8U ) +#define RTC_ALM_ALMMIN_Msk ( 0x7fUL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN ( RTC_ALM_ALMMIN_Msk ) +#define RTC_ALM_ALMMIN_0 ( 0x1UL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN_1 ( 0x2UL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN_2 ( 0x4UL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN_3 ( 0x8UL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN_4 ( 0x10UL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN_5 ( 0x20UL << RTC_ALM_ALMMIN_Pos ) +#define RTC_ALM_ALMMIN_6 ( 0x40UL << RTC_ALM_ALMMIN_Pos ) + +#define RTC_ALM_ALMSEC_Pos ( 0U ) +#define RTC_ALM_ALMSEC_Msk ( 0x7fUL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC ( RTC_ALM_ALMSEC_Msk ) +#define RTC_ALM_ALMSEC_0 ( 0x1UL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC_1 ( 0x2UL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC_2 ( 0x4UL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC_3 ( 0x8UL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC_4 ( 0x10UL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC_5 ( 0x20UL << RTC_ALM_ALMSEC_Pos ) +#define RTC_ALM_ALMSEC_6 ( 0x40UL << RTC_ALM_ALMSEC_Pos ) + + +/*************** Bits definition for RTC_CR **********************/ + +#define RTC_CR_WUCKSEL_Pos ( 24U ) +#define RTC_CR_WUCKSEL_Msk ( 0x7UL << RTC_CR_WUCKSEL_Pos ) +#define RTC_CR_WUCKSEL ( RTC_CR_WUCKSEL_Msk ) +#define RTC_CR_WUCKSEL_0 ( 0x1UL << RTC_CR_WUCKSEL_Pos ) +#define RTC_CR_WUCKSEL_1 ( 0x2UL << RTC_CR_WUCKSEL_Pos ) +#define RTC_CR_WUCKSEL_2 ( 0x4UL << RTC_CR_WUCKSEL_Pos ) + +#define RTC_CR_WUTE_Pos ( 23U ) +#define RTC_CR_WUTE_Msk ( 0x1UL << RTC_CR_WUTE_Pos ) +#define RTC_CR_WUTE ( RTC_CR_WUTE_Msk ) + +#define RTC_CR_TAMPFLTCLK_Pos ( 22U ) +#define RTC_CR_TAMPFLTCLK_Msk ( 0x1UL << RTC_CR_TAMPFLTCLK_Pos ) +#define RTC_CR_TAMPFLTCLK ( RTC_CR_TAMPFLTCLK_Msk ) + +#define RTC_CR_TS2EDGE_Pos ( 21U ) +#define RTC_CR_TS2EDGE_Msk ( 0x1UL << RTC_CR_TS2EDGE_Pos ) +#define RTC_CR_TS2EDGE ( RTC_CR_TS2EDGE_Msk ) + +#define RTC_CR_TAMP2FLT_Pos ( 19U ) +#define RTC_CR_TAMP2FLT_Msk ( 0x3UL << RTC_CR_TAMP2FLT_Pos ) +#define RTC_CR_TAMP2FLT ( RTC_CR_TAMP2FLT_Msk ) +#define RTC_CR_TAMP2FLT_0 ( 0x1UL << RTC_CR_TAMP2FLT_Pos ) +#define RTC_CR_TAMP2FLT_1 ( 0x2UL << RTC_CR_TAMP2FLT_Pos ) + +#define RTC_CR_TAMP2FLTEN_Pos ( 18U ) +#define RTC_CR_TAMP2FLTEN_Msk ( 0x1UL << RTC_CR_TAMP2FLTEN_Pos ) +#define RTC_CR_TAMP2FLTEN ( RTC_CR_TAMP2FLTEN_Msk ) + +#define RTC_CR_TAMP2FCLR_Pos ( 17U ) +#define RTC_CR_TAMP2FCLR_Msk ( 0x1UL << RTC_CR_TAMP2FCLR_Pos ) +#define RTC_CR_TAMP2FCLR ( RTC_CR_TAMP2FCLR_Msk ) + +#define RTC_CR_TAMP2RCLR_Pos ( 16U ) +#define RTC_CR_TAMP2RCLR_Msk ( 0x1UL << RTC_CR_TAMP2RCLR_Pos ) +#define RTC_CR_TAMP2RCLR ( RTC_CR_TAMP2RCLR_Msk ) + +#define RTC_CR_TS1EDGE_Pos ( 15U ) +#define RTC_CR_TS1EDGE_Msk ( 0x1UL << RTC_CR_TS1EDGE_Pos ) +#define RTC_CR_TS1EDGE ( RTC_CR_TS1EDGE_Msk ) + +#define RTC_CR_TAMP1FLT_Pos ( 13U ) +#define RTC_CR_TAMP1FLT_Msk ( 0x3UL << RTC_CR_TAMP1FLT_Pos ) +#define RTC_CR_TAMP1FLT ( RTC_CR_TAMP1FLT_Msk ) +#define RTC_CR_TAMP1FLT_0 ( 0x1UL << RTC_CR_TAMP1FLT_Pos ) +#define RTC_CR_TAMP1FLT_1 ( 0x2UL << RTC_CR_TAMP1FLT_Pos ) + +#define RTC_CR_TAMP1FLTEN_Pos ( 12U ) +#define RTC_CR_TAMP1FLTEN_Msk ( 0x1UL << RTC_CR_TAMP1FLTEN_Pos ) +#define RTC_CR_TAMP1FLTEN ( RTC_CR_TAMP1FLTEN_Msk ) + +#define RTC_CR_ALM_MSKD_Pos ( 11U ) +#define RTC_CR_ALM_MSKD_Msk ( 0x1UL << RTC_CR_ALM_MSKD_Pos ) +#define RTC_CR_ALM_MSKD ( RTC_CR_ALM_MSKD_Msk ) + +#define RTC_CR_ALM_MSKH_Pos ( 10U ) +#define RTC_CR_ALM_MSKH_Msk ( 0x1UL << RTC_CR_ALM_MSKH_Pos ) +#define RTC_CR_ALM_MSKH ( RTC_CR_ALM_MSKH_Msk ) + +#define RTC_CR_ALM_MSKM_Pos ( 9U ) +#define RTC_CR_ALM_MSKM_Msk ( 0x1UL << RTC_CR_ALM_MSKM_Pos ) +#define RTC_CR_ALM_MSKM ( RTC_CR_ALM_MSKM_Msk ) + +#define RTC_CR_TAMP1FCLR_Pos ( 8U ) +#define RTC_CR_TAMP1FCLR_Msk ( 0x1UL << RTC_CR_TAMP1FCLR_Pos ) +#define RTC_CR_TAMP1FCLR ( RTC_CR_TAMP1FCLR_Msk ) + +#define RTC_CR_TAMP1RCLR_Pos ( 7U ) +#define RTC_CR_TAMP1RCLR_Msk ( 0x1UL << RTC_CR_TAMP1RCLR_Pos ) +#define RTC_CR_TAMP1RCLR ( RTC_CR_TAMP1RCLR_Msk ) + +#define RTC_CR_TAMP2EN_Pos ( 6U ) +#define RTC_CR_TAMP2EN_Msk ( 0x1UL << RTC_CR_TAMP2EN_Pos ) +#define RTC_CR_TAMP2EN ( RTC_CR_TAMP2EN_Msk ) + +#define RTC_CR_TAMP1EN_Pos ( 5U ) +#define RTC_CR_TAMP1EN_Msk ( 0x1UL << RTC_CR_TAMP1EN_Pos ) +#define RTC_CR_TAMP1EN ( RTC_CR_TAMP1EN_Msk ) + +#define RTC_CR_ALM_EN_Pos ( 4U ) +#define RTC_CR_ALM_EN_Msk ( 0x1UL << RTC_CR_ALM_EN_Pos ) +#define RTC_CR_ALM_EN ( RTC_CR_ALM_EN_Msk ) + +#define RTC_CR_FSEL_Pos ( 0U ) +#define RTC_CR_FSEL_Msk ( 0xfUL << RTC_CR_FSEL_Pos ) +#define RTC_CR_FSEL ( RTC_CR_FSEL_Msk ) +#define RTC_CR_FSEL_0 ( 0x1UL << RTC_CR_FSEL_Pos ) +#define RTC_CR_FSEL_1 ( 0x2UL << RTC_CR_FSEL_Pos ) +#define RTC_CR_FSEL_2 ( 0x4UL << RTC_CR_FSEL_Pos ) +#define RTC_CR_FSEL_3 ( 0x8UL << RTC_CR_FSEL_Pos ) + + +/*************** Bits definition for RTC_ADJUST **********************/ + +#define RTC_ADJUST_ADJSIGN_Pos ( 9U ) +#define RTC_ADJUST_ADJSIGN_Msk ( 0x1UL << RTC_ADJUST_ADJSIGN_Pos ) +#define RTC_ADJUST_ADJSIGN ( RTC_ADJUST_ADJSIGN_Msk ) + +#define RTC_ADJUST_ADJVALUE_Pos ( 0U ) +#define RTC_ADJUST_ADJVALUE_Msk ( 0x1ffUL << RTC_ADJUST_ADJVALUE_Pos ) +#define RTC_ADJUST_ADJVALUE ( RTC_ADJUST_ADJVALUE_Msk ) + + +/*************** Bits definition for RTC_MSECCNT **********************/ + +#define RTC_MSECCNT_MSCNT_Pos ( 0U ) +#define RTC_MSECCNT_MSCNT_Msk ( 0x3fUL << RTC_MSECCNT_MSCNT_Pos ) +#define RTC_MSECCNT_MSCNT ( RTC_MSECCNT_MSCNT_Msk ) +#define RTC_MSECCNT_MSCNT_0 ( 0x1UL << RTC_MSECCNT_MSCNT_Pos ) +#define RTC_MSECCNT_MSCNT_1 ( 0x2UL << RTC_MSECCNT_MSCNT_Pos ) +#define RTC_MSECCNT_MSCNT_2 ( 0x4UL << RTC_MSECCNT_MSCNT_Pos ) +#define RTC_MSECCNT_MSCNT_3 ( 0x8UL << RTC_MSECCNT_MSCNT_Pos ) +#define RTC_MSECCNT_MSCNT_4 ( 0x10UL << RTC_MSECCNT_MSCNT_Pos ) +#define RTC_MSECCNT_MSCNT_5 ( 0x20UL << RTC_MSECCNT_MSCNT_Pos ) + + +/*************** Bits definition for RTC_CLKSTAMP1 **********************/ + +#define RTC_CLKSTAMP1_HRSTP1_Pos ( 16U ) +#define RTC_CLKSTAMP1_HRSTP1_Msk ( 0x3fUL << RTC_CLKSTAMP1_HRSTP1_Pos ) +#define RTC_CLKSTAMP1_HRSTP1 ( RTC_CLKSTAMP1_HRSTP1_Msk ) +#define RTC_CLKSTAMP1_HRSTP1_0 ( 0x1UL << RTC_CLKSTAMP1_HRSTP1_Pos ) +#define RTC_CLKSTAMP1_HRSTP1_1 ( 0x2UL << RTC_CLKSTAMP1_HRSTP1_Pos ) +#define RTC_CLKSTAMP1_HRSTP1_2 ( 0x4UL << RTC_CLKSTAMP1_HRSTP1_Pos ) +#define RTC_CLKSTAMP1_HRSTP1_3 ( 0x8UL << RTC_CLKSTAMP1_HRSTP1_Pos ) +#define RTC_CLKSTAMP1_HRSTP1_4 ( 0x10UL << RTC_CLKSTAMP1_HRSTP1_Pos ) +#define RTC_CLKSTAMP1_HRSTP1_5 ( 0x20UL << RTC_CLKSTAMP1_HRSTP1_Pos ) + +#define RTC_CLKSTAMP1_MINSTP1_Pos ( 8U ) +#define RTC_CLKSTAMP1_MINSTP1_Msk ( 0x7fUL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1 ( RTC_CLKSTAMP1_MINSTP1_Msk ) +#define RTC_CLKSTAMP1_MINSTP1_0 ( 0x1UL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1_1 ( 0x2UL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1_2 ( 0x4UL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1_3 ( 0x8UL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1_4 ( 0x10UL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1_5 ( 0x20UL << RTC_CLKSTAMP1_MINSTP1_Pos ) +#define RTC_CLKSTAMP1_MINSTP1_6 ( 0x40UL << RTC_CLKSTAMP1_MINSTP1_Pos ) + +#define RTC_CLKSTAMP1_SECSTP1_Pos ( 0U ) +#define RTC_CLKSTAMP1_SECSTP1_Msk ( 0x7fUL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1 ( RTC_CLKSTAMP1_SECSTP1_Msk ) +#define RTC_CLKSTAMP1_SECSTP1_0 ( 0x1UL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1_1 ( 0x2UL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1_2 ( 0x4UL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1_3 ( 0x8UL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1_4 ( 0x10UL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1_5 ( 0x20UL << RTC_CLKSTAMP1_SECSTP1_Pos ) +#define RTC_CLKSTAMP1_SECSTP1_6 ( 0x40UL << RTC_CLKSTAMP1_SECSTP1_Pos ) + + +/*************** Bits definition for RTC_CALSTAMP1 **********************/ + +#define RTC_CALSTAMP1_YEARSTP1_Pos ( 24U ) +#define RTC_CALSTAMP1_YEARSTP1_Msk ( 0xffUL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1 ( RTC_CALSTAMP1_YEARSTP1_Msk ) +#define RTC_CALSTAMP1_YEARSTP1_0 ( 0x1UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_1 ( 0x2UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_2 ( 0x4UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_3 ( 0x8UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_4 ( 0x10UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_5 ( 0x20UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_6 ( 0x40UL << RTC_CALSTAMP1_YEARSTP1_Pos ) +#define RTC_CALSTAMP1_YEARSTP1_7 ( 0x80UL << RTC_CALSTAMP1_YEARSTP1_Pos ) + +#define RTC_CALSTAMP1_MONSTP1_Pos ( 16U ) +#define RTC_CALSTAMP1_MONSTP1_Msk ( 0x1fUL << RTC_CALSTAMP1_MONSTP1_Pos ) +#define RTC_CALSTAMP1_MONSTP1 ( RTC_CALSTAMP1_MONSTP1_Msk ) +#define RTC_CALSTAMP1_MONSTP1_0 ( 0x1UL << RTC_CALSTAMP1_MONSTP1_Pos ) +#define RTC_CALSTAMP1_MONSTP1_1 ( 0x2UL << RTC_CALSTAMP1_MONSTP1_Pos ) +#define RTC_CALSTAMP1_MONSTP1_2 ( 0x4UL << RTC_CALSTAMP1_MONSTP1_Pos ) +#define RTC_CALSTAMP1_MONSTP1_3 ( 0x8UL << RTC_CALSTAMP1_MONSTP1_Pos ) +#define RTC_CALSTAMP1_MONSTP1_4 ( 0x10UL << RTC_CALSTAMP1_MONSTP1_Pos ) + +#define RTC_CALSTAMP1_WKSTP1_Pos ( 8U ) +#define RTC_CALSTAMP1_WKSTP1_Msk ( 0x7UL << RTC_CALSTAMP1_WKSTP1_Pos ) +#define RTC_CALSTAMP1_WKSTP1 ( RTC_CALSTAMP1_WKSTP1_Msk ) +#define RTC_CALSTAMP1_WKSTP1_0 ( 0x1UL << RTC_CALSTAMP1_WKSTP1_Pos ) +#define RTC_CALSTAMP1_WKSTP1_1 ( 0x2UL << RTC_CALSTAMP1_WKSTP1_Pos ) +#define RTC_CALSTAMP1_WKSTP1_2 ( 0x4UL << RTC_CALSTAMP1_WKSTP1_Pos ) + +#define RTC_CALSTAMP1_DAYSTP1_Pos ( 0U ) +#define RTC_CALSTAMP1_DAYSTP1_Msk ( 0x3fUL << RTC_CALSTAMP1_DAYSTP1_Pos ) +#define RTC_CALSTAMP1_DAYSTP1 ( RTC_CALSTAMP1_DAYSTP1_Msk ) +#define RTC_CALSTAMP1_DAYSTP1_0 ( 0x1UL << RTC_CALSTAMP1_DAYSTP1_Pos ) +#define RTC_CALSTAMP1_DAYSTP1_1 ( 0x2UL << RTC_CALSTAMP1_DAYSTP1_Pos ) +#define RTC_CALSTAMP1_DAYSTP1_2 ( 0x4UL << RTC_CALSTAMP1_DAYSTP1_Pos ) +#define RTC_CALSTAMP1_DAYSTP1_3 ( 0x8UL << RTC_CALSTAMP1_DAYSTP1_Pos ) +#define RTC_CALSTAMP1_DAYSTP1_4 ( 0x10UL << RTC_CALSTAMP1_DAYSTP1_Pos ) +#define RTC_CALSTAMP1_DAYSTP1_5 ( 0x20UL << RTC_CALSTAMP1_DAYSTP1_Pos ) + + +/*************** Bits definition for RTC_CLKSTAMP2 **********************/ + +#define RTC_CLKSTAMP2_HRSTP2_Pos ( 16U ) +#define RTC_CLKSTAMP2_HRSTP2_Msk ( 0x3fUL << RTC_CLKSTAMP2_HRSTP2_Pos ) +#define RTC_CLKSTAMP2_HRSTP2 ( RTC_CLKSTAMP2_HRSTP2_Msk ) +#define RTC_CLKSTAMP2_HRSTP2_0 ( 0x1UL << RTC_CLKSTAMP2_HRSTP2_Pos ) +#define RTC_CLKSTAMP2_HRSTP2_1 ( 0x2UL << RTC_CLKSTAMP2_HRSTP2_Pos ) +#define RTC_CLKSTAMP2_HRSTP2_2 ( 0x4UL << RTC_CLKSTAMP2_HRSTP2_Pos ) +#define RTC_CLKSTAMP2_HRSTP2_3 ( 0x8UL << RTC_CLKSTAMP2_HRSTP2_Pos ) +#define RTC_CLKSTAMP2_HRSTP2_4 ( 0x10UL << RTC_CLKSTAMP2_HRSTP2_Pos ) +#define RTC_CLKSTAMP2_HRSTP2_5 ( 0x20UL << RTC_CLKSTAMP2_HRSTP2_Pos ) + +#define RTC_CLKSTAMP2_MINSTP2_Pos ( 8U ) +#define RTC_CLKSTAMP2_MINSTP2_Msk ( 0x7fUL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2 ( RTC_CLKSTAMP2_MINSTP2_Msk ) +#define RTC_CLKSTAMP2_MINSTP2_0 ( 0x1UL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2_1 ( 0x2UL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2_2 ( 0x4UL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2_3 ( 0x8UL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2_4 ( 0x10UL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2_5 ( 0x20UL << RTC_CLKSTAMP2_MINSTP2_Pos ) +#define RTC_CLKSTAMP2_MINSTP2_6 ( 0x40UL << RTC_CLKSTAMP2_MINSTP2_Pos ) + +#define RTC_CLKSTAMP2_SECSTP2_Pos ( 0U ) +#define RTC_CLKSTAMP2_SECSTP2_Msk ( 0x7fUL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2 ( RTC_CLKSTAMP2_SECSTP2_Msk ) +#define RTC_CLKSTAMP2_SECSTP2_0 ( 0x1UL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2_1 ( 0x2UL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2_2 ( 0x4UL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2_3 ( 0x8UL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2_4 ( 0x10UL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2_5 ( 0x20UL << RTC_CLKSTAMP2_SECSTP2_Pos ) +#define RTC_CLKSTAMP2_SECSTP2_6 ( 0x40UL << RTC_CLKSTAMP2_SECSTP2_Pos ) + + +/*************** Bits definition for RTC_CALSTAMP2 **********************/ + +#define RTC_CALSTAMP2_YEARSTP2_Pos ( 24U ) +#define RTC_CALSTAMP2_YEARSTP2_Msk ( 0xffUL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2 ( RTC_CALSTAMP2_YEARSTP2_Msk ) +#define RTC_CALSTAMP2_YEARSTP2_0 ( 0x1UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_1 ( 0x2UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_2 ( 0x4UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_3 ( 0x8UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_4 ( 0x10UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_5 ( 0x20UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_6 ( 0x40UL << RTC_CALSTAMP2_YEARSTP2_Pos ) +#define RTC_CALSTAMP2_YEARSTP2_7 ( 0x80UL << RTC_CALSTAMP2_YEARSTP2_Pos ) + +#define RTC_CALSTAMP2_MONSTP2_Pos ( 16U ) +#define RTC_CALSTAMP2_MONSTP2_Msk ( 0x1fUL << RTC_CALSTAMP2_MONSTP2_Pos ) +#define RTC_CALSTAMP2_MONSTP2 ( RTC_CALSTAMP2_MONSTP2_Msk ) +#define RTC_CALSTAMP2_MONSTP2_0 ( 0x1UL << RTC_CALSTAMP2_MONSTP2_Pos ) +#define RTC_CALSTAMP2_MONSTP2_1 ( 0x2UL << RTC_CALSTAMP2_MONSTP2_Pos ) +#define RTC_CALSTAMP2_MONSTP2_2 ( 0x4UL << RTC_CALSTAMP2_MONSTP2_Pos ) +#define RTC_CALSTAMP2_MONSTP2_3 ( 0x8UL << RTC_CALSTAMP2_MONSTP2_Pos ) +#define RTC_CALSTAMP2_MONSTP2_4 ( 0x10UL << RTC_CALSTAMP2_MONSTP2_Pos ) + +#define RTC_CALSTAMP2_WKSTP2_Pos ( 8U ) +#define RTC_CALSTAMP2_WKSTP2_Msk ( 0x7UL << RTC_CALSTAMP2_WKSTP2_Pos ) +#define RTC_CALSTAMP2_WKSTP2 ( RTC_CALSTAMP2_WKSTP2_Msk ) +#define RTC_CALSTAMP2_WKSTP2_0 ( 0x1UL << RTC_CALSTAMP2_WKSTP2_Pos ) +#define RTC_CALSTAMP2_WKSTP2_1 ( 0x2UL << RTC_CALSTAMP2_WKSTP2_Pos ) +#define RTC_CALSTAMP2_WKSTP2_2 ( 0x4UL << RTC_CALSTAMP2_WKSTP2_Pos ) + +#define RTC_CALSTAMP2_DAYSTP2_Pos ( 0U ) +#define RTC_CALSTAMP2_DAYSTP2_Msk ( 0x3fUL << RTC_CALSTAMP2_DAYSTP2_Pos ) +#define RTC_CALSTAMP2_DAYSTP2 ( RTC_CALSTAMP2_DAYSTP2_Msk ) +#define RTC_CALSTAMP2_DAYSTP2_0 ( 0x1UL << RTC_CALSTAMP2_DAYSTP2_Pos ) +#define RTC_CALSTAMP2_DAYSTP2_1 ( 0x2UL << RTC_CALSTAMP2_DAYSTP2_Pos ) +#define RTC_CALSTAMP2_DAYSTP2_2 ( 0x4UL << RTC_CALSTAMP2_DAYSTP2_Pos ) +#define RTC_CALSTAMP2_DAYSTP2_3 ( 0x8UL << RTC_CALSTAMP2_DAYSTP2_Pos ) +#define RTC_CALSTAMP2_DAYSTP2_4 ( 0x10UL << RTC_CALSTAMP2_DAYSTP2_Pos ) +#define RTC_CALSTAMP2_DAYSTP2_5 ( 0x20UL << RTC_CALSTAMP2_DAYSTP2_Pos ) + + +/*************** Bits definition for RTC_WUTR **********************/ + +#define RTC_WUTR_WUT_Pos ( 0U ) +#define RTC_WUTR_WUT_Msk ( 0xffffUL << RTC_WUTR_WUT_Pos ) +#define RTC_WUTR_WUT ( RTC_WUTR_WUT_Msk ) + + +/*************** Bits definition for RTC_BAKUPx **********************/ + +#define RTC_BAKUPX_BAKUP_Pos ( 0U ) +#define RTC_BAKUPX_BAKUP_Msk ( 0xffffffffUL << RTC_BAKUPX_BAKUP_Pos ) +#define RTC_BAKUPX_BAKUP ( RTC_BAKUPX_BAKUP_Msk ) + + +/*************** Bits definition for WDT_LOAD **********************/ + +#define WDT_LOAD_LOAD_Pos ( 0U ) +#define WDT_LOAD_LOAD_Msk ( 0xffffffffUL << WDT_LOAD_LOAD_Pos ) +#define WDT_LOAD_LOAD ( WDT_LOAD_LOAD_Msk ) + + +/*************** Bits definition for WDT_COUNT **********************/ + +#define WDT_COUNT_COUNT_Pos ( 0U ) +#define WDT_COUNT_COUNT_Msk ( 0xffffffffUL << WDT_COUNT_COUNT_Pos ) +#define WDT_COUNT_COUNT ( WDT_COUNT_COUNT_Msk ) + + +/*************** Bits definition for WDT_CTRL **********************/ + +#define WDT_CTRL_EN_Pos ( 7U ) +#define WDT_CTRL_EN_Msk ( 0x1UL << WDT_CTRL_EN_Pos ) +#define WDT_CTRL_EN ( WDT_CTRL_EN_Msk ) + +#define WDT_CTRL_MODE_Pos ( 6U ) +#define WDT_CTRL_MODE_Msk ( 0x1UL << WDT_CTRL_MODE_Pos ) +#define WDT_CTRL_MODE ( WDT_CTRL_MODE_Msk ) + +#define WDT_CTRL_INTEN_Pos ( 4U ) +#define WDT_CTRL_INTEN_Msk ( 0x1UL << WDT_CTRL_INTEN_Pos ) +#define WDT_CTRL_INTEN ( WDT_CTRL_INTEN_Msk ) + +#define WDT_CTRL_DIVISOR_Pos ( 0U ) +#define WDT_CTRL_DIVISOR_Msk ( 0x7UL << WDT_CTRL_DIVISOR_Pos ) +#define WDT_CTRL_DIVISOR ( WDT_CTRL_DIVISOR_Msk ) +#define WDT_CTRL_DIVISOR_0 ( 0x1UL << WDT_CTRL_DIVISOR_Pos ) +#define WDT_CTRL_DIVISOR_1 ( 0x2UL << WDT_CTRL_DIVISOR_Pos ) +#define WDT_CTRL_DIVISOR_2 ( 0x4UL << WDT_CTRL_DIVISOR_Pos ) + + +/*************** Bits definition for WDT_FEED **********************/ + +#define WDT_FEED_FEED_Pos ( 0U ) +#define WDT_FEED_FEED_Msk ( 0xffffffffUL << WDT_FEED_FEED_Pos ) +#define WDT_FEED_FEED ( WDT_FEED_FEED_Msk ) + + +/*************** Bits definition for WDT_INTCLRTIME **********************/ + +#define WDT_INTCLRTIME_INTCLRT_Pos ( 0U ) +#define WDT_INTCLRTIME_INTCLRT_Msk ( 0xffffUL << WDT_INTCLRTIME_INTCLRT_Pos ) +#define WDT_INTCLRTIME_INTCLRT ( WDT_INTCLRTIME_INTCLRT_Msk ) + + +/*************** Bits definition for WDT_RIS **********************/ + +#define WDT_RIS_WDT_RIS_Pos ( 0U ) +#define WDT_RIS_WDT_RIS_Msk ( 0x1UL << WDT_RIS_WDT_RIS_Pos ) +#define WDT_RIS_WDT_RIS ( WDT_RIS_WDT_RIS_Msk ) + + +/*************** Bits definition for IWDT_CMDR **********************/ + +#define IWDT_CMDR_CMD_Pos ( 0U ) +#define IWDT_CMDR_CMD_Msk ( 0xffffUL << IWDT_CMDR_CMD_Pos ) +#define IWDT_CMDR_CMD ( IWDT_CMDR_CMD_Msk ) + + +/*************** Bits definition for IWDT_PR **********************/ + +#define IWDT_PR_PR_Pos ( 0U ) +#define IWDT_PR_PR_Msk ( 0x7UL << IWDT_PR_PR_Pos ) +#define IWDT_PR_PR ( IWDT_PR_PR_Msk ) +#define IWDT_PR_PR_0 ( 0x1UL << IWDT_PR_PR_Pos ) +#define IWDT_PR_PR_1 ( 0x2UL << IWDT_PR_PR_Pos ) +#define IWDT_PR_PR_2 ( 0x4UL << IWDT_PR_PR_Pos ) + + +/*************** Bits definition for IWDT_RLR **********************/ + +#define IWDT_RLR_PL_Pos ( 0U ) +#define IWDT_RLR_PL_Msk ( 0xfffUL << IWDT_RLR_PL_Pos ) +#define IWDT_RLR_PL ( IWDT_RLR_PL_Msk ) + + +/*************** Bits definition for IWDT_SR **********************/ + +#define IWDT_SR_RLF_Pos ( 4U ) +#define IWDT_SR_RLF_Msk ( 0x1UL << IWDT_SR_RLF_Pos ) +#define IWDT_SR_RLF ( IWDT_SR_RLF_Msk ) + +#define IWDT_SR_WTU_Pos ( 3U ) +#define IWDT_SR_WTU_Msk ( 0x1UL << IWDT_SR_WTU_Pos ) +#define IWDT_SR_WTU ( IWDT_SR_WTU_Msk ) + +#define IWDT_SR_WVU_Pos ( 2U ) +#define IWDT_SR_WVU_Msk ( 0x1UL << IWDT_SR_WVU_Pos ) +#define IWDT_SR_WVU ( IWDT_SR_WVU_Msk ) + +#define IWDT_SR_RVU_Pos ( 1U ) +#define IWDT_SR_RVU_Msk ( 0x1UL << IWDT_SR_RVU_Pos ) +#define IWDT_SR_RVU ( IWDT_SR_RVU_Msk ) + +#define IWDT_SR_PVU_Pos ( 0U ) +#define IWDT_SR_PVU_Msk ( 0x1UL << IWDT_SR_PVU_Pos ) +#define IWDT_SR_PVU ( IWDT_SR_PVU_Msk ) + + +/*************** Bits definition for IWDT_WINR **********************/ + +#define IWDT_WINR_WIN_Pos ( 0U ) +#define IWDT_WINR_WIN_Msk ( 0xfffUL << IWDT_WINR_WIN_Pos ) +#define IWDT_WINR_WIN ( IWDT_WINR_WIN_Msk ) + + +/*************** Bits definition for IWDT_WUTR **********************/ + +#define IWDT_WUTR_WUT_Pos ( 0U ) +#define IWDT_WUTR_WUT_Msk ( 0xfffUL << IWDT_WUTR_WUT_Pos ) +#define IWDT_WUTR_WUT ( IWDT_WUTR_WUT_Msk ) + + +/*************** Bits definition for ADC_SR **********************/ + +#define ADC_SR_AFE_EOC_Pos ( 8U ) +#define ADC_SR_AFE_EOC_Msk ( 0x1UL << ADC_SR_AFE_EOC_Pos ) +#define ADC_SR_AFE_EOC ( ADC_SR_AFE_EOC_Msk ) + +#define ADC_SR_AWD_Pos ( 7U ) +#define ADC_SR_AWD_Msk ( 0x1UL << ADC_SR_AWD_Pos ) +#define ADC_SR_AWD ( ADC_SR_AWD_Msk ) + +#define ADC_SR_JEOG_Pos ( 6U ) +#define ADC_SR_JEOG_Msk ( 0x1UL << ADC_SR_JEOG_Pos ) +#define ADC_SR_JEOG ( ADC_SR_JEOG_Msk ) + +#define ADC_SR_JEOC_Pos ( 5U ) +#define ADC_SR_JEOC_Msk ( 0x1UL << ADC_SR_JEOC_Pos ) +#define ADC_SR_JEOC ( ADC_SR_JEOC_Msk ) + +#define ADC_SR_OVERF_Pos ( 4U ) +#define ADC_SR_OVERF_Msk ( 0x1UL << ADC_SR_OVERF_Pos ) +#define ADC_SR_OVERF ( ADC_SR_OVERF_Msk ) + +#define ADC_SR_EOG_Pos ( 3U ) +#define ADC_SR_EOG_Msk ( 0x1UL << ADC_SR_EOG_Pos ) +#define ADC_SR_EOG ( ADC_SR_EOG_Msk ) + +#define ADC_SR_EOC_Pos ( 2U ) +#define ADC_SR_EOC_Msk ( 0x1UL << ADC_SR_EOC_Pos ) +#define ADC_SR_EOC ( ADC_SR_EOC_Msk ) + +#define ADC_SR_EOSMP_Pos ( 1U ) +#define ADC_SR_EOSMP_Msk ( 0x1UL << ADC_SR_EOSMP_Pos ) +#define ADC_SR_EOSMP ( ADC_SR_EOSMP_Msk ) + +#define ADC_SR_ADRDY_Pos ( 0U ) +#define ADC_SR_ADRDY_Msk ( 0x1UL << ADC_SR_ADRDY_Pos ) +#define ADC_SR_ADRDY ( ADC_SR_ADRDY_Msk ) + + +/*************** Bits definition for ADC_IE **********************/ + +#define ADC_IE_AWDIE_Pos ( 7U ) +#define ADC_IE_AWDIE_Msk ( 0x1UL << ADC_IE_AWDIE_Pos ) +#define ADC_IE_AWDIE ( ADC_IE_AWDIE_Msk ) + +#define ADC_IE_JEOGIE_Pos ( 6U ) +#define ADC_IE_JEOGIE_Msk ( 0x1UL << ADC_IE_JEOGIE_Pos ) +#define ADC_IE_JEOGIE ( ADC_IE_JEOGIE_Msk ) + +#define ADC_IE_JEOCIE_Pos ( 5U ) +#define ADC_IE_JEOCIE_Msk ( 0x1UL << ADC_IE_JEOCIE_Pos ) +#define ADC_IE_JEOCIE ( ADC_IE_JEOCIE_Msk ) + +#define ADC_IE_OVERFIE_Pos ( 4U ) +#define ADC_IE_OVERFIE_Msk ( 0x1UL << ADC_IE_OVERFIE_Pos ) +#define ADC_IE_OVERFIE ( ADC_IE_OVERFIE_Msk ) + +#define ADC_IE_EOGIE_Pos ( 3U ) +#define ADC_IE_EOGIE_Msk ( 0x1UL << ADC_IE_EOGIE_Pos ) +#define ADC_IE_EOGIE ( ADC_IE_EOGIE_Msk ) + +#define ADC_IE_EOCIE_Pos ( 2U ) +#define ADC_IE_EOCIE_Msk ( 0x1UL << ADC_IE_EOCIE_Pos ) +#define ADC_IE_EOCIE ( ADC_IE_EOCIE_Msk ) + +#define ADC_IE_EOSMPIE_Pos ( 1U ) +#define ADC_IE_EOSMPIE_Msk ( 0x1UL << ADC_IE_EOSMPIE_Pos ) +#define ADC_IE_EOSMPIE ( ADC_IE_EOSMPIE_Msk ) + + +/*************** Bits definition for ADC_CR1 **********************/ + +#define ADC_CR1_DISCNUM_Pos ( 28U ) +#define ADC_CR1_DISCNUM_Msk ( 0x7UL << ADC_CR1_DISCNUM_Pos ) +#define ADC_CR1_DISCNUM ( ADC_CR1_DISCNUM_Msk ) +#define ADC_CR1_DISCNUM_0 ( 0x1UL << ADC_CR1_DISCNUM_Pos ) +#define ADC_CR1_DISCNUM_1 ( 0x2UL << ADC_CR1_DISCNUM_Pos ) +#define ADC_CR1_DISCNUM_2 ( 0x4UL << ADC_CR1_DISCNUM_Pos ) + +#define ADC_CR1_JDISCEN_Pos ( 27U ) +#define ADC_CR1_JDISCEN_Msk ( 0x1UL << ADC_CR1_JDISCEN_Pos ) +#define ADC_CR1_JDISCEN ( ADC_CR1_JDISCEN_Msk ) + +#define ADC_CR1_DISCEN_Pos ( 26U ) +#define ADC_CR1_DISCEN_Msk ( 0x1UL << ADC_CR1_DISCEN_Pos ) +#define ADC_CR1_DISCEN ( ADC_CR1_DISCEN_Msk ) + +#define ADC_CR1_JAUTO_Pos ( 25U ) +#define ADC_CR1_JAUTO_Msk ( 0x1UL << ADC_CR1_JAUTO_Pos ) +#define ADC_CR1_JAUTO ( ADC_CR1_JAUTO_Msk ) + +#define ADC_CR1_CONT_Pos ( 24U ) +#define ADC_CR1_CONT_Msk ( 0x1UL << ADC_CR1_CONT_Pos ) +#define ADC_CR1_CONT ( ADC_CR1_CONT_Msk ) + +#define ADC_CR1_SWSTART_Pos ( 23U ) +#define ADC_CR1_SWSTART_Msk ( 0x1UL << ADC_CR1_SWSTART_Pos ) +#define ADC_CR1_SWSTART ( ADC_CR1_SWSTART_Msk ) + +#define ADC_CR1_JSWSTART_Pos ( 22U ) +#define ADC_CR1_JSWSTART_Msk ( 0x1UL << ADC_CR1_JSWSTART_Pos ) +#define ADC_CR1_JSWSTART ( ADC_CR1_JSWSTART_Msk ) + +#define ADC_CR1_EXTSEL_Pos ( 16U ) +#define ADC_CR1_EXTSEL_Msk ( 0x1fUL << ADC_CR1_EXTSEL_Pos ) +#define ADC_CR1_EXTSEL ( ADC_CR1_EXTSEL_Msk ) +#define ADC_CR1_EXTSEL_0 ( 0x1UL << ADC_CR1_EXTSEL_Pos ) +#define ADC_CR1_EXTSEL_1 ( 0x2UL << ADC_CR1_EXTSEL_Pos ) +#define ADC_CR1_EXTSEL_2 ( 0x4UL << ADC_CR1_EXTSEL_Pos ) +#define ADC_CR1_EXTSEL_3 ( 0x8UL << ADC_CR1_EXTSEL_Pos ) +#define ADC_CR1_EXTSEL_4 ( 0x10UL << ADC_CR1_EXTSEL_Pos ) + +#define ADC_CR1_EXTEN_Pos ( 14U ) +#define ADC_CR1_EXTEN_Msk ( 0x3UL << ADC_CR1_EXTEN_Pos ) +#define ADC_CR1_EXTEN ( ADC_CR1_EXTEN_Msk ) +#define ADC_CR1_EXTEN_0 ( 0x1UL << ADC_CR1_EXTEN_Pos ) +#define ADC_CR1_EXTEN_1 ( 0x2UL << ADC_CR1_EXTEN_Pos ) + +#define ADC_CR1_DMA_Pos ( 13U ) +#define ADC_CR1_DMA_Msk ( 0x1UL << ADC_CR1_DMA_Pos ) +#define ADC_CR1_DMA ( ADC_CR1_DMA_Msk ) + +#define ADC_CR1_AWDEN_Pos ( 12U ) +#define ADC_CR1_AWDEN_Msk ( 0x1UL << ADC_CR1_AWDEN_Pos ) +#define ADC_CR1_AWDEN ( ADC_CR1_AWDEN_Msk ) + +#define ADC_CR1_JAWDEN_Pos ( 11U ) +#define ADC_CR1_JAWDEN_Msk ( 0x1UL << ADC_CR1_JAWDEN_Pos ) +#define ADC_CR1_JAWDEN ( ADC_CR1_JAWDEN_Msk ) + +#define ADC_CR1_AWDSGL_Pos ( 10U ) +#define ADC_CR1_AWDSGL_Msk ( 0x1UL << ADC_CR1_AWDSGL_Pos ) +#define ADC_CR1_AWDSGL ( ADC_CR1_AWDSGL_Msk ) + +#define ADC_CR1_AWDJCH_Pos ( 5U ) +#define ADC_CR1_AWDJCH_Msk ( 0x1fUL << ADC_CR1_AWDJCH_Pos ) +#define ADC_CR1_AWDJCH ( ADC_CR1_AWDJCH_Msk ) +#define ADC_CR1_AWDJCH_0 ( 0x1UL << ADC_CR1_AWDJCH_Pos ) +#define ADC_CR1_AWDJCH_1 ( 0x2UL << ADC_CR1_AWDJCH_Pos ) +#define ADC_CR1_AWDJCH_2 ( 0x4UL << ADC_CR1_AWDJCH_Pos ) +#define ADC_CR1_AWDJCH_3 ( 0x8UL << ADC_CR1_AWDJCH_Pos ) +#define ADC_CR1_AWDJCH_4 ( 0x10UL << ADC_CR1_AWDJCH_Pos ) + +#define ADC_CR1_AWDCH_Pos ( 0U ) +#define ADC_CR1_AWDCH_Msk ( 0x1fUL << ADC_CR1_AWDCH_Pos ) +#define ADC_CR1_AWDCH ( ADC_CR1_AWDCH_Msk ) +#define ADC_CR1_AWDCH_0 ( 0x1UL << ADC_CR1_AWDCH_Pos ) +#define ADC_CR1_AWDCH_1 ( 0x2UL << ADC_CR1_AWDCH_Pos ) +#define ADC_CR1_AWDCH_2 ( 0x4UL << ADC_CR1_AWDCH_Pos ) +#define ADC_CR1_AWDCH_3 ( 0x8UL << ADC_CR1_AWDCH_Pos ) +#define ADC_CR1_AWDCH_4 ( 0x10UL << ADC_CR1_AWDCH_Pos ) + + +/*************** Bits definition for ADC_CR2 **********************/ + +#define ADC_CR2_ADCCAL_Pos ( 31U ) +#define ADC_CR2_ADCCAL_Msk ( 0x1UL << ADC_CR2_ADCCAL_Pos ) +#define ADC_CR2_ADCCAL ( ADC_CR2_ADCCAL_Msk ) + +#define ADC_CR2_ADCCALDIF_Pos ( 30U ) +#define ADC_CR2_ADCCALDIF_Msk ( 0x1UL << ADC_CR2_ADCCALDIF_Pos ) +#define ADC_CR2_ADCCALDIF ( ADC_CR2_ADCCALDIF_Msk ) + +#define ADC_CR2_ADCRSTN_Pos ( 29U ) +#define ADC_CR2_ADCRSTN_Msk ( 0x1UL << ADC_CR2_ADCRSTN_Pos ) +#define ADC_CR2_ADCRSTN ( ADC_CR2_ADCRSTN_Msk ) + +#define ADC_CR2_ADCVREGEN_Pos ( 28U ) +#define ADC_CR2_ADCVREGEN_Msk ( 0x1UL << ADC_CR2_ADCVREGEN_Pos ) +#define ADC_CR2_ADCVREGEN ( ADC_CR2_ADCVREGEN_Msk ) + +#define ADC_CR2_JOVSE_Pos ( 25U ) +#define ADC_CR2_JOVSE_Msk ( 0x1UL << ADC_CR2_JOVSE_Pos ) +#define ADC_CR2_JOVSE ( ADC_CR2_JOVSE_Msk ) + +#define ADC_CR2_TROVS_Pos ( 24U ) +#define ADC_CR2_TROVS_Msk ( 0x1UL << ADC_CR2_TROVS_Pos ) +#define ADC_CR2_TROVS ( ADC_CR2_TROVS_Msk ) + +#define ADC_CR2_OVSS_Pos ( 20U ) +#define ADC_CR2_OVSS_Msk ( 0xfUL << ADC_CR2_OVSS_Pos ) +#define ADC_CR2_OVSS ( ADC_CR2_OVSS_Msk ) +#define ADC_CR2_OVSS_0 ( 0x1UL << ADC_CR2_OVSS_Pos ) +#define ADC_CR2_OVSS_1 ( 0x2UL << ADC_CR2_OVSS_Pos ) +#define ADC_CR2_OVSS_2 ( 0x4UL << ADC_CR2_OVSS_Pos ) +#define ADC_CR2_OVSS_3 ( 0x8UL << ADC_CR2_OVSS_Pos ) + +#define ADC_CR2_OVSR_Pos ( 17U ) +#define ADC_CR2_OVSR_Msk ( 0x7UL << ADC_CR2_OVSR_Pos ) +#define ADC_CR2_OVSR ( ADC_CR2_OVSR_Msk ) +#define ADC_CR2_OVSR_0 ( 0x1UL << ADC_CR2_OVSR_Pos ) +#define ADC_CR2_OVSR_1 ( 0x2UL << ADC_CR2_OVSR_Pos ) +#define ADC_CR2_OVSR_2 ( 0x4UL << ADC_CR2_OVSR_Pos ) + +#define ADC_CR2_OVSE_Pos ( 16U ) +#define ADC_CR2_OVSE_Msk ( 0x1UL << ADC_CR2_OVSE_Pos ) +#define ADC_CR2_OVSE ( ADC_CR2_OVSE_Msk ) + +#define ADC_CR2_TRIMLDO12_Pos ( 6U ) +#define ADC_CR2_TRIMLDO12_Msk ( 0xfUL << ADC_CR2_TRIMLDO12_Pos ) +#define ADC_CR2_TRIMLDO12 ( ADC_CR2_TRIMLDO12_Msk ) +#define ADC_CR2_TRIMLDO12_0 ( 0x1UL << ADC_CR2_TRIMLDO12_Pos ) +#define ADC_CR2_TRIMLDO12_1 ( 0x2UL << ADC_CR2_TRIMLDO12_Pos ) +#define ADC_CR2_TRIMLDO12_2 ( 0x4UL << ADC_CR2_TRIMLDO12_Pos ) +#define ADC_CR2_TRIMLDO12_3 ( 0x8UL << ADC_CR2_TRIMLDO12_Pos ) + +#define ADC_CR2_RES_Pos ( 4U ) +#define ADC_CR2_RES_Msk ( 0x3UL << ADC_CR2_RES_Pos ) +#define ADC_CR2_RES ( ADC_CR2_RES_Msk ) +#define ADC_CR2_RES_0 ( 0x1UL << ADC_CR2_RES_Pos ) +#define ADC_CR2_RES_1 ( 0x2UL << ADC_CR2_RES_Pos ) + +#define ADC_CR2_ALIGN_Pos ( 3U ) +#define ADC_CR2_ALIGN_Msk ( 0x1UL << ADC_CR2_ALIGN_Pos ) +#define ADC_CR2_ALIGN ( ADC_CR2_ALIGN_Msk ) + +#define ADC_CR2_STP_Pos ( 2U ) +#define ADC_CR2_STP_Msk ( 0x1UL << ADC_CR2_STP_Pos ) +#define ADC_CR2_STP ( ADC_CR2_STP_Msk ) + +#define ADC_CR2_OVRMOD_Pos ( 1U ) +#define ADC_CR2_OVRMOD_Msk ( 0x1UL << ADC_CR2_OVRMOD_Pos ) +#define ADC_CR2_OVRMOD ( ADC_CR2_OVRMOD_Msk ) + +#define ADC_CR2_EN_Pos ( 0U ) +#define ADC_CR2_EN_Msk ( 0x1UL << ADC_CR2_EN_Pos ) +#define ADC_CR2_EN ( ADC_CR2_EN_Msk ) + + +/*************** Bits definition for ADC_SMPR1 **********************/ + +#define ADC_SMPR1_SMP7_Pos ( 28U ) +#define ADC_SMPR1_SMP7_Msk ( 0xfUL << ADC_SMPR1_SMP7_Pos ) +#define ADC_SMPR1_SMP7 ( ADC_SMPR1_SMP7_Msk ) +#define ADC_SMPR1_SMP7_0 ( 0x1UL << ADC_SMPR1_SMP7_Pos ) +#define ADC_SMPR1_SMP7_1 ( 0x2UL << ADC_SMPR1_SMP7_Pos ) +#define ADC_SMPR1_SMP7_2 ( 0x4UL << ADC_SMPR1_SMP7_Pos ) +#define ADC_SMPR1_SMP7_3 ( 0x8UL << ADC_SMPR1_SMP7_Pos ) + +#define ADC_SMPR1_SMP6_Pos ( 24U ) +#define ADC_SMPR1_SMP6_Msk ( 0xfUL << ADC_SMPR1_SMP6_Pos ) +#define ADC_SMPR1_SMP6 ( ADC_SMPR1_SMP6_Msk ) +#define ADC_SMPR1_SMP6_0 ( 0x1UL << ADC_SMPR1_SMP6_Pos ) +#define ADC_SMPR1_SMP6_1 ( 0x2UL << ADC_SMPR1_SMP6_Pos ) +#define ADC_SMPR1_SMP6_2 ( 0x4UL << ADC_SMPR1_SMP6_Pos ) +#define ADC_SMPR1_SMP6_3 ( 0x8UL << ADC_SMPR1_SMP6_Pos ) + +#define ADC_SMPR1_SMP5_Pos ( 20U ) +#define ADC_SMPR1_SMP5_Msk ( 0xfUL << ADC_SMPR1_SMP5_Pos ) +#define ADC_SMPR1_SMP5 ( ADC_SMPR1_SMP5_Msk ) +#define ADC_SMPR1_SMP5_0 ( 0x1UL << ADC_SMPR1_SMP5_Pos ) +#define ADC_SMPR1_SMP5_1 ( 0x2UL << ADC_SMPR1_SMP5_Pos ) +#define ADC_SMPR1_SMP5_2 ( 0x4UL << ADC_SMPR1_SMP5_Pos ) +#define ADC_SMPR1_SMP5_3 ( 0x8UL << ADC_SMPR1_SMP5_Pos ) + +#define ADC_SMPR1_SMP4_Pos ( 16U ) +#define ADC_SMPR1_SMP4_Msk ( 0xfUL << ADC_SMPR1_SMP4_Pos ) +#define ADC_SMPR1_SMP4 ( ADC_SMPR1_SMP4_Msk ) +#define ADC_SMPR1_SMP4_0 ( 0x1UL << ADC_SMPR1_SMP4_Pos ) +#define ADC_SMPR1_SMP4_1 ( 0x2UL << ADC_SMPR1_SMP4_Pos ) +#define ADC_SMPR1_SMP4_2 ( 0x4UL << ADC_SMPR1_SMP4_Pos ) +#define ADC_SMPR1_SMP4_3 ( 0x8UL << ADC_SMPR1_SMP4_Pos ) + +#define ADC_SMPR1_SMP3_Pos ( 12U ) +#define ADC_SMPR1_SMP3_Msk ( 0xfUL << ADC_SMPR1_SMP3_Pos ) +#define ADC_SMPR1_SMP3 ( ADC_SMPR1_SMP3_Msk ) +#define ADC_SMPR1_SMP3_0 ( 0x1UL << ADC_SMPR1_SMP3_Pos ) +#define ADC_SMPR1_SMP3_1 ( 0x2UL << ADC_SMPR1_SMP3_Pos ) +#define ADC_SMPR1_SMP3_2 ( 0x4UL << ADC_SMPR1_SMP3_Pos ) +#define ADC_SMPR1_SMP3_3 ( 0x8UL << ADC_SMPR1_SMP3_Pos ) + +#define ADC_SMPR1_SMP2_Pos ( 8U ) +#define ADC_SMPR1_SMP2_Msk ( 0xfUL << ADC_SMPR1_SMP2_Pos ) +#define ADC_SMPR1_SMP2 ( ADC_SMPR1_SMP2_Msk ) +#define ADC_SMPR1_SMP2_0 ( 0x1UL << ADC_SMPR1_SMP2_Pos ) +#define ADC_SMPR1_SMP2_1 ( 0x2UL << ADC_SMPR1_SMP2_Pos ) +#define ADC_SMPR1_SMP2_2 ( 0x4UL << ADC_SMPR1_SMP2_Pos ) +#define ADC_SMPR1_SMP2_3 ( 0x8UL << ADC_SMPR1_SMP2_Pos ) + +#define ADC_SMPR1_SMP1_Pos ( 4U ) +#define ADC_SMPR1_SMP1_Msk ( 0xfUL << ADC_SMPR1_SMP1_Pos ) +#define ADC_SMPR1_SMP1 ( ADC_SMPR1_SMP1_Msk ) +#define ADC_SMPR1_SMP1_0 ( 0x1UL << ADC_SMPR1_SMP1_Pos ) +#define ADC_SMPR1_SMP1_1 ( 0x2UL << ADC_SMPR1_SMP1_Pos ) +#define ADC_SMPR1_SMP1_2 ( 0x4UL << ADC_SMPR1_SMP1_Pos ) +#define ADC_SMPR1_SMP1_3 ( 0x8UL << ADC_SMPR1_SMP1_Pos ) + +#define ADC_SMPR1_SMP0_Pos ( 0U ) +#define ADC_SMPR1_SMP0_Msk ( 0xfUL << ADC_SMPR1_SMP0_Pos ) +#define ADC_SMPR1_SMP0 ( ADC_SMPR1_SMP0_Msk ) +#define ADC_SMPR1_SMP0_0 ( 0x1UL << ADC_SMPR1_SMP0_Pos ) +#define ADC_SMPR1_SMP0_1 ( 0x2UL << ADC_SMPR1_SMP0_Pos ) +#define ADC_SMPR1_SMP0_2 ( 0x4UL << ADC_SMPR1_SMP0_Pos ) +#define ADC_SMPR1_SMP0_3 ( 0x8UL << ADC_SMPR1_SMP0_Pos ) + + +/*************** Bits definition for ADC_SMPR2 **********************/ + +#define ADC_SMPR2_SMP15_Pos ( 28U ) +#define ADC_SMPR2_SMP15_Msk ( 0xfUL << ADC_SMPR2_SMP15_Pos ) +#define ADC_SMPR2_SMP15 ( ADC_SMPR2_SMP15_Msk ) +#define ADC_SMPR2_SMP15_0 ( 0x1UL << ADC_SMPR2_SMP15_Pos ) +#define ADC_SMPR2_SMP15_1 ( 0x2UL << ADC_SMPR2_SMP15_Pos ) +#define ADC_SMPR2_SMP15_2 ( 0x4UL << ADC_SMPR2_SMP15_Pos ) +#define ADC_SMPR2_SMP15_3 ( 0x8UL << ADC_SMPR2_SMP15_Pos ) + +#define ADC_SMPR2_SMP14_Pos ( 24U ) +#define ADC_SMPR2_SMP14_Msk ( 0xfUL << ADC_SMPR2_SMP14_Pos ) +#define ADC_SMPR2_SMP14 ( ADC_SMPR2_SMP14_Msk ) +#define ADC_SMPR2_SMP14_0 ( 0x1UL << ADC_SMPR2_SMP14_Pos ) +#define ADC_SMPR2_SMP14_1 ( 0x2UL << ADC_SMPR2_SMP14_Pos ) +#define ADC_SMPR2_SMP14_2 ( 0x4UL << ADC_SMPR2_SMP14_Pos ) +#define ADC_SMPR2_SMP14_3 ( 0x8UL << ADC_SMPR2_SMP14_Pos ) + +#define ADC_SMPR2_SMP13_Pos ( 20U ) +#define ADC_SMPR2_SMP13_Msk ( 0xfUL << ADC_SMPR2_SMP13_Pos ) +#define ADC_SMPR2_SMP13 ( ADC_SMPR2_SMP13_Msk ) +#define ADC_SMPR2_SMP13_0 ( 0x1UL << ADC_SMPR2_SMP13_Pos ) +#define ADC_SMPR2_SMP13_1 ( 0x2UL << ADC_SMPR2_SMP13_Pos ) +#define ADC_SMPR2_SMP13_2 ( 0x4UL << ADC_SMPR2_SMP13_Pos ) +#define ADC_SMPR2_SMP13_3 ( 0x8UL << ADC_SMPR2_SMP13_Pos ) + +#define ADC_SMPR2_SMP12_Pos ( 16U ) +#define ADC_SMPR2_SMP12_Msk ( 0xfUL << ADC_SMPR2_SMP12_Pos ) +#define ADC_SMPR2_SMP12 ( ADC_SMPR2_SMP12_Msk ) +#define ADC_SMPR2_SMP12_0 ( 0x1UL << ADC_SMPR2_SMP12_Pos ) +#define ADC_SMPR2_SMP12_1 ( 0x2UL << ADC_SMPR2_SMP12_Pos ) +#define ADC_SMPR2_SMP12_2 ( 0x4UL << ADC_SMPR2_SMP12_Pos ) +#define ADC_SMPR2_SMP12_3 ( 0x8UL << ADC_SMPR2_SMP12_Pos ) + +#define ADC_SMPR2_SMP11_Pos ( 12U ) +#define ADC_SMPR2_SMP11_Msk ( 0xfUL << ADC_SMPR2_SMP11_Pos ) +#define ADC_SMPR2_SMP11 ( ADC_SMPR2_SMP11_Msk ) +#define ADC_SMPR2_SMP11_0 ( 0x1UL << ADC_SMPR2_SMP11_Pos ) +#define ADC_SMPR2_SMP11_1 ( 0x2UL << ADC_SMPR2_SMP11_Pos ) +#define ADC_SMPR2_SMP11_2 ( 0x4UL << ADC_SMPR2_SMP11_Pos ) +#define ADC_SMPR2_SMP11_3 ( 0x8UL << ADC_SMPR2_SMP11_Pos ) + +#define ADC_SMPR2_SMP10_Pos ( 8U ) +#define ADC_SMPR2_SMP10_Msk ( 0xfUL << ADC_SMPR2_SMP10_Pos ) +#define ADC_SMPR2_SMP10 ( ADC_SMPR2_SMP10_Msk ) +#define ADC_SMPR2_SMP10_0 ( 0x1UL << ADC_SMPR2_SMP10_Pos ) +#define ADC_SMPR2_SMP10_1 ( 0x2UL << ADC_SMPR2_SMP10_Pos ) +#define ADC_SMPR2_SMP10_2 ( 0x4UL << ADC_SMPR2_SMP10_Pos ) +#define ADC_SMPR2_SMP10_3 ( 0x8UL << ADC_SMPR2_SMP10_Pos ) + +#define ADC_SMPR2_SMP9_Pos ( 4U ) +#define ADC_SMPR2_SMP9_Msk ( 0xfUL << ADC_SMPR2_SMP9_Pos ) +#define ADC_SMPR2_SMP9 ( ADC_SMPR2_SMP9_Msk ) +#define ADC_SMPR2_SMP9_0 ( 0x1UL << ADC_SMPR2_SMP9_Pos ) +#define ADC_SMPR2_SMP9_1 ( 0x2UL << ADC_SMPR2_SMP9_Pos ) +#define ADC_SMPR2_SMP9_2 ( 0x4UL << ADC_SMPR2_SMP9_Pos ) +#define ADC_SMPR2_SMP9_3 ( 0x8UL << ADC_SMPR2_SMP9_Pos ) + +#define ADC_SMPR2_SMP8_Pos ( 0U ) +#define ADC_SMPR2_SMP8_Msk ( 0xfUL << ADC_SMPR2_SMP8_Pos ) +#define ADC_SMPR2_SMP8 ( ADC_SMPR2_SMP8_Msk ) +#define ADC_SMPR2_SMP8_0 ( 0x1UL << ADC_SMPR2_SMP8_Pos ) +#define ADC_SMPR2_SMP8_1 ( 0x2UL << ADC_SMPR2_SMP8_Pos ) +#define ADC_SMPR2_SMP8_2 ( 0x4UL << ADC_SMPR2_SMP8_Pos ) +#define ADC_SMPR2_SMP8_3 ( 0x8UL << ADC_SMPR2_SMP8_Pos ) + + +/*************** Bits definition for ADC_SMPR3 **********************/ + +#define ADC_SMPR3_CONV_PLUS_Pos ( 20U ) +#define ADC_SMPR3_CONV_PLUS_Msk ( 0x3UL << ADC_SMPR3_CONV_PLUS_Pos ) +#define ADC_SMPR3_CONV_PLUS ( ADC_SMPR3_CONV_PLUS_Msk ) +#define ADC_SMPR3_CONV_PLUS_0 ( 0x1UL << ADC_SMPR3_CONV_PLUS_Pos ) +#define ADC_SMPR3_CONV_PLUS_1 ( 0x2UL << ADC_SMPR3_CONV_PLUS_Pos ) + +#define ADC_SMPR3_SMP20_Pos ( 16U ) +#define ADC_SMPR3_SMP20_Msk ( 0xfUL << ADC_SMPR3_SMP20_Pos ) +#define ADC_SMPR3_SMP20 ( ADC_SMPR3_SMP20_Msk ) +#define ADC_SMPR3_SMP20_0 ( 0x1UL << ADC_SMPR3_SMP20_Pos ) +#define ADC_SMPR3_SMP20_1 ( 0x2UL << ADC_SMPR3_SMP20_Pos ) +#define ADC_SMPR3_SMP20_2 ( 0x4UL << ADC_SMPR3_SMP20_Pos ) +#define ADC_SMPR3_SMP20_3 ( 0x8UL << ADC_SMPR3_SMP20_Pos ) + +#define ADC_SMPR3_SMP19_Pos ( 12U ) +#define ADC_SMPR3_SMP19_Msk ( 0xfUL << ADC_SMPR3_SMP19_Pos ) +#define ADC_SMPR3_SMP19 ( ADC_SMPR3_SMP19_Msk ) +#define ADC_SMPR3_SMP19_0 ( 0x1UL << ADC_SMPR3_SMP19_Pos ) +#define ADC_SMPR3_SMP19_1 ( 0x2UL << ADC_SMPR3_SMP19_Pos ) +#define ADC_SMPR3_SMP19_2 ( 0x4UL << ADC_SMPR3_SMP19_Pos ) +#define ADC_SMPR3_SMP19_3 ( 0x8UL << ADC_SMPR3_SMP19_Pos ) + +#define ADC_SMPR3_SMP18_Pos ( 8U ) +#define ADC_SMPR3_SMP18_Msk ( 0xfUL << ADC_SMPR3_SMP18_Pos ) +#define ADC_SMPR3_SMP18 ( ADC_SMPR3_SMP18_Msk ) +#define ADC_SMPR3_SMP18_0 ( 0x1UL << ADC_SMPR3_SMP18_Pos ) +#define ADC_SMPR3_SMP18_1 ( 0x2UL << ADC_SMPR3_SMP18_Pos ) +#define ADC_SMPR3_SMP18_2 ( 0x4UL << ADC_SMPR3_SMP18_Pos ) +#define ADC_SMPR3_SMP18_3 ( 0x8UL << ADC_SMPR3_SMP18_Pos ) + +#define ADC_SMPR3_SMP17_Pos ( 4U ) +#define ADC_SMPR3_SMP17_Msk ( 0xfUL << ADC_SMPR3_SMP17_Pos ) +#define ADC_SMPR3_SMP17 ( ADC_SMPR3_SMP17_Msk ) +#define ADC_SMPR3_SMP17_0 ( 0x1UL << ADC_SMPR3_SMP17_Pos ) +#define ADC_SMPR3_SMP17_1 ( 0x2UL << ADC_SMPR3_SMP17_Pos ) +#define ADC_SMPR3_SMP17_2 ( 0x4UL << ADC_SMPR3_SMP17_Pos ) +#define ADC_SMPR3_SMP17_3 ( 0x8UL << ADC_SMPR3_SMP17_Pos ) + +#define ADC_SMPR3_SMP16_Pos ( 0U ) +#define ADC_SMPR3_SMP16_Msk ( 0xfUL << ADC_SMPR3_SMP16_Pos ) +#define ADC_SMPR3_SMP16 ( ADC_SMPR3_SMP16_Msk ) +#define ADC_SMPR3_SMP16_0 ( 0x1UL << ADC_SMPR3_SMP16_Pos ) +#define ADC_SMPR3_SMP16_1 ( 0x2UL << ADC_SMPR3_SMP16_Pos ) +#define ADC_SMPR3_SMP16_2 ( 0x4UL << ADC_SMPR3_SMP16_Pos ) +#define ADC_SMPR3_SMP16_3 ( 0x8UL << ADC_SMPR3_SMP16_Pos ) + + +/*************** Bits definition for ADC_HTR **********************/ + +#define ADC_HTR_HT_Pos ( 0U ) +#define ADC_HTR_HT_Msk ( 0xfffUL << ADC_HTR_HT_Pos ) +#define ADC_HTR_HT ( ADC_HTR_HT_Msk ) + + +/*************** Bits definition for ADC_LTR **********************/ + +#define ADC_LTR_LT_Pos ( 0U ) +#define ADC_LTR_LT_Msk ( 0xfffUL << ADC_LTR_LT_Pos ) +#define ADC_LTR_LT ( ADC_LTR_LT_Msk ) + + +/*************** Bits definition for ADC_SQR1 **********************/ + +#define ADC_SQR1_SQ5_Pos ( 25U ) +#define ADC_SQR1_SQ5_Msk ( 0x1fUL << ADC_SQR1_SQ5_Pos ) +#define ADC_SQR1_SQ5 ( ADC_SQR1_SQ5_Msk ) +#define ADC_SQR1_SQ5_0 ( 0x1UL << ADC_SQR1_SQ5_Pos ) +#define ADC_SQR1_SQ5_1 ( 0x2UL << ADC_SQR1_SQ5_Pos ) +#define ADC_SQR1_SQ5_2 ( 0x4UL << ADC_SQR1_SQ5_Pos ) +#define ADC_SQR1_SQ5_3 ( 0x8UL << ADC_SQR1_SQ5_Pos ) +#define ADC_SQR1_SQ5_4 ( 0x10UL << ADC_SQR1_SQ5_Pos ) + +#define ADC_SQR1_SQ4_Pos ( 20U ) +#define ADC_SQR1_SQ4_Msk ( 0x1fUL << ADC_SQR1_SQ4_Pos ) +#define ADC_SQR1_SQ4 ( ADC_SQR1_SQ4_Msk ) +#define ADC_SQR1_SQ4_0 ( 0x1UL << ADC_SQR1_SQ4_Pos ) +#define ADC_SQR1_SQ4_1 ( 0x2UL << ADC_SQR1_SQ4_Pos ) +#define ADC_SQR1_SQ4_2 ( 0x4UL << ADC_SQR1_SQ4_Pos ) +#define ADC_SQR1_SQ4_3 ( 0x8UL << ADC_SQR1_SQ4_Pos ) +#define ADC_SQR1_SQ4_4 ( 0x10UL << ADC_SQR1_SQ4_Pos ) + +#define ADC_SQR1_SQ3_Pos ( 15U ) +#define ADC_SQR1_SQ3_Msk ( 0x1fUL << ADC_SQR1_SQ3_Pos ) +#define ADC_SQR1_SQ3 ( ADC_SQR1_SQ3_Msk ) +#define ADC_SQR1_SQ3_0 ( 0x1UL << ADC_SQR1_SQ3_Pos ) +#define ADC_SQR1_SQ3_1 ( 0x2UL << ADC_SQR1_SQ3_Pos ) +#define ADC_SQR1_SQ3_2 ( 0x4UL << ADC_SQR1_SQ3_Pos ) +#define ADC_SQR1_SQ3_3 ( 0x8UL << ADC_SQR1_SQ3_Pos ) +#define ADC_SQR1_SQ3_4 ( 0x10UL << ADC_SQR1_SQ3_Pos ) + +#define ADC_SQR1_SQ2_Pos ( 10U ) +#define ADC_SQR1_SQ2_Msk ( 0x1fUL << ADC_SQR1_SQ2_Pos ) +#define ADC_SQR1_SQ2 ( ADC_SQR1_SQ2_Msk ) +#define ADC_SQR1_SQ2_0 ( 0x1UL << ADC_SQR1_SQ2_Pos ) +#define ADC_SQR1_SQ2_1 ( 0x2UL << ADC_SQR1_SQ2_Pos ) +#define ADC_SQR1_SQ2_2 ( 0x4UL << ADC_SQR1_SQ2_Pos ) +#define ADC_SQR1_SQ2_3 ( 0x8UL << ADC_SQR1_SQ2_Pos ) +#define ADC_SQR1_SQ2_4 ( 0x10UL << ADC_SQR1_SQ2_Pos ) + +#define ADC_SQR1_SQ1_Pos ( 5U ) +#define ADC_SQR1_SQ1_Msk ( 0x1fUL << ADC_SQR1_SQ1_Pos ) +#define ADC_SQR1_SQ1 ( ADC_SQR1_SQ1_Msk ) +#define ADC_SQR1_SQ1_0 ( 0x1UL << ADC_SQR1_SQ1_Pos ) +#define ADC_SQR1_SQ1_1 ( 0x2UL << ADC_SQR1_SQ1_Pos ) +#define ADC_SQR1_SQ1_2 ( 0x4UL << ADC_SQR1_SQ1_Pos ) +#define ADC_SQR1_SQ1_3 ( 0x8UL << ADC_SQR1_SQ1_Pos ) +#define ADC_SQR1_SQ1_4 ( 0x10UL << ADC_SQR1_SQ1_Pos ) + +#define ADC_SQR1_L_Pos ( 0U ) +#define ADC_SQR1_L_Msk ( 0xfUL << ADC_SQR1_L_Pos ) +#define ADC_SQR1_L ( ADC_SQR1_L_Msk ) +#define ADC_SQR1_L_0 ( 0x1UL << ADC_SQR1_L_Pos ) +#define ADC_SQR1_L_1 ( 0x2UL << ADC_SQR1_L_Pos ) +#define ADC_SQR1_L_2 ( 0x4UL << ADC_SQR1_L_Pos ) +#define ADC_SQR1_L_3 ( 0x8UL << ADC_SQR1_L_Pos ) + + +/*************** Bits definition for ADC_SQR2 **********************/ + +#define ADC_SQR2_SQ11_Pos ( 25U ) +#define ADC_SQR2_SQ11_Msk ( 0x1fUL << ADC_SQR2_SQ11_Pos ) +#define ADC_SQR2_SQ11 ( ADC_SQR2_SQ11_Msk ) +#define ADC_SQR2_SQ11_0 ( 0x1UL << ADC_SQR2_SQ11_Pos ) +#define ADC_SQR2_SQ11_1 ( 0x2UL << ADC_SQR2_SQ11_Pos ) +#define ADC_SQR2_SQ11_2 ( 0x4UL << ADC_SQR2_SQ11_Pos ) +#define ADC_SQR2_SQ11_3 ( 0x8UL << ADC_SQR2_SQ11_Pos ) +#define ADC_SQR2_SQ11_4 ( 0x10UL << ADC_SQR2_SQ11_Pos ) + +#define ADC_SQR2_SQ10_Pos ( 20U ) +#define ADC_SQR2_SQ10_Msk ( 0x1fUL << ADC_SQR2_SQ10_Pos ) +#define ADC_SQR2_SQ10 ( ADC_SQR2_SQ10_Msk ) +#define ADC_SQR2_SQ10_0 ( 0x1UL << ADC_SQR2_SQ10_Pos ) +#define ADC_SQR2_SQ10_1 ( 0x2UL << ADC_SQR2_SQ10_Pos ) +#define ADC_SQR2_SQ10_2 ( 0x4UL << ADC_SQR2_SQ10_Pos ) +#define ADC_SQR2_SQ10_3 ( 0x8UL << ADC_SQR2_SQ10_Pos ) +#define ADC_SQR2_SQ10_4 ( 0x10UL << ADC_SQR2_SQ10_Pos ) + +#define ADC_SQR2_SQ9_Pos ( 15U ) +#define ADC_SQR2_SQ9_Msk ( 0x1fUL << ADC_SQR2_SQ9_Pos ) +#define ADC_SQR2_SQ9 ( ADC_SQR2_SQ9_Msk ) +#define ADC_SQR2_SQ9_0 ( 0x1UL << ADC_SQR2_SQ9_Pos ) +#define ADC_SQR2_SQ9_1 ( 0x2UL << ADC_SQR2_SQ9_Pos ) +#define ADC_SQR2_SQ9_2 ( 0x4UL << ADC_SQR2_SQ9_Pos ) +#define ADC_SQR2_SQ9_3 ( 0x8UL << ADC_SQR2_SQ9_Pos ) +#define ADC_SQR2_SQ9_4 ( 0x10UL << ADC_SQR2_SQ9_Pos ) + +#define ADC_SQR2_SQ8_Pos ( 10U ) +#define ADC_SQR2_SQ8_Msk ( 0x1fUL << ADC_SQR2_SQ8_Pos ) +#define ADC_SQR2_SQ8 ( ADC_SQR2_SQ8_Msk ) +#define ADC_SQR2_SQ8_0 ( 0x1UL << ADC_SQR2_SQ8_Pos ) +#define ADC_SQR2_SQ8_1 ( 0x2UL << ADC_SQR2_SQ8_Pos ) +#define ADC_SQR2_SQ8_2 ( 0x4UL << ADC_SQR2_SQ8_Pos ) +#define ADC_SQR2_SQ8_3 ( 0x8UL << ADC_SQR2_SQ8_Pos ) +#define ADC_SQR2_SQ8_4 ( 0x10UL << ADC_SQR2_SQ8_Pos ) + +#define ADC_SQR2_SQ7_Pos ( 5U ) +#define ADC_SQR2_SQ7_Msk ( 0x1fUL << ADC_SQR2_SQ7_Pos ) +#define ADC_SQR2_SQ7 ( ADC_SQR2_SQ7_Msk ) +#define ADC_SQR2_SQ7_0 ( 0x1UL << ADC_SQR2_SQ7_Pos ) +#define ADC_SQR2_SQ7_1 ( 0x2UL << ADC_SQR2_SQ7_Pos ) +#define ADC_SQR2_SQ7_2 ( 0x4UL << ADC_SQR2_SQ7_Pos ) +#define ADC_SQR2_SQ7_3 ( 0x8UL << ADC_SQR2_SQ7_Pos ) +#define ADC_SQR2_SQ7_4 ( 0x10UL << ADC_SQR2_SQ7_Pos ) + +#define ADC_SQR2_SQ6_Pos ( 0U ) +#define ADC_SQR2_SQ6_Msk ( 0x1fUL << ADC_SQR2_SQ6_Pos ) +#define ADC_SQR2_SQ6 ( ADC_SQR2_SQ6_Msk ) +#define ADC_SQR2_SQ6_0 ( 0x1UL << ADC_SQR2_SQ6_Pos ) +#define ADC_SQR2_SQ6_1 ( 0x2UL << ADC_SQR2_SQ6_Pos ) +#define ADC_SQR2_SQ6_2 ( 0x4UL << ADC_SQR2_SQ6_Pos ) +#define ADC_SQR2_SQ6_3 ( 0x8UL << ADC_SQR2_SQ6_Pos ) +#define ADC_SQR2_SQ6_4 ( 0x10UL << ADC_SQR2_SQ6_Pos ) + + +/*************** Bits definition for ADC_SQR3 **********************/ + +#define ADC_SQR3_SQ16_Pos ( 20U ) +#define ADC_SQR3_SQ16_Msk ( 0x1fUL << ADC_SQR3_SQ16_Pos ) +#define ADC_SQR3_SQ16 ( ADC_SQR3_SQ16_Msk ) +#define ADC_SQR3_SQ16_0 ( 0x1UL << ADC_SQR3_SQ16_Pos ) +#define ADC_SQR3_SQ16_1 ( 0x2UL << ADC_SQR3_SQ16_Pos ) +#define ADC_SQR3_SQ16_2 ( 0x4UL << ADC_SQR3_SQ16_Pos ) +#define ADC_SQR3_SQ16_3 ( 0x8UL << ADC_SQR3_SQ16_Pos ) +#define ADC_SQR3_SQ16_4 ( 0x10UL << ADC_SQR3_SQ16_Pos ) + +#define ADC_SQR3_SQ15_Pos ( 15U ) +#define ADC_SQR3_SQ15_Msk ( 0x1fUL << ADC_SQR3_SQ15_Pos ) +#define ADC_SQR3_SQ15 ( ADC_SQR3_SQ15_Msk ) +#define ADC_SQR3_SQ15_0 ( 0x1UL << ADC_SQR3_SQ15_Pos ) +#define ADC_SQR3_SQ15_1 ( 0x2UL << ADC_SQR3_SQ15_Pos ) +#define ADC_SQR3_SQ15_2 ( 0x4UL << ADC_SQR3_SQ15_Pos ) +#define ADC_SQR3_SQ15_3 ( 0x8UL << ADC_SQR3_SQ15_Pos ) +#define ADC_SQR3_SQ15_4 ( 0x10UL << ADC_SQR3_SQ15_Pos ) + +#define ADC_SQR3_SQ14_Pos ( 10U ) +#define ADC_SQR3_SQ14_Msk ( 0x1fUL << ADC_SQR3_SQ14_Pos ) +#define ADC_SQR3_SQ14 ( ADC_SQR3_SQ14_Msk ) +#define ADC_SQR3_SQ14_0 ( 0x1UL << ADC_SQR3_SQ14_Pos ) +#define ADC_SQR3_SQ14_1 ( 0x2UL << ADC_SQR3_SQ14_Pos ) +#define ADC_SQR3_SQ14_2 ( 0x4UL << ADC_SQR3_SQ14_Pos ) +#define ADC_SQR3_SQ14_3 ( 0x8UL << ADC_SQR3_SQ14_Pos ) +#define ADC_SQR3_SQ14_4 ( 0x10UL << ADC_SQR3_SQ14_Pos ) + +#define ADC_SQR3_SQ13_Pos ( 5U ) +#define ADC_SQR3_SQ13_Msk ( 0x1fUL << ADC_SQR3_SQ13_Pos ) +#define ADC_SQR3_SQ13 ( ADC_SQR3_SQ13_Msk ) +#define ADC_SQR3_SQ13_0 ( 0x1UL << ADC_SQR3_SQ13_Pos ) +#define ADC_SQR3_SQ13_1 ( 0x2UL << ADC_SQR3_SQ13_Pos ) +#define ADC_SQR3_SQ13_2 ( 0x4UL << ADC_SQR3_SQ13_Pos ) +#define ADC_SQR3_SQ13_3 ( 0x8UL << ADC_SQR3_SQ13_Pos ) +#define ADC_SQR3_SQ13_4 ( 0x10UL << ADC_SQR3_SQ13_Pos ) + +#define ADC_SQR3_SQ12_Pos ( 0U ) +#define ADC_SQR3_SQ12_Msk ( 0x1fUL << ADC_SQR3_SQ12_Pos ) +#define ADC_SQR3_SQ12 ( ADC_SQR3_SQ12_Msk ) +#define ADC_SQR3_SQ12_0 ( 0x1UL << ADC_SQR3_SQ12_Pos ) +#define ADC_SQR3_SQ12_1 ( 0x2UL << ADC_SQR3_SQ12_Pos ) +#define ADC_SQR3_SQ12_2 ( 0x4UL << ADC_SQR3_SQ12_Pos ) +#define ADC_SQR3_SQ12_3 ( 0x8UL << ADC_SQR3_SQ12_Pos ) +#define ADC_SQR3_SQ12_4 ( 0x10UL << ADC_SQR3_SQ12_Pos ) + + +/*************** Bits definition for ADC_JSQR **********************/ + +#define ADC_JSQR_JEXTSEL_Pos ( 27U ) +#define ADC_JSQR_JEXTSEL_Msk ( 0x1fUL << ADC_JSQR_JEXTSEL_Pos ) +#define ADC_JSQR_JEXTSEL ( ADC_JSQR_JEXTSEL_Msk ) +#define ADC_JSQR_JEXTSEL_0 ( 0x1UL << ADC_JSQR_JEXTSEL_Pos ) +#define ADC_JSQR_JEXTSEL_1 ( 0x2UL << ADC_JSQR_JEXTSEL_Pos ) +#define ADC_JSQR_JEXTSEL_2 ( 0x4UL << ADC_JSQR_JEXTSEL_Pos ) +#define ADC_JSQR_JEXTSEL_3 ( 0x8UL << ADC_JSQR_JEXTSEL_Pos ) +#define ADC_JSQR_JEXTSEL_4 ( 0x10UL << ADC_JSQR_JEXTSEL_Pos ) + +#define ADC_JSQR_JEXTEN_Pos ( 25U ) +#define ADC_JSQR_JEXTEN_Msk ( 0x3UL << ADC_JSQR_JEXTEN_Pos ) +#define ADC_JSQR_JEXTEN ( ADC_JSQR_JEXTEN_Msk ) +#define ADC_JSQR_JEXTEN_0 ( 0x1UL << ADC_JSQR_JEXTEN_Pos ) +#define ADC_JSQR_JEXTEN_1 ( 0x2UL << ADC_JSQR_JEXTEN_Pos ) + +#define ADC_JSQR_JSQ4_Pos ( 20U ) +#define ADC_JSQR_JSQ4_Msk ( 0x1fUL << ADC_JSQR_JSQ4_Pos ) +#define ADC_JSQR_JSQ4 ( ADC_JSQR_JSQ4_Msk ) +#define ADC_JSQR_JSQ4_0 ( 0x1UL << ADC_JSQR_JSQ4_Pos ) +#define ADC_JSQR_JSQ4_1 ( 0x2UL << ADC_JSQR_JSQ4_Pos ) +#define ADC_JSQR_JSQ4_2 ( 0x4UL << ADC_JSQR_JSQ4_Pos ) +#define ADC_JSQR_JSQ4_3 ( 0x8UL << ADC_JSQR_JSQ4_Pos ) +#define ADC_JSQR_JSQ4_4 ( 0x10UL << ADC_JSQR_JSQ4_Pos ) + +#define ADC_JSQR_JSQ3_Pos ( 15U ) +#define ADC_JSQR_JSQ3_Msk ( 0x1fUL << ADC_JSQR_JSQ3_Pos ) +#define ADC_JSQR_JSQ3 ( ADC_JSQR_JSQ3_Msk ) +#define ADC_JSQR_JSQ3_0 ( 0x1UL << ADC_JSQR_JSQ3_Pos ) +#define ADC_JSQR_JSQ3_1 ( 0x2UL << ADC_JSQR_JSQ3_Pos ) +#define ADC_JSQR_JSQ3_2 ( 0x4UL << ADC_JSQR_JSQ3_Pos ) +#define ADC_JSQR_JSQ3_3 ( 0x8UL << ADC_JSQR_JSQ3_Pos ) +#define ADC_JSQR_JSQ3_4 ( 0x10UL << ADC_JSQR_JSQ3_Pos ) + +#define ADC_JSQR_JSQ2_Pos ( 10U ) +#define ADC_JSQR_JSQ2_Msk ( 0x1fUL << ADC_JSQR_JSQ2_Pos ) +#define ADC_JSQR_JSQ2 ( ADC_JSQR_JSQ2_Msk ) +#define ADC_JSQR_JSQ2_0 ( 0x1UL << ADC_JSQR_JSQ2_Pos ) +#define ADC_JSQR_JSQ2_1 ( 0x2UL << ADC_JSQR_JSQ2_Pos ) +#define ADC_JSQR_JSQ2_2 ( 0x4UL << ADC_JSQR_JSQ2_Pos ) +#define ADC_JSQR_JSQ2_3 ( 0x8UL << ADC_JSQR_JSQ2_Pos ) +#define ADC_JSQR_JSQ2_4 ( 0x10UL << ADC_JSQR_JSQ2_Pos ) + +#define ADC_JSQR_JSQ1_Pos ( 5U ) +#define ADC_JSQR_JSQ1_Msk ( 0x1fUL << ADC_JSQR_JSQ1_Pos ) +#define ADC_JSQR_JSQ1 ( ADC_JSQR_JSQ1_Msk ) +#define ADC_JSQR_JSQ1_0 ( 0x1UL << ADC_JSQR_JSQ1_Pos ) +#define ADC_JSQR_JSQ1_1 ( 0x2UL << ADC_JSQR_JSQ1_Pos ) +#define ADC_JSQR_JSQ1_2 ( 0x4UL << ADC_JSQR_JSQ1_Pos ) +#define ADC_JSQR_JSQ1_3 ( 0x8UL << ADC_JSQR_JSQ1_Pos ) +#define ADC_JSQR_JSQ1_4 ( 0x10UL << ADC_JSQR_JSQ1_Pos ) + +#define ADC_JSQR_JL_Pos ( 0U ) +#define ADC_JSQR_JL_Msk ( 0x3UL << ADC_JSQR_JL_Pos ) +#define ADC_JSQR_JL ( ADC_JSQR_JL_Msk ) +#define ADC_JSQR_JL_0 ( 0x1UL << ADC_JSQR_JL_Pos ) +#define ADC_JSQR_JL_1 ( 0x2UL << ADC_JSQR_JL_Pos ) + + +/*************** Bits definition for ADC_JDRx **********************/ + +#define ADC_JDRX_JCH_Pos ( 16U ) +#define ADC_JDRX_JCH_Msk ( 0x1fUL << ADC_JDRX_JCH_Pos ) +#define ADC_JDRX_JCH ( ADC_JDRX_JCH_Msk ) +#define ADC_JDRX_JCH_0 ( 0x1UL << ADC_JDRX_JCH_Pos ) +#define ADC_JDRX_JCH_1 ( 0x2UL << ADC_JDRX_JCH_Pos ) +#define ADC_JDRX_JCH_2 ( 0x4UL << ADC_JDRX_JCH_Pos ) +#define ADC_JDRX_JCH_3 ( 0x8UL << ADC_JDRX_JCH_Pos ) +#define ADC_JDRX_JCH_4 ( 0x10UL << ADC_JDRX_JCH_Pos ) + +#define ADC_JDRX_JDATA_Pos ( 0U ) +#define ADC_JDRX_JDATA_Msk ( 0xffffUL << ADC_JDRX_JDATA_Pos ) +#define ADC_JDRX_JDATA ( ADC_JDRX_JDATA_Msk ) + + +/*************** Bits definition for ADC_DR **********************/ + +#define ADC_DR_CH_Pos ( 16U ) +#define ADC_DR_CH_Msk ( 0x1fUL << ADC_DR_CH_Pos ) +#define ADC_DR_CH ( ADC_DR_CH_Msk ) +#define ADC_DR_CH_0 ( 0x1UL << ADC_DR_CH_Pos ) +#define ADC_DR_CH_1 ( 0x2UL << ADC_DR_CH_Pos ) +#define ADC_DR_CH_2 ( 0x4UL << ADC_DR_CH_Pos ) +#define ADC_DR_CH_3 ( 0x8UL << ADC_DR_CH_Pos ) +#define ADC_DR_CH_4 ( 0x10UL << ADC_DR_CH_Pos ) + +#define ADC_DR_DATA_Pos ( 0U ) +#define ADC_DR_DATA_Msk ( 0xffffUL << ADC_DR_DATA_Pos ) +#define ADC_DR_DATA ( ADC_DR_DATA_Msk ) + + +/*************** Bits definition for ADC_DIFSEL **********************/ + +#define ADC_DIFSEL_DIFSEL_Pos ( 0U ) +#define ADC_DIFSEL_DIFSEL_Msk ( 0x7ffffUL << ADC_DIFSEL_DIFSEL_Pos ) +#define ADC_DIFSEL_DIFSEL ( ADC_DIFSEL_DIFSEL_Msk ) + + +/*************** Bits definition for ADC_OFRx **********************/ + +#define ADC_OFRX_OFFSETY_EN_Pos ( 31U ) +#define ADC_OFRX_OFFSETY_EN_Msk ( 0x1UL << ADC_OFRX_OFFSETY_EN_Pos ) +#define ADC_OFRX_OFFSETY_EN ( ADC_OFRX_OFFSETY_EN_Msk ) + +#define ADC_OFRX_OFFSETY_CH_Pos ( 26U ) +#define ADC_OFRX_OFFSETY_CH_Msk ( 0x1fUL << ADC_OFRX_OFFSETY_CH_Pos ) +#define ADC_OFRX_OFFSETY_CH ( ADC_OFRX_OFFSETY_CH_Msk ) +#define ADC_OFRX_OFFSETY_CH_0 ( 0x1UL << ADC_OFRX_OFFSETY_CH_Pos ) +#define ADC_OFRX_OFFSETY_CH_1 ( 0x2UL << ADC_OFRX_OFFSETY_CH_Pos ) +#define ADC_OFRX_OFFSETY_CH_2 ( 0x4UL << ADC_OFRX_OFFSETY_CH_Pos ) +#define ADC_OFRX_OFFSETY_CH_3 ( 0x8UL << ADC_OFRX_OFFSETY_CH_Pos ) +#define ADC_OFRX_OFFSETY_CH_4 ( 0x10UL << ADC_OFRX_OFFSETY_CH_Pos ) + +#define ADC_OFRX_OFFSETY_SAT_Pos ( 25U ) +#define ADC_OFRX_OFFSETY_SAT_Msk ( 0x1UL << ADC_OFRX_OFFSETY_SAT_Pos ) +#define ADC_OFRX_OFFSETY_SAT ( ADC_OFRX_OFFSETY_SAT_Msk ) + +#define ADC_OFRX_OFFSETY_POS_Pos ( 24U ) +#define ADC_OFRX_OFFSETY_POS_Msk ( 0x1UL << ADC_OFRX_OFFSETY_POS_Pos ) +#define ADC_OFRX_OFFSETY_POS ( ADC_OFRX_OFFSETY_POS_Msk ) + +#define ADC_OFRX_OFFSETY_Pos ( 0U ) +#define ADC_OFRX_OFFSETY_Msk ( 0xfffUL << ADC_OFRX_OFFSETY_Pos ) +#define ADC_OFRX_OFFSETY ( ADC_OFRX_OFFSETY_Msk ) + + +/*************** Bits definition for ADC_CALFACT **********************/ + +#define ADC_CALFACT_CALFACT_D_Pos ( 16U ) +#define ADC_CALFACT_CALFACT_D_Msk ( 0x7fUL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D ( ADC_CALFACT_CALFACT_D_Msk ) +#define ADC_CALFACT_CALFACT_D_0 ( 0x1UL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D_1 ( 0x2UL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D_2 ( 0x4UL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D_3 ( 0x8UL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D_4 ( 0x10UL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D_5 ( 0x20UL << ADC_CALFACT_CALFACT_D_Pos ) +#define ADC_CALFACT_CALFACT_D_6 ( 0x40UL << ADC_CALFACT_CALFACT_D_Pos ) + +#define ADC_CALFACT_CALFACT_S_Pos ( 0U ) +#define ADC_CALFACT_CALFACT_S_Msk ( 0x7fUL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S ( ADC_CALFACT_CALFACT_S_Msk ) +#define ADC_CALFACT_CALFACT_S_0 ( 0x1UL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S_1 ( 0x2UL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S_2 ( 0x4UL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S_3 ( 0x8UL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S_4 ( 0x10UL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S_5 ( 0x20UL << ADC_CALFACT_CALFACT_S_Pos ) +#define ADC_CALFACT_CALFACT_S_6 ( 0x40UL << ADC_CALFACT_CALFACT_S_Pos ) + + +/*************** Bits definition for ADC_CSR **********************/ + +#define ADC_CSR_AWD_SLV_Pos ( 23U ) +#define ADC_CSR_AWD_SLV_Msk ( 0x1UL << ADC_CSR_AWD_SLV_Pos ) +#define ADC_CSR_AWD_SLV ( ADC_CSR_AWD_SLV_Msk ) + +#define ADC_CSR_JEOG_SLV_Pos ( 22U ) +#define ADC_CSR_JEOG_SLV_Msk ( 0x1UL << ADC_CSR_JEOG_SLV_Pos ) +#define ADC_CSR_JEOG_SLV ( ADC_CSR_JEOG_SLV_Msk ) + +#define ADC_CSR_JEOC_SLV_Pos ( 21U ) +#define ADC_CSR_JEOC_SLV_Msk ( 0x1UL << ADC_CSR_JEOC_SLV_Pos ) +#define ADC_CSR_JEOC_SLV ( ADC_CSR_JEOC_SLV_Msk ) + +#define ADC_CSR_OVERF_SLV_Pos ( 20U ) +#define ADC_CSR_OVERF_SLV_Msk ( 0x1UL << ADC_CSR_OVERF_SLV_Pos ) +#define ADC_CSR_OVERF_SLV ( ADC_CSR_OVERF_SLV_Msk ) + +#define ADC_CSR_EOG_SLV_Pos ( 19U ) +#define ADC_CSR_EOG_SLV_Msk ( 0x1UL << ADC_CSR_EOG_SLV_Pos ) +#define ADC_CSR_EOG_SLV ( ADC_CSR_EOG_SLV_Msk ) + +#define ADC_CSR_EOC_SLV_Pos ( 18U ) +#define ADC_CSR_EOC_SLV_Msk ( 0x1UL << ADC_CSR_EOC_SLV_Pos ) +#define ADC_CSR_EOC_SLV ( ADC_CSR_EOC_SLV_Msk ) + +#define ADC_CSR_EOSMP_SLV_Pos ( 17U ) +#define ADC_CSR_EOSMP_SLV_Msk ( 0x1UL << ADC_CSR_EOSMP_SLV_Pos ) +#define ADC_CSR_EOSMP_SLV ( ADC_CSR_EOSMP_SLV_Msk ) + +#define ADC_CSR_ADRDY_SLV_Pos ( 16U ) +#define ADC_CSR_ADRDY_SLV_Msk ( 0x1UL << ADC_CSR_ADRDY_SLV_Pos ) +#define ADC_CSR_ADRDY_SLV ( ADC_CSR_ADRDY_SLV_Msk ) + +#define ADC_CSR_AWD_MST_Pos ( 7U ) +#define ADC_CSR_AWD_MST_Msk ( 0x1UL << ADC_CSR_AWD_MST_Pos ) +#define ADC_CSR_AWD_MST ( ADC_CSR_AWD_MST_Msk ) + +#define ADC_CSR_JEOG_MST_Pos ( 6U ) +#define ADC_CSR_JEOG_MST_Msk ( 0x1UL << ADC_CSR_JEOG_MST_Pos ) +#define ADC_CSR_JEOG_MST ( ADC_CSR_JEOG_MST_Msk ) + +#define ADC_CSR_JEOC_MST_Pos ( 5U ) +#define ADC_CSR_JEOC_MST_Msk ( 0x1UL << ADC_CSR_JEOC_MST_Pos ) +#define ADC_CSR_JEOC_MST ( ADC_CSR_JEOC_MST_Msk ) + +#define ADC_CSR_OVERF_MST_Pos ( 4U ) +#define ADC_CSR_OVERF_MST_Msk ( 0x1UL << ADC_CSR_OVERF_MST_Pos ) +#define ADC_CSR_OVERF_MST ( ADC_CSR_OVERF_MST_Msk ) + +#define ADC_CSR_EOG_MST_Pos ( 3U ) +#define ADC_CSR_EOG_MST_Msk ( 0x1UL << ADC_CSR_EOG_MST_Pos ) +#define ADC_CSR_EOG_MST ( ADC_CSR_EOG_MST_Msk ) + +#define ADC_CSR_EOC_MST_Pos ( 2U ) +#define ADC_CSR_EOC_MST_Msk ( 0x1UL << ADC_CSR_EOC_MST_Pos ) +#define ADC_CSR_EOC_MST ( ADC_CSR_EOC_MST_Msk ) + +#define ADC_CSR_EOSMP_MST_Pos ( 1U ) +#define ADC_CSR_EOSMP_MST_Msk ( 0x1UL << ADC_CSR_EOSMP_MST_Pos ) +#define ADC_CSR_EOSMP_MST ( ADC_CSR_EOSMP_MST_Msk ) + +#define ADC_CSR_ADRDY_MST_Pos ( 0U ) +#define ADC_CSR_ADRDY_MST_Msk ( 0x1UL << ADC_CSR_ADRDY_MST_Pos ) +#define ADC_CSR_ADRDY_MST ( ADC_CSR_ADRDY_MST_Msk ) + + +/*************** Bits definition for ADC_CCR **********************/ + +#define ADC_CCR_VBATEN_Pos ( 24U ) +#define ADC_CCR_VBATEN_Msk ( 0x01UL << ADC_CCR_VBATEN_Pos ) +#define ADC_CCR_VBATEN ( ADC_CCR_VBATEN_Msk ) + +#define ADC_CCR_VREFINTEN_Pos ( 23U ) +#define ADC_CCR_VREFINTEN_Msk ( 0x01UL << ADC_CCR_VREFINTEN_Pos ) +#define ADC_CCR_VREFINTEN ( ADC_CCR_VREFINTEN_Msk ) + +#define ADC_CCR_TSEN_Pos ( 22U ) +#define ADC_CCR_TSEN_Msk ( 0x01UL << ADC_CCR_TSEN_Pos ) +#define ADC_CCR_TSEN ( ADC_CCR_TSEN_Msk ) + +#define ADC_CCR_ADCDIV_Pos ( 16U ) +#define ADC_CCR_ADCDIV_Msk ( 0x3fUL << ADC_CCR_ADCDIV_Pos ) +#define ADC_CCR_ADCDIV ( ADC_CCR_ADCDIV_Msk ) +#define ADC_CCR_ADCDIV_0 ( 0x1UL << ADC_CCR_ADCDIV_Pos ) +#define ADC_CCR_ADCDIV_1 ( 0x2UL << ADC_CCR_ADCDIV_Pos ) +#define ADC_CCR_ADCDIV_2 ( 0x4UL << ADC_CCR_ADCDIV_Pos ) +#define ADC_CCR_ADCDIV_3 ( 0x8UL << ADC_CCR_ADCDIV_Pos ) +#define ADC_CCR_ADCDIV_4 ( 0x10UL << ADC_CCR_ADCDIV_Pos ) +#define ADC_CCR_ADCDIV_5 ( 0x20UL << ADC_CCR_ADCDIV_Pos ) + +#define ADC_CCR_DMADUAL_Pos ( 14U ) +#define ADC_CCR_DMADUAL_Msk ( 0x3UL << ADC_CCR_DMADUAL_Pos ) +#define ADC_CCR_DMADUAL ( ADC_CCR_DMADUAL_Msk ) +#define ADC_CCR_DMADUAL_0 ( 0x1UL << ADC_CCR_DMADUAL_Pos ) +#define ADC_CCR_DMADUAL_1 ( 0x2UL << ADC_CCR_DMADUAL_Pos ) + +#define ADC_CCR_CLKMODE_Pos ( 13U ) +#define ADC_CCR_CLKMODE_Msk ( 0x1UL << ADC_CCR_CLKMODE_Pos ) +#define ADC_CCR_CLKMODE ( ADC_CCR_CLKMODE_Msk ) + +#define ADC_CCR_DELAY_Pos ( 8U ) +#define ADC_CCR_DELAY_Msk ( 0xfUL << ADC_CCR_DELAY_Pos ) +#define ADC_CCR_DELAY ( ADC_CCR_DELAY_Msk ) +#define ADC_CCR_DELAY_0 ( 0x1UL << ADC_CCR_DELAY_Pos ) +#define ADC_CCR_DELAY_1 ( 0x2UL << ADC_CCR_DELAY_Pos ) +#define ADC_CCR_DELAY_2 ( 0x4UL << ADC_CCR_DELAY_Pos ) +#define ADC_CCR_DELAY_3 ( 0x8UL << ADC_CCR_DELAY_Pos ) + +#define ADC_CCR_DUALMOD_Pos ( 0U ) +#define ADC_CCR_DUALMOD_Msk ( 0x1fUL << ADC_CCR_DUALMOD_Pos ) +#define ADC_CCR_DUALMOD ( ADC_CCR_DUALMOD_Msk ) +#define ADC_CCR_DUALMOD_0 ( 0x1UL << ADC_CCR_DUALMOD_Pos ) +#define ADC_CCR_DUALMOD_1 ( 0x2UL << ADC_CCR_DUALMOD_Pos ) +#define ADC_CCR_DUALMOD_2 ( 0x4UL << ADC_CCR_DUALMOD_Pos ) +#define ADC_CCR_DUALMOD_3 ( 0x8UL << ADC_CCR_DUALMOD_Pos ) +#define ADC_CCR_DUALMOD_4 ( 0x10UL << ADC_CCR_DUALMOD_Pos ) + + +/*************** Bits definition for ADC_CDR **********************/ + +#define ADC_CDR_DATA2_Pos ( 16U ) +#define ADC_CDR_DATA2_Msk ( 0xffffUL << ADC_CDR_DATA2_Pos ) +#define ADC_CDR_DATA2 ( ADC_CDR_DATA2_Msk ) + +#define ADC_CDR_DATA1_Pos ( 0U ) +#define ADC_CDR_DATA1_Msk ( 0xffffUL << ADC_CDR_DATA1_Pos ) +#define ADC_CDR_DATA1 ( ADC_CDR_DATA1_Msk ) + + +/*************** Bits definition for ADC_CVRB **********************/ + +#define ADC_CVRB_VRBTRIM_Pos ( 4U ) +#define ADC_CVRB_VRBTRIM_Msk ( 0x1fUL << ADC_CVRB_VRBTRIM_Pos ) +#define ADC_CVRB_VRBTRIM ( ADC_CVRB_VRBTRIM_Msk ) +#define ADC_CVRB_VRBTRIM_0 ( 0x1UL << ADC_CVRB_VRBTRIM_Pos ) +#define ADC_CVRB_VRBTRIM_1 ( 0x2UL << ADC_CVRB_VRBTRIM_Pos ) +#define ADC_CVRB_VRBTRIM_2 ( 0x4UL << ADC_CVRB_VRBTRIM_Pos ) +#define ADC_CVRB_VRBTRIM_3 ( 0x8UL << ADC_CVRB_VRBTRIM_Pos ) +#define ADC_CVRB_VRBTRIM_4 ( 0x10UL << ADC_CVRB_VRBTRIM_Pos ) + +#define ADC_CVRB_VRS_Pos ( 2U ) +#define ADC_CVRB_VRS_Msk ( 0x3UL << ADC_CVRB_VRS_Pos ) +#define ADC_CVRB_VRS ( ADC_CVRB_VRS_Msk ) +#define ADC_CVRB_VRS_0 ( 0x1UL << ADC_CVRB_VRS_Pos ) +#define ADC_CVRB_VRS_1 ( 0x2UL << ADC_CVRB_VRS_Pos ) + +#define ADC_CVRB_HIZ_Pos ( 1U ) +#define ADC_CVRB_HIZ_Msk ( 0x1UL << ADC_CVRB_HIZ_Pos ) +#define ADC_CVRB_HIZ ( ADC_CVRB_HIZ_Msk ) + +#define ADC_CVRB_ENVR_Pos ( 0U ) +#define ADC_CVRB_ENVR_Msk ( 0x1UL << ADC_CVRB_ENVR_Pos ) +#define ADC_CVRB_ENVR ( ADC_CVRB_ENVR_Msk ) + + +/*************** Bits definition for DAC_CR register ***********************/ + +#define DAC_CR_CEN2_Pos ( 30U ) +#define DAC_CR_CEN2_Msk ( 0x1UL << DAC_CR_CEN2_Pos ) +#define DAC_CR_CEN2 ( DAC_CR_CEN2_Msk ) + +#define DAC_CR_DMAUDIE2_Pos ( 29U ) +#define DAC_CR_DMAUDIE2_Msk ( 0x1UL << DAC_CR_DMAUDIE2_Pos ) +#define DAC_CR_DMAUDIE2 ( DAC_CR_DMAUDIE2_Msk ) + +#define DAC_CR_DMAEN2_Pos ( 28U ) +#define DAC_CR_DMAEN2_Msk ( 0x1UL << DAC_CR_DMAEN2_Pos ) +#define DAC_CR_DMAEN2 ( DAC_CR_DMAEN2_Msk ) + +#define DAC_CR_MAMP2_Pos ( 24U ) +#define DAC_CR_MAMP2_Msk ( 0xFUL << DAC_CR_MAMP2_Pos ) +#define DAC_CR_MAMP2 ( DAC_CR_MAMP2_Msk ) +#define DAC_CR_MAMP2_0 ( 0x1UL << DAC_CR_MAMP2_Pos ) +#define DAC_CR_MAMP2_1 ( 0x2UL << DAC_CR_MAMP2_Pos ) +#define DAC_CR_MAMP2_2 ( 0x4UL << DAC_CR_MAMP2_Pos ) +#define DAC_CR_MAMP2_3 ( 0x8UL << DAC_CR_MAMP2_Pos ) + +#define DAC_CR_WAVE2_Pos ( 22U ) +#define DAC_CR_WAVE2_Msk ( 0x3UL << DAC_CR_WAVE2_Pos ) +#define DAC_CR_WAVE2 ( DAC_CR_WAVE2_Msk ) +#define DAC_CR_WAVE2_0 ( 0x1UL << DAC_CR_WAVE2_Pos ) +#define DAC_CR_WAVE2_1 ( 0x2UL << DAC_CR_WAVE2_Pos ) + +#define DAC_CR_TSEL2_Pos ( 18U ) +#define DAC_CR_TSEL2_Msk ( 0xFUL << DAC_CR_TSEL2_Pos ) +#define DAC_CR_TSEL2 ( DAC_CR_TSEL2_Msk ) +#define DAC_CR_TSEL2_0 ( 0x1UL << DAC_CR_TSEL2_Pos ) +#define DAC_CR_TSEL2_1 ( 0x2UL << DAC_CR_TSEL2_Pos ) +#define DAC_CR_TSEL2_2 ( 0x4UL << DAC_CR_TSEL2_Pos ) +#define DAC_CR_TSEL2_3 ( 0x8UL << DAC_CR_TSEL2_Pos ) + +#define DAC_CR_TEN2_Pos ( 17U ) +#define DAC_CR_TEN2_Msk ( 0x1UL << DAC_CR_TEN2_Pos ) +#define DAC_CR_TEN2 ( DAC_CR_TEN2_Msk ) + +#define DAC_CR_EN2_Pos ( 16U ) +#define DAC_CR_EN2_Msk ( 0x1UL << DAC_CR_EN2_Pos ) +#define DAC_CR_EN2 ( DAC_CR_EN2_Msk ) + +#define DAC_CR_CEN1_Pos ( 14U ) +#define DAC_CR_CEN1_Msk ( 0x1UL << DAC_CR_CEN1_Pos ) +#define DAC_CR_CEN1 ( DAC_CR_CEN1_Msk ) + +#define DAC_CR_DMAUDIE1_Pos ( 13U ) +#define DAC_CR_DMAUDIE1_Msk ( 0x1UL << DAC_CR_DMAUDIE1_Pos ) +#define DAC_CR_DMAUDIE1 ( DAC_CR_DMAUDIE1_Msk ) + +#define DAC_CR_DMAEN1_Pos ( 12U ) +#define DAC_CR_DMAEN1_Msk ( 0x1UL << DAC_CR_DMAEN1_Pos ) +#define DAC_CR_DMAEN1 ( DAC_CR_DMAEN1_Msk ) + +#define DAC_CR_MAMP1_Pos ( 8U ) +#define DAC_CR_MAMP1_Msk ( 0xFUL << DAC_CR_MAMP1_Pos ) +#define DAC_CR_MAMP1 ( DAC_CR_MAMP1_Msk ) +#define DAC_CR_MAMP1_0 ( 0x1UL << DAC_CR_MAMP1_Pos ) +#define DAC_CR_MAMP1_1 ( 0x2UL << DAC_CR_MAMP1_Pos ) +#define DAC_CR_MAMP1_2 ( 0x4UL << DAC_CR_MAMP1_Pos ) +#define DAC_CR_MAMP1_3 ( 0x8UL << DAC_CR_MAMP1_Pos ) + +#define DAC_CR_WAVE1_Pos ( 6U ) +#define DAC_CR_WAVE1_Msk ( 0x3UL << DAC_CR_WAVE1_Pos ) +#define DAC_CR_WAVE1 ( DAC_CR_WAVE1_Msk ) +#define DAC_CR_WAVE1_0 ( 0x1UL << DAC_CR_WAVE1_Pos ) +#define DAC_CR_WAVE1_1 ( 0x2UL << DAC_CR_WAVE1_Pos ) + +#define DAC_CR_TSEL1_Pos ( 2U ) +#define DAC_CR_TSEL1_Msk ( 0xFUL << DAC_CR_TSEL1_Pos ) +#define DAC_CR_TSEL1 ( DAC_CR_TSEL1_Msk ) +#define DAC_CR_TSEL1_0 ( 0x1UL << DAC_CR_TSEL1_Pos ) +#define DAC_CR_TSEL1_1 ( 0x2UL << DAC_CR_TSEL1_Pos ) +#define DAC_CR_TSEL1_2 ( 0x4UL << DAC_CR_TSEL1_Pos ) +#define DAC_CR_TSEL1_3 ( 0x8UL << DAC_CR_TSEL1_Pos ) + +#define DAC_CR_TEN1_Pos ( 1U ) +#define DAC_CR_TEN1_Msk ( 0x1UL << DAC_CR_TEN1_Pos ) +#define DAC_CR_TEN1 ( DAC_CR_TEN1_Msk ) + +#define DAC_CR_EN1_Pos ( 0U ) +#define DAC_CR_EN1_Msk ( 0x1UL << DAC_CR_EN1_Pos ) +#define DAC_CR_EN1 ( DAC_CR_EN1_Msk ) + +/*************** Bits definition for DAC_SWTRIGR register ******************/ + +#define DAC_SWTRIGR_SWTRIGB2_Pos ( 17U ) +#define DAC_SWTRIGR_SWTRIGB2_Msk ( 0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos ) +#define DAC_SWTRIGR_SWTRIGB2 ( DAC_SWTRIGR_SWTRIGB2_Msk ) + +#define DAC_SWTRIGR_SWTRIGB1_Pos ( 16U ) +#define DAC_SWTRIGR_SWTRIGB1_Msk ( 0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos ) +#define DAC_SWTRIGR_SWTRIGB1 ( DAC_SWTRIGR_SWTRIGB1_Msk ) + +#define DAC_SWTRIGR_SWTRIG2_Pos ( 1U ) +#define DAC_SWTRIGR_SWTRIG2_Msk ( 0x1UL << DAC_SWTRIGR_SWTRIG2_Pos ) +#define DAC_SWTRIGR_SWTRIG2 ( DAC_SWTRIGR_SWTRIG2_Msk ) + +#define DAC_SWTRIGR_SWTRIG1_Pos ( 0U ) +#define DAC_SWTRIGR_SWTRIG1_Msk ( 0x1UL << DAC_SWTRIGR_SWTRIG1_Pos ) +#define DAC_SWTRIGR_SWTRIG1 ( DAC_SWTRIGR_SWTRIG1_Msk ) + + +/*************** Bits definition for DAC_DHR12R1 register ******************/ + +#define DAC_DHR12R1_DACC1DHRB_Pos ( 16U ) +#define DAC_DHR12R1_DACC1DHRB_Msk ( 0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos ) +#define DAC_DHR12R1_DACC1DHRB ( DAC_DHR12R1_DACC1DHRB_Msk ) + +#define DAC_DHR12R1_DACC1DHR_Pos ( 0U ) +#define DAC_DHR12R1_DACC1DHR_Msk ( 0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos ) +#define DAC_DHR12R1_DACC1DHR ( DAC_DHR12R1_DACC1DHR_Msk ) + + +/*************** Bits definition for DAC_DHR12L1 register ******************/ + +#define DAC_DHR12L1_DACC1DHRB_Pos ( 20U ) +#define DAC_DHR12L1_DACC1DHRB_Msk ( 0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos ) +#define DAC_DHR12L1_DACC1DHRB ( DAC_DHR12L1_DACC1DHRB_Msk ) + +#define DAC_DHR12L1_DACC1DHR_Pos ( 4U ) +#define DAC_DHR12L1_DACC1DHR_Msk ( 0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos ) +#define DAC_DHR12L1_DACC1DHR ( DAC_DHR12L1_DACC1DHR_Msk ) + + +/*************** Bits definition for DAC_DHR8R1 register *******************/ + +#define DAC_DHR8R1_DACC1DHRB_Pos ( 8U ) +#define DAC_DHR8R1_DACC1DHRB_Msk ( 0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos ) +#define DAC_DHR8R1_DACC1DHRB ( DAC_DHR8R1_DACC1DHRB_Msk ) + +#define DAC_DHR8R1_DACC1DHR_Pos ( 0U ) +#define DAC_DHR8R1_DACC1DHR_Msk ( 0xFFUL << DAC_DHR8R1_DACC1DHR_Pos ) +#define DAC_DHR8R1_DACC1DHR ( DAC_DHR8R1_DACC1DHR_Msk ) + + +/*************** Bits definition for DAC_DHR12R2 register ******************/ + +#define DAC_DHR12R2_DACC2DHRB_Pos ( 16U ) +#define DAC_DHR12R2_DACC2DHRB_Msk ( 0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos ) +#define DAC_DHR12R2_DACC2DHRB ( DAC_DHR12R2_DACC2DHRB_Msk ) + +#define DAC_DHR12R2_DACC2DHR_Pos ( 0U ) +#define DAC_DHR12R2_DACC2DHR_Msk ( 0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos ) +#define DAC_DHR12R2_DACC2DHR ( DAC_DHR12R2_DACC2DHR_Msk ) + + +/*************** Bits definition for DAC_DHR12L2 register ******************/ + +#define DAC_DHR12L2_DACC2DHRB_Pos ( 20U ) +#define DAC_DHR12L2_DACC2DHRB_Msk ( 0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos ) +#define DAC_DHR12L2_DACC2DHRB ( DAC_DHR12L2_DACC2DHRB_Msk ) + +#define DAC_DHR12L2_DACC2DHR_Pos ( 4U ) +#define DAC_DHR12L2_DACC2DHR_Msk ( 0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos ) +#define DAC_DHR12L2_DACC2DHR ( DAC_DHR12L2_DACC2DHR_Msk ) + + +/*************** Bits definition for DAC_DHR8R2 register *******************/ + +#define DAC_DHR8R2_DACC2DHRB_Pos ( 8U ) +#define DAC_DHR8R2_DACC2DHRB_Msk ( 0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos ) +#define DAC_DHR8R2_DACC2DHRB ( DAC_DHR8R2_DACC2DHRB_Msk ) + +#define DAC_DHR8R2_DACC2DHR_Pos ( 0U ) +#define DAC_DHR8R2_DACC2DHR_Msk ( 0xFFUL << DAC_DHR8R2_DACC2DHR_Pos ) +#define DAC_DHR8R2_DACC2DHR ( DAC_DHR8R2_DACC2DHR_Msk ) + + +/*************** Bits definition for DAC_DHR12RD register ******************/ + +#define DAC_DHR12RD_DACC2DHR_Pos ( 16U ) +#define DAC_DHR12RD_DACC2DHR_Msk ( 0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos ) +#define DAC_DHR12RD_DACC2DHR ( DAC_DHR12RD_DACC2DHR_Msk ) + +#define DAC_DHR12RD_DACC1DHR_Pos ( 0U ) +#define DAC_DHR12RD_DACC1DHR_Msk ( 0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos ) +#define DAC_DHR12RD_DACC1DHR ( DAC_DHR12RD_DACC1DHR_Msk ) + + +/*************** Bits definition for DAC_DHR12LD register ******************/ + +#define DAC_DHR12LD_DACC2DHR_Pos ( 20U ) +#define DAC_DHR12LD_DACC2DHR_Msk ( 0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos ) +#define DAC_DHR12LD_DACC2DHR ( DAC_DHR12LD_DACC2DHR_Msk ) + +#define DAC_DHR12LD_DACC1DHR_Pos ( 4U ) +#define DAC_DHR12LD_DACC1DHR_Msk ( 0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos ) +#define DAC_DHR12LD_DACC1DHR ( DAC_DHR12LD_DACC1DHR_Msk ) + + +/*************** Bits definition for DAC_DHR8RD register *******************/ + +#define DAC_DHR8RD_DACC2DHR_Pos ( 16U ) +#define DAC_DHR8RD_DACC2DHR_Msk ( 0xFFUL << DAC_DHR8RD_DACC2DHR_Pos ) +#define DAC_DHR8RD_DACC2DHR ( DAC_DHR8RD_DACC2DHR_Msk ) + +#define DAC_DHR8RD_DACC1DHR_Pos ( 0U ) +#define DAC_DHR8RD_DACC1DHR_Msk ( 0xFFUL << DAC_DHR8RD_DACC1DHR_Pos ) +#define DAC_DHR8RD_DACC1DHR ( DAC_DHR8RD_DACC1DHR_Msk ) + + +/*************** Bits definition for DAC_DOR1 register *********************/ + +#define DAC_DOR1_DACC1DORB_Pos ( 16U ) +#define DAC_DOR1_DACC1DORB_Msk ( 0xFFFUL << DAC_DOR1_DACC1DORB_Pos ) +#define DAC_DOR1_DACC1DORB ( DAC_DOR1_DACC1DORB_Msk ) + +#define DAC_DOR1_DACC1DOR_Pos ( 0U ) +#define DAC_DOR1_DACC1DOR_Msk ( 0xFFFUL << DAC_DOR1_DACC1DOR_Pos ) +#define DAC_DOR1_DACC1DOR ( DAC_DOR1_DACC1DOR_Msk ) + + +/*************** Bits definition for DAC_DOR2 register *********************/ + +#define DAC_DOR2_DACC2DORB_Pos ( 16U ) +#define DAC_DOR2_DACC2DORB_Msk ( 0xFFFUL << DAC_DOR2_DACC2DORB_Pos ) +#define DAC_DOR2_DACC2DORB ( DAC_DOR2_DACC2DORB_Msk ) + +#define DAC_DOR2_DACC2DOR_Pos ( 0U ) +#define DAC_DOR2_DACC2DOR_Msk ( 0xFFFUL << DAC_DOR2_DACC2DOR_Pos ) +#define DAC_DOR2_DACC2DOR ( DAC_DOR2_DACC2DOR_Msk ) + + +/*************** Bits definition for DAC_SR register ***********************/ + +#define DAC_SR_CALFLAG2_Pos ( 30U ) +#define DAC_SR_CALFLAG2_Msk ( 0x1UL << DAC_SR_CALFLAG2_Pos ) +#define DAC_SR_CALFLAG2 ( DAC_SR_CALFLAG2_Msk ) + +#define DAC_SR_DMAUDR2_Pos ( 29U ) +#define DAC_SR_DMAUDR2_Msk ( 0x1UL << DAC_SR_DMAUDR2_Pos ) +#define DAC_SR_DMAUDR2 ( DAC_SR_DMAUDR2_Msk ) + +#define DAC_SR_DORSTAT2_Pos ( 28U ) +#define DAC_SR_DORSTAT2_Msk ( 0x1UL << DAC_SR_DORSTAT2_Pos ) +#define DAC_SR_DORSTAT2 ( DAC_SR_DORSTAT2_Msk ) + +#define DAC_SR_SAMOV2_Pos ( 24U ) +#define DAC_SR_SAMOV2_Msk ( 0x1UL << DAC_SR_SAMOV2_Pos ) +#define DAC_SR_SAMOV2 ( DAC_SR_SAMOV2_Msk ) + +#define DAC_SR_CALFLAG1_Pos ( 14U ) +#define DAC_SR_CALFLAG1_Msk ( 0x1UL << DAC_SR_CALFLAG1_Pos ) +#define DAC_SR_CALFLAG1 ( DAC_SR_CALFLAG1_Msk ) + +#define DAC_SR_DMAUDR1_Pos ( 13U ) +#define DAC_SR_DMAUDR1_Msk ( 0x1UL << DAC_SR_DMAUDR1_Pos ) +#define DAC_SR_DMAUDR1 ( DAC_SR_DMAUDR1_Msk ) + +#define DAC_SR_DORSTAT1_Pos ( 12U ) +#define DAC_SR_DORSTAT1_Msk ( 0x1UL << DAC_SR_DORSTAT1_Pos ) +#define DAC_SR_DORSTAT1 ( DAC_SR_DORSTAT1_Msk ) + +#define DAC_SR_SAMOV1_Pos ( 8U ) +#define DAC_SR_SAMOV1_Msk ( 0x1UL << DAC_SR_SAMOV1_Pos ) +#define DAC_SR_SAMOV1 ( DAC_SR_SAMOV1_Msk ) + + +/*************** Bits definition for DAC_CCR register **********************/ + +#define DAC_CCR_OTRIM2_Pos ( 16U ) +#define DAC_CCR_OTRIM2_Msk ( 0x1FUL << DAC_CCR_OTRIM2_Pos ) +#define DAC_CCR_OTRIM2 ( DAC_CCR_OTRIM2_Msk ) +#define DAC_CCR_OTRIM2_0 ( 0x1UL << DAC_CCR_OTRIM2_Pos ) +#define DAC_CCR_OTRIM2_1 ( 0x2UL << DAC_CCR_OTRIM2_Pos ) +#define DAC_CCR_OTRIM2_2 ( 0x4UL << DAC_CCR_OTRIM2_Pos ) +#define DAC_CCR_OTRIM2_3 ( 0x8UL << DAC_CCR_OTRIM2_Pos ) +#define DAC_CCR_OTRIM2_4 ( 0x10UL << DAC_CCR_OTRIM2_Pos ) + +#define DAC_CCR_OTRIM1_Pos ( 0U ) +#define DAC_CCR_OTRIM1_Msk ( 0x1FUL << DAC_CCR_OTRIM1_Pos ) +#define DAC_CCR_OTRIM1 ( DAC_CCR_OTRIM1_Msk ) +#define DAC_CCR_OTRIM1_0 ( 0x1UL << DAC_CCR_OTRIM1_Pos ) +#define DAC_CCR_OTRIM1_1 ( 0x2UL << DAC_CCR_OTRIM1_Pos ) +#define DAC_CCR_OTRIM1_2 ( 0x4UL << DAC_CCR_OTRIM1_Pos ) +#define DAC_CCR_OTRIM1_3 ( 0x8UL << DAC_CCR_OTRIM1_Pos ) +#define DAC_CCR_OTRIM1_4 ( 0x10UL << DAC_CCR_OTRIM1_Pos ) + + +/*************** Bits definition for DAC_MCR register **********************/ + +#define DAC_MCR_SINFORMAT2_Pos ( 25U ) +#define DAC_MCR_SINFORMAT2_Msk ( 0x1UL << DAC_MCR_SINFORMAT2_Pos ) +#define DAC_MCR_SINFORMAT2 ( DAC_MCR_SINFORMAT2_Msk ) + +#define DAC_MCR_DMADOUBLE2_Pos ( 24U ) +#define DAC_MCR_DMADOUBLE2_Msk ( 0x1UL << DAC_MCR_DMADOUBLE2_Pos ) +#define DAC_MCR_DMADOUBLE2 ( DAC_MCR_DMADOUBLE2_Msk ) + +#define DAC_MCR_MODE2_Pos ( 16U ) +#define DAC_MCR_MODE2_Msk ( 0x7UL << DAC_MCR_MODE2_Pos ) +#define DAC_MCR_MODE2 ( DAC_MCR_MODE2_Msk ) +#define DAC_MCR_MODE2_0 ( 0x1UL << DAC_MCR_MODE2_Pos ) +#define DAC_MCR_MODE2_1 ( 0x2UL << DAC_MCR_MODE2_Pos ) +#define DAC_MCR_MODE2_2 ( 0x4UL << DAC_MCR_MODE2_Pos ) + +#define DAC_MCR_SINFORMAT1_Pos ( 9U ) +#define DAC_MCR_SINFORMAT1_Msk ( 0x1UL << DAC_MCR_SINFORMAT1_Pos ) +#define DAC_MCR_SINFORMAT1 ( DAC_MCR_SINFORMAT1_Msk ) + +#define DAC_MCR_DMADOUBLE1_Pos ( 8U ) +#define DAC_MCR_DMADOUBLE1_Msk ( 0x1UL << DAC_MCR_DMADOUBLE1_Pos ) +#define DAC_MCR_DMADOUBLE1 ( DAC_MCR_DMADOUBLE1_Msk ) + +#define DAC_MCR_MODE1_Pos ( 0U ) +#define DAC_MCR_MODE1_Msk ( 0x7UL << DAC_MCR_MODE1_Pos ) +#define DAC_MCR_MODE1 ( DAC_MCR_MODE1_Msk ) +#define DAC_MCR_MODE1_0 ( 0x1UL << DAC_MCR_MODE1_Pos ) +#define DAC_MCR_MODE1_1 ( 0x2UL << DAC_MCR_MODE1_Pos ) +#define DAC_MCR_MODE1_2 ( 0x4UL << DAC_MCR_MODE1_Pos ) + + +/*************** Bits definition for DAC_SHSR1 register ********************/ + +#define DAC_SHSR1_TSAMPLE1_Pos ( 0U ) +#define DAC_SHSR1_TSAMPLE1_Msk ( 0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos ) +#define DAC_SHSR1_TSAMPLE1 ( DAC_SHSR1_TSAMPLE1_Msk ) + + +/*************** Bits definition for DAC_SHSR2 register ********************/ + +#define DAC_SHSR2_TSAMPLE2_Pos ( 0U ) +#define DAC_SHSR2_TSAMPLE2_Msk ( 0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos ) +#define DAC_SHSR2_TSAMPLE2 ( DAC_SHSR2_TSAMPLE2_Msk ) + + +/*************** Bits definition for DAC_SHHR register *********************/ + +#define DAC_SHHR_THOLD2_Pos ( 16U ) +#define DAC_SHHR_THOLD2_Msk ( 0x3FFUL << DAC_SHHR_THOLD2_Pos ) +#define DAC_SHHR_THOLD2 ( DAC_SHHR_THOLD2_Msk ) + +#define DAC_SHHR_THOLD1_Pos ( 0U ) +#define DAC_SHHR_THOLD1_Msk ( 0x3FFUL << DAC_SHHR_THOLD1_Pos ) +#define DAC_SHHR_THOLD1 ( DAC_SHHR_THOLD1_Msk ) + + +/*************** Bits definition for DAC_SHRR register *********************/ + +#define DAC_SHRR_TREFRESH2_Pos ( 16U ) +#define DAC_SHRR_TREFRESH2_Msk ( 0xFFUL << DAC_SHRR_TREFRESH2_Pos ) +#define DAC_SHRR_TREFRESH2 ( DAC_SHRR_TREFRESH2_Msk ) + +#define DAC_SHRR_TREFRESH1_Pos ( 0U ) +#define DAC_SHRR_TREFRESH1_Msk ( 0xFFUL << DAC_SHRR_TREFRESH1_Pos ) +#define DAC_SHRR_TREFRESH1 ( DAC_SHRR_TREFRESH1_Msk ) + + +/*************** Bits definition for DAC_STR1 register *********************/ + +#define DAC_STR1_STINCDATA1_Pos ( 16U ) +#define DAC_STR1_STINCDATA1_Msk ( 0xFFFFUL << DAC_STR1_STINCDATA1_Pos ) +#define DAC_STR1_STINCDATA1 ( DAC_STR1_STINCDATA1_Msk ) + +#define DAC_STR1_STDIR1_Pos ( 12U ) +#define DAC_STR1_STDIR1_Msk ( 0x1UL << DAC_STR1_STDIR1_Pos ) +#define DAC_STR1_STDIR1 ( DAC_STR1_STDIR1_Msk ) + +#define DAC_STR1_STRSTDATA1_Pos ( 0U ) +#define DAC_STR1_STRSTDATA1_Msk ( 0xFFFUL << DAC_STR1_STRSTDATA1_Pos ) +#define DAC_STR1_STRSTDATA1 ( DAC_STR1_STRSTDATA1_Msk ) + + +/*************** Bits definition for DAC_STR2 register *********************/ + +#define DAC_STR2_STINCDATA2_Pos ( 16U ) +#define DAC_STR2_STINCDATA2_Msk ( 0xFFFFUL << DAC_STR2_STINCDATA2_Pos ) +#define DAC_STR2_STINCDATA2 ( DAC_STR2_STINCDATA2_Msk ) + +#define DAC_STR2_STDIR2_Pos ( 12U ) +#define DAC_STR2_STDIR2_Msk ( 0x1UL << DAC_STR2_STDIR2_Pos ) +#define DAC_STR2_STDIR2 ( DAC_STR2_STDIR2_Msk ) + +#define DAC_STR2_STRSTDATA2_Pos ( 0U ) +#define DAC_STR2_STRSTDATA2_Msk ( 0xFFFUL << DAC_STR2_STRSTDATA2_Pos ) +#define DAC_STR2_STRSTDATA2 ( DAC_STR2_STRSTDATA2_Msk ) + + +/*************** Bits definition for DAC_STMODR register *******************/ + +#define DAC_STMODR_STINCTRIGSEL2_Pos ( 24U ) +#define DAC_STMODR_STINCTRIGSEL2_Msk ( 0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos ) +#define DAC_STMODR_STINCTRIGSEL2 ( DAC_STMODR_STINCTRIGSEL2_Msk ) +#define DAC_STMODR_STINCTRIGSEL2_0 ( 0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos ) +#define DAC_STMODR_STINCTRIGSEL2_1 ( 0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos ) +#define DAC_STMODR_STINCTRIGSEL2_2 ( 0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos ) +#define DAC_STMODR_STINCTRIGSEL2_3 ( 0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos ) + +#define DAC_STMODR_STRSTTRIGSEL2_Pos ( 16U ) +#define DAC_STMODR_STRSTTRIGSEL2_Msk ( 0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos ) +#define DAC_STMODR_STRSTTRIGSEL2 ( DAC_STMODR_STRSTTRIGSEL2_Msk ) +#define DAC_STMODR_STRSTTRIGSEL2_0 ( 0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos ) +#define DAC_STMODR_STRSTTRIGSEL2_1 ( 0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos ) +#define DAC_STMODR_STRSTTRIGSEL2_2 ( 0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos ) +#define DAC_STMODR_STRSTTRIGSEL2_3 ( 0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos ) + +#define DAC_STMODR_STINCTRIGSEL1_Pos ( 8U ) +#define DAC_STMODR_STINCTRIGSEL1_Msk ( 0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos ) +#define DAC_STMODR_STINCTRIGSEL1 ( DAC_STMODR_STINCTRIGSEL1_Msk ) +#define DAC_STMODR_STINCTRIGSEL1_0 ( 0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos ) +#define DAC_STMODR_STINCTRIGSEL1_1 ( 0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos ) +#define DAC_STMODR_STINCTRIGSEL1_2 ( 0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos ) +#define DAC_STMODR_STINCTRIGSEL1_3 ( 0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos ) + +#define DAC_STMODR_STRSTTRIGSEL1_Pos ( 0U ) +#define DAC_STMODR_STRSTTRIGSEL1_Msk ( 0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos ) +#define DAC_STMODR_STRSTTRIGSEL1 ( DAC_STMODR_STRSTTRIGSEL1_Msk ) +#define DAC_STMODR_STRSTTRIGSEL1_0 ( 0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos ) +#define DAC_STMODR_STRSTTRIGSEL1_1 ( 0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos ) +#define DAC_STMODR_STRSTTRIGSEL1_2 ( 0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos ) +#define DAC_STMODR_STRSTTRIGSEL1_3 ( 0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos ) + +/*************** Bits definition for MDAC_VDACx_CR **********************/ + +#define MDAC_VDACX_CR_CAL_FLAG_Pos ( 16U ) +#define MDAC_VDACX_CR_CAL_FLAG_Msk ( 0x1UL << MDAC_VDACX_CR_CAL_FLAG_Pos ) +#define MDAC_VDACX_CR_CAL_FLAG ( MDAC_VDACX_CR_CAL_FLAG_Msk ) + +#define MDAC_VDACX_CR_SAMPLE_EN_Pos ( 10U ) +#define MDAC_VDACX_CR_SAMPLE_EN_Msk ( 0x1UL << MDAC_VDACX_CR_SAMPLE_EN_Pos ) +#define MDAC_VDACX_CR_SAMPLE_EN ( MDAC_VDACX_CR_SAMPLE_EN_Msk ) + +#define MDAC_VDACX_CR_OTRIM_Pos ( 5U ) +#define MDAC_VDACX_CR_OTRIM_Msk ( 0x1FL << MDAC_VDACX_CR_OTRIM_Pos ) +#define MDAC_VDACX_CR_OTRIM ( MDAC_VDACX_CR_OTRIM_Msk ) + +#define MDAC_VDACX_CR_OTRIM4_Pos ( 9U ) +#define MDAC_VDACX_CR_OTRIM4_Msk ( 0x1UL << MDAC_VDACX_CR_OTRIM4_Pos ) +#define MDAC_VDACX_CR_OTRIM4 ( MDAC_VDACX_CR_OTRIM4_Msk ) + + +#define MDAC_VDACX_CR_OTRIM3_Pos ( 8U ) +#define MDAC_VDACX_CR_OTRIM3_Msk ( 0x1UL << MDAC_VDACX_CR_OTRIM3_Pos ) +#define MDAC_VDACX_CR_OTRIM3 ( MDAC_VDACX_CR_OTRIM3_Msk ) + + +#define MDAC_VDACX_CR_OTRIM2_Pos ( 7U ) +#define MDAC_VDACX_CR_OTRIM2_Msk ( 0x1UL << MDAC_VDACX_CR_OTRIM2_Pos ) +#define MDAC_VDACX_CR_OTRIM2 ( MDAC_VDACX_CR_OTRIM2_Msk ) + + +#define MDAC_VDACX_CR_OTRIM1_Pos ( 6U ) +#define MDAC_VDACX_CR_OTRIM1_Msk ( 0x1UL << MDAC_VDACX_CR_OTRIM1_Pos ) +#define MDAC_VDACX_CR_OTRIM1 ( MDAC_VDACX_CR_OTRIM1_Msk ) + + +#define MDAC_VDACX_CR_OTRIM0_Pos ( 5U ) +#define MDAC_VDACX_CR_OTRIM0_Msk ( 0x1UL << MDAC_VDACX_CR_OTRIM0_Pos ) +#define MDAC_VDACX_CR_OTRIM0 ( MDAC_VDACX_CR_OTRIM0_Msk ) + + +#define MDAC_VDACX_CR_CEN_Pos ( 4U ) +#define MDAC_VDACX_CR_CEN_Msk ( 0x1UL << MDAC_VDACX_CR_CEN_Pos ) +#define MDAC_VDACX_CR_CEN ( MDAC_VDACX_CR_CEN_Msk ) + +#define MDAC_VDACX_CR_MODE_Pos ( 1U ) +#define MDAC_VDACX_CR_MODE_Msk ( 0x7UL << MDAC_VDACX_CR_MODE_Pos ) +#define MDAC_VDACX_CR_MODE ( MDAC_VDACX_CR_MODE_Msk ) + +#define MDAC_VDACX_CR_MODE2_Pos ( 3U ) +#define MDAC_VDACX_CR_MODE2_Msk ( 0x1UL << MDAC_VDACX_CR_MODE2_Pos ) +#define MDAC_VDACX_CR_MODE2 ( MDAC_VDACX_CR_MODE2_Msk ) + + +#define MDAC_VDACX_CR_MODE1_Pos ( 2U ) +#define MDAC_VDACX_CR_MODE1_Msk ( 0x1UL << MDAC_VDACX_CR_MODE1_Pos ) +#define MDAC_VDACX_CR_MODE1 ( MDAC_VDACX_CR_MODE1_Msk ) + + +#define MDAC_VDACX_CR_MODE0_Pos ( 1U ) +#define MDAC_VDACX_CR_MODE0_Msk ( 0x1UL << MDAC_VDACX_CR_MODE0_Pos ) +#define MDAC_VDACX_CR_MODE0 ( MDAC_VDACX_CR_MODE0_Msk ) + + +#define MDAC_VDACX_CR_EN_Pos ( 0U ) +#define MDAC_VDACX_CR_EN_Msk ( 0x1UL << MDAC_VDACX_CR_EN_Pos ) +#define MDAC_VDACX_CR_EN ( MDAC_VDACX_CR_EN_Msk ) + + +/*************** Bits definition for MDAC_IDACx_CR **********************/ + +#define MDAC_IDACX_CR_ITURE_Pos ( 1U ) +#define MDAC_IDACX_CR_ITURE_Msk ( 0x1FUL << MDAC_IDACX_CR_ITURE_Pos ) +#define MDAC_IDACX_CR_ITURE ( MDAC_IDACX_CR_ITURE_Msk ) + +#define MDAC_IDACX_CR_ITURE4_Pos ( 5U ) +#define MDAC_IDACX_CR_ITURE4_Msk ( 0x1UL << MDAC_IDACX_CR_ITURE4_Pos ) +#define MDAC_IDACX_CR_ITURE4 ( MDAC_IDACX_CR_ITURE4_Msk ) + + +#define MDAC_IDACX_CR_ITURE3_Pos ( 4U ) +#define MDAC_IDACX_CR_ITURE3_Msk ( 0x1UL << MDAC_IDACX_CR_ITURE3_Pos ) +#define MDAC_IDACX_CR_ITURE3 ( MDAC_IDACX_CR_ITURE3_Msk ) + + +#define MDAC_IDACX_CR_ITURE2_Pos ( 3U ) +#define MDAC_IDACX_CR_ITURE2_Msk ( 0x1UL << MDAC_IDACX_CR_ITURE2_Pos ) +#define MDAC_IDACX_CR_ITURE2 ( MDAC_IDACX_CR_ITURE2_Msk ) + + +#define MDAC_IDACX_CR_ITURE1_Pos ( 2U ) +#define MDAC_IDACX_CR_ITURE1_Msk ( 0x1UL << MDAC_IDACX_CR_ITURE1_Pos ) +#define MDAC_IDACX_CR_ITURE1 ( MDAC_IDACX_CR_ITURE1_Msk ) + + +#define MDAC_IDACX_CR_ITURE0_Pos ( 1U ) +#define MDAC_IDACX_CR_ITURE0_Msk ( 0x1UL << MDAC_IDACX_CR_ITURE0_Pos ) +#define MDAC_IDACX_CR_ITURE0 ( MDAC_IDACX_CR_ITURE0_Msk ) + + +#define MDAC_IDACX_CR_EN_Pos ( 0U ) +#define MDAC_IDACX_CR_EN_Msk ( 0x1UL << MDAC_IDACX_CR_EN_Pos ) +#define MDAC_IDACX_CR_EN ( MDAC_IDACX_CR_EN_Msk ) + + +/*************** Bits definition for MDAC_DACx_DOR **********************/ + +#define MDAC_DACX_DOR_DACDOR11_Pos ( 11U ) +#define MDAC_DACX_DOR_DACDOR11_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR11_Pos ) +#define MDAC_DACX_DOR_DACDOR11 ( MDAC_DACX_DOR_DACDOR11_Msk ) + + +#define MDAC_DACX_DOR_DACDOR10_Pos ( 10U ) +#define MDAC_DACX_DOR_DACDOR10_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR10_Pos ) +#define MDAC_DACX_DOR_DACDOR10 ( MDAC_DACX_DOR_DACDOR10_Msk ) + + +#define MDAC_DACX_DOR_DACDOR9_Pos ( 9U ) +#define MDAC_DACX_DOR_DACDOR9_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR9_Pos ) +#define MDAC_DACX_DOR_DACDOR9 ( MDAC_DACX_DOR_DACDOR9_Msk ) + + +#define MDAC_DACX_DOR_DACDOR8_Pos ( 8U ) +#define MDAC_DACX_DOR_DACDOR8_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR8_Pos ) +#define MDAC_DACX_DOR_DACDOR8 ( MDAC_DACX_DOR_DACDOR8_Msk ) + + +#define MDAC_DACX_DOR_DACDOR7_Pos ( 7U ) +#define MDAC_DACX_DOR_DACDOR7_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR7_Pos ) +#define MDAC_DACX_DOR_DACDOR7 ( MDAC_DACX_DOR_DACDOR7_Msk ) + + +#define MDAC_DACX_DOR_DACDOR6_Pos ( 6U ) +#define MDAC_DACX_DOR_DACDOR6_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR6_Pos ) +#define MDAC_DACX_DOR_DACDOR6 ( MDAC_DACX_DOR_DACDOR6_Msk ) + + +#define MDAC_DACX_DOR_DACDOR5_Pos ( 5U ) +#define MDAC_DACX_DOR_DACDOR5_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR5_Pos ) +#define MDAC_DACX_DOR_DACDOR5 ( MDAC_DACX_DOR_DACDOR5_Msk ) + + +#define MDAC_DACX_DOR_DACDOR4_Pos ( 4U ) +#define MDAC_DACX_DOR_DACDOR4_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR4_Pos ) +#define MDAC_DACX_DOR_DACDOR4 ( MDAC_DACX_DOR_DACDOR4_Msk ) + + +#define MDAC_DACX_DOR_DACDOR3_Pos ( 3U ) +#define MDAC_DACX_DOR_DACDOR3_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR3_Pos ) +#define MDAC_DACX_DOR_DACDOR3 ( MDAC_DACX_DOR_DACDOR3_Msk ) + + +#define MDAC_DACX_DOR_DACDOR2_Pos ( 2U ) +#define MDAC_DACX_DOR_DACDOR2_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR2_Pos ) +#define MDAC_DACX_DOR_DACDOR2 ( MDAC_DACX_DOR_DACDOR2_Msk ) + + +#define MDAC_DACX_DOR_DACDOR1_Pos ( 1U ) +#define MDAC_DACX_DOR_DACDOR1_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR1_Pos ) +#define MDAC_DACX_DOR_DACDOR1 ( MDAC_DACX_DOR_DACDOR1_Msk ) + + +#define MDAC_DACX_DOR_DACDOR0_Pos ( 0U ) +#define MDAC_DACX_DOR_DACDOR0_Msk ( 0x1UL << MDAC_DACX_DOR_DACDOR0_Pos ) +#define MDAC_DACX_DOR_DACDOR0 ( MDAC_DACX_DOR_DACDOR0_Msk ) + +/*************** Bits definition for TKEY_SR **********************/ + +#define TKEY_SR_MEOC_Pos ( 11U ) +#define TKEY_SR_MEOC_Msk ( 0x1UL << TKEY_SR_MEOC_Pos ) +#define TKEY_SR_MEOC ( TKEY_SR_MEOC_Msk ) + +#define TKEY_SR_CHGDONE_Pos ( 10U ) +#define TKEY_SR_CHGDONE_Msk ( 0x1UL << TKEY_SR_CHGDONE_Pos ) +#define TKEY_SR_CHGDONE ( TKEY_SR_CHGDONE_Msk ) + +#define TKEY_SR_CHG_Pos ( 9U ) +#define TKEY_SR_CHG_Msk ( 0x1UL << TKEY_SR_CHG_Pos ) +#define TKEY_SR_CHG ( TKEY_SR_CHG_Msk ) + +#define TKEY_SR_DONE_Pos ( 8U ) +#define TKEY_SR_DONE_Msk ( 0x1UL << TKEY_SR_DONE_Pos ) +#define TKEY_SR_DONE ( TKEY_SR_DONE_Msk ) + +#define TKEY_SR_CHNUM_Pos ( 4U ) +#define TKEY_SR_CHNUM_Msk ( 0xfUL << TKEY_SR_CHNUM_Pos ) +#define TKEY_SR_CHNUM ( TKEY_SR_CHNUM_Msk ) +#define TKEY_SR_CHNUM_0 ( 0x1UL << TKEY_SR_CHNUM_Pos ) +#define TKEY_SR_CHNUM_1 ( 0x2UL << TKEY_SR_CHNUM_Pos ) +#define TKEY_SR_CHNUM_2 ( 0x4UL << TKEY_SR_CHNUM_Pos ) +#define TKEY_SR_CHNUM_3 ( 0x8UL << TKEY_SR_CHNUM_Pos ) + +#define TKEY_SR_BUSY_Pos ( 3U ) +#define TKEY_SR_BUSY_Msk ( 0x1UL << TKEY_SR_BUSY_Pos ) +#define TKEY_SR_BUSY ( TKEY_SR_BUSY_Msk ) + +#define TKEY_SR_TIMEOUT_Pos ( 2U ) +#define TKEY_SR_TIMEOUT_Msk ( 0x1UL << TKEY_SR_TIMEOUT_Pos ) +#define TKEY_SR_TIMEOUT ( TKEY_SR_TIMEOUT_Msk ) + +#define TKEY_SR_YESTOUCH_Pos ( 1U ) +#define TKEY_SR_YESTOUCH_Msk ( 0x1UL << TKEY_SR_YESTOUCH_Pos ) +#define TKEY_SR_YESTOUCH ( TKEY_SR_YESTOUCH_Msk ) + +#define TKEY_SR_EOC_Pos ( 0U ) +#define TKEY_SR_EOC_Msk ( 0x1UL << TKEY_SR_EOC_Pos ) +#define TKEY_SR_EOC ( TKEY_SR_EOC_Msk ) + + +/*************** Bits definition for TKEY_IER **********************/ + +#define TKEY_IER_MEOCIE_Pos ( 11U ) +#define TKEY_IER_MEOCIE_Msk ( 0x1UL << TKEY_IER_MEOCIE_Pos ) +#define TKEY_IER_MEOCIE ( TKEY_IER_MEOCIE_Msk ) + +#define TKEY_IER_CHGDONEIE_Pos ( 10U ) +#define TKEY_IER_CHGDONEIE_Msk ( 0x1UL << TKEY_IER_CHGDONEIE_Pos ) +#define TKEY_IER_CHGDONEIE ( TKEY_IESR_CHGDONEIE_Msk ) + +#define TKEY_IER_CHIE_Pos ( 9U ) +#define TKEY_IER_CHIE_Msk ( 0x1UL << TKEY_IER_CHIE_Pos ) +#define TKEY_IER_CHIE ( TKEY_IER_CHIE_Msk ) + +#define TKEY_IER_DONEIE_Pos ( 8U ) +#define TKEY_IER_DONEIE_Msk ( 0x1UL << TKEY_IER_DONEIE_Pos ) +#define TKEY_IER_DONEIE ( TKEY_IER_DONEIE_Msk ) + +#define TKEY_IER_TIMEOUTIE_Pos ( 2U ) +#define TKEY_IER_TIMEOUTIE_Msk ( 0x1UL << TKEY_IER_TIMEOUTIE_Pos ) +#define TKEY_IER_TIMEOUTIE ( TKEY_IER_TIMEOUTIE_Msk ) + +#define TKEY_IER_YESTOUCHIE_Pos ( 1U ) +#define TKEY_IER_YESTOUCHIE_Msk ( 0x1UL << TKEY_IER_YESTOUCHIE_Pos ) +#define TKEY_IER_YESTOUCHIE ( TKEY_IER_YESTOUCHIE_Msk ) + +#define TKEY_IER_EOCIE_Pos ( 0U ) +#define TKEY_IER_EOCIE_Msk ( 0x1UL << TKEY_IER_EOCIE_Pos ) +#define TKEY_IER_EOCIE ( TKEY_IER_EOCIE_Msk ) + + +/*************** Bits definition for TKEY_CR **********************/ + +#define TKEY_CR_CHGDONEEN_Pos ( 15U ) +#define TKEY_CR_CHGDONEEN_Msk ( 0x1UL << TKEY_CR_CHGDONEEN_Pos ) +#define TKEY_CR_CHGDONEEN ( TKEY_CR_CHGDONEEN_Msk ) + +#define TKEY_CR_CHGEN_Pos ( 14U ) +#define TKEY_CR_CHGEN_Msk ( 0x1UL << TKEY_CR_CHGEN_Pos ) +#define TKEY_CR_CHGEN ( TKEY_CR_CHGEN_Msk ) + +#define TKEY_CR_DISMS_Pos ( 11U ) +#define TKEY_CR_DISMS_Msk ( 0x7UL << TKEY_CR_DISMS_Pos ) +#define TKEY_CR_DISMS ( TKEY_CR_DISMS_Msk ) +#define TKEY_CR_DISMS_0 ( 0x1UL << TKEY_CR_DISMS_Pos ) +#define TKEY_CR_DISMS_1 ( 0x2UL << TKEY_CR_DISMS_Pos ) +#define TKEY_CR_DISMS_2 ( 0x4UL << TKEY_CR_DISMS_Pos ) + +#define TKEY_CR_RANDM_Pos ( 9U ) +#define TKEY_CR_RANDM_Msk ( 0x3UL << TKEY_CR_RANDM_Pos ) +#define TKEY_CR_RANDM ( TKEY_CR_RANDM_Msk ) +#define TKEY_CR_RANDM_0 ( 0x1UL << TKEY_CR_RANDM_Pos ) +#define TKEY_CR_RANDM_1 ( 0x2UL << TKEY_CR_RANDM_Pos ) + +#define TKEY_CR_AUTO_Pos ( 8U ) +#define TKEY_CR_AUTO_Msk ( 0x1UL << TKEY_CR_AUTO_Pos ) +#define TKEY_CR_AUTO ( TKEY_CR_AUTO_Msk ) + +#define TKEY_CR_SPREAD_Pos ( 7U ) +#define TKEY_CR_SPREAD_Msk ( 0x1UL << TKEY_CR_SPREAD_Pos ) +#define TKEY_CR_SPREAD ( TKEY_CR_SPREAD_Msk ) + +#define TKEY_CR_CONT_Pos ( 6U ) +#define TKEY_CR_CONT_Msk ( 0x1UL << TKEY_CR_CONT_Pos ) +#define TKEY_CR_CONT ( TKEY_CR_CONT_Msk ) + +#define TKEY_CR_SHIELDEN_Pos ( 5U ) +#define TKEY_CR_SHIELDEN_Msk ( 0x1UL << TKEY_CR_SHIELDEN_Pos ) +#define TKEY_CR_SHIELDEN ( TKEY_CR_SHIELDEN_Msk ) + +#define TKEY_CR_PCEN_Pos ( 4U ) +#define TKEY_CR_PCEN_Msk ( 0x1UL << TKEY_CR_PCEN_Pos ) +#define TKEY_CR_PCEN ( TKEY_CR_PCEN_Msk ) + +#define TKEY_CR_CHEN_Pos ( 3U ) +#define TKEY_CR_CHEN_Msk ( 0x1UL << TKEY_CR_CHEN_Pos ) +#define TKEY_CR_CHEN ( TKEY_CR_CHEN_Msk ) + +#define TKEY_CR_START_Pos ( 2U ) +#define TKEY_CR_START_Msk ( 0x1UL << TKEY_CR_START_Pos ) +#define TKEY_CR_START ( TKEY_CR_START_Msk ) + +#define TKEY_CR_TKMS_Pos ( 1U ) +#define TKEY_CR_TKMS_Msk ( 0x1UL << TKEY_CR_TKMS_Pos ) +#define TKEY_CR_TKMS ( TKEY_CR_TKMS_Msk ) + +#define TKEY_CR_TKEN_Pos ( 0U ) +#define TKEY_CR_TKEN_Msk ( 0x1UL << TKEY_CR_TKEN_Pos ) +#define TKEY_CR_TKEN ( TKEY_CR_TKEN_Msk ) + + +/*************** Bits definition for TKEY_CFGR1 **********************/ + +#define TKEY_CFGR1_FLTSEL_Pos ( 11U ) +#define TKEY_CFGR1_FLTSEL_Msk ( 0x7UL << TKEY_CFGR1_FLTSEL_Pos ) +#define TKEY_CFGR1_FLTSEL ( TKEY_CFGR1_FLTSEL_Msk ) +#define TKEY_CFGR1_FLTSEL_0 ( 0x1UL << TKEY_CFGR1_FLTSEL_Pos ) +#define TKEY_CFGR1_FLTSEL_1 ( 0x2UL << TKEY_CFGR1_FLTSEL_Pos ) +#define TKEY_CFGR1_FLTSEL_2 ( 0x4UL << TKEY_CFGR1_FLTSEL_Pos ) + +#define TKEY_CFGR1_SMPSEL_Pos ( 9U ) +#define TKEY_CFGR1_SMPSEL_Msk ( 0x3UL << TKEY_CFGR1_SMPSEL_Pos ) +#define TKEY_CFGR1_SMPSEL ( TKEY_CFGR1_SMPSEL_Msk ) +#define TKEY_CFGR1_SMPSEL_0 ( 0x1UL << TKEY_CFGR1_SMPSEL_Pos ) +#define TKEY_CFGR1_SMPSEL_1 ( 0x2UL << TKEY_CFGR1_SMPSEL_Pos ) + +#define TKEY_CFGR1_CCPSEL_Pos ( 6U ) +#define TKEY_CFGR1_CCPSEL_Msk ( 0x7UL << TKEY_CFGR1_CCPSEL_Pos ) +#define TKEY_CFGR1_CCPSEL ( TKEY_CFGR1_CCPSEL_Msk ) +#define TKEY_CFGR1_CCPSEL_0 ( 0x1UL << TKEY_CFGR1_CCPSEL_Pos ) +#define TKEY_CFGR1_CCPSEL_1 ( 0x2UL << TKEY_CFGR1_CCPSEL_Pos ) +#define TKEY_CFGR1_CCPSEL_2 ( 0x4UL << TKEY_CFGR1_CCPSEL_Pos ) + +#define TKEY_CFGR1_RCPSEL_Pos ( 4U ) +#define TKEY_CFGR1_RCPSEL_Msk ( 0x3UL << TKEY_CFGR1_RCPSEL_Pos ) +#define TKEY_CFGR1_RCPSEL ( TKEY_CFGR1_RCPSEL_Msk ) +#define TKEY_CFGR1_RCPSEL_0 ( 0x1UL << TKEY_CFGR1_RCPSEL_Pos ) +#define TKEY_CFGR1_RCPSEL_1 ( 0x2UL << TKEY_CFGR1_RCPSEL_Pos ) + +#define TKEY_CFGR1_VCHRSEL_Pos ( 2U ) +#define TKEY_CFGR1_VCHRSEL_Msk ( 0x3UL << TKEY_CFGR1_VCHRSEL_Pos ) +#define TKEY_CFGR1_VCHRSEL ( TKEY_CFGR1_VCHRSEL_Msk ) +#define TKEY_CFGR1_VCHRSEL_0 ( 0x1UL << TKEY_CFGR1_VCHRSEL_Pos ) +#define TKEY_CFGR1_VCHRSEL_1 ( 0x2UL << TKEY_CFGR1_VCHRSEL_Pos ) + +#define TKEY_CFGR1_VCMPSEL_Pos ( 0U ) +#define TKEY_CFGR1_VCMPSEL_Msk ( 0x3UL << TKEY_CFGR1_VCMPSEL_Pos ) +#define TKEY_CFGR1_VCMPSEL ( TKEY_CFGR1_VCMPSEL_Msk ) +#define TKEY_CFGR1_VCMPSEL_0 ( 0x1UL << TKEY_CFGR1_VCMPSEL_Pos ) +#define TKEY_CFGR1_VCMPSEL_1 ( 0x2UL << TKEY_CFGR1_VCMPSEL_Pos ) + + +/*************** Bits definition for TKEY_CFGR2 **********************/ + +#define TKEY_CFGR2_IDISSEL_Pos ( 8U ) +#define TKEY_CFGR2_IDISSEL_Msk ( 0xffUL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL ( TKEY_CFGR2_IDISSEL_Msk ) +#define TKEY_CFGR2_IDISSEL_0 ( 0x1UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_1 ( 0x2UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_2 ( 0x4UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_3 ( 0x8UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_4 ( 0x10UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_5 ( 0x20UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_6 ( 0x40UL << TKEY_CFGR2_IDISSEL_Pos ) +#define TKEY_CFGR2_IDISSEL_7 ( 0x80UL << TKEY_CFGR2_IDISSEL_Pos ) + +#define TKEY_CFGR2_RDISSEL_Pos ( 0U ) +#define TKEY_CFGR2_RDISSEL_Msk ( 0xffUL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL ( TKEY_CFGR2_RDISSEL_Msk ) +#define TKEY_CFGR2_RDISSEL_0 ( 0x1UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_1 ( 0x2UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_2 ( 0x4UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_3 ( 0x8UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_4 ( 0x10UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_5 ( 0x20UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_6 ( 0x40UL << TKEY_CFGR2_RDISSEL_Pos ) +#define TKEY_CFGR2_RDISSEL_7 ( 0x80UL << TKEY_CFGR2_RDISSEL_Pos ) + + +/*************** Bits definition for TKEY_SMPCR **********************/ + +#define TKEY_INTVLR_INTERVAL_Pos ( 0U ) +#define TKEY_INTVLR_INTERVAL_Msk ( 0xffffUL << TKEY_SMPCR_GAP_Pos ) +#define TKEY_INTVLR_INTERVAL ( TKEY_SMPCR_GAP_Msk ) + +/*************** Bits definition for TKEY_CCR **********************/ + +#define TKEY_DIVR_SCANCLKDIV_Pos ( 8U ) +#define TKEY_DIVR_SCANCLKDIV_Msk ( 0xffUL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV ( TKEY_DIVR_SCANCLKDIV_Msk ) +#define TKEY_DIVR_SCANCLKDIV_0 ( 0x1UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_1 ( 0x2UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_2 ( 0x4UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_3 ( 0x8UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_4 ( 0x10UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_5 ( 0x20UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_6 ( 0x40UL << TKEY_DIVR_SCANCLKDIV_Pos ) +#define TKEY_DIVR_SCANCLKDIV_7 ( 0x80UL << TKEY_DIVR_SCANCLKDIV_Pos ) + +#define TKEY_DIVR_SMPCLKDIV_Pos ( 0U ) +#define TKEY_DIVR_SMPCLKDIV_Msk ( 0xffUL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV ( TKEY_DIVR_SMPCLKDIV_Msk ) +#define TKEY_DIVR_SMPCLKDIV_0 ( 0x1UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_1 ( 0x2UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_2 ( 0x4UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_3 ( 0x8UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_4 ( 0x10UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_5 ( 0x20UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_6 ( 0x40UL << TKEY_DIVR_SMPCLKDIV_Pos ) +#define TKEY_DIVR_SMPCLKDIV_7 ( 0x80UL << TKEY_DIVR_SMPCLKDIV_Pos ) + + +/*************** Bits definition for TKEY_SCCR **********************/ + +#define TKEY_SCCR_SW1H_Pos ( 8U ) +#define TKEY_SCCR_SW1H_Msk ( 0xffUL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H ( TKEY_SCCR_SW1H_Msk ) +#define TKEY_SCCR_SW1H_0 ( 0x1UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_1 ( 0x2UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_2 ( 0x4UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_3 ( 0x8UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_4 ( 0x10UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_5 ( 0x20UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_6 ( 0x40UL << TKEY_SCCR_SW1H_Pos ) +#define TKEY_SCCR_SW1H_7 ( 0x80UL << TKEY_SCCR_SW1H_Pos ) + +#define TKEY_SCCR_SW1L_Pos ( 0U ) +#define TKEY_SCCR_SW1L_Msk ( 0xffUL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L ( TKEY_SCCR_SW1L_Msk ) +#define TKEY_SCCR_SW1L_0 ( 0x1UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_1 ( 0x2UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_2 ( 0x4UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_3 ( 0x8UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_4 ( 0x10UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_5 ( 0x20UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_6 ( 0x40UL << TKEY_SCCR_SW1L_Pos ) +#define TKEY_SCCR_SW1L_7 ( 0x80UL << TKEY_SCCR_SW1L_Pos ) + + +/*************** Bits definition for TKEY_TSETR **********************/ + +#define TKEY_TSETR_TEST_Pos ( 4U ) +#define TKEY_TSETR_TEST_Msk ( 0xfffUL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST ( TKEY_TSETR_TEST_Msk ) +#define TKEY_TSETR_TEST_0 ( 0x1UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_1 ( 0x2UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_2 ( 0x4UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_3 ( 0x8UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_4 ( 0x10UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_5 ( 0x20UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_6 ( 0x40UL << TKEY_TSETR_TEST_Pos ) +#define TKEY_TSETR_TEST_7 ( 0x80UL << TKEY_TSETR_TEST_Pos ) + +#define TKEY_TSETR_CST_Pos ( 0U ) +#define TKEY_TSETR_CST_Msk ( 0xfUL << TKEY_TSETR_CST_Pos ) +#define TKEY_TSETR_CST ( TKEY_TSETR_CST_Msk ) +#define TKEY_TSETR_CST_0 ( 0x1UL << TKEY_TSETR_CST_Pos ) +#define TKEY_TSETR_CST_1 ( 0x2UL << TKEY_TSETR_CST_Pos ) +#define TKEY_TSETR_CST_2 ( 0x4UL << TKEY_TSETR_CST_Pos ) +#define TKEY_TSETR_CST_3 ( 0x8UL << TKEY_TSETR_CST_Pos ) + + +/*************** Bits definition for TKEY_CXENR **********************/ + +#define TKEY_CXENR_CX15EN_Pos ( 15U ) +#define TKEY_CXENR_CX15EN_Msk ( 0x1UL << TKEY_CXENR_CX15EN_Pos ) +#define TKEY_CXENR_CX15EN ( TKEY_CXENR_CX15EN_Msk ) + +#define TKEY_CXENR_CX14EN_Pos ( 14U ) +#define TKEY_CXENR_CX14EN_Msk ( 0x1UL << TKEY_CXENR_CX14EN_Pos ) +#define TKEY_CXENR_CX14EN ( TKEY_CXENR_CX14EN_Msk ) + +#define TKEY_CXENR_CX13EN_Pos ( 13U ) +#define TKEY_CXENR_CX13EN_Msk ( 0x1UL << TKEY_CXENR_CX13EN_Pos ) +#define TKEY_CXENR_CX13EN ( TKEY_CXENR_CX13EN_Msk ) + +#define TKEY_CXENR_CX12EN_Pos ( 12U ) +#define TKEY_CXENR_CX12EN_Msk ( 0x1UL << TKEY_CXENR_CX12EN_Pos ) +#define TKEY_CXENR_CX12EN ( TKEY_CXENR_CX12EN_Msk ) + +#define TKEY_CXENR_CX11EN_Pos ( 11U ) +#define TKEY_CXENR_CX11EN_Msk ( 0x1UL << TKEY_CXENR_CX11EN_Pos ) +#define TKEY_CXENR_CX11EN ( TKEY_CXENR_CX11EN_Msk ) + +#define TKEY_CXENR_CX10EN_Pos ( 10U ) +#define TKEY_CXENR_CX10EN_Msk ( 0x1UL << TKEY_CXENR_CX10EN_Pos ) +#define TKEY_CXENR_CX10EN ( TKEY_CXENR_CX10EN_Msk ) + +#define TKEY_CXENR_CX9EN_Pos ( 9U ) +#define TKEY_CXENR_CX9EN_Msk ( 0x1UL << TKEY_CXENR_CX9EN_Pos ) +#define TKEY_CXENR_CX9EN ( TKEY_CXENR_CX9EN_Msk ) + +#define TKEY_CXENR_CX8EN_Pos ( 8U ) +#define TKEY_CXENR_CX8EN_Msk ( 0x1UL << TKEY_CXENR_CX8EN_Pos ) +#define TKEY_CXENR_CX8EN ( TKEY_CXENR_CX8EN_Msk ) + +#define TKEY_CXENR_CX7EN_Pos ( 7U ) +#define TKEY_CXENR_CX7EN_Msk ( 0x1UL << TKEY_CXENR_CX7EN_Pos ) +#define TKEY_CXENR_CX7EN ( TKEY_CXENR_CX7EN_Msk ) + +#define TKEY_CXENR_CX6EN_Pos ( 6U ) +#define TKEY_CXENR_CX6EN_Msk ( 0x1UL << TKEY_CXENR_CX6EN_Pos ) +#define TKEY_CXENR_CX6EN ( TKEY_CXENR_CX6EN_Msk ) + +#define TKEY_CXENR_CX5EN_Pos ( 5U ) +#define TKEY_CXENR_CX5EN_Msk ( 0x1UL << TKEY_CXENR_CX5EN_Pos ) +#define TKEY_CXENR_CX5EN ( TKEY_CXENR_CX5EN_Msk ) + +#define TKEY_CXENR_CX4EN_Pos ( 4U ) +#define TKEY_CXENR_CX4EN_Msk ( 0x1UL << TKEY_CXENR_CX4EN_Pos ) +#define TKEY_CXENR_CX4EN ( TKEY_CXENR_CX4EN_Msk ) + +#define TKEY_CXENR_CX3EN_Pos ( 3U ) +#define TKEY_CXENR_CX3EN_Msk ( 0x1UL << TKEY_CXENR_CX3EN_Pos ) +#define TKEY_CXENR_CX3EN ( TKEY_CXENR_CX3EN_Msk ) + +#define TKEY_CXENR_CX2EN_Pos ( 2U ) +#define TKEY_CXENR_CX2EN_Msk ( 0x1UL << TKEY_CXENR_CX2EN_Pos ) +#define TKEY_CXENR_CX2EN ( TKEY_CXENR_CX2EN_Msk ) + +#define TKEY_CXENR_CX1EN_Pos ( 1U ) +#define TKEY_CXENR_CX1EN_Msk ( 0x1UL << TKEY_CXENR_CX1EN_Pos ) +#define TKEY_CXENR_CX1EN ( TKEY_CXENR_CX1EN_Msk ) + +#define TKEY_CXENR_CX0EN_Pos ( 0U ) +#define TKEY_CXENR_CX0EN_Msk ( 0x1UL << TKEY_CXENR_CX0EN_Pos ) +#define TKEY_CXENR_CX0EN ( TKEY_CXENR_CX0EN_Msk ) + + +/*************** Bits definition for TKEY_DR **********************/ + +#define TKEY_DR_DATA_Pos ( 0U ) +#define TKEY_DR_DATA_Msk ( 0xffffUL << TKEY_DR_DATA_Pos ) +#define TKEY_DR_DATA ( TKEY_DR_DATA_Msk ) + + +/*************** Bits definition for TKEY_THx **********************/ + +#define TKEY_THX_DNX_Pos ( 0U ) +#define TKEY_THX_DNX_Msk ( 0xffUL << TKEY_THX_DNX_Pos ) +#define TKEY_THX_DNX ( TKEY_THX_DNX_Msk ) + + +/*************** Bits definition for TKEY_CHx **********************/ + +#define TKEY_CHX_CNTX_Pos ( 0U ) +#define TKEY_CHX_CNTX_Msk ( 0xffffUL << TKEY_CHX_CNTX_Pos ) +#define TKEY_CHX_CNTX ( TKEY_CHX_CNTX_Msk ) + + +/*************** Bits definition for TKEY_CFLTR **********************/ + +#define TKEY_CFLTR_CFLTNUM_Pos ( 1U ) +#define TKEY_CFLTR_CFLTNUM_Msk ( 0xfUL << TKEY_CFLTR_CFLTNUM_Pos ) +#define TKEY_CFLTR_CFLTNUM ( TKEY_CFLTR_CFLTNUM_Msk ) +#define TKEY_CFLTR_CFLTNUM_0 ( 0x1UL << TKEY_CFLTR_CFLTNUM_Pos ) +#define TKEY_CFLTR_CFLTNUM_1 ( 0x2UL << TKEY_CFLTR_CFLTNUM_Pos ) +#define TKEY_CFLTR_CFLTNUM_2 ( 0x4UL << TKEY_CFLTR_CFLTNUM_Pos ) +#define TKEY_CFLTR_CFLTNUM_3 ( 0x8UL << TKEY_CFLTR_CFLTNUM_Pos ) + +#define TKEY_CFLTR_CFLTEN_Pos ( 0U ) +#define TKEY_CFLTR_CFLTEN_Msk ( 0x1UL << TKEY_CFLTR_CFLTEN_Pos ) +#define TKEY_CFLTR_CFLTEN ( TKEY_CFLTR_CFLTEN_Msk ) + + +/*************** Bits definition for TKEY_NSETR **********************/ + +#define TKEY_NSETR_CHGNUM_Pos ( 0U ) +#define TKEY_NSETR_CHGNUM_Msk ( 0xffffUL << TKEY_NSETR_CHGNUM_Pos ) +#define TKEY_NSETR_CHGNUM ( TKEY_NSETR_CHGNUM_Msk ) + + +/*************** Bits definition for TKEY_TWAITR **********************/ + +#define TKEY_TWAITR_WAITTIME_Pos ( 0U ) +#define TKEY_TWAITR_WAITTIME_Msk ( 0xffffUL << TKEY_TWAITR_WAITTIME_Pos ) +#define TKEY_TWAITR_WAITTIME ( TKEY_TWAITR_WAITTIME_Msk ) + + +/*************** Bits definition for TKEY_MUTUALR **********************/ + +#define TKEY_MUTUALR_TXNUM_Pos ( 11U ) +#define TKEY_MUTUALR_TXNUM_Msk ( 0x1fUL << TKEY_MUTUALR_TXNUM_Pos ) +#define TKEY_MUTUALR_TXNUM ( TKEY_MUTUALR_TXNUM_Msk ) + +#define TKEY_MUTUALR_MTXDLY_Pos ( 3U ) +#define TKEY_MUTUALR_MTXDLY_Msk ( 0xffUL << TKEY_MUTUALR_MTXDLY_Pos ) +#define TKEY_MUTUALR_MTXDLY ( TKEY_MUTUALR_MTXDLY_Msk ) + +#define TKEY_MUTUALR_MTXDLYEN_Pos ( 2U ) +#define TKEY_MUTUALR_MTXDLYEN_Msk ( 0x1UL << TKEY_MUTUALR_MTXDLYEN_Pos ) +#define TKEY_MUTUALR_MTXDLYEN ( TKEY_MUTUALR_MTXDLYEN_Msk ) + +#define TKEY_MUTUALR_MTXRST_Pos ( 1U ) +#define TKEY_MUTUALR_MTXRST_Msk ( 0x1UL << TKEY_MUTUALR_MTXRST_Pos ) +#define TKEY_MUTUALR_MTXRST ( TKEY_MUTUALR_MTXRST_Msk ) + +#define TKEY_MUTUALR_MUTUALEN_Pos ( 0U ) +#define TKEY_MUTUALR_MUTUALEN_Msk ( 0x1UL << TKEY_MUTUALR_MUTUALEN_Pos ) +#define TKEY_MUTUALR_MUTUALEN ( TKEY_MUTUALR_MUTUALEN_Msk ) + + +/*************** Bits definition for TKEY_TXENR1 **********************/ + +#define TKEY_TXENR1_TX15EN_Pos ( 15U ) +#define TKEY_TXENR1_TX15EN_Msk ( 0x1UL << TKEY_TXENR1_TX15EN_Pos ) +#define TKEY_TXENR1_TX15EN ( TKEY_TXENR1_TX15EN_Msk ) + +#define TKEY_TXENR1_TX14EN_Pos ( 14U ) +#define TKEY_TXENR1_TX14EN_Msk ( 0x1UL << TKEY_TXENR1_TX14EN_Pos ) +#define TKEY_TXENR1_TX14EN ( TKEY_TXENR1_TX14EN_Msk ) + +#define TKEY_TXENR1_TX13EN_Pos ( 13U ) +#define TKEY_TXENR1_TX13EN_Msk ( 0x1UL << TKEY_TXENR1_TX13EN_Pos ) +#define TKEY_TXENR1_TX13EN ( TKEY_TXENR1_TX13EN_Msk ) + +#define TKEY_TXENR1_TX12EN_Pos ( 12U ) +#define TKEY_TXENR1_TX12EN_Msk ( 0x1UL << TKEY_TXENR1_TX12EN_Pos ) +#define TKEY_TXENR1_TX12EN ( TKEY_TXENR1_TX12EN_Msk ) + +#define TKEY_TXENR1_TX11EN_Pos ( 11U ) +#define TKEY_TXENR1_TX11EN_Msk ( 0x1UL << TKEY_TXENR1_TX11EN_Pos ) +#define TKEY_TXENR1_TX11EN ( TKEY_TXENR1_TX11EN_Msk ) + +#define TKEY_TXENR1_TX10EN_Pos ( 10U ) +#define TKEY_TXENR1_TX10EN_Msk ( 0x1UL << TKEY_TXENR1_TX10EN_Pos ) +#define TKEY_TXENR1_TX10EN ( TKEY_TXENR1_TX10EN_Msk ) + +#define TKEY_TXENR1_TX9EN_Pos ( 9U ) +#define TKEY_TXENR1_TX9EN_Msk ( 0x1UL << TKEY_TXENR1_TX9EN_Pos ) +#define TKEY_TXENR1_TX9EN ( TKEY_TXENR1_TX9EN_Msk ) + +#define TKEY_TXENR1_TX8EN_Pos ( 8U ) +#define TKEY_TXENR1_TX8EN_Msk ( 0x1UL << TKEY_TXENR1_TX8EN_Pos ) +#define TKEY_TXENR1_TX8EN ( TKEY_TXENR1_TX8EN_Msk ) + +#define TKEY_TXENR1_TX7EN_Pos ( 7U ) +#define TKEY_TXENR1_TX7EN_Msk ( 0x1UL << TKEY_TXENR1_TX7EN_Pos ) +#define TKEY_TXENR1_TX7EN ( TKEY_TXENR1_TX7EN_Msk ) + +#define TKEY_TXENR1_TX6EN_Pos ( 6U ) +#define TKEY_TXENR1_TX6EN_Msk ( 0x1UL << TKEY_TXENR1_TX6EN_Pos ) +#define TKEY_TXENR1_TX6EN ( TKEY_TXENR1_TX6EN_Msk ) + +#define TKEY_TXENR1_TX5EN_Pos ( 5U ) +#define TKEY_TXENR1_TX5EN_Msk ( 0x1UL << TKEY_TXENR1_TX5EN_Pos ) +#define TKEY_TXENR1_TX5EN ( TKEY_TXENR1_TX5EN_Msk ) + +#define TKEY_TXENR1_TX4EN_Pos ( 4U ) +#define TKEY_TXENR1_TX4EN_Msk ( 0x1UL << TKEY_TXENR1_TX4EN_Pos ) +#define TKEY_TXENR1_TX4EN ( TKEY_TXENR1_TX4EN_Msk ) + +#define TKEY_TXENR1_TX3EN_Pos ( 3U ) +#define TKEY_TXENR1_TX3EN_Msk ( 0x1UL << TKEY_TXENR1_TX3EN_Pos ) +#define TKEY_TXENR1_TX3EN ( TKEY_TXENR1_TX3EN_Msk ) + +#define TKEY_TXENR1_TX2EN_Pos ( 2U ) +#define TKEY_TXENR1_TX2EN_Msk ( 0x1UL << TKEY_TXENR1_TX2EN_Pos ) +#define TKEY_TXENR1_TX2EN ( TKEY_TXENR1_TX2EN_Msk ) + +#define TKEY_TXENR1_TX1EN_Pos ( 1U ) +#define TKEY_TXENR1_TX1EN_Msk ( 0x1UL << TKEY_TXENR1_TX1EN_Pos ) +#define TKEY_TXENR1_TX1EN ( TKEY_TXENR1_TX1EN_Msk ) + +#define TKEY_TXENR1_TX0EN_Pos ( 0U ) +#define TKEY_TXENR1_TX0EN_Msk ( 0x1UL << TKEY_TXENR1_TX0EN_Pos ) +#define TKEY_TXENR1_TX0EN ( TKEY_TXENR1_TX0EN_Msk ) + + +/*************** Bits definition for TKEY_TXENR1 **********************/ + + +#define TKEY_TXENR2_TX27EN_Pos ( 11U ) +#define TKEY_TXENR2_TX27EN_Msk ( 0x1UL << TKEY_TXENR2_TX27EN_Pos ) +#define TKEY_TXENR2_TX27EN ( TKEY_TXENR2_TX27EN_Msk ) + +#define TKEY_TXENR2_TX26EN_Pos ( 10U ) +#define TKEY_TXENR2_TX26EN_Msk ( 0x1UL << TKEY_TXENR2_TX26EN_Pos ) +#define TKEY_TXENR2_TX26EN ( TKEY_TXENR1_TX26EN_Msk ) + +#define TKEY_TXENR2_TX25EN_Pos ( 9U ) +#define TKEY_TXENR2_TX25EN_Msk ( 0x1UL << TKEY_TXENR2_TX25EN_Pos ) +#define TKEY_TXENR2_TX25EN ( TKEY_TXENR2_TX25EN_Msk ) + +#define TKEY_TXENR2_TX24EN_Pos ( 8U ) +#define TKEY_TXENR2_TX24EN_Msk ( 0x1UL << TKEY_TXENR2_TX24EN_Pos ) +#define TKEY_TXENR2_TX24EN ( TKEY_TXENR2_TX24EN_Msk ) + +#define TKEY_TXENR2_TX23EN_Pos ( 7U ) +#define TKEY_TXENR2_TX23EN_Msk ( 0x1UL << TKEY_TXENR2_TX23EN_Pos ) +#define TKEY_TXENR2_TX23EN ( TKEY_TXENR2_TX23EN_Msk ) + +#define TKEY_TXENR2_TX22EN_Pos ( 6U ) +#define TKEY_TXENR2_TX22EN_Msk ( 0x1UL << TKEY_TXENR2_TX22EN_Pos ) +#define TKEY_TXENR2_TX22EN ( TKEY_TXENR2_TX22EN_Msk ) + +#define TKEY_TXENR2_TX21EN_Pos ( 5U ) +#define TKEY_TXENR2_TX21EN_Msk ( 0x1UL << TKEY_TXENR2_TX21EN_Pos ) +#define TKEY_TXENR2_TX21EN ( TKEY_TXENR2_TX21EN_Msk ) + +#define TKEY_TXENR2_TX20EN_Pos ( 4U ) +#define TKEY_TXENR2_TX20EN_Msk ( 0x1UL << TKEY_TXENR2_TX20EN_Pos ) +#define TKEY_TXENR2_TX20EN TKEY_TXENR2_TX20EN_Msk ) + +#define TKEY_TXENR2_TX19EN_Pos ( 3U ) +#define TKEY_TXENR2_TX19EN_Msk ( 0x1UL << TKEY_TXENR2_TX19EN_Pos ) +#define TKEY_TXENR2_TX19EN ( TKEY_TXENR2_TX19EN_Msk ) + +#define TKEY_TXENR2_TX18EN_Pos ( 2U ) +#define TKEY_TXENR2_TX18EN_Msk ( 0x1UL << TKEY_TXENR2_TX18EN_Pos ) +#define TKEY_TXENR2_TX18EN ( TKEY_TXENR2_TX18EN_Msk ) + +#define TKEY_TXENR2_TX17EN_Pos ( 1U ) +#define TKEY_TXENR2_TX17EN_Msk ( 0x1UL << TKEY_TXENR2_TX17EN_Pos ) +#define TKEY_TXENR2_TX17EN ( TKEY_TXENR2_TX17EN_Msk ) + +#define TKEY_TXENR2_TX16EN_Pos ( 0U ) +#define TKEY_TXENR2_TX16EN_Msk ( 0x1UL << TKEY_TXENR2_TX16EN_Pos ) +#define TKEY_TXENR2_TX16EN ( TKEY_TXENR2_TX16EN_Msk ) + + +/*************** Bits definition for OSPI_DAT **********************/ + +#define OSPI_TX_DAT_TX_DAT2_Pos ( 8U ) +#define OSPI_TX_DAT_TX_DAT2_Msk ( 0xffffffUL << OSPI_TX_DAT_TX_DAT2_Pos ) +#define OSPI_TX_DAT_TX_DAT2 ( OSPI_TX_DAT_TX_DAT2_Msk ) + +#define OSPI_TX_RX_DAT_Pos ( 0U ) +#define OSPI_TX_RX_DAT_Msk ( 0xffUL << OSPI_TX_DAT_TX_DAT1_Pos ) +#define OSPI_TX_RX_DAT ( OSPI_TX_DAT_TX_DAT1_Msk ) + + +/*************** Bits definition for OSPI_BAUD **********************/ + +#define OSPI_BAUD_DIV2_Pos ( 8U ) +#define OSPI_BAUD_DIV2_Msk ( 0xffUL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2 ( OSPI_BAUD_DIV2_Msk ) +#define OSPI_BAUD_DIV2_0 ( 0x1UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_1 ( 0x2UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_2 ( 0x4UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_3 ( 0x8UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_4 ( 0x10UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_5 ( 0x20UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_6 ( 0x40UL << OSPI_BAUD_DIV2_Pos ) +#define OSPI_BAUD_DIV2_7 ( 0x80UL << OSPI_BAUD_DIV2_Pos ) + +#define OSPI_BAUD_DIV1_Pos ( 0U ) +#define OSPI_BAUD_DIV1_Msk ( 0xffUL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1 ( OSPI_BAUD_DIV1_Msk ) +#define OSPI_BAUD_DIV1_0 ( 0x1UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_1 ( 0x2UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_2 ( 0x4UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_3 ( 0x8UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_4 ( 0x10UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_5 ( 0x20UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_6 ( 0x40UL << OSPI_BAUD_DIV1_Pos ) +#define OSPI_BAUD_DIV1_7 ( 0x80UL << OSPI_BAUD_DIV1_Pos ) + + +/*************** Bits definition for OSPI_CTL **********************/ + +#define OSPI_CTL_FR_MODE_Pos ( 30U ) +#define OSPI_CTL_FR_MODE_Msk ( 0x3UL << OSPI_CTL_FR_MODE_Pos ) +#define OSPI_CTL_FR_MODE ( OSPI_CTL_FR_MODE_Msk ) +#define OSPI_CTL_FR_MODE_0 ( 0x1UL << OSPI_CTL_FR_MODE_Pos ) +#define OSPI_CTL_FR_MODE_1 ( 0x2UL << OSPI_CTL_FR_MODE_Pos ) + +#define OSPI_CTL_FW_MODE_Pos ( 28U ) +#define OSPI_CTL_FW_MODE_Msk ( 0x3UL << OSPI_CTL_FW_MODE_Pos ) +#define OSPI_CTL_FW_MODE ( OSPI_CTL_FW_MODE_Msk ) +#define OSPI_CTL_FW_MODE_0 ( 0x1UL << OSPI_CTL_FW_MODE_Pos ) +#define OSPI_CTL_FW_MODE_1 ( 0x2UL << OSPI_CTL_FW_MODE_Pos ) + +#define OSPI_CTL_DMCTRL_Pos ( 27U ) +#define OSPI_CTL_DMCTRL_Msk ( 0x1UL << OSPI_CTL_DMCTRL_Pos ) +#define OSPI_CTL_DMCTRL ( OSPI_CTL_DMCTRL_Msk ) + +#define OSPI_CTL_DM_EN_Pos ( 26U ) +#define OSPI_CTL_DM_EN_Msk ( 0x1UL << OSPI_CTL_DM_EN_Pos ) +#define OSPI_CTL_DM_EN ( OSPI_CTL_DM_EN_Msk ) + +#define OSPI_CTL_APMD_CLK_Pos ( 23U ) +#define OSPI_CTL_APMD_CLK_Msk ( 0x7UL << OSPI_CTL_APMD_CLK_Pos ) +#define OSPI_CTL_APMD_CLK ( OSPI_CTL_APMD_CLK_Msk ) +#define OSPI_CTL_APMD_CLK_0 ( 0x1UL << OSPI_CTL_APMD_CLK_Pos ) +#define OSPI_CTL_APMD_CLK_1 ( 0x2UL << OSPI_CTL_APMD_CLK_Pos ) +#define OSPI_CTL_APMD_CLK_2 ( 0x4UL << OSPI_CTL_APMD_CLK_Pos ) + +#define OSPI_CTL_MEM_MODE_Pos ( 21U ) +#define OSPI_CTL_MEM_MODE_Msk ( 0x3UL << OSPI_CTL_MEM_MODE_Pos ) +#define OSPI_CTL_MEM_MODE ( OSPI_CTL_MEM_MODE_Msk ) +#define OSPI_CTL_MEM_MODE_0 ( 0x1UL << OSPI_CTL_MEM_MODE_Pos ) +#define OSPI_CTL_MEM_MODE_1 ( 0x2UL << OSPI_CTL_MEM_MODE_Pos ) + +#define OSPI_CTL_CS_TIME_Pos ( 11U ) +#define OSPI_CTL_CS_TIME_Msk ( 0xffUL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME ( OSPI_CTL_CS_TIME_Msk ) +#define OSPI_CTL_CS_TIME_0 ( 0x1UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_1 ( 0x2UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_2 ( 0x4UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_3 ( 0x8UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_4 ( 0x10UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_5 ( 0x20UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_6 ( 0x40UL << OSPI_CTL_CS_TIME_Pos ) +#define OSPI_CTL_CS_TIME_7 ( 0x80UL << OSPI_CTL_CS_TIME_Pos ) + +#define OSPI_CTL_DQSOE_Pos ( 9U ) +#define OSPI_CTL_DQSOE_Msk ( 0x1UL << OSPI_CTL_DQSOE_Pos ) +#define OSPI_CTL_DQSOE ( OSPI_CTL_DQSOE_Msk ) + +#define OSPI_CTL_DTRM_Pos ( 8U ) +#define OSPI_CTL_DTRM_Msk ( 0x1UL << OSPI_CTL_DTRM_Pos ) +#define OSPI_CTL_DTRM ( OSPI_CTL_DTRM_Msk ) + +#define OSPI_CTL_IO_MODE_Pos ( 7U ) +#define OSPI_CTL_IO_MODE_Msk ( 0x1UL << OSPI_CTL_IO_MODE_Pos ) +#define OSPI_CTL_IO_MODE ( OSPI_CTL_IO_MODE_Msk ) + +#define OSPI_CTL_X_MODE_Pos ( 5U ) +#define OSPI_CTL_X_MODE_Msk ( 0x3UL << OSPI_CTL_X_MODE_Pos ) +#define OSPI_CTL_X_MODE ( OSPI_CTL_X_MODE_Msk ) +#define OSPI_CTL_X_MODE_0 ( 0x1UL << OSPI_CTL_X_MODE_Pos ) +#define OSPI_CTL_X_MODE_1 ( 0x2UL << OSPI_CTL_X_MODE_Pos ) + +#define OSPI_CTL_LSB_FIRST_Pos ( 4U ) +#define OSPI_CTL_LSB_FIRST_Msk ( 0x1UL << OSPI_CTL_LSB_FIRST_Pos ) +#define OSPI_CTL_LSB_FIRST ( OSPI_CTL_LSB_FIRST_Msk ) + +#define OSPI_CTL_CPOL_Pos ( 3U ) +#define OSPI_CTL_CPOL_Msk ( 0x1UL << OSPI_CTL_CPOL_Pos ) +#define OSPI_CTL_CPOL ( OSPI_CTL_CPOL_Msk ) + +#define OSPI_CTL_CPHA_Pos ( 2U ) +#define OSPI_CTL_CPHA_Msk ( 0x1UL << OSPI_CTL_CPHA_Pos ) +#define OSPI_CTL_CPHA ( OSPI_CTL_CPHA_Msk ) + +#define OSPI_CTL_MST_MODE_Pos ( 0U ) +#define OSPI_CTL_MST_MODE_Msk ( 0x1UL << OSPI_CTL_MST_MODE_Pos ) +#define OSPI_CTL_MST_MODE ( OSPI_CTL_MST_MODE_Msk ) + + +/*************** Bits definition for OSPI_TX_CTL **********************/ + +#define OSPI_TX_CTL_OUTDLY_Pos ( 16U ) +#define OSPI_TX_CTL_OUTDLY_Msk ( 0x3UL << OSPI_TX_CTL_OUTDLY_Pos ) +#define OSPI_TX_CTL_OUTDLY ( OSPI_TX_CTL_OUTDLY_Msk ) +#define OSPI_TX_CTL_OUTDLY_0 ( 0x1UL << OSPI_TX_CTL_OUTDLY_Pos ) +#define OSPI_TX_CTL_OUTDLY_1 ( 0x2UL << OSPI_TX_CTL_OUTDLY_Pos ) + +#define OSPI_TX_CTL_DUMMY_Pos ( 8U ) +#define OSPI_TX_CTL_DUMMY_Msk ( 0xffUL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY ( OSPI_TX_CTL_DUMMY_Msk ) +#define OSPI_TX_CTL_DUMMY_0 ( 0x1UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_1 ( 0x2UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_2 ( 0x4UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_3 ( 0x8UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_4 ( 0x10UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_5 ( 0x20UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_6 ( 0x40UL << OSPI_TX_CTL_DUMMY_Pos ) +#define OSPI_TX_CTL_DUMMY_7 ( 0x80UL << OSPI_TX_CTL_DUMMY_Pos ) + +#define OSPI_TX_CTL_TX_DMA_LEVEL_Pos ( 4U ) +#define OSPI_TX_CTL_TX_DMA_LEVEL_Msk ( 0xfUL << OSPI_TX_CTL_TX_DMA_LEVEL_Pos ) +#define OSPI_TX_CTL_TX_DMA_LEVEL ( OSPI_TX_CTL_TX_DMA_LEVEL_Msk ) +#define OSPI_TX_CTL_TX_DMA_LEVEL_0 ( 0x1UL << OSPI_TX_CTL_TX_DMA_LEVEL_Pos ) +#define OSPI_TX_CTL_TX_DMA_LEVEL_1 ( 0x2UL << OSPI_TX_CTL_TX_DMA_LEVEL_Pos ) +#define OSPI_TX_CTL_TX_DMA_LEVEL_2 ( 0x4UL << OSPI_TX_CTL_TX_DMA_LEVEL_Pos ) +#define OSPI_TX_CTL_TX_DMA_LEVEL_3 ( 0x8UL << OSPI_TX_CTL_TX_DMA_LEVEL_Pos ) + +#define OSPI_TX_CTL_TX_DMA_REQ_EN_Pos ( 3U ) +#define OSPI_TX_CTL_TX_DMA_REQ_EN_Msk ( 0x1UL << OSPI_TX_CTL_TX_DMA_REQ_EN_Pos ) +#define OSPI_TX_CTL_TX_DMA_REQ_EN ( OSPI_TX_CTL_TX_DMA_REQ_EN_Msk ) + +#define OSPI_TX_CTL_TX_FIFO_RESET_Pos ( 1U ) +#define OSPI_TX_CTL_TX_FIFO_RESET_Msk ( 0x1UL << OSPI_TX_CTL_TX_FIFO_RESET_Pos ) +#define OSPI_TX_CTL_TX_FIFO_RESET ( OSPI_TX_CTL_TX_FIFO_RESET_Msk ) + +#define OSPI_TX_CTL_TX_EN_Pos ( 0U ) +#define OSPI_TX_CTL_TX_EN_Msk ( 0x1UL << OSPI_TX_CTL_TX_EN_Pos ) +#define OSPI_TX_CTL_TX_EN ( OSPI_TX_CTL_TX_EN_Msk ) + + +/*************** Bits definition for OSPI_RX_CTL **********************/ + +#define OSPI_RX_CTL_SSHIFT_Pos ( 28U ) +#define OSPI_RX_CTL_SSHIFT_Msk ( 0xfUL << OSPI_RX_CTL_SSHIFT_Pos ) +#define OSPI_RX_CTL_SSHIFT ( OSPI_RX_CTL_SSHIFT_Msk ) +#define OSPI_RX_CTL_SSHIFT_0 ( 0x1UL << OSPI_RX_CTL_SSHIFT_Pos ) +#define OSPI_RX_CTL_SSHIFT_1 ( 0x2UL << OSPI_RX_CTL_SSHIFT_Pos ) +#define OSPI_RX_CTL_SSHIFT_2 ( 0x4UL << OSPI_RX_CTL_SSHIFT_Pos ) +#define OSPI_RX_CTL_SSHIFT_3 ( 0x8UL << OSPI_RX_CTL_SSHIFT_Pos ) + +#define OSPI_RX_CTL_MSDHA_X7_Pos ( 26U ) +#define OSPI_RX_CTL_MSDHA_X7_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X7_Pos ) +#define OSPI_RX_CTL_MSDHA_X7 ( OSPI_RX_CTL_MSDHA_X7_Msk ) + +#define OSPI_RX_CTL_MSDHA_X6_Pos ( 25U ) +#define OSPI_RX_CTL_MSDHA_X6_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X6_Pos ) +#define OSPI_RX_CTL_MSDHA_X6 ( OSPI_RX_CTL_MSDHA_X6_Msk ) + +#define OSPI_RX_CTL_MSDHA_X5_Pos ( 24U ) +#define OSPI_RX_CTL_MSDHA_X5_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X5_Pos ) +#define OSPI_RX_CTL_MSDHA_X5 ( OSPI_RX_CTL_MSDHA_X5_Msk ) + +#define OSPI_RX_CTL_MSDHA_X4_Pos ( 23U ) +#define OSPI_RX_CTL_MSDHA_X4_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X4_Pos ) +#define OSPI_RX_CTL_MSDHA_X4 ( OSPI_RX_CTL_MSDHA_X4_Msk ) + +#define OSPI_RX_CTL_MSDHA_X3_Pos ( 22U ) +#define OSPI_RX_CTL_MSDHA_X3_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X3_Pos ) +#define OSPI_RX_CTL_MSDHA_X3 ( OSPI_RX_CTL_MSDHA_X3_Msk ) + +#define OSPI_RX_CTL_MSDHA_X2_Pos ( 21U ) +#define OSPI_RX_CTL_MSDHA_X2_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X2_Pos ) +#define OSPI_RX_CTL_MSDHA_X2 ( OSPI_RX_CTL_MSDHA_X2_Msk ) + +#define OSPI_RX_CTL_MSDHA_X1_Pos ( 20U ) +#define OSPI_RX_CTL_MSDHA_X1_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X1_Pos ) +#define OSPI_RX_CTL_MSDHA_X1 ( OSPI_RX_CTL_MSDHA_X1_Msk ) + +#define OSPI_RX_CTL_MSDHA_X0_Pos ( 19U ) +#define OSPI_RX_CTL_MSDHA_X0_Msk ( 0x1UL << OSPI_RX_CTL_MSDHA_X0_Pos ) +#define OSPI_RX_CTL_MSDHA_X0 ( OSPI_RX_CTL_MSDHA_X0_Msk ) + +#define OSPI_RX_CTL_MSDA_X7_Pos ( 18U ) +#define OSPI_RX_CTL_MSDA_X7_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X7_Pos ) +#define OSPI_RX_CTL_MSDA_X7 ( OSPI_RX_CTL_MSDA_X7_Msk ) + +#define OSPI_RX_CTL_MSDA_X6_Pos ( 17U ) +#define OSPI_RX_CTL_MSDA_X6_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X6_Pos ) +#define OSPI_RX_CTL_MSDA_X6 ( OSPI_RX_CTL_MSDA_X6_Msk ) + +#define OSPI_RX_CTL_MSDA_X5_Pos ( 16U ) +#define OSPI_RX_CTL_MSDA_X5_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X5_Pos ) +#define OSPI_RX_CTL_MSDA_X5 ( OSPI_RX_CTL_MSDA_X5_Msk ) + +#define OSPI_RX_CTL_MSDA_X4_Pos ( 15U ) +#define OSPI_RX_CTL_MSDA_X4_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X4_Pos ) +#define OSPI_RX_CTL_MSDA_X4 ( OSPI_RX_CTL_MSDA_X4_Msk ) + +#define OSPI_RX_CTL_MSDA_X3_Pos ( 14U ) +#define OSPI_RX_CTL_MSDA_X3_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X3_Pos ) +#define OSPI_RX_CTL_MSDA_X3 ( OSPI_RX_CTL_MSDA_X3_Msk ) + +#define OSPI_RX_CTL_MSDA_X2_Pos ( 13U ) +#define OSPI_RX_CTL_MSDA_X2_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X2_Pos ) +#define OSPI_RX_CTL_MSDA_X2 ( OSPI_RX_CTL_MSDA_X2_Msk ) + +#define OSPI_RX_CTL_MSDA_X1_Pos ( 12U ) +#define OSPI_RX_CTL_MSDA_X1_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X1_Pos ) +#define OSPI_RX_CTL_MSDA_X1 ( OSPI_RX_CTL_MSDA_X1_Msk ) + +#define OSPI_RX_CTL_MSDA_X0_Pos ( 11U ) +#define OSPI_RX_CTL_MSDA_X0_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_X0_Pos ) +#define OSPI_RX_CTL_MSDA_X0 ( OSPI_RX_CTL_MSDA_X0_Msk ) + +#define OSPI_RX_CTL_MSDA_EN_Pos ( 10U ) +#define OSPI_RX_CTL_MSDA_EN_Msk ( 0x1UL << OSPI_RX_CTL_MSDA_EN_Pos ) +#define OSPI_RX_CTL_MSDA_EN ( OSPI_RX_CTL_MSDA_EN_Msk ) + +#define OSPI_RX_CTL_DQS_SAMP_EN_Pos ( 8U ) +#define OSPI_RX_CTL_DQS_SAMP_EN_Msk ( 0x1UL << OSPI_RX_CTL_DQS_SAMP_EN_Pos ) +#define OSPI_RX_CTL_DQS_SAMP_EN ( OSPI_RX_CTL_DQS_SAMP_EN_Msk ) + +#define OSPI_RX_CTL_RX_DMA_LEVEL_Pos ( 4U ) +#define OSPI_RX_CTL_RX_DMA_LEVEL_Msk ( 0xfUL << OSPI_RX_CTL_RX_DMA_LEVEL_Pos ) +#define OSPI_RX_CTL_RX_DMA_LEVEL ( OSPI_RX_CTL_RX_DMA_LEVEL_Msk ) +#define OSPI_RX_CTL_RX_DMA_LEVEL_0 ( 0x1UL << OSPI_RX_CTL_RX_DMA_LEVEL_Pos ) +#define OSPI_RX_CTL_RX_DMA_LEVEL_1 ( 0x2UL << OSPI_RX_CTL_RX_DMA_LEVEL_Pos ) +#define OSPI_RX_CTL_RX_DMA_LEVEL_2 ( 0x4UL << OSPI_RX_CTL_RX_DMA_LEVEL_Pos ) +#define OSPI_RX_CTL_RX_DMA_LEVEL_3 ( 0x8UL << OSPI_RX_CTL_RX_DMA_LEVEL_Pos ) + +#define OSPI_RX_CTL_RX_DMA_REQ_EN_Pos ( 3U ) +#define OSPI_RX_CTL_RX_DMA_REQ_EN_Msk ( 0x1UL << OSPI_RX_CTL_RX_DMA_REQ_EN_Pos ) +#define OSPI_RX_CTL_RX_DMA_REQ_EN ( OSPI_RX_CTL_RX_DMA_REQ_EN_Msk ) + +#define OSPI_RX_CTL_RX_FIFO_RESET_Pos ( 1U ) +#define OSPI_RX_CTL_RX_FIFO_RESET_Msk ( 0x1UL << OSPI_RX_CTL_RX_FIFO_RESET_Pos ) +#define OSPI_RX_CTL_RX_FIFO_RESET ( OSPI_RX_CTL_RX_FIFO_RESET_Msk ) + +#define OSPI_RX_CTL_RX_EN_Pos ( 0U ) +#define OSPI_RX_CTL_RX_EN_Msk ( 0x1UL << OSPI_RX_CTL_RX_EN_Pos ) +#define OSPI_RX_CTL_RX_EN ( OSPI_RX_CTL_RX_EN_Msk ) + + +/*************** Bits definition for OSPI_IE **********************/ + +#define OSPI_IE_RX_BATCH_DONE_EN_Pos ( 15U ) +#define OSPI_IE_RX_BATCH_DONE_EN_Msk ( 0x1UL << OSPI_IE_RX_BATCH_DONE_EN_Pos ) +#define OSPI_IE_RX_BATCH_DONE_EN ( OSPI_IE_RX_BATCH_DONE_EN_Msk ) + +#define OSPI_IE_TX_BATCH_DONE_EN_Pos ( 14U ) +#define OSPI_IE_TX_BATCH_DONE_EN_Msk ( 0x1UL << OSPI_IE_TX_BATCH_DONE_EN_Pos ) +#define OSPI_IE_TX_BATCH_DONE_EN ( OSPI_IE_TX_BATCH_DONE_EN_Msk ) + +#define OSPI_IE_RX_FIFO_NOT_EMPTY_EN_Pos ( 11U ) +#define OSPI_IE_RX_FIFO_NOT_EMPTY_EN_Msk ( 0x1UL << OSPI_IE_RX_FIFO_NOT_EMPTY_EN_Pos ) +#define OSPI_IE_RX_FIFO_NOT_EMPTY_EN ( OSPI_IE_RX_FIFO_NOT_EMPTY_EN_Msk ) + +#define OSPI_IE_RX_FIFO_HALF_FULL_EN_Pos ( 9U ) +#define OSPI_IE_RX_FIFO_HALF_FULL_EN_Msk ( 0x1UL << OSPI_IE_RX_FIFO_HALF_FULL_EN_Pos ) +#define OSPI_IE_RX_FIFO_HALF_FULL_EN ( OSPI_IE_RX_FIFO_HALF_FULL_EN_Msk ) + +#define OSPI_IE_RX_FIFO_HALF_EMPTY_EN_Pos ( 8U ) +#define OSPI_IE_RX_FIFO_HALF_EMPTY_EN_Msk ( 0x1UL << OSPI_IE_RX_FIFO_HALF_EMPTY_EN_Pos ) +#define OSPI_IE_RX_FIFO_HALF_EMPTY_EN ( OSPI_IE_RX_FIFO_HALF_EMPTY_EN_Msk ) + +#define OSPI_IE_TX_FIFO_HALF_FULL_EN_Pos ( 7U ) +#define OSPI_IE_TX_FIFO_HALF_FULL_EN_Msk ( 0x1UL << OSPI_IE_TX_FIFO_HALF_FULL_EN_Pos ) +#define OSPI_IE_TX_FIFO_HALF_FULL_EN ( OSPI_IE_TX_FIFO_HALF_FULL_EN_Msk ) + +#define OSPI_IE_TX_FIFO_HALF_EMPTY_EN_Pos ( 6U ) +#define OSPI_IE_TX_FIFO_HALF_EMPTY_EN_Msk ( 0x1UL << OSPI_IE_TX_FIFO_HALF_EMPTY_EN_Pos ) +#define OSPI_IE_TX_FIFO_HALF_EMPTY_EN ( OSPI_IE_TX_FIFO_HALF_EMPTY_EN_Msk ) + +#define OSPI_IE_RX_FIFO_FULL_EN_Pos ( 5U ) +#define OSPI_IE_RX_FIFO_FULL_EN_Msk ( 0x1UL << OSPI_IE_RX_FIFO_FULL_EN_Pos ) +#define OSPI_IE_RX_FIFO_FULL_EN ( OSPI_IE_RX_FIFO_FULL_EN_Msk ) + +#define OSPI_IE_RX_FIFO_EMPTY_EN_Pos ( 4U ) +#define OSPI_IE_RX_FIFO_EMPTY_EN_Msk ( 0x1UL << OSPI_IE_RX_FIFO_EMPTY_EN_Pos ) +#define OSPI_IE_RX_FIFO_EMPTY_EN ( OSPI_IE_RX_FIFO_EMPTY_EN_Msk ) + +#define OSPI_IE_TX_FIFO_FULL_EN_Pos ( 3U ) +#define OSPI_IE_TX_FIFO_FULL_EN_Msk ( 0x1UL << OSPI_IE_TX_FIFO_FULL_EN_Pos ) +#define OSPI_IE_TX_FIFO_FULL_EN ( OSPI_IE_TX_FIFO_FULL_EN_Msk ) + +#define OSPI_IE_TX_FIFO_EMPTY_EN_Pos ( 2U ) +#define OSPI_IE_TX_FIFO_EMPTY_EN_Msk ( 0x1UL << OSPI_IE_TX_FIFO_EMPTY_EN_Pos ) +#define OSPI_IE_TX_FIFO_EMPTY_EN ( OSPI_IE_TX_FIFO_EMPTY_EN_Msk ) + +#define OSPI_IE_BATCH_DONE_EN_Pos ( 1U ) +#define OSPI_IE_BATCH_DONE_EN_Msk ( 0x1UL << OSPI_IE_BATCH_DONE_EN_Pos ) +#define OSPI_IE_BATCH_DONE_EN ( OSPI_IE_BATCH_DONE_EN_Msk ) + + +/*************** Bits definition for OSPI_STATUS **********************/ + + +#define OSPI_STATUS_INSTR_SEND_DONE_Pos ( 18U ) +#define OSPI_STATUS_INSTR_SEND_DONE_Msk ( 0x1UL << OSPI_STATUS_INSTR_SEND_DONE_Pos ) +#define OSPI_STATUS_INSTR_SEND_DONE ( OSPI_STATUS_INSTR_SEND_DONE_Msk ) + +#define OSPI_STATUS_RWDS_Pos ( 17U ) +#define OSPI_STATUS_RWDS_Msk ( 0x1UL << OSPI_STATUS_RWDS_Pos ) +#define OSPI_STATUS_RWDS ( OSPI_STATUS_RWDS_Msk ) + +#define OSPI_STATUS_APM_DUMY_DONE_Pos ( 16U ) +#define OSPI_STATUS_APM_DUMY_DONE_Msk ( 0x1UL << OSPI_STATUS_APM_DUMY_DONE_Pos ) +#define OSPI_STATUS_APM_DUMY_DONE ( OSPI_STATUS_APM_DUMY_DONE_Msk ) + +#define OSPI_STATUS_RX_BATCH_DONE_Pos ( 15U ) +#define OSPI_STATUS_RX_BATCH_DONE_Msk ( 0x1UL << OSPI_STATUS_RX_BATCH_DONE_Pos ) +#define OSPI_STATUS_RX_BATCH_DONE ( OSPI_STATUS_RX_BATCH_DONE_Msk ) + +#define OSPI_STATUS_TX_BATCH_DONE_Pos ( 14U ) +#define OSPI_STATUS_TX_BATCH_DONE_Msk ( 0x1UL << OSPI_STATUS_TX_BATCH_DONE_Pos ) +#define OSPI_STATUS_TX_BATCH_DONE ( OSPI_STATUS_TX_BATCH_DONE_Msk ) + +#define OSPI_STATUS_RX_FIFO_NOT_EMPTY_Pos ( 11U ) +#define OSPI_STATUS_RX_FIFO_NOT_EMPTY_Msk ( 0x1UL << OSPI_STATUS_RX_FIFO_NOT_EMPTY_Pos ) +#define OSPI_STATUS_RX_FIFO_NOT_EMPTY ( OSPI_STATUS_RX_FIFO_NOT_EMPTY_Msk ) + +#define OSPI_STATUS_RX_FIFO_HALF_FULL_Pos ( 9U ) +#define OSPI_STATUS_RX_FIFO_HALF_FULL_Msk ( 0x1UL << OSPI_STATUS_RX_FIFO_HALF_FULL_Pos ) +#define OSPI_STATUS_RX_FIFO_HALF_FULL ( OSPI_STATUS_RX_FIFO_HALF_FULL_Msk ) + +#define OSPI_STATUS_RX_FIFO_HALF_EMPTY_Pos ( 8U ) +#define OSPI_STATUS_RX_FIFO_HALF_EMPTY_Msk ( 0x1UL << OSPI_STATUS_RX_FIFO_HALF_EMPTY_Pos ) +#define OSPI_STATUS_RX_FIFO_HALF_EMPTY ( OSPI_STATUS_RX_FIFO_HALF_EMPTY_Msk ) + +#define OSPI_STATUS_TX_FIFO_HALF_FULL_Pos ( 7U ) +#define OSPI_STATUS_TX_FIFO_HALF_FULL_Msk ( 0x1UL << OSPI_STATUS_TX_FIFO_HALF_FULL_Pos ) +#define OSPI_STATUS_TX_FIFO_HALF_FULL ( OSPI_STATUS_TX_FIFO_HALF_FULL_Msk ) + +#define OSPI_STATUS_TX_FIFO_HALF_EMPTY_Pos ( 6U ) +#define OSPI_STATUS_TX_FIFO_HALF_EMPTY_Msk ( 0x1UL << OSPI_STATUS_TX_FIFO_HALF_EMPTY_Pos ) +#define OSPI_STATUS_TX_FIFO_HALF_EMPTY ( OSPI_STATUS_TX_FIFO_HALF_EMPTY_Msk ) + +#define OSPI_STATUS_RX_FIFO_FULL_Pos ( 5U ) +#define OSPI_STATUS_RX_FIFO_FULL_Msk ( 0x1UL << OSPI_STATUS_RX_FIFO_FULL_Pos ) +#define OSPI_STATUS_RX_FIFO_FULL ( OSPI_STATUS_RX_FIFO_FULL_Msk ) + +#define OSPI_STATUS_RX_FIFO_EMPTY_Pos ( 4U ) +#define OSPI_STATUS_RX_FIFO_EMPTY_Msk ( 0x1UL << OSPI_STATUS_RX_FIFO_EMPTY_Pos ) +#define OSPI_STATUS_RX_FIFO_EMPTY ( OSPI_STATUS_RX_FIFO_EMPTY_Msk ) + +#define OSPI_STATUS_TX_FIFO_FULL_Pos ( 3U ) +#define OSPI_STATUS_TX_FIFO_FULL_Msk ( 0x1UL << OSPI_STATUS_TX_FIFO_FULL_Pos ) +#define OSPI_STATUS_TX_FIFO_FULL ( OSPI_STATUS_TX_FIFO_FULL_Msk ) + +#define OSPI_STATUS_TX_FIFO_EMPTY_Pos ( 2U ) +#define OSPI_STATUS_TX_FIFO_EMPTY_Msk ( 0x1UL << OSPI_STATUS_TX_FIFO_EMPTY_Pos ) +#define OSPI_STATUS_TX_FIFO_EMPTY ( OSPI_STATUS_TX_FIFO_EMPTY_Msk ) + +#define OSPI_STATUS_BATCH_DONE_Pos ( 1U ) +#define OSPI_STATUS_BATCH_DONE_Msk ( 0x1UL << OSPI_STATUS_BATCH_DONE_Pos ) +#define OSPI_STATUS_BATCH_DONE ( OSPI_STATUS_BATCH_DONE_Msk ) + +#define OSPI_STATUS_TX_BUSY_Pos ( 0U ) +#define OSPI_STATUS_TX_BUSY_Msk ( 0x1UL << OSPI_STATUS_TX_BUSY_Pos ) +#define OSPI_STATUS_TX_BUSY ( OSPI_STATUS_TX_BUSY_Msk ) + + +/*************** Bits definition for OSPI_TXDelay **********************/ + +#define OSPI_TXDELAY_TDY_Pos ( 0U ) +#define OSPI_TXDELAY_TDY_Msk ( 0xffffffffUL << OSPI_TXDELAY_TDY_Pos ) +#define OSPI_TXDELAY_TDY ( OSPI_TXDELAY_TDY_Msk ) + + +/*************** Bits definition for OSPI_BATCH **********************/ + +#define OSPI_BATCH_BATCH_NUMBER_Pos ( 0U ) +#define OSPI_BATCH_BATCH_NUMBER_Msk ( 0xffffffffUL << OSPI_BATCH_BATCH_NUMBER_Pos ) +#define OSPI_BATCH_BATCH_NUMBER ( OSPI_BATCH_BATCH_NUMBER_Msk ) + + +/*************** Bits definition for OSPI_CS **********************/ + +#define OSPI_CS_CSMAP_EN_Pos ( 3U ) +#define OSPI_CS_CSMAP_EN_Msk ( 0x1UL << OSPI_CS_CSMAP_EN_Pos ) +#define OSPI_CS_CSMAP_EN ( OSPI_CS_CSMAP_EN_Msk ) + +#define OSPI_CS_CS_Pos ( 0U ) +#define OSPI_CS_CS_Msk ( 0x7UL << OSPI_CS_CS_Pos ) +#define OSPI_CS_CS ( OSPI_CS_CS_Msk ) +#define OSPI_CS_CS_0 ( 0x1UL << OSPI_CS_CS_Pos ) +#define OSPI_CS_CS_1 ( 0x2UL << OSPI_CS_CS_Pos ) +#define OSPI_CS_CS_2 ( 0x4UL << OSPI_CS_CS_Pos ) + + +/*************** Bits definition for OSPI_OUT_EN **********************/ + +#define OSPI_OUT_EN_IO7_EN_Pos ( 7U ) +#define OSPI_OUT_EN_IO7_EN_Msk ( 0x1UL << OSPI_OUT_EN_IO7_EN_Pos ) +#define OSPI_OUT_EN_IO7_EN ( OSPI_OUT_EN_IO7_EN_Msk ) + +#define OSPI_OUT_EN_IO6_EN_Pos ( 6U ) +#define OSPI_OUT_EN_IO6_EN_Msk ( 0x1UL << OSPI_OUT_EN_IO6_EN_Pos ) +#define OSPI_OUT_EN_IO6_EN ( OSPI_OUT_EN_IO6_EN_Msk ) + +#define OSPI_OUT_EN_IO5_EN_Pos ( 5U ) +#define OSPI_OUT_EN_IO5_EN_Msk ( 0x1UL << OSPI_OUT_EN_IO5_EN_Pos ) +#define OSPI_OUT_EN_IO5_EN ( OSPI_OUT_EN_IO5_EN_Msk ) + +#define OSPI_OUT_EN_IO4_EN_Pos ( 4U ) +#define OSPI_OUT_EN_IO4_EN_Msk ( 0x1UL << OSPI_OUT_EN_IO4_EN_Pos ) +#define OSPI_OUT_EN_IO4_EN ( OSPI_OUT_EN_IO4_EN_Msk ) + +#define OSPI_OUT_EN_HOLD_EN_Pos ( 3U ) +#define OSPI_OUT_EN_HOLD_EN_Msk ( 0x1UL << OSPI_OUT_EN_HOLD_EN_Pos ) +#define OSPI_OUT_EN_HOLD_EN ( OSPI_OUT_EN_HOLD_EN_Msk ) + +#define OSPI_OUT_EN_WP_EN_Pos ( 2U ) +#define OSPI_OUT_EN_WP_EN_Msk ( 0x1UL << OSPI_OUT_EN_WP_EN_Pos ) +#define OSPI_OUT_EN_WP_EN ( OSPI_OUT_EN_WP_EN_Msk ) + +#define OSPI_OUT_EN_MISO_EN_Pos ( 1U ) +#define OSPI_OUT_EN_MISO_EN_Msk ( 0x1UL << OSPI_OUT_EN_MISO_EN_Pos ) +#define OSPI_OUT_EN_MISO_EN ( OSPI_OUT_EN_MISO_EN_Msk ) + +#define OSPI_OUT_EN_MOSI_EN_Pos ( 0U ) +#define OSPI_OUT_EN_MOSI_EN_Msk ( 0x1UL << OSPI_OUT_EN_MOSI_EN_Pos ) +#define OSPI_OUT_EN_MOSI_EN ( OSPI_OUT_EN_MOSI_EN_Msk ) + + +/*************** Bits definition for OSPI_MEMO_ACC1 **********************/ + + +#define OSPI_MEMO_ACC1_HYPER_BT_Pos ( 27U ) +#define OSPI_MEMO_ACC1_HYPER_BT_Msk ( 0x1UL << OSPI_MEMO_ACC1_HYPER_BT_Pos ) +#define OSPI_MEMO_ACC1_HYPER_BT ( OSPI_MEMO_ACC1_HYPER_BT_Msk ) + +#define OSPI_MEMO_ACC1_DATA_MODE_Pos ( 25U ) +#define OSPI_MEMO_ACC1_DATA_MODE_Msk ( 0x3UL << OSPI_MEMO_ACC1_DATA_MODE_Pos ) +#define OSPI_MEMO_ACC1_DATA_MODE ( OSPI_MEMO_ACC1_DATA_MODE_Msk ) +#define OSPI_MEMO_ACC1_DATA_MODE_0 ( 0x1UL << OSPI_MEMO_ACC1_DATA_MODE_Pos ) +#define OSPI_MEMO_ACC1_DATA_MODE_1 ( 0x2UL << OSPI_MEMO_ACC1_DATA_MODE_Pos ) + +#define OSPI_MEMO_ACC1_ALTER_BYTE_MODE_Pos ( 23U ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_MODE_Msk ( 0x3UL << OSPI_MEMO_ACC1_ALTER_BYTE_MODE_Pos ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_MODE ( OSPI_MEMO_ACC1_ALTER_BYTE_MODE_Msk ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_MODE_0 ( 0x1UL << OSPI_MEMO_ACC1_ALTER_BYTE_MODE_Pos ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_MODE_1 ( 0x2UL << OSPI_MEMO_ACC1_ALTER_BYTE_MODE_Pos ) + +#define OSPI_MEMO_ACC1_ADDR_MODE_Pos ( 21U ) +#define OSPI_MEMO_ACC1_ADDR_MODE_Msk ( 0x3UL << OSPI_MEMO_ACC1_ADDR_MODE_Pos ) +#define OSPI_MEMO_ACC1_ADDR_MODE ( OSPI_MEMO_ACC1_ADDR_MODE_Msk ) +#define OSPI_MEMO_ACC1_ADDR_MODE_0 ( 0x1UL << OSPI_MEMO_ACC1_ADDR_MODE_Pos ) +#define OSPI_MEMO_ACC1_ADDR_MODE_1 ( 0x2UL << OSPI_MEMO_ACC1_ADDR_MODE_Pos ) + +#define OSPI_MEMO_ACC1_INSTR_MODE_Pos ( 19U ) +#define OSPI_MEMO_ACC1_INSTR_MODE_Msk ( 0x3UL << OSPI_MEMO_ACC1_INSTR_MODE_Pos ) +#define OSPI_MEMO_ACC1_INSTR_MODE ( OSPI_MEMO_ACC1_INSTR_MODE_Msk ) +#define OSPI_MEMO_ACC1_INSTR_MODE_0 ( 0x1UL << OSPI_MEMO_ACC1_INSTR_MODE_Pos ) +#define OSPI_MEMO_ACC1_INSTR_MODE_1 ( 0x2UL << OSPI_MEMO_ACC1_INSTR_MODE_Pos ) + +#define OSPI_MEMO_ACC1_ADDR_WIDTH_Pos ( 17U ) +#define OSPI_MEMO_ACC1_ADDR_WIDTH_Msk ( 0x3UL << OSPI_MEMO_ACC1_ADDR_WIDTH_Pos ) +#define OSPI_MEMO_ACC1_ADDR_WIDTH ( OSPI_MEMO_ACC1_ADDR_WIDTH_Msk ) +#define OSPI_MEMO_ACC1_ADDR_WIDTH_0 ( 0x1UL << OSPI_MEMO_ACC1_ADDR_WIDTH_Pos ) +#define OSPI_MEMO_ACC1_ADDR_WIDTH_1 ( 0x2UL << OSPI_MEMO_ACC1_ADDR_WIDTH_Pos ) + +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ( 12U ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Msk ( 0x1fUL << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE ( OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Msk ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_0 ( 0x1UL << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_1 ( 0x2UL << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_2 ( 0x4UL << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_3 ( 0x8UL << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_4 ( 0x10UL << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos ) + +#define OSPI_MEMO_ACC1_RD_DB_EN_Pos ( 11U ) +#define OSPI_MEMO_ACC1_RD_DB_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_RD_DB_EN_Pos ) +#define OSPI_MEMO_ACC1_RD_DB_EN ( OSPI_MEMO_ACC1_RD_DB_EN_Msk ) + +#define OSPI_MEMO_ACC1_WR_DB_EN_Pos ( 10U ) +#define OSPI_MEMO_ACC1_WR_DB_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_WR_DB_EN_Pos ) +#define OSPI_MEMO_ACC1_WR_DB_EN ( OSPI_MEMO_ACC1_WR_DB_EN_Msk ) + +#define OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_Pos ( 7U ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_Msk ( 0x3UL << OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_SIZE ( OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_Msk ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_0 ( 0x1UL << OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_Pos ) +#define OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_1 ( 0x2UL << OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_Pos ) + +#define OSPI_MEMO_ACC1_RD_AB_EN_Pos ( 6U ) +#define OSPI_MEMO_ACC1_RD_AB_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_RD_AB_EN_Pos ) +#define OSPI_MEMO_ACC1_RD_AB_EN ( OSPI_MEMO_ACC1_RD_AB_EN_Msk ) + +#define OSPI_MEMO_ACC1_WR_AB_EN_Pos ( 5U ) +#define OSPI_MEMO_ACC1_WR_AB_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_WR_AB_EN_Pos ) +#define OSPI_MEMO_ACC1_WR_AB_EN ( OSPI_MEMO_ACC1_WR_AB_EN_Msk ) + +#define OSPI_MEMO_ACC1_SEND_INSTR_ONCE_EN_Pos ( 4U ) +#define OSPI_MEMO_ACC1_SEND_INSTR_ONCE_EN_CMD_Msk ( 0x1UL << OSPI_MEMO_ACC1_SEND_INSTR_ONCE_EN_Pos ) +#define OSPI_MEMO_ACC1_SEND_INSTR_ONCE_EN ( OSPI_MEMO_ACC1_SEND_INSTR_ONCE_EN_CMD_Msk ) + +#define OSPI_MEMO_ACC1_CON_MODE_EN_Pos ( 3U ) +#define OSPI_MEMO_ACC1_CON_MODE_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_CON_MODE_EN_Pos ) +#define OSPI_MEMO_ACC1_CON_MODE_EN ( OSPI_MEMO_ACC1_CON_MODE_EN_Msk ) + +#define OSPI_MEMO_ACC1_CS_TIMEOUT_EN_Pos ( 1U ) +#define OSPI_MEMO_ACC1_CS_TIMEOUT_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_CS_TIMEOUT_EN_Pos ) +#define OSPI_MEMO_ACC1_CS_TIMEOUT_EN ( OSPI_MEMO_ACC1_CS_TIMEOUT_EN_Msk ) + +#define OSPI_MEMO_ACC1_ACC_EN_Pos ( 0U ) +#define OSPI_MEMO_ACC1_ACC_EN_Msk ( 0x1UL << OSPI_MEMO_ACC1_ACC_EN_Pos ) +#define OSPI_MEMO_ACC1_ACC_EN ( OSPI_MEMO_ACC1_ACC_EN_Msk ) + + +/*************** Bits definition for OSPI_CMD **********************/ + +#define OSPI_CMD_WR_CMD_Pos ( 8U ) +#define OSPI_CMD_WR_CMD_Msk ( 0xffUL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD ( OSPI_CMD_WR_CMD_Msk ) +#define OSPI_CMD_WR_CMD_0 ( 0x1UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_1 ( 0x2UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_2 ( 0x4UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_3 ( 0x8UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_4 ( 0x10UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_5 ( 0x20UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_6 ( 0x40UL << OSPI_CMD_WR_CMD_Pos ) +#define OSPI_CMD_WR_CMD_7 ( 0x80UL << OSPI_CMD_WR_CMD_Pos ) + +#define OSPI_CMD_RD_CMD_Pos ( 0U ) +#define OSPI_CMD_RD_CMD_Msk ( 0xffUL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD ( OSPI_CMD_RD_CMD_Msk ) +#define OSPI_CMD_RD_CMD_0 ( 0x1UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_1 ( 0x2UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_2 ( 0x4UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_3 ( 0x8UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_4 ( 0x10UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_5 ( 0x20UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_6 ( 0x40UL << OSPI_CMD_RD_CMD_Pos ) +#define OSPI_CMD_RD_CMD_7 ( 0x80UL << OSPI_CMD_RD_CMD_Pos ) + + +/*************** Bits definition for OSPI_ALTER_BYTE **********************/ + +#define OSPI_ALTER_BYTE_Pos ( 0U ) +#define OSPI_ALTER_BYTE_Msk ( 0xffffffffUL << OSPI_ALTER_BYTE_Pos ) +#define OSPI_ALTER_BYTE ( OSPI_ALTER_BYTE_Msk ) + + +/*************** Bits definition for OSPI_CS_TOUT_VAL **********************/ + +#define OSPI_CS_TIMEOUT_VAL_Pos ( 0U ) +#define OSPI_CS_TIMEOUT_VAL_Msk ( 0xffffUL << OSPI_CS_TIMEOUT_VAL_Pos ) +#define OSPI_CS_TIMEOUT_VAL ( OSPI_CS_TIMEOUT_VAL_Msk ) + + +/*************** Bits definition for OSPI_MEMO_ACC2 **********************/ + +#define OSPI_MEMO_ACC2_WRPS_Pos ( 12U ) +#define OSPI_MEMO_ACC2_WRPS_Msk ( 0xfUL << OSPI_MEMO_ACC2_WRPS_Pos ) +#define OSPI_MEMO_ACC2_WRPS ( OSPI_MEMO_ACC2_WRPS_Msk ) +#define OSPI_MEMO_ACC2_WRPS_0 ( 0x1UL << OSPI_MEMO_ACC2_WRPS_Pos ) +#define OSPI_MEMO_ACC2_WRPS_1 ( 0x2UL << OSPI_MEMO_ACC2_WRPS_Pos ) +#define OSPI_MEMO_ACC2_WRPS_2 ( 0x4UL << OSPI_MEMO_ACC2_WRPS_Pos ) + +#define OSPI_MEMO_ACC2_BL_Pos ( 8U ) +#define OSPI_MEMO_ACC2_BL_Msk ( 0xfUL << OSPI_MEMO_ACC2_BL_Pos ) +#define OSPI_MEMO_ACC2_BL ( OSPI_MEMO_ACC2_BL_Msk ) +#define OSPI_MEMO_ACC2_BL_0 ( 0x1UL << OSPI_MEMO_ACC2_BL_Pos ) +#define OSPI_MEMO_ACC2_BL_1 ( 0x2UL << OSPI_MEMO_ACC2_BL_Pos ) +#define OSPI_MEMO_ACC2_BL_2 ( 0x4UL << OSPI_MEMO_ACC2_BL_Pos ) + +#define OSPI_MEMO_ACC2_HXLC1_Pos ( 4U ) +#define OSPI_MEMO_ACC2_HXLC1_Msk ( 0xfUL << OSPI_MEMO_ACC2_HXLC1_Pos ) +#define OSPI_MEMO_ACC2_HXLC1 ( OSPI_MEMO_ACC2_HXLC1_Msk ) +#define OSPI_MEMO_ACC2_HXLC1_0 ( 0x1UL << OSPI_MEMO_ACC2_HXLC1_Pos ) +#define OSPI_MEMO_ACC2_HXLC1_1 ( 0x2UL << OSPI_MEMO_ACC2_HXLC1_Pos ) +#define OSPI_MEMO_ACC2_HXLC1_2 ( 0x4UL << OSPI_MEMO_ACC2_HXLC1_Pos ) +#define OSPI_MEMO_ACC2_HXLC1_3 ( 0x8UL << OSPI_MEMO_ACC2_HXLC1_Pos ) + +#define OSPI_MEMO_ACC2_HXLC0_Pos ( 0U ) +#define OSPI_MEMO_ACC2_HXLC0_Msk ( 0xfUL << OSPI_MEMO_ACC2_HXLC0_Pos ) +#define OSPI_MEMO_ACC2_HXLC0 ( OSPI_MEMO_ACC2_HXLC0_Msk ) +#define OSPI_MEMO_ACC2_HXLC0_0 ( 0x1UL << OSPI_MEMO_ACC2_HXLC0_Pos ) +#define OSPI_MEMO_ACC2_HXLC0_1 ( 0x2UL << OSPI_MEMO_ACC2_HXLC0_Pos ) +#define OSPI_MEMO_ACC2_HXLC0_2 ( 0x4UL << OSPI_MEMO_ACC2_HXLC0_Pos ) +#define OSPI_MEMO_ACC2_HXLC0_3 ( 0x8UL << OSPI_MEMO_ACC2_HXLC0_Pos ) + + + + +/*************** Bits definition for FMC_SNCTLx **********************/ + +#define FMC_SNCTLX_SYNCWR_Pos ( 19U ) +#define FMC_SNCTLX_SYNCWR_Msk ( 0x1UL << FMC_SNCTLX_SYNCWR_Pos ) +#define FMC_SNCTLX_SYNCWR ( FMC_SNCTLX_SYNCWR_Msk ) + +#define FMC_SNCTLX_CPS_Pos ( 16U ) +#define FMC_SNCTLX_CPS_Msk ( 0x7UL << FMC_SNCTLX_CPS_Pos ) +#define FMC_SNCTLX_CPS ( FMC_SNCTLX_CPS_Msk ) +#define FMC_SNCTLX_CPS_0 ( 0x1UL << FMC_SNCTLX_CPS_Pos ) +#define FMC_SNCTLX_CPS_1 ( 0x2UL << FMC_SNCTLX_CPS_Pos ) +#define FMC_SNCTLX_CPS_2 ( 0x4UL << FMC_SNCTLX_CPS_Pos ) + +#define FMC_SNCTLX_ASYNCWAIT_Pos ( 15U ) +#define FMC_SNCTLX_ASYNCWAIT_Msk ( 0x1UL << FMC_SNCTLX_ASYNCWAIT_Pos ) +#define FMC_SNCTLX_ASYNCWAIT ( FMC_SNCTLX_ASYNCWAIT_Msk ) + +#define FMC_SNCTLX_EXMODEN_Pos ( 14U ) +#define FMC_SNCTLX_EXMODEN_Msk ( 0x1UL << FMC_SNCTLX_EXMODEN_Pos ) +#define FMC_SNCTLX_EXMODEN ( FMC_SNCTLX_EXMODEN_Msk ) + +#define FMC_SNCTLX_NRWTEN_Pos ( 13U ) +#define FMC_SNCTLX_NRWTEN_Msk ( 0x1UL << FMC_SNCTLX_NRWTEN_Pos ) +#define FMC_SNCTLX_NRWTEN ( FMC_SNCTLX_NRWTEN_Msk ) + +#define FMC_SNCTLX_WREN_Pos ( 12U ) +#define FMC_SNCTLX_WREN_Msk ( 0x1UL << FMC_SNCTLX_WREN_Pos ) +#define FMC_SNCTLX_WREN ( FMC_SNCTLX_WREN_Msk ) + +#define FMC_SNCTLX_NRWTCFG_Pos ( 11U ) +#define FMC_SNCTLX_NRWTCFG_Msk ( 0x1UL << FMC_SNCTLX_NRWTCFG_Pos ) +#define FMC_SNCTLX_NRWTCFG ( FMC_SNCTLX_NRWTCFG_Msk ) + +#define FMC_SNCTLX_WRAPEN_Pos ( 10U ) +#define FMC_SNCTLX_WRAPEN_Msk ( 0x1UL << FMC_SNCTLX_WRAPEN_Pos ) +#define FMC_SNCTLX_WRAPEN ( FMC_SNCTLX_WRAPEN_Msk ) + +#define FMC_SNCTLX_NRWTPOL_Pos ( 9U ) +#define FMC_SNCTLX_NRWTPOL_Msk ( 0x1UL << FMC_SNCTLX_NRWTPOL_Pos ) +#define FMC_SNCTLX_NRWTPOL ( FMC_SNCTLX_NRWTPOL_Msk ) + +#define FMC_SNCTLX_SBRSTEN_Pos ( 8U ) +#define FMC_SNCTLX_SBRSTEN_Msk ( 0x1UL << FMC_SNCTLX_SBRSTEN_Pos ) +#define FMC_SNCTLX_SBRSTEN ( FMC_SNCTLX_SBRSTEN_Msk ) + +#define FMC_SNCTLX_NREN_Pos ( 6U ) +#define FMC_SNCTLX_NREN_Msk ( 0x1UL << FMC_SNCTLX_NREN_Pos ) +#define FMC_SNCTLX_NREN ( FMC_SNCTLX_NREN_Msk ) + +#define FMC_SNCTLX_NRW_Pos ( 4U ) +#define FMC_SNCTLX_NRW_Msk ( 0x3UL << FMC_SNCTLX_NRW_Pos ) +#define FMC_SNCTLX_NRW ( FMC_SNCTLX_NRW_Msk ) +#define FMC_SNCTLX_NRW_0 ( 0x1UL << FMC_SNCTLX_NRW_Pos ) +#define FMC_SNCTLX_NRW_1 ( 0x2UL << FMC_SNCTLX_NRW_Pos ) + +#define FMC_SNCTLX_NRTP_Pos ( 2U ) +#define FMC_SNCTLX_NRTP_Msk ( 0x3UL << FMC_SNCTLX_NRTP_Pos ) +#define FMC_SNCTLX_NRTP ( FMC_SNCTLX_NRTP_Msk ) +#define FMC_SNCTLX_NRTP_0 ( 0x1UL << FMC_SNCTLX_NRTP_Pos ) +#define FMC_SNCTLX_NRTP_1 ( 0x2UL << FMC_SNCTLX_NRTP_Pos ) + +#define FMC_SNCTLX_NRMUX_Pos ( 1U ) +#define FMC_SNCTLX_NRMUX_Msk ( 0x1UL << FMC_SNCTLX_NRMUX_Pos ) +#define FMC_SNCTLX_NRMUX ( FMC_SNCTLX_NRMUX_Msk ) + +#define FMC_SNCTLX_NRBKEN_Pos ( 0U ) +#define FMC_SNCTLX_NRBKEN_Msk ( 0x1UL << FMC_SNCTLX_NRBKEN_Pos ) +#define FMC_SNCTLX_NRBKEN ( FMC_SNCTLX_NRBKEN_Msk ) + + +/*************** Bits definition for FMC_SNTCFGx **********************/ + +#define FMC_SNTCFGX_ASYNCMOD_Pos ( 28U ) +#define FMC_SNTCFGX_ASYNCMOD_Msk ( 0x3UL << FMC_SNTCFGX_ASYNCMOD_Pos ) +#define FMC_SNTCFGX_ASYNCMOD ( FMC_SNTCFGX_ASYNCMOD_Msk ) +#define FMC_SNTCFGX_ASYNCMOD_0 ( 0x1UL << FMC_SNTCFGX_ASYNCMOD_Pos ) +#define FMC_SNTCFGX_ASYNCMOD_1 ( 0x2UL << FMC_SNTCFGX_ASYNCMOD_Pos ) + +#define FMC_SNTCFGX_DLAT_Pos ( 24U ) +#define FMC_SNTCFGX_DLAT_Msk ( 0xfUL << FMC_SNTCFGX_DLAT_Pos ) +#define FMC_SNTCFGX_DLAT ( FMC_SNTCFGX_DLAT_Msk ) +#define FMC_SNTCFGX_DLAT_0 ( 0x1UL << FMC_SNTCFGX_DLAT_Pos ) +#define FMC_SNTCFGX_DLAT_1 ( 0x2UL << FMC_SNTCFGX_DLAT_Pos ) +#define FMC_SNTCFGX_DLAT_2 ( 0x4UL << FMC_SNTCFGX_DLAT_Pos ) +#define FMC_SNTCFGX_DLAT_3 ( 0x8UL << FMC_SNTCFGX_DLAT_Pos ) + +#define FMC_SNTCFGX_CKDIV_Pos ( 20U ) +#define FMC_SNTCFGX_CKDIV_Msk ( 0xfUL << FMC_SNTCFGX_CKDIV_Pos ) +#define FMC_SNTCFGX_CKDIV ( FMC_SNTCFGX_CKDIV_Msk ) +#define FMC_SNTCFGX_CKDIV_0 ( 0x1UL << FMC_SNTCFGX_CKDIV_Pos ) +#define FMC_SNTCFGX_CKDIV_1 ( 0x2UL << FMC_SNTCFGX_CKDIV_Pos ) +#define FMC_SNTCFGX_CKDIV_2 ( 0x4UL << FMC_SNTCFGX_CKDIV_Pos ) +#define FMC_SNTCFGX_CKDIV_3 ( 0x8UL << FMC_SNTCFGX_CKDIV_Pos ) + +#define FMC_SNTCFGX_BUSLAT_Pos ( 16U ) +#define FMC_SNTCFGX_BUSLAT_Msk ( 0xfUL << FMC_SNTCFGX_BUSLAT_Pos ) +#define FMC_SNTCFGX_BUSLAT ( FMC_SNTCFGX_BUSLAT_Msk ) +#define FMC_SNTCFGX_BUSLAT_0 ( 0x1UL << FMC_SNTCFGX_BUSLAT_Pos ) +#define FMC_SNTCFGX_BUSLAT_1 ( 0x2UL << FMC_SNTCFGX_BUSLAT_Pos ) +#define FMC_SNTCFGX_BUSLAT_2 ( 0x4UL << FMC_SNTCFGX_BUSLAT_Pos ) +#define FMC_SNTCFGX_BUSLAT_3 ( 0x8UL << FMC_SNTCFGX_BUSLAT_Pos ) + +#define FMC_SNTCFGX_DSET_Pos ( 8U ) +#define FMC_SNTCFGX_DSET_Msk ( 0xffUL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET ( FMC_SNTCFGX_DSET_Msk ) +#define FMC_SNTCFGX_DSET_0 ( 0x1UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_1 ( 0x2UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_2 ( 0x4UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_3 ( 0x8UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_4 ( 0x10UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_5 ( 0x20UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_6 ( 0x40UL << FMC_SNTCFGX_DSET_Pos ) +#define FMC_SNTCFGX_DSET_7 ( 0x80UL << FMC_SNTCFGX_DSET_Pos ) + +#define FMC_SNTCFGX_AHLD_Pos ( 4U ) +#define FMC_SNTCFGX_AHLD_Msk ( 0xfUL << FMC_SNTCFGX_AHLD_Pos ) +#define FMC_SNTCFGX_AHLD ( FMC_SNTCFGX_AHLD_Msk ) +#define FMC_SNTCFGX_AHLD_0 ( 0x1UL << FMC_SNTCFGX_AHLD_Pos ) +#define FMC_SNTCFGX_AHLD_1 ( 0x2UL << FMC_SNTCFGX_AHLD_Pos ) +#define FMC_SNTCFGX_AHLD_2 ( 0x4UL << FMC_SNTCFGX_AHLD_Pos ) +#define FMC_SNTCFGX_AHLD_3 ( 0x8UL << FMC_SNTCFGX_AHLD_Pos ) + +#define FMC_SNTCFGX_ASET_Pos ( 0U ) +#define FMC_SNTCFGX_ASET_Msk ( 0xfUL << FMC_SNTCFGX_ASET_Pos ) +#define FMC_SNTCFGX_ASET ( FMC_SNTCFGX_ASET_Msk ) +#define FMC_SNTCFGX_ASET_0 ( 0x1UL << FMC_SNTCFGX_ASET_Pos ) +#define FMC_SNTCFGX_ASET_1 ( 0x2UL << FMC_SNTCFGX_ASET_Pos ) +#define FMC_SNTCFGX_ASET_2 ( 0x4UL << FMC_SNTCFGX_ASET_Pos ) +#define FMC_SNTCFGX_ASET_3 ( 0x8UL << FMC_SNTCFGX_ASET_Pos ) + + +/*************** Bits definition for FMC_SNWTCFGx **********************/ + +#define FMC_SNWTCFGX_WASYNCMOD_Pos ( 28U ) +#define FMC_SNWTCFGX_WASYNCMOD_Msk ( 0x3UL << FMC_SNWTCFGX_WASYNCMOD_Pos ) +#define FMC_SNWTCFGX_WASYNCMOD ( FMC_SNWTCFGX_WASYNCMOD_Msk ) +#define FMC_SNWTCFGX_WASYNCMOD_0 ( 0x1UL << FMC_SNWTCFGX_WASYNCMOD_Pos ) +#define FMC_SNWTCFGX_WASYNCMOD_1 ( 0x2UL << FMC_SNWTCFGX_WASYNCMOD_Pos ) + +#define FMC_SNWTCFGX_DLAT_Pos ( 24U ) +#define FMC_SNWTCFGX_DLAT_Msk ( 0xfUL << FMC_SNWTCFGX_DLAT_Pos ) +#define FMC_SNWTCFGX_DLAT ( FMC_SNWTCFGX_DLAT_Msk ) +#define FMC_SNWTCFGX_DLAT_0 ( 0x1UL << FMC_SNWTCFGX_DLAT_Pos ) +#define FMC_SNWTCFGX_DLAT_1 ( 0x2UL << FMC_SNWTCFGX_DLAT_Pos ) +#define FMC_SNWTCFGX_DLAT_2 ( 0x4UL << FMC_SNWTCFGX_DLAT_Pos ) +#define FMC_SNWTCFGX_DLAT_3 ( 0x8UL << FMC_SNWTCFGX_DLAT_Pos ) + +#define FMC_SNWTCFGX_WBUSLAT_Pos ( 16U ) +#define FMC_SNWTCFGX_WBUSLAT_Msk ( 0xfUL << FMC_SNWTCFGX_WBUSLAT_Pos ) +#define FMC_SNWTCFGX_WBUSLAT ( FMC_SNWTCFGX_WBUSLAT_Msk ) +#define FMC_SNWTCFGX_WBUSLAT_0 ( 0x1UL << FMC_SNWTCFGX_WBUSLAT_Pos ) +#define FMC_SNWTCFGX_WBUSLAT_1 ( 0x2UL << FMC_SNWTCFGX_WBUSLAT_Pos ) +#define FMC_SNWTCFGX_WBUSLAT_2 ( 0x4UL << FMC_SNWTCFGX_WBUSLAT_Pos ) +#define FMC_SNWTCFGX_WBUSLAT_3 ( 0x8UL << FMC_SNWTCFGX_WBUSLAT_Pos ) + +#define FMC_SNWTCFGX_WDSET_Pos ( 8U ) +#define FMC_SNWTCFGX_WDSET_Msk ( 0xffUL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET ( FMC_SNWTCFGX_WDSET_Msk ) +#define FMC_SNWTCFGX_WDSET_0 ( 0x1UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_1 ( 0x2UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_2 ( 0x4UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_3 ( 0x8UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_4 ( 0x10UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_5 ( 0x20UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_6 ( 0x40UL << FMC_SNWTCFGX_WDSET_Pos ) +#define FMC_SNWTCFGX_WDSET_7 ( 0x80UL << FMC_SNWTCFGX_WDSET_Pos ) + +#define FMC_SNWTCFGX_WAHLD_Pos ( 4U ) +#define FMC_SNWTCFGX_WAHLD_Msk ( 0xfUL << FMC_SNWTCFGX_WAHLD_Pos ) +#define FMC_SNWTCFGX_WAHLD ( FMC_SNWTCFGX_WAHLD_Msk ) +#define FMC_SNWTCFGX_WAHLD_0 ( 0x1UL << FMC_SNWTCFGX_WAHLD_Pos ) +#define FMC_SNWTCFGX_WAHLD_1 ( 0x2UL << FMC_SNWTCFGX_WAHLD_Pos ) +#define FMC_SNWTCFGX_WAHLD_2 ( 0x4UL << FMC_SNWTCFGX_WAHLD_Pos ) +#define FMC_SNWTCFGX_WAHLD_3 ( 0x8UL << FMC_SNWTCFGX_WAHLD_Pos ) + +#define FMC_SNWTCFGX_WASET_Pos ( 0U ) +#define FMC_SNWTCFGX_WASET_Msk ( 0xfUL << FMC_SNWTCFGX_WASET_Pos ) +#define FMC_SNWTCFGX_WASET ( FMC_SNWTCFGX_WASET_Msk ) +#define FMC_SNWTCFGX_WASET_0 ( 0x1UL << FMC_SNWTCFGX_WASET_Pos ) +#define FMC_SNWTCFGX_WASET_1 ( 0x2UL << FMC_SNWTCFGX_WASET_Pos ) +#define FMC_SNWTCFGX_WASET_2 ( 0x4UL << FMC_SNWTCFGX_WASET_Pos ) +#define FMC_SNWTCFGX_WASET_3 ( 0x8UL << FMC_SNWTCFGX_WASET_Pos ) + +/*************** Bits definition for FMC_SDRCR **********************/ + +#define FMC_SDRCR_WBUSRLS_Pos ( 20U ) +#define FMC_SDRCR_WBUSRLS_Msk ( 0x1UL << FMC_SDRCR_WBUSRLS_Pos ) +#define FMC_SDRCR_WBUSRLS ( FMC_SDRCR_WBUSRLS_Msk ) + +#define FMC_SDRCR_RBUSRLS_Pos ( 19U ) +#define FMC_SDRCR_RBUSRLS_Msk ( 0x1UL << FMC_SDRCR_RBUSRLS_Pos ) +#define FMC_SDRCR_RBUSRLS ( FMC_SDRCR_RBUSRLS_Msk ) + +#define FMC_SDRCR_BDEPTH_Pos ( 16U ) +#define FMC_SDRCR_BDEPTH_Msk ( 0x7UL << FMC_SDRCR_BDEPTH_Pos ) +#define FMC_SDRCR_BDEPTH_0 ( 0x1UL << FMC_SDRCR_BDEPTH_Pos ) +#define FMC_SDRCR_BDEPTH_1 ( 0x2UL << FMC_SDRCR_BDEPTH_Pos ) +#define FMC_SDRCR_BDEPTH_2 ( 0x4UL << FMC_SDRCR_BDEPTH_Pos ) + +#define FMC_SDRCR_W2RDLY_Pos ( 15U ) +#define FMC_SDRCR_W2RDLY_Msk ( 0x1UL << FMC_SDRCR_W2RDLY_Pos ) +#define FMC_SDRCR_W2RDLY ( FMC_SDRCR_W2RDLY_Msk ) + +#define FMC_SDRCR_RPIPE_Pos ( 13U ) +#define FMC_SDRCR_RPIPE_Msk ( 0x3UL << FMC_SDRCR_RPIPE_Pos ) +#define FMC_SDRCR_RPIPE ( FMC_SDRCR_RPIPE_Msk ) +#define FMC_SDRCR_RPIPE_0 ( 0x1UL << FMC_SDRCR_RPIPE_Pos ) +#define FMC_SDRCR_RPIPE_1 ( 0x2UL << FMC_SDRCR_RPIPE_Pos ) + +#define FMC_SDRCR_RBURST_Pos ( 12U ) +#define FMC_SDRCR_RBURST_Msk ( 0x1UL << FMC_SDRCR_RBURST_Pos ) +#define FMC_SDRCR_RBURST ( FMC_SDRCR_RBURST_Msk ) + +#define FMC_SDRCR_CLKDIV_Pos ( 10U ) +#define FMC_SDRCR_CLKDIV_Msk ( 0x3UL << FMC_SDRCR_CLKDIV_Pos ) +#define FMC_SDRCR_CLKDIV ( FMC_SDRCR_CLKDIV_Msk ) +#define FMC_SDRCR_CLKDIV_0 ( 0x1UL << FMC_SDRCR_CLKDIV_Pos ) +#define FMC_SDRCR_CLKDIV_1 ( 0x2UL << FMC_SDRCR_CLKDIV_Pos ) + +#define FMC_SDRCR_WP_Pos ( 9U ) +#define FMC_SDRCR_WP_Msk ( 0x1UL << FMC_SDRCR_WP_Pos ) +#define FMC_SDRCR_WP ( FMC_SDRCR_WP_Msk ) + +#define FMC_SDRCR_CAS_Pos ( 7U ) +#define FMC_SDRCR_CAS_Msk ( 0x3UL << FMC_SDRCR_CAS_Pos ) +#define FMC_SDRCR_CAS ( FMC_SDRCR_CAS_Msk ) +#define FMC_SDRCR_CAS_0 ( 0x1UL << FMC_SDRCR_CAS_Pos ) +#define FMC_SDRCR_CAS_1 ( 0x2UL << FMC_SDRCR_CAS_Pos ) + +#define FMC_SDRCR_NB_Pos ( 6U ) +#define FMC_SDRCR_NB_Msk ( 0x1UL << FMC_SDRCR_NB_Pos ) +#define FMC_SDRCR_NB ( FMC_SDRCR_NB_Msk ) + +#define FMC_SDRCR_MWID_Pos ( 4U ) +#define FMC_SDRCR_MWID_Msk ( 0x3UL << FMC_SDRCR_MWID_Pos ) +#define FMC_SDRCR_MWID ( FMC_SDRCR_MWID_Msk ) +#define FMC_SDRCR_MWID_0 ( 0x1UL << FMC_SDRCR_MWID_Pos ) +#define FMC_SDRCR_MWID_1 ( 0x2UL << FMC_SDRCR_MWID_Pos ) + +#define FMC_SDRCR_NRA_Pos ( 2U ) +#define FMC_SDRCR_NRA_Msk ( 0x3UL << FMC_SDRCR_NRA_Pos ) +#define FMC_SDRCR_NRA ( FMC_SDRCR_NRA_Msk ) +#define FMC_SDRCR_NRA_0 ( 0x1UL << FMC_SDRCR_NRA_Pos ) +#define FMC_SDRCR_NRA_1 ( 0x2UL << FMC_SDRCR_NRA_Pos ) + +#define FMC_SDRCR_NCA_Pos ( 0U ) +#define FMC_SDRCR_NCA_Msk ( 0x3UL << FMC_SDRCR_NCA_Pos ) +#define FMC_SDRCR_NCA ( FMC_SDRCR_NCA_Msk ) +#define FMC_SDRCR_NCA_0 ( 0x1UL << FMC_SDRCR_NCA_Pos ) +#define FMC_SDRCR_NCA_1 ( 0x2UL << FMC_SDRCR_NCA_Pos ) + + +/*************** Bits definition for FMC_SDRTR **********************/ + +#define FMC_SDRTR_TRCD_Pos ( 24U ) +#define FMC_SDRTR_TRCD_Msk ( 0xfUL << FMC_SDRTR_TRCD_Pos ) +#define FMC_SDRTR_TRCD ( FMC_SDRTR_TRCD_Msk ) +#define FMC_SDRTR_TRCD_0 ( 0x1UL << FMC_SDRTR_TRCD_Pos ) +#define FMC_SDRTR_TRCD_1 ( 0x2UL << FMC_SDRTR_TRCD_Pos ) +#define FMC_SDRTR_TRCD_2 ( 0x4UL << FMC_SDRTR_TRCD_Pos ) +#define FMC_SDRTR_TRCD_3 ( 0x8UL << FMC_SDRTR_TRCD_Pos ) + +#define FMC_SDRTR_TRP_Pos ( 20U ) +#define FMC_SDRTR_TRP_Msk ( 0xfUL << FMC_SDRTR_TRP_Pos ) +#define FMC_SDRTR_TRP ( FMC_SDRTR_TRP_Msk ) +#define FMC_SDRTR_TRP_0 ( 0x1UL << FMC_SDRTR_TRP_Pos ) +#define FMC_SDRTR_TRP_1 ( 0x2UL << FMC_SDRTR_TRP_Pos ) +#define FMC_SDRTR_TRP_2 ( 0x4UL << FMC_SDRTR_TRP_Pos ) +#define FMC_SDRTR_TRP_3 ( 0x8UL << FMC_SDRTR_TRP_Pos ) + +#define FMC_SDRTR_TWR_Pos ( 16U ) +#define FMC_SDRTR_TWR_Msk ( 0xfUL << FMC_SDRTR_TWR_Pos ) +#define FMC_SDRTR_TWR ( FMC_SDRTR_TWR_Msk ) +#define FMC_SDRTR_TWR_0 ( 0x1UL << FMC_SDRTR_TWR_Pos ) +#define FMC_SDRTR_TWR_1 ( 0x2UL << FMC_SDRTR_TWR_Pos ) +#define FMC_SDRTR_TWR_2 ( 0x4UL << FMC_SDRTR_TWR_Pos ) +#define FMC_SDRTR_TWR_3 ( 0x8UL << FMC_SDRTR_TWR_Pos ) + +#define FMC_SDRTR_TRC_Pos ( 12U ) +#define FMC_SDRTR_TRC_Msk ( 0xfUL << FMC_SDRTR_TRC_Pos ) +#define FMC_SDRTR_TRC ( FMC_SDRTR_TRC_Msk ) +#define FMC_SDRTR_TRC_0 ( 0x1UL << FMC_SDRTR_TRC_Pos ) +#define FMC_SDRTR_TRC_1 ( 0x2UL << FMC_SDRTR_TRC_Pos ) +#define FMC_SDRTR_TRC_2 ( 0x4UL << FMC_SDRTR_TRC_Pos ) +#define FMC_SDRTR_TRC_3 ( 0x8UL << FMC_SDRTR_TRC_Pos ) + +#define FMC_SDRTR_TRAS_Pos ( 8U ) +#define FMC_SDRTR_TRAS_Msk ( 0xfUL << FMC_SDRTR_TRAS_Pos ) +#define FMC_SDRTR_TRAS ( FMC_SDRTR_TRAS_Msk ) +#define FMC_SDRTR_TRAS_0 ( 0x1UL << FMC_SDRTR_TRAS_Pos ) +#define FMC_SDRTR_TRAS_1 ( 0x2UL << FMC_SDRTR_TRAS_Pos ) +#define FMC_SDRTR_TRAS_2 ( 0x4UL << FMC_SDRTR_TRAS_Pos ) +#define FMC_SDRTR_TRAS_3 ( 0x8UL << FMC_SDRTR_TRAS_Pos ) + +#define FMC_SDRTR_TXSR_Pos ( 4U ) +#define FMC_SDRTR_TXSR_Msk ( 0xfUL << FMC_SDRTR_TXSR_Pos ) +#define FMC_SDRTR_TXSR ( FMC_SDRTR_TXSR_Msk ) +#define FMC_SDRTR_TXSR_0 ( 0x1UL << FMC_SDRTR_TXSR_Pos ) +#define FMC_SDRTR_TXSR_1 ( 0x2UL << FMC_SDRTR_TXSR_Pos ) +#define FMC_SDRTR_TXSR_2 ( 0x4UL << FMC_SDRTR_TXSR_Pos ) +#define FMC_SDRTR_TXSR_3 ( 0x8UL << FMC_SDRTR_TXSR_Pos ) + +#define FMC_SDRTR_TMRD_Pos ( 0U ) +#define FMC_SDRTR_TMRD_Msk ( 0xfUL << FMC_SDRTR_TMRD_Pos ) +#define FMC_SDRTR_TMRD ( FMC_SDRTR_TMRD_Msk ) +#define FMC_SDRTR_TMRD_0 ( 0x1UL << FMC_SDRTR_TMRD_Pos ) +#define FMC_SDRTR_TMRD_1 ( 0x2UL << FMC_SDRTR_TMRD_Pos ) +#define FMC_SDRTR_TMRD_2 ( 0x4UL << FMC_SDRTR_TMRD_Pos ) +#define FMC_SDRTR_TMRD_3 ( 0x8UL << FMC_SDRTR_TMRD_Pos ) + + +/*************** Bits definition for FMC_SDRCMD **********************/ + +#define FMC_SDRCMD_MRD_Pos ( 9U ) +#define FMC_SDRCMD_MRD_Msk ( 0x1fffUL << FMC_SDRCMD_MRD_Pos ) +#define FMC_SDRCMD_MRD ( FMC_SDRCMD_MRD_Msk ) + +#define FMC_SDRCMD_NARF_Pos ( 5U ) +#define FMC_SDRCMD_NARF_Msk ( 0xfUL << FMC_SDRCMD_NARF_Pos ) +#define FMC_SDRCMD_NARF ( FMC_SDRCMD_NARF_Msk ) +#define FMC_SDRCMD_NARF_0 ( 0x1UL << FMC_SDRCMD_NARF_Pos ) +#define FMC_SDRCMD_NARF_1 ( 0x2UL << FMC_SDRCMD_NARF_Pos ) +#define FMC_SDRCMD_NARF_2 ( 0x4UL << FMC_SDRCMD_NARF_Pos ) +#define FMC_SDRCMD_NARF_3 ( 0x8UL << FMC_SDRCMD_NARF_Pos ) + +#define FMC_SDRCMD_CTD1_Pos ( 4U ) +#define FMC_SDRCMD_CTD1_Msk ( 0x1UL << FMC_SDRCMD_CTD1_Pos ) +#define FMC_SDRCMD_CTD1 ( FMC_SDRCMD_CTD1_Msk ) + +#define FMC_SDRCMD_CTD2_Pos ( 3U ) +#define FMC_SDRCMD_CTD2_Msk ( 0x1UL << FMC_SDRCMD_CTD2_Pos ) +#define FMC_SDRCMD_CTD2 ( FMC_SDRCMD_CTD2_Msk ) + +#define FMC_SDRCMD_CMD_Pos ( 0U ) +#define FMC_SDRCMD_CMD_Msk ( 0x7UL << FMC_SDRCMD_CMD_Pos ) +#define FMC_SDRCMD_CMD ( FMC_SDRCMD_CMD_Msk ) +#define FMC_SDRCMD_CMD_0 ( 0x1UL << FMC_SDRCMD_CMD_Pos ) +#define FMC_SDRCMD_CMD_1 ( 0x2UL << FMC_SDRCMD_CMD_Pos ) +#define FMC_SDRCMD_CMD_2 ( 0x4UL << FMC_SDRCMD_CMD_Pos ) + + +/*************** Bits definition for FMC_SDRART **********************/ + +#define FMC_SDRART_RFEIE_Pos ( 14U ) +#define FMC_SDRART_RFEIE_Msk ( 0x1UL << FMC_SDRART_RFEIE_Pos ) +#define FMC_SDRART_RFEIE ( FMC_SDRART_RFEIE_Msk ) + +#define FMC_SDRART_COUNT_Pos ( 1U ) +#define FMC_SDRART_COUNT_Msk ( 0x1fffUL << FMC_SDRART_COUNT_Pos ) +#define FMC_SDRART_COUNT ( FMC_SDRART_COUNT_Msk ) + +#define FMC_SDRART_CRFE_Pos ( 0U ) +#define FMC_SDRART_CRFE_Msk ( 0x1UL << FMC_SDRART_CRFE_Pos ) +#define FMC_SDRART_CRFE ( FMC_SDRART_CRFE_Msk ) + + +/*************** Bits definition for FMC_SDRSR **********************/ + +#define FMC_SDRSR_BUSY_Pos ( 5U ) +#define FMC_SDRSR_BUSY_Msk ( 0x1UL << FMC_SDRSR_BUSY_Pos ) +#define FMC_SDRSR_BUSY ( FMC_SDRSR_BUSY_Msk ) + +#define FMC_SDRSR_STA2_Pos ( 3U ) +#define FMC_SDRSR_STA2_Msk ( 0x3UL << FMC_SDRSR_STA2_Pos ) +#define FMC_SDRSR_STA2 ( FMC_SDRSR_STA2_Msk ) +#define FMC_SDRSR_STA2_0 ( 0x1UL << FMC_SDRSR_STA2_Pos ) +#define FMC_SDRSR_STA2_1 ( 0x2UL << FMC_SDRSR_STA2_Pos ) + +#define FMC_SDRSR_STA1_Pos ( 1U ) +#define FMC_SDRSR_STA1_Msk ( 0x3UL << FMC_SDRSR_STA1_Pos ) +#define FMC_SDRSR_STA1 ( FMC_SDRSR_STA1_Msk ) +#define FMC_SDRSR_STA1_0 ( 0x1UL << FMC_SDRSR_STA1_Pos ) +#define FMC_SDRSR_STA1_1 ( 0x2UL << FMC_SDRSR_STA1_Pos ) + +#define FMC_SDRSR_RFE_Pos ( 0U ) +#define FMC_SDRSR_RFE_Msk ( 0x1UL << FMC_SDRSR_RFE_Pos ) +#define FMC_SDRSR_RFE ( FMC_SDRSR_RFE_Msk ) + + +/*************** Bits definition for FMC_SDRSMA1 **********************/ + +#define FMC_SDRSMA_SMA1_Pos ( 0U ) +#define FMC_SDRSMA_SMA1_Msk ( 0xffffffffUL << FMC_SDRSMA_SMA1_Pos ) +#define FMC_SDRSMA_SMA1 ( FMC_SDRSMA_SMA1_Msk ) + +/*************** Bits definition for FMC_SDRSMA2 **********************/ + +#define FMC_SDRSMA_SMA2_Pos ( 0U ) +#define FMC_SDRSMA_SMA2_Msk ( 0xffffffffUL << FMC_SDRSMA_SMA2_Pos ) +#define FMC_SDRSMA_SMA2 ( FMC_SDRSMA_SMA2_Msk ) + +/*************** Bits definition for LPTIM_ISR **********************/ + +#define LPTIM_ISR_REPOK_Pos ( 8U ) +#define LPTIM_ISR_REPOK_Msk ( 0x1UL << LPTIM_ISR_REPOK_Pos ) +#define LPTIM_ISR_REPOK ( LPTIM_ISR_REPOK_Msk ) + +#define LPTIM_ISR_REPUE_Pos ( 7U ) +#define LPTIM_ISR_REPUE_Msk ( 0x1UL << LPTIM_ISR_REPUE_Pos ) +#define LPTIM_ISR_REPUE ( LPTIM_ISR_REPUE_Msk ) + +#define LPTIM_ISR_DOWN_Pos ( 6U ) +#define LPTIM_ISR_DOWN_Msk ( 0x1UL << LPTIM_ISR_DOWN_Pos ) +#define LPTIM_ISR_DOWN ( LPTIM_ISR_DOWN_Msk ) + +#define LPTIM_ISR_UP_Pos ( 5U ) +#define LPTIM_ISR_UP_Msk ( 0x1UL << LPTIM_ISR_UP_Pos ) +#define LPTIM_ISR_UP ( LPTIM_ISR_UP_Msk ) + +#define LPTIM_ISR_ARROK_Pos ( 4U ) +#define LPTIM_ISR_ARROK_Msk ( 0x1UL << LPTIM_ISR_ARROK_Pos ) +#define LPTIM_ISR_ARROK ( LPTIM_ISR_ARROK_Msk ) + +#define LPTIM_ISR_CMPOK_Pos ( 3U ) +#define LPTIM_ISR_CMPOK_Msk ( 0x1UL << LPTIM_ISR_CMPOK_Pos ) +#define LPTIM_ISR_CMPOK ( LPTIM_ISR_CMPOK_Msk ) + +#define LPTIM_ISR_EXTTRIG_Pos ( 2U ) +#define LPTIM_ISR_EXTTRIG_Msk ( 0x1UL << LPTIM_ISR_EXTTRIG_Pos ) +#define LPTIM_ISR_EXTTRIG ( LPTIM_ISR_EXTTRIG_Msk ) + +#define LPTIM_ISR_ARRM_Pos ( 1U ) +#define LPTIM_ISR_ARRM_Msk ( 0x1UL << LPTIM_ISR_ARRM_Pos ) +#define LPTIM_ISR_ARRM ( LPTIM_ISR_ARRM_Msk ) + +#define LPTIM_ISR_CMPM_Pos ( 0U ) +#define LPTIM_ISR_CMPM_Msk ( 0x1UL << LPTIM_ISR_CMPM_Pos ) +#define LPTIM_ISR_CMPM ( LPTIM_ISR_CMPM_Msk ) + + +/*************** Bits definition for LPTIM_ICR **********************/ + +#define LPTIM_ICR_REPOKCF_Pos ( 8U ) +#define LPTIM_ICR_REPOKCF_Msk ( 0x1UL << LPTIM_ICR_REPOKCF_Pos ) +#define LPTIM_ICR_REPOKCF ( LPTIM_ICR_REPOKCF_Msk ) + +#define LPTIM_ICR_REPUECF_Pos ( 7U ) +#define LPTIM_ICR_REPUECF_Msk ( 0x1UL << LPTIM_ICR_REPUECF_Pos ) +#define LPTIM_ICR_REPUECF ( LPTIM_ICR_REPUECF_Msk ) + +#define LPTIM_ICR_DOWNCF_Pos ( 6U ) +#define LPTIM_ICR_DOWNCF_Msk ( 0x1UL << LPTIM_ICR_DOWNCF_Pos ) +#define LPTIM_ICR_DOWNCF ( LPTIM_ICR_DOWNCF_Msk ) + +#define LPTIM_ICR_UPCF_Pos ( 5U ) +#define LPTIM_ICR_UPCF_Msk ( 0x1UL << LPTIM_ICR_UPCF_Pos ) +#define LPTIM_ICR_UPCF ( LPTIM_ICR_UPCF_Msk ) + +#define LPTIM_ICR_ARROKCF_Pos ( 4U ) +#define LPTIM_ICR_ARROKCF_Msk ( 0x1UL << LPTIM_ICR_ARROKCF_Pos ) +#define LPTIM_ICR_ARROKCF ( LPTIM_ICR_ARROKCF_Msk ) + +#define LPTIM_ICR_CMPOKCF_Pos ( 3U ) +#define LPTIM_ICR_CMPOKCF_Msk ( 0x1UL << LPTIM_ICR_CMPOKCF_Pos ) +#define LPTIM_ICR_CMPOKCF ( LPTIM_ICR_CMPOKCF_Msk ) + +#define LPTIM_ICR_EXTTRIGCF_Pos ( 2U ) +#define LPTIM_ICR_EXTTRIGCF_Msk ( 0x1UL << LPTIM_ICR_EXTTRIGCF_Pos ) +#define LPTIM_ICR_EXTTRIGCF ( LPTIM_ICR_EXTTRIGCF_Msk ) + +#define LPTIM_ICR_ARRMCF_Pos ( 1U ) +#define LPTIM_ICR_ARRMCF_Msk ( 0x1UL << LPTIM_ICR_ARRMCF_Pos ) +#define LPTIM_ICR_ARRMCF ( LPTIM_ICR_ARRMCF_Msk ) + +#define LPTIM_ICR_CMPMCF_Pos ( 0U ) +#define LPTIM_ICR_CMPMCF_Msk ( 0x1UL << LPTIM_ICR_CMPMCF_Pos ) +#define LPTIM_ICR_CMPMCF ( LPTIM_ICR_CMPMCF_Msk ) + + +/*************** Bits definition for LPTIM_IER **********************/ + +#define LPTIM_IER_REPOKIE_Pos ( 8U ) +#define LPTIM_IER_REPOKIE_Msk ( 0x1UL << LPTIM_IER_REPOKIE_Pos ) +#define LPTIM_IER_REPOKIE ( LPTIM_IER_REPOKIE_Msk ) + +#define LPTIM_IER_REPUEIE_Pos ( 7U ) +#define LPTIM_IER_REPUEIE_Msk ( 0x1UL << LPTIM_IER_REPUEIE_Pos ) +#define LPTIM_IER_REPUEIE ( LPTIM_IER_REPUEIE_Msk ) + +#define LPTIM_IER_DOWNIE_Pos ( 6U ) +#define LPTIM_IER_DOWNIE_Msk ( 0x1UL << LPTIM_IER_DOWNIE_Pos ) +#define LPTIM_IER_DOWNIE ( LPTIM_IER_DOWNIE_Msk ) + +#define LPTIM_IER_UPIE_Pos ( 5U ) +#define LPTIM_IER_UPIE_Msk ( 0x1UL << LPTIM_IER_UPIE_Pos ) +#define LPTIM_IER_UPIE ( LPTIM_IER_UPIE_Msk ) + +#define LPTIM_IER_ARROKIE_Pos ( 4U ) +#define LPTIM_IER_ARROKIE_Msk ( 0x1UL << LPTIM_IER_ARROKIE_Pos ) +#define LPTIM_IER_ARROKIE ( LPTIM_IER_ARROKIE_Msk ) + +#define LPTIM_IER_CMPOKIE_Pos ( 3U ) +#define LPTIM_IER_CMPOKIE_Msk ( 0x1UL << LPTIM_IER_CMPOKIE_Pos ) +#define LPTIM_IER_CMPOKIE ( LPTIM_IER_CMPOKIE_Msk ) + +#define LPTIM_IER_EXTTRIGIE_Pos ( 2U ) +#define LPTIM_IER_EXTTRIGIE_Msk ( 0x1UL << LPTIM_IER_EXTTRIGIE_Pos ) +#define LPTIM_IER_EXTTRIGIE ( LPTIM_IER_EXTTRIGIE_Msk ) + +#define LPTIM_IER_ARRMIE_Pos ( 1U ) +#define LPTIM_IER_ARRMIE_Msk ( 0x1UL << LPTIM_IER_ARRMIE_Pos ) +#define LPTIM_IER_ARRMIE ( LPTIM_IER_ARRMIE_Msk ) + +#define LPTIM_IER_CMPMIE_Pos ( 0U ) +#define LPTIM_IER_CMPMIE_Msk ( 0x1UL << LPTIM_IER_CMPMIE_Pos ) +#define LPTIM_IER_CMPMIE ( LPTIM_IER_CMPMIE_Msk ) + + +/*************** Bits definition for LPTIM_CFGR1 **********************/ + +#define LPTIM_CFGR1_REP_LODMOD_Pos ( 25U ) +#define LPTIM_CFGR1_REP_LODMOD_Msk ( 0x1UL << LPTIM_CFGR1_REP_LODMOD_Pos ) +#define LPTIM_CFGR1_REP_LODMOD ( LPTIM_CFGR1_REP_LODMOD_Msk ) + +#define LPTIM_CFGR1_ENC_Pos ( 24U ) +#define LPTIM_CFGR1_ENC_Msk ( 0x1UL << LPTIM_CFGR1_ENC_Pos ) +#define LPTIM_CFGR1_ENC ( LPTIM_CFGR1_ENC_Msk ) + +#define LPTIM_CFGR1_COUNTMODE_Pos ( 23U ) +#define LPTIM_CFGR1_COUNTMODE_Msk ( 0x1UL << LPTIM_CFGR1_COUNTMODE_Pos ) +#define LPTIM_CFGR1_COUNTMODE ( LPTIM_CFGR1_COUNTMODE_Msk ) + +#define LPTIM_CFGR1_PRELOAD_Pos ( 22U ) +#define LPTIM_CFGR1_PRELOAD_Msk ( 0x1UL << LPTIM_CFGR1_PRELOAD_Pos ) +#define LPTIM_CFGR1_PRELOAD ( LPTIM_CFGR1_PRELOAD_Msk ) + +#define LPTIM_CFGR1_WAVPOL_Pos ( 21U ) +#define LPTIM_CFGR1_WAVPOL_Msk ( 0x1UL << LPTIM_CFGR1_WAVPOL_Pos ) +#define LPTIM_CFGR1_WAVPOL ( LPTIM_CFGR1_WAVPOL_Msk ) + +#define LPTIM_CFGR1_WAVE_Pos ( 20U ) +#define LPTIM_CFGR1_WAVE_Msk ( 0x1UL << LPTIM_CFGR1_WAVE_Pos ) +#define LPTIM_CFGR1_WAVE ( LPTIM_CFGR1_WAVE_Msk ) + +#define LPTIM_CFGR1_TIMEOUT_Pos ( 19U ) +#define LPTIM_CFGR1_TIMEOUT_Msk ( 0x1UL << LPTIM_CFGR1_TIMEOUT_Pos ) +#define LPTIM_CFGR1_TIMEOUT ( LPTIM_CFGR1_TIMEOUT_Msk ) + +#define LPTIM_CFGR1_TRIGEN_Pos ( 17U ) +#define LPTIM_CFGR1_TRIGEN_Msk ( 0x3UL << LPTIM_CFGR1_TRIGEN_Pos ) +#define LPTIM_CFGR1_TRIGEN ( LPTIM_CFGR1_TRIGEN_Msk ) +#define LPTIM_CFGR1_TRIGEN_0 ( 0x1UL << LPTIM_CFGR1_TRIGEN_Pos ) +#define LPTIM_CFGR1_TRIGEN_1 ( 0x2UL << LPTIM_CFGR1_TRIGEN_Pos ) + +#define LPTIM_CFGR1_TRIGSEL_Pos ( 13U ) +#define LPTIM_CFGR1_TRIGSEL_Msk ( 0xfUL << LPTIM_CFGR1_TRIGSEL_Pos ) +#define LPTIM_CFGR1_TRIGSEL ( LPTIM_CFGR1_TRIGSEL_Msk ) +#define LPTIM_CFGR1_TRIGSEL_0 ( 0x1UL << LPTIM_CFGR1_TRIGSEL_Pos ) +#define LPTIM_CFGR1_TRIGSEL_1 ( 0x2UL << LPTIM_CFGR1_TRIGSEL_Pos ) +#define LPTIM_CFGR1_TRIGSEL_2 ( 0x4UL << LPTIM_CFGR1_TRIGSEL_Pos ) +#define LPTIM_CFGR1_TRIGSEL_3 ( 0x8UL << LPTIM_CFGR1_TRIGSEL_Pos ) + +#define LPTIM_CFGR1_PRESC_Pos ( 9U ) +#define LPTIM_CFGR1_PRESC_Msk ( 0x7UL << LPTIM_CFGR1_PRESC_Pos ) +#define LPTIM_CFGR1_PRESC ( LPTIM_CFGR1_PRESC_Msk ) +#define LPTIM_CFGR1_PRESC_0 ( 0x1UL << LPTIM_CFGR1_PRESC_Pos ) +#define LPTIM_CFGR1_PRESC_1 ( 0x2UL << LPTIM_CFGR1_PRESC_Pos ) +#define LPTIM_CFGR1_PRESC_2 ( 0x4UL << LPTIM_CFGR1_PRESC_Pos ) + +#define LPTIM_CFGR1_TRGFLT_Pos ( 6U ) +#define LPTIM_CFGR1_TRGFLT_Msk ( 0x3UL << LPTIM_CFGR1_TRGFLT_Pos ) +#define LPTIM_CFGR1_TRGFLT ( LPTIM_CFGR1_TRGFLT_Msk ) +#define LPTIM_CFGR1_TRGFLT_0 ( 0x1UL << LPTIM_CFGR1_TRGFLT_Pos ) +#define LPTIM_CFGR1_TRGFLT_1 ( 0x2UL << LPTIM_CFGR1_TRGFLT_Pos ) + +#define LPTIM_CFGR1_CKFLT_Pos ( 3U ) +#define LPTIM_CFGR1_CKFLT_Msk ( 0x3UL << LPTIM_CFGR1_CKFLT_Pos ) +#define LPTIM_CFGR1_CKFLT ( LPTIM_CFGR1_CKFLT_Msk ) +#define LPTIM_CFGR1_CKFLT_0 ( 0x1UL << LPTIM_CFGR1_CKFLT_Pos ) +#define LPTIM_CFGR1_CKFLT_1 ( 0x2UL << LPTIM_CFGR1_CKFLT_Pos ) + +#define LPTIM_CFGR1_CKPOL_Pos ( 1U ) +#define LPTIM_CFGR1_CKPOL_Msk ( 0x3UL << LPTIM_CFGR1_CKPOL_Pos ) +#define LPTIM_CFGR1_CKPOL ( LPTIM_CFGR1_CKPOL_Msk ) +#define LPTIM_CFGR1_CKPOL_0 ( 0x1UL << LPTIM_CFGR1_CKPOL_Pos ) +#define LPTIM_CFGR1_CKPOL_1 ( 0x2UL << LPTIM_CFGR1_CKPOL_Pos ) + +#define LPTIM_CFGR1_CKSEL_Pos ( 0U ) +#define LPTIM_CFGR1_CKSEL_Msk ( 0x1UL << LPTIM_CFGR1_CKSEL_Pos ) +#define LPTIM_CFGR1_CKSEL ( LPTIM_CFGR1_CKSEL_Msk ) + + +/*************** Bits definition for LPTIM_CR **********************/ + +#define LPTIM_CR_RSTARE_Pos ( 4U ) +#define LPTIM_CR_RSTARE_Msk ( 0x1UL << LPTIM_CR_RSTARE_Pos ) +#define LPTIM_CR_RSTARE ( LPTIM_CR_RSTARE_Msk ) + +#define LPTIM_CR_COUNTRST_Pos ( 3U ) +#define LPTIM_CR_COUNTRST_Msk ( 0x1UL << LPTIM_CR_COUNTRST_Pos ) +#define LPTIM_CR_COUNTRST ( LPTIM_CR_COUNTRST_Msk ) + +#define LPTIM_CR_CNTSTRT_Pos ( 2U ) +#define LPTIM_CR_CNTSTRT_Msk ( 0x1UL << LPTIM_CR_CNTSTRT_Pos ) +#define LPTIM_CR_CNTSTRT ( LPTIM_CR_CNTSTRT_Msk ) + +#define LPTIM_CR_SNGSTRT_Pos ( 1U ) +#define LPTIM_CR_SNGSTRT_Msk ( 0x1UL << LPTIM_CR_SNGSTRT_Pos ) +#define LPTIM_CR_SNGSTRT ( LPTIM_CR_SNGSTRT_Msk ) + +#define LPTIM_CR_ENABLE_Pos ( 0U ) +#define LPTIM_CR_ENABLE_Msk ( 0x1UL << LPTIM_CR_ENABLE_Pos ) +#define LPTIM_CR_ENABLE ( LPTIM_CR_ENABLE_Msk ) + + +/*************** Bits definition for LPTIM_CMP **********************/ + +#define LPTIM_CMP_CMP_Pos ( 0U ) +#define LPTIM_CMP_CMP_Msk ( 0xffffUL << LPTIM_CMP_CMP_Pos ) +#define LPTIM_CMP_CMP ( LPTIM_CMP_CMP_Msk ) + + +/*************** Bits definition for LPTIM_ARR **********************/ + +#define LPTIM_ARR_ARR_Pos ( 0U ) +#define LPTIM_ARR_ARR_Msk ( 0xffffUL << LPTIM_ARR_ARR_Pos ) +#define LPTIM_ARR_ARR ( LPTIM_ARR_ARR_Msk ) + + +/*************** Bits definition for LPTIM_CNT **********************/ + +#define LPTIM_CNT_CNT_Pos ( 0U ) +#define LPTIM_CNT_CNT_Msk ( 0xffffUL << LPTIM_CNT_CNT_Pos ) +#define LPTIM_CNT_CNT ( LPTIM_CNT_CNT_Msk ) + + +/*************** Bits definition for LPTIM_CFGR2 **********************/ + +#define LPTIM_CFGR2_IN2SEL_Pos ( 4U ) +#define LPTIM_CFGR2_IN2SEL_Msk ( 0xfUL << LPTIM_CFGR2_IN2SEL_Pos ) +#define LPTIM_CFGR2_IN2SEL ( LPTIM_CFGR2_IN2SEL_Msk ) +#define LPTIM_CFGR2_IN2SEL_0 ( 0x1UL << LPTIM_CFGR2_IN2SEL_Pos ) +#define LPTIM_CFGR2_IN2SEL_1 ( 0x2UL << LPTIM_CFGR2_IN2SEL_Pos ) +#define LPTIM_CFGR2_IN2SEL_2 ( 0x4UL << LPTIM_CFGR2_IN2SEL_Pos ) +#define LPTIM_CFGR2_IN2SEL_3 ( 0x8UL << LPTIM_CFGR2_IN2SEL_Pos ) + +#define LPTIM_CFGR2_IN1SEL_Pos ( 0U ) +#define LPTIM_CFGR2_IN1SEL_Msk ( 0xfUL << LPTIM_CFGR2_IN1SEL_Pos ) +#define LPTIM_CFGR2_IN1SEL ( LPTIM_CFGR2_IN1SEL_Msk ) +#define LPTIM_CFGR2_IN1SEL_0 ( 0x1UL << LPTIM_CFGR2_IN1SEL_Pos ) +#define LPTIM_CFGR2_IN1SEL_1 ( 0x2UL << LPTIM_CFGR2_IN1SEL_Pos ) +#define LPTIM_CFGR2_IN1SEL_2 ( 0x4UL << LPTIM_CFGR2_IN1SEL_Pos ) +#define LPTIM_CFGR2_IN1SEL_3 ( 0x8UL << LPTIM_CFGR2_IN1SEL_Pos ) + + +/*************** Bits definition for LPTIM_RCR **********************/ + +#define LPTIM_RCR_REP_Pos ( 0U ) +#define LPTIM_RCR_REP_Msk ( 0xffUL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP ( LPTIM_RCR_REP_Msk ) +#define LPTIM_RCR_REP_0 ( 0x1UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_1 ( 0x2UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_2 ( 0x4UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_3 ( 0x8UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_4 ( 0x10UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_5 ( 0x20UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_6 ( 0x40UL << LPTIM_RCR_REP_Pos ) +#define LPTIM_RCR_REP_7 ( 0x80UL << LPTIM_RCR_REP_Pos ) + + +/*************** Bits definition for OPA_CSR **********************/ + +#define OPA_CSR_LOCK_Pos ( 31U ) +#define OPA_CSR_LOCK_Msk ( 0x1UL << OPA_CSR_LOCK_Pos ) +#define OPA_CSR_LOCK ( OPA_CSR_LOCK_Msk ) + +#define OPA_CSR_REV_Pos ( 29U ) +#define OPA_CSR_REV_Msk ( 0x3UL << OPA_CSR_REV_Pos ) +#define OPA_CSR_REV ( OPA_CSR_REV_Msk ) +#define OPA_CSR_REV_0 ( 0x1UL << OPA_CSR_REV_Pos ) +#define OPA_CSR_REV_1 ( 0x2UL << OPA_CSR_REV_Pos ) + +#define OPA_CSR_HSM_Pos ( 28U ) +#define OPA_CSR_HSM_Msk ( 0x1UL << OPA_CSR_HSM_Pos ) +#define OPA_CSR_HSM ( OPA_CSR_HSM_Msk ) + +#define OPA_CSR_GAIN_SEL_Pos ( 23U ) +#define OPA_CSR_GAIN_SEL_Msk ( 0x1fUL << OPA_CSR_GAIN_SEL_Pos ) +#define OPA_CSR_GAIN_SEL ( OPA_CSR_GAIN_SEL_Msk ) +#define OPA_CSR_GAIN_SEL_0 ( 0x1UL << OPA_CSR_GAIN_SEL_Pos ) +#define OPA_CSR_GAIN_SEL_1 ( 0x2UL << OPA_CSR_GAIN_SEL_Pos ) +#define OPA_CSR_GAIN_SEL_2 ( 0x4UL << OPA_CSR_GAIN_SEL_Pos ) +#define OPA_CSR_GAIN_SEL_3 ( 0x8UL << OPA_CSR_GAIN_SEL_Pos ) +#define OPA_CSR_GAIN_SEL_4 ( 0x10UL << OPA_CSR_GAIN_SEL_Pos ) + +#define OPA_CSR_POL_SEL_Pos ( 21U ) +#define OPA_CSR_POL_SEL_Msk ( 0x3UL << OPA_CSR_POL_SEL_Pos ) +#define OPA_CSR_POL_SEL ( OPA_CSR_POL_SEL_Msk ) +#define OPA_CSR_POL_SEL_0 ( 0x1UL << OPA_CSR_POL_SEL_Pos ) +#define OPA_CSR_POL_SEL_1 ( 0x2UL << OPA_CSR_POL_SEL_Pos ) + +#define OPA_CSR_VINM0_EN_Pos ( 20U ) +#define OPA_CSR_VINM0_EN_Msk ( 0x1UL << OPA_CSR_VINM0_EN_Pos ) +#define OPA_CSR_VINM0_EN ( OPA_CSR_VINM0_EN_Msk ) + +#define OPA_CSR_MODE_SEL_Pos ( 18U ) +#define OPA_CSR_MODE_SEL_Msk ( 0x3UL << OPA_CSR_MODE_SEL_Pos ) +#define OPA_CSR_MODE_SEL ( OPA_CSR_MODE_SEL_Msk ) +#define OPA_CSR_MODE_SEL_0 ( 0x1UL << OPA_CSR_MODE_SEL_Pos ) +#define OPA_CSR_MODE_SEL_1 ( 0x2UL << OPA_CSR_MODE_SEL_Pos ) + +#define OPA_CSR_VINP_SEL_Pos ( 16U ) +#define OPA_CSR_VINP_SEL_Msk ( 0x3UL << OPA_CSR_VINP_SEL_Pos ) +#define OPA_CSR_VINP_SEL ( OPA_CSR_VINP_SEL_Msk ) +#define OPA_CSR_VINP_SEL_0 ( 0x1UL << OPA_CSR_VINP_SEL_Pos ) +#define OPA_CSR_VINP_SEL_1 ( 0x2UL << OPA_CSR_VINP_SEL_Pos ) + +#define OPA_CSR_OUT_SEL_Pos ( 14U ) +#define OPA_CSR_OUT_SEL_Msk ( 0x3UL << OPA_CSR_OUT_SEL_Pos ) +#define OPA_CSR_OUT_SEL ( OPA_CSR_OUT_SEL_Msk ) +#define OPA_CSR_OUT_SEL_0 ( 0x1UL << OPA_CSR_OUT_SEL_Pos ) +#define OPA_CSR_OUT_SEL_1 ( 0x2UL << OPA_CSR_OUT_SEL_Pos ) + +#define OPA_CSR_TRIM_OSN_Pos ( 9U ) +#define OPA_CSR_TRIM_OSN_Msk ( 0x1fUL << OPA_CSR_TRIM_OSN_Pos ) +#define OPA_CSR_TRIM_OSN ( OPA_CSR_TRIM_OSN_Msk ) +#define OPA_CSR_TRIM_OSN_0 ( 0x1UL << OPA_CSR_TRIM_OSN_Pos ) +#define OPA_CSR_TRIM_OSN_1 ( 0x2UL << OPA_CSR_TRIM_OSN_Pos ) +#define OPA_CSR_TRIM_OSN_2 ( 0x4UL << OPA_CSR_TRIM_OSN_Pos ) +#define OPA_CSR_TRIM_OSN_3 ( 0x8UL << OPA_CSR_TRIM_OSN_Pos ) +#define OPA_CSR_TRIM_OSN_4 ( 0x10UL << OPA_CSR_TRIM_OSN_Pos ) + +#define OPA_CSR_TRIM_OSP_Pos ( 4U ) +#define OPA_CSR_TRIM_OSP_Msk ( 0x1fUL << OPA_CSR_TRIM_OSP_Pos ) +#define OPA_CSR_TRIM_OSP ( OPA_CSR_TRIM_OSP_Msk ) +#define OPA_CSR_TRIM_OSP_0 ( 0x1UL << OPA_CSR_TRIM_OSP_Pos ) +#define OPA_CSR_TRIM_OSP_1 ( 0x2UL << OPA_CSR_TRIM_OSP_Pos ) +#define OPA_CSR_TRIM_OSP_2 ( 0x4UL << OPA_CSR_TRIM_OSP_Pos ) +#define OPA_CSR_TRIM_OSP_3 ( 0x8UL << OPA_CSR_TRIM_OSP_Pos ) +#define OPA_CSR_TRIM_OSP_4 ( 0x10UL << OPA_CSR_TRIM_OSP_Pos ) + +#define OPA_CSR_CAL_OUT_Pos ( 3U ) +#define OPA_CSR_CAL_OUT_Msk ( 0x1UL << OPA_CSR_CAL_OUT_Pos ) +#define OPA_CSR_CAL_OUT ( OPA_CSR_CAL_OUT_Msk ) + +#define OPA_CSR_CAL_NEN_Pos ( 2U ) +#define OPA_CSR_CAL_NEN_Msk ( 0x1UL << OPA_CSR_CAL_NEN_Pos ) +#define OPA_CSR_CAL_NEN ( OPA_CSR_CAL_NEN_Msk ) + +#define OPA_CSR_CAL_PEN_Pos ( 1U ) +#define OPA_CSR_CAL_PEN_Msk ( 0x1UL << OPA_CSR_CAL_PEN_Pos ) +#define OPA_CSR_CAL_PEN ( OPA_CSR_CAL_PEN_Msk ) + +#define OPA_CSR_EN_Pos ( 0U ) +#define OPA_CSR_EN_Msk ( 0x1UL << OPA_CSR_EN_Pos ) +#define OPA_CSR_EN ( OPA_CSR_EN_Msk ) + +/*************** Bits definition for FMC_NAND_CTRL **********************/ + +#define FMC_NAND_CTRL_EDO_EN_Pos ( 7U ) +#define FMC_NAND_CTRL_EDO_EN_Msk ( 0x1UL << FMC_NAND_CTRL_EDO_EN_Pos ) +#define FMC_NAND_CTRL_EDO_EN ( FMC_NAND_CTRL_EDO_EN_Msk ) + +#define FMC_NAND_CTRL_RBNINT_EN_Pos ( 6U ) +#define FMC_NAND_CTRL_RBNINT_EN_Msk ( 0x1UL << FMC_NAND_CTRL_RBNINTEN_Pos ) +#define FMC_NAND_CTRL_RBNINT_EN ( FMC_NAND_CTRL_RBNINTEN_Msk ) + +#define FMC_NAND_CTRL_ENDIAN_EN_Pos ( 5U ) +#define FMC_NAND_CTRL_ENDIAN_EN_Msk ( 0x1UL << FMC_NAND_CTRL_ENDIAN_Pos ) +#define FMC_NAND_CTRL_ENDIAN_EN ( FMC_NAND_CTRL_ENDIAN_Msk ) + +#define FMC_NAND_CTRL_FWP_Pos ( 4U ) +#define FMC_NAND_CTRL_FWP_Msk ( 0x1UL << FMC_NAND_CTRL_FWP_Pos ) +#define FMC_NAND_CTRL_FWP ( FMC_NAND_CTRL_FWP_Msk ) + +#define FMC_NAND_CTRL_FCE_Pos ( 0U ) +#define FMC_NAND_CTRL_FCE_Msk ( 0xfUL << FMC_NAND_CTRL_FCE_Pos ) +#define FMC_NAND_CTRL_FCE ( FMC_NAND_CTRL_FCE_Msk ) +#define FMC_NAND_CTRL_FCE_0 ( 0x1UL << FMC_NAND_CTRL_FCE_Pos ) +#define FMC_NAND_CTRL_FCE_1 ( 0x2UL << FMC_NAND_CTRL_FCE_Pos ) +#define FMC_NAND_CTRL_FCE_2 ( 0x4UL << FMC_NAND_CTRL_FCE_Pos ) +#define FMC_NAND_CTRL_FCE_3 ( 0x8UL << FMC_NAND_CTRL_FCE_Pos ) + +/*************** Bits definition for FMC_NAND_WST **********************/ + +#define FMC_NAND_WST_TADL_Pos ( 24U ) +#define FMC_NAND_WST_TADL_Msk ( 0xfUL << FMC_NAND_WST_TADL_Pos ) +#define FMC_NAND_WST_TADL ( FMC_NAND_WST_TADL_Msk ) +#define FMC_NAND_WST_TADL_0 ( 0x1UL << FMC_NAND_WST_TADL_Pos ) +#define FMC_NAND_WST_TADL_1 ( 0x2UL << FMC_NAND_WST_TADL_Pos ) +#define FMC_NAND_WST_TADL_2 ( 0x4UL << FMC_NAND_WST_TADL_Pos ) +#define FMC_NAND_WST_TADL_3 ( 0x8UL << FMC_NAND_WST_TADL_Pos ) + +#define FMC_NAND_WST_TRHW_Pos ( 20U ) +#define FMC_NAND_WST_TRHW_Msk ( 0xfUL << FMC_NAND_WST_TRHW_Pos ) +#define FMC_NAND_WST_TRHW ( FMC_NAND_WST_TRHW_Msk ) +#define FMC_NAND_WST_TRHW_0 ( 0x1UL << FMC_NAND_WST_TRHW_Pos ) +#define FMC_NAND_WST_TRHW_1 ( 0x2UL << FMC_NAND_WST_TRHW_Pos ) +#define FMC_NAND_WST_TRHW_2 ( 0x4UL << FMC_NAND_WST_TRHW_Pos ) +#define FMC_NAND_WST_TRHW_3 ( 0x8UL << FMC_NAND_WST_TRHW_Pos ) + +#define FMC_NAND_WST_TWHR_Pos ( 16U ) +#define FMC_NAND_WST_TWHR_Msk ( 0xfUL << FMC_NAND_WST_TWHR_Pos ) +#define FMC_NAND_WST_TWHR ( FMC_NAND_WST_TWHR_Msk ) +#define FMC_NAND_WST_TWHR_0 ( 0x1UL << FMC_NAND_WST_TWHR_Pos ) +#define FMC_NAND_WST_TWHR_1 ( 0x2UL << FMC_NAND_WST_TWHR_Pos ) +#define FMC_NAND_WST_TWHR_2 ( 0x4UL << FMC_NAND_WST_TWHR_Pos ) +#define FMC_NAND_WST_TWHR_3 ( 0x8UL << FMC_NAND_WST_TWHR_Pos ) + +#define FMC_NAND_WST_TREH_Pos ( 12U ) +#define FMC_NAND_WST_TREH_Msk ( 0xfUL << FMC_NAND_WST_TREH_Pos ) +#define FMC_NAND_WST_TREH ( FMC_NAND_WST_TREH_Msk ) +#define FMC_NAND_WST_TREH_0 ( 0x1UL << FMC_NAND_WST_TREH_Pos ) +#define FMC_NAND_WST_TREH_1 ( 0x2UL << FMC_NAND_WST_TREH_Pos ) +#define FMC_NAND_WST_TREH_2 ( 0x4UL << FMC_NAND_WST_TREH_Pos ) +#define FMC_NAND_WST_TREH_3 ( 0x8UL << FMC_NAND_WST_TREH_Pos ) + + +#define FMC_NAND_WST_TRP_Pos ( 8U ) +#define FMC_NAND_WST_TRP_Msk ( 0xfUL << FMC_NAND_WST_TRP_Pos ) +#define FMC_NAND_WST_TRP ( FMC_NAND_WST_TRP_Msk ) +#define FMC_NAND_WST_TRP_0 ( 0x1UL << FMC_NAND_WST_TRP_Pos ) +#define FMC_NAND_WST_TRP_1 ( 0x2UL << FMC_NAND_WST_TRP_Pos ) +#define FMC_NAND_WST_TRP_2 ( 0x4UL << FMC_NAND_WST_TRP_Pos ) +#define FMC_NAND_WST_TRP_3 ( 0x8UL << FMC_NAND_WST_TRP_Pos ) + +#define FMC_NAND_WST_TWH_Pos ( 4U ) +#define FMC_NAND_WST_TWH_Msk ( 0xfUL << FMC_NAND_WST_TWH_Pos ) +#define FMC_NAND_WST_TWH ( FMC_NAND_WST_TWH_Msk ) +#define FMC_NAND_WST_TWH_0 ( 0x1UL << FMC_NAND_WST_TWH_Pos ) +#define FMC_NAND_WST_TWH_1 ( 0x2UL << FMC_NAND_WST_TWH_Pos ) +#define FMC_NAND_WST_TWH_2 ( 0x4UL << FMC_NAND_WST_TWH_Pos ) +#define FMC_NAND_WST_TWH_3 ( 0x8UL << FMC_NAND_WST_TWH_Pos ) + +#define FMC_NAND_WST_TWP_Pos ( 0U ) +#define FMC_NAND_WST_TWP_Msk ( 0xfUL << FMC_NAND_WST_TWP_Pos ) +#define FMC_NAND_WST_TWP ( FMC_NAND_WST_TWP_Msk ) +#define FMC_NAND_WST_TWP_0 ( 0x1UL << FMC_NAND_WST_TWP_Pos ) +#define FMC_NAND_WST_TWP_1 ( 0x2UL << FMC_NAND_WST_TWP_Pos ) +#define FMC_NAND_WST_TWP_2 ( 0x4UL << FMC_NAND_WST_TWP_Pos ) +#define FMC_NAND_WST_TWP_3 ( 0x8UL << FMC_NAND_WST_TWP_Pos ) + +/*************** Bits definition for FMC_NAND_STATUS **********************/ + +#define FMC_NAND_STATUS_POS_RBN_Pos ( 4U ) +#define FMC_NAND_STATUS_POS_RBN_Msk ( 0xfUL << FMC_NAND_STATUS_POS_RBN_Pos ) +#define FMC_NAND_STATUS_POS_RBN ( FMC_NAND_STATUS_POS_RBN_Msk ) +#define FMC_NAND_STATUS_POS_RBN_0 ( 0x1UL << FMC_NAND_STATUS_POS_RBN_Pos ) +#define FMC_NAND_STATUS_POS_RBN_1 ( 0x2UL << FMC_NAND_STATUS_POS_RBN_Pos ) +#define FMC_NAND_STATUS_POS_RBN_2 ( 0x4UL << FMC_NAND_STATUS_POS_RBN_Pos ) +#define FMC_NAND_STATUS_POS_RBN_3 ( 0x8UL << FMC_NAND_STATUS_POS_RBN_Pos ) + +#define FMC_NAND_STATUS_RBN_Pos ( 0U ) +#define FMC_NAND_STATUS_RBN_Msk ( 0xfUL << FMC_NAND_STATUS_RBN_Pos ) +#define FMC_NAND_STATUS_RBN ( FMC_NAND_STATUS_RBN_Msk ) +#define FMC_NAND_STATUS_RBN_0 ( 0x1UL << FMC_NAND_STATUS_RBN_Pos ) +#define FMC_NAND_STATUS_RBN_1 ( 0x2UL << FMC_NAND_STATUS_RBN_Pos ) +#define FMC_NAND_STATUS_RBN_2 ( 0x4UL << FMC_NAND_STATUS_RBN_Pos ) +#define FMC_NAND_STATUS_RBN_3 ( 0x8UL << FMC_NAND_STATUS_RBN_Pos ) + +/*************** Bits definition for FMC_NAND_BCH_CONFIG **********************/ + +#define FMC_NAND_BCH_CONFIG_BCH_TYPE_Pos ( 0U ) +#define FMC_NAND_BCH_CONFIG_BCH_TYPE_Msk ( 0x7UL << FMC_NAND_BCH_CONFIG_BCH_TYPE_Pos ) +#define FMC_NAND_BCH_CONFIG_BCH_TYPE ( FMC_NAND_BCH_CONFIG_BCH_TYPE_Msk ) +#define FMC_NAND_BCH_CONFIG_BCH_TYPE_0 ( 0x1UL << FMC_NAND_BCH_CONFIG_BCH_TYPE_Pos ) +#define FMC_NAND_BCH_CONFIG_BCH_TYPE_1 ( 0x2UL << FMC_NAND_BCH_CONFIG_BCH_TYPE_Pos ) +#define FMC_NAND_BCH_CONFIG_BCH_TYPE_2 ( 0x4UL << FMC_NAND_BCH_CONFIG_BCH_TYPE_Pos ) + +/*************** Bits definition for FMC_NAND_BCH_CTRL **********************/ + +#define FMC_NAND_BCH_CTRL_AUTO_CORRECT_Pos ( 5U ) +#define FMC_NAND_BCH_CTRL_AUTO_CORRECT_Msk ( 0x1UL << FMC_NAND_BCH_CTRL_AUTO_CORRECT_Pos ) +#define FMC_NAND_BCH_CTRL_AUTO_CORRECT ( FMC_NAND_BCH_CTRL_AUTO_CORRECT_Msk ) + +#define FMC_NAND_BCH_CTRL_DECODE_INT_ENABLE_Pos ( 4U ) +#define FMC_NAND_BCH_CTRL_DECODE_INT_ENABLE_Msk ( 0x1UL << FMC_NAND_BCH_CTRL_DECODE_INT_ENABLE_Pos ) +#define FMC_NAND_BCH_CTRL_DECODE_INT_ENABLE ( FMC_NAND_BCH_CTRL_DECODE_INT_ENABLE_Msk ) + +#define FMC_NAND_BCH_CTRL_RESET_CHANNEL_Pos ( 3U ) +#define FMC_NAND_BCH_CTRL_RESET_CHANNEL_Msk ( 0x1UL << FMC_NAND_BCH_CTRL_RESET_CHANNEL_Pos ) +#define FMC_NAND_BCH_CTRL_RESET_CHANNEL ( FMC_NAND_BCH_CTRL_RESET_CHANNEL_Msk ) + +#define FMC_NAND_BCH_CTRL_IGALL1_Pos ( 1U ) +#define FMC_NAND_BCH_CTRL_IGALL1_Msk ( 0x1UL << FMC_NAND_BCH_CTRL_IGALL1_Pos ) +#define FMC_NAND_BCH_CTRL_IGALL1 ( FMC_NAND_BCH_CTRL_IGALL1_Msk ) + +#define FMC_NAND_BCH_CTRL_MODE_Pos ( 0U ) +#define FMC_NAND_BCH_CTRL_MODE_Msk ( 0x1UL << FMC_NAND_BCH_CTRL_MODE_Pos ) +#define FMC_NAND_BCH_CTRL_MODE ( FMC_NAND_BCH_CTRL_MODE_Msk ) + +/*************** Bits definition for FMC_NAND_BCH_STATUS **********************/ + +#define FMC_NAND_BCH_STATUS_CEN_Pos ( 24U ) +#define FMC_NAND_BCH_STATUS_CEN_Msk ( 0xffUL << FMC_NAND_BCH_STATUS_CEN_Pos ) +#define FMC_NAND_BCH_STATUS_CEN ( FMC_NAND_BCH_STATUS_CEN_Msk ) + +#define FMC_NAND_BCH_STATUS_DEN_Pos ( 16U ) +#define FMC_NAND_BCH_STATUS_DEN_Msk ( 0xffUL << FMC_NAND_BCH_STATUS_DEN_Pos ) +#define FMC_NAND_BCH_STATUS_DEN ( FMC_NAND_BCH_STATUS_DEN_Msk ) + +#define FMC_NAND_BCH_STATUS_ERN_Pos ( 8U ) +#define FMC_NAND_BCH_STATUS_ERN_Msk ( 0xffUL << FMC_NAND_BCH_STATUS_ERN_Pos ) +#define FMC_NAND_BCH_STATUS_ERN ( FMC_NAND_BCH_STATUS_ERN_Msk ) + +#define FMC_NAND_BCH_STATUS_DATA_ALL0_Pos ( 6U ) +#define FMC_NAND_BCH_STATUS_DATA_ALL0_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_DATA_ALL0_Pos ) +#define FMC_NAND_BCH_STATUS_DATA_ALL0 ( FMC_NAND_BCH_STATUS_DATA_ALL0_Msk ) + +#define FMC_NAND_BCH_STATUS_DATA_ALL1_Pos ( 5U ) +#define FMC_NAND_BCH_STATUS_DATA_ALL1_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_DATA_ALL1_Pos ) +#define FMC_NAND_BCH_STATUS_DATA_ALL1 ( FMC_NAND_BCH_STATUS_DATA_ALL1_Msk ) + +#define FMC_NAND_BCH_STATUS_BCH_FAIL_Pos ( 4U ) +#define FMC_NAND_BCH_STATUS_BCH_FAIL_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_BCH_FAIL_Pos ) +#define FMC_NAND_BCH_STATUS_BCH_FAIL ( FMC_NAND_BCH_STATUS_BCH_FAIL_Msk ) + +#define FMC_NAND_BCH_STATUS_CORRECT_DONE_Pos ( 3U ) +#define FMC_NAND_BCH_STATUS_CORRECT_DONE_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_CORRECT_DONE_Pos ) +#define FMC_NAND_BCH_STATUS_CORRECT_DONE ( FMC_NAND_BCH_STATUS_CORRECT_DONE_Msk ) + +#define FMC_NAND_BCH_STATUS_BM_DONE_Pos ( 2U ) +#define FMC_NAND_BCH_STATUS_BM_DONE_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_BM_DONE_Pos ) +#define FMC_NAND_BCH_STATUS_BM_DONE ( FMC_NAND_BCH_STATUS_BM_DONE_Msk ) + +#define FMC_NAND_BCH_STATUS_SNYDROME_DONE_Pos ( 1U ) +#define FMC_NAND_BCH_STATUS_SNYDROME_DONE_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_SNYDROME_DONE_Pos ) +#define FMC_NAND_BCH_STATUS_SNYDROME_DONE ( FMC_NAND_BCH_STATUS_SNYDROME_DONE_Msk ) + +#define FMC_NAND_BCH_STATUS_ENCODE_CLR_Pos ( 0U ) +#define FMC_NAND_BCH_STATUS_ENCODE_CLR_Msk ( 0x1UL << FMC_NAND_BCH_STATUS_ENCODE_CLR_Pos ) +#define FMC_NAND_BCH_STATUS_ENCODE_CLR ( FMC_NAND_BCH_STATUS_ENCODE_CLR_Msk ) + +/*************** Bits definition for COMP_CR **********************/ + +#define COMP_CR_LOCK_Pos ( 31U ) +#define COMP_CR_LOCK_Msk ( 0x1UL << COMP_CR_LOCK_Pos ) +#define COMP_CR_LOCK ( COMP_CR_LOCK_Msk ) + +#define COMP_CR_CRV_CFG_Pos ( 25U ) +#define COMP_CR_CRV_CFG_Msk ( 0xfUL << COMP_CR_CRV_CFG_Pos ) +#define COMP_CR_CRV_CFG ( COMP_CR_CRV_CFG_Msk ) +#define COMP_CR_CRV_CFG_0 ( 0x1UL << COMP_CR_CRV_CFG_Pos ) +#define COMP_CR_CRV_CFG_1 ( 0x2UL << COMP_CR_CRV_CFG_Pos ) +#define COMP_CR_CRV_CFG_2 ( 0x4UL << COMP_CR_CRV_CFG_Pos ) +#define COMP_CR_CRV_CFG_3 ( 0x8UL << COMP_CR_CRV_CFG_Pos ) + +#define COMP_CR_CRV_SEL_Pos ( 24U ) +#define COMP_CR_CRV_SEL_Msk ( 0x1UL << COMP_CR_CRV_SEL_Pos ) +#define COMP_CR_CRV_SEL ( COMP_CR_CRV_SEL_Msk ) + +#define COMP_CR_CRV_EN_Pos ( 23U ) +#define COMP_CR_CRV_EN_Msk ( 0x1UL << COMP_CR_CRV_EN_Pos ) +#define COMP_CR_CRV_EN ( COMP_CR_CRV_EN_Msk ) + +#define COMP_CR_POLARITY_Pos ( 20U ) +#define COMP_CR_POLARITY_Msk ( 0x1UL << COMP_CR_POLARITY_Pos ) +#define COMP_CR_POLARITY ( COMP_CR_POLARITY_Msk ) + +#define COMP_CR_FLTEN_Pos ( 19U ) +#define COMP_CR_FLTEN_Msk ( 0x1UL << COMP_CR_FLTEN_Pos ) +#define COMP_CR_FLTEN ( COMP_CR_FLTEN_Msk ) + +#define COMP_CR_FLTTIME_Pos ( 16U ) +#define COMP_CR_FLTTIME_Msk ( 0x7UL << COMP_CR_FLTTIME_Pos ) +#define COMP_CR_FLTTIME ( COMP_CR_FLTTIME_Msk ) +#define COMP_CR_FLTTIME_0 ( 0x1UL << COMP_CR_FLTTIME_Pos ) +#define COMP_CR_FLTTIME_1 ( 0x2UL << COMP_CR_FLTTIME_Pos ) +#define COMP_CR_FLTTIME_2 ( 0x4UL << COMP_CR_FLTTIME_Pos ) + +#define COMP_CR_BLANKSEL_Pos ( 12U ) +#define COMP_CR_BLANKSEL_Msk ( 0x7UL << COMP_CR_BLANKSEL_Pos ) +#define COMP_CR_BLANKSEL ( COMP_CR_BLANKSEL_Msk ) +#define COMP_CR_BLANKSEL_0 ( 0x1UL << COMP_CR_BLANKSEL_Pos ) +#define COMP_CR_BLANKSEL_1 ( 0x2UL << COMP_CR_BLANKSEL_Pos ) +#define COMP_CR_BLANKSEL_2 ( 0x4UL << COMP_CR_BLANKSEL_Pos ) + +#define COMP_CR_INPSEL_Pos ( 8U ) +#define COMP_CR_INPSEL_Msk ( 0xfUL << COMP_CR_INPSEL_Pos ) +#define COMP_CR_INPSEL ( COMP_CR_INPSEL_Msk ) +#define COMP_CR_INPSEL_0 ( 0x1UL << COMP_CR_INPSEL_Pos ) +#define COMP_CR_INPSEL_1 ( 0x2UL << COMP_CR_INPSEL_Pos ) +#define COMP_CR_INPSEL_2 ( 0x4UL << COMP_CR_INPSEL_Pos ) +#define COMP_CR_INPSEL_3 ( 0x8UL << COMP_CR_INPSEL_Pos ) + +#define COMP_CR_INMSEL_Pos ( 4U ) +#define COMP_CR_INMSEL_Msk ( 0xfUL << COMP_CR_INMSEL_Pos ) +#define COMP_CR_INMSEL ( COMP_CR_INMSEL_Msk ) +#define COMP_CR_INMSEL_0 ( 0x1UL << COMP_CR_INMSEL_Pos ) +#define COMP_CR_INMSEL_1 ( 0x2UL << COMP_CR_INMSEL_Pos ) +#define COMP_CR_INMSEL_2 ( 0x4UL << COMP_CR_INMSEL_Pos ) +#define COMP_CR_INMSEL_3 ( 0x8UL << COMP_CR_INMSEL_Pos ) + +#define COMP_CR_HYS_Pos ( 1U ) +#define COMP_CR_HYS_Msk ( 0x7UL << COMP_CR_HYS_Pos ) +#define COMP_CR_HYS ( COMP_CR_HYS_Msk ) +#define COMP_CR_HYS_0 ( 0x1UL << COMP_CR_HYS_Pos ) +#define COMP_CR_HYS_1 ( 0x2UL << COMP_CR_HYS_Pos ) +#define COMP_CR_HYS_2 ( 0x4UL << COMP_CR_HYS_Pos ) + +#define COMP_CR_EN_Pos ( 0U ) +#define COMP_CR_EN_Msk ( 0x1UL << COMP_CR_EN_Pos ) +#define COMP_CR_EN ( COMP_CR_EN_Msk ) + + +/*************** Bits definition for COMP_SR **********************/ + +#define COMP_SR_VCOUT1_ORG_Pos ( 4U ) +#define COMP_SR_VCOUT1_ORG_Msk ( 0x1UL << COMP_SR_VCOUT1_ORG_Pos ) +#define COMP_SR_VCOUT1_ORG ( COMP_SR_VCOUT1_ORG_Msk ) + +#define COMP_SR_VCOUT1_Pos ( 0U ) +#define COMP_SR_VCOUT1_Msk ( 0x1UL << COMP_SR_VCOUT1_Pos ) +#define COMP_SR_VCOUT1 ( COMP_SR_VCOUT1_Msk ) + + + +/*************** Bits definition for EFUSE_WP **********************/ + +#define EFUSE_WP_WP_Pos ( 0U ) +#define EFUSE_WP_WP_Msk ( 0xffffffffUL << EFUSE_WP_WP_Pos ) +#define EFUSE_WP_WP ( EFUSE_WP_WP_Msk ) + + +/*************** Bits definition for EFUSE_CTRL **********************/ + +#define EFUSE_CTRL_MODE_Pos ( 4U ) +#define EFUSE_CTRL_MODE_Msk ( 0x1UL << EFUSE_CTRL_MODE_Pos ) +#define EFUSE_CTRL_MODE ( EFUSE_CTRL_MODE_Msk ) + +#define EFUSE_CTRL_TRIG_Pos ( 0U ) +#define EFUSE_CTRL_TRIG_Msk ( 0x1UL << EFUSE_CTRL_TRIG_Pos ) +#define EFUSE_CTRL_TRIG ( EFUSE_CTRL_TRIG_Msk ) + + +/*************** Bits definition for EFUSE_AR **********************/ + +#define EFUSE_AR_ADDR_Pos ( 0U ) +#define EFUSE_AR_ADDR_Msk ( 0x7ffUL << EFUSE_AR_ADDR_Pos ) +#define EFUSE_AR_ADDR ( EFUSE_AR_ADDR_Msk ) + + +/*************** Bits definition for EFUSE_DWR **********************/ + +#define EFUSE_DWR_WDATA_Pos ( 0U ) +#define EFUSE_DWR_WDATA_Msk ( 0xffUL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA ( EFUSE_DWR_WDATA_Msk ) +#define EFUSE_DWR_WDATA_0 ( 0x1UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_1 ( 0x2UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_2 ( 0x4UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_3 ( 0x8UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_4 ( 0x10UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_5 ( 0x20UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_6 ( 0x40UL << EFUSE_DWR_WDATA_Pos ) +#define EFUSE_DWR_WDATA_7 ( 0x80UL << EFUSE_DWR_WDATA_Pos ) + + +/*************** Bits definition for EFUSE_SR **********************/ + +#define EFUSE_SR_PREREAD_DONE_Pos ( 31U ) +#define EFUSE_SR_PREREAD_DONE_Msk ( 0x1UL << EFUSE_SR_PREREAD_DONE_Pos ) +#define EFUSE_SR_PREREAD_DONE ( EFUSE_SR_PREREAD_DONE_Msk ) + +#define EFUSE_SR_UNPG_Pos ( 1U ) +#define EFUSE_SR_UNPG_Msk ( 0x1UL << EFUSE_SR_UNPG_Pos ) +#define EFUSE_SR_UNPG ( EFUSE_SR_UNPG_Msk ) + +#define EFUSE_SR_DONE_Pos ( 0U ) +#define EFUSE_SR_DONE_Msk ( 0x1UL << EFUSE_SR_DONE_Pos ) +#define EFUSE_SR_DONE ( EFUSE_SR_DONE_Msk ) + + +/*************** Bits definition for EFUSE_CLR **********************/ + +#define EFUSE_CLR_CUNPG_Pos ( 1U ) +#define EFUSE_CLR_CUNPG_Msk ( 0x1UL << EFUSE_CLR_CUNPG_Pos ) +#define EFUSE_CLR_CUNPG ( EFUSE_CLR_CUNPG_Msk ) + +#define EFUSE_CLR_CDONE_Pos ( 0U ) +#define EFUSE_CLR_CDONE_Msk ( 0x1UL << EFUSE_CLR_CDONE_Pos ) +#define EFUSE_CLR_CDONE ( EFUSE_CLR_CDONE_Msk ) + + +/*************** Bits definition for EFUSE_DR **********************/ + +#define EFUSE_DR_DATA_Pos ( 0U ) +#define EFUSE_DR_DATA_Msk ( 0xffUL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA ( EFUSE_DR_DATA_Msk ) +#define EFUSE_DR_DATA_0 ( 0x1UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_1 ( 0x2UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_2 ( 0x4UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_3 ( 0x8UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_4 ( 0x10UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_5 ( 0x20UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_6 ( 0x40UL << EFUSE_DR_DATA_Pos ) +#define EFUSE_DR_DATA_7 ( 0x80UL << EFUSE_DR_DATA_Pos ) + + +/*************** Bits definition for EFUSE_DSDP **********************/ + +#define EFUSE_DSDP_DP_Pos ( 0U ) +#define EFUSE_DSDP_DP_Msk ( 0xffffffffUL << EFUSE_DSDP_DP_Pos ) +#define EFUSE_DSDP_DP ( EFUSE_DSDP_DP_Msk ) + + +/*************** Bits definition for EFUSE_BYTEWP **********************/ + +#define EFUSE_BYTEWP_BYTEWP_Pos ( 0U ) +#define EFUSE_BYTEWP_BYTEWP_Msk ( 0xffffffffUL << EFUSE_BYTEWP_BYTEWP_Pos ) +#define EFUSE_BYTEWP_BYTEWP ( EFUSE_BYTEWP_BYTEWP_Msk ) + + +/*************** Bits definition for EFUSE_PGCFG **********************/ + +#define EFUSE_PGCFG_AVDD_SP_Pos ( 24U ) +#define EFUSE_PGCFG_AVDD_SP_Msk ( 0xffUL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP ( EFUSE_PGCFG_AVDD_SP_Msk ) +#define EFUSE_PGCFG_AVDD_SP_0 ( 0x1UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_1 ( 0x2UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_2 ( 0x4UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_3 ( 0x8UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_4 ( 0x10UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_5 ( 0x20UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_6 ( 0x40UL << EFUSE_PGCFG_AVDD_SP_Pos ) +#define EFUSE_PGCFG_AVDD_SP_7 ( 0x80UL << EFUSE_PGCFG_AVDD_SP_Pos ) + +#define EFUSE_PGCFG_AVDD_HD_Pos ( 16U ) +#define EFUSE_PGCFG_AVDD_HD_Msk ( 0xffUL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD ( EFUSE_PGCFG_AVDD_HD_Msk ) +#define EFUSE_PGCFG_AVDD_HD_0 ( 0x1UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_1 ( 0x2UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_2 ( 0x4UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_3 ( 0x8UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_4 ( 0x10UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_5 ( 0x20UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_6 ( 0x40UL << EFUSE_PGCFG_AVDD_HD_Pos ) +#define EFUSE_PGCFG_AVDD_HD_7 ( 0x80UL << EFUSE_PGCFG_AVDD_HD_Pos ) + +#define EFUSE_PGCFG_PGWT_Pos ( 8U ) +#define EFUSE_PGCFG_PGWT_Msk ( 0xffUL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT ( EFUSE_PGCFG_PGWT_Msk ) +#define EFUSE_PGCFG_PGWT_0 ( 0x1UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_1 ( 0x2UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_2 ( 0x4UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_3 ( 0x8UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_4 ( 0x10UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_5 ( 0x20UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_6 ( 0x40UL << EFUSE_PGCFG_PGWT_Pos ) +#define EFUSE_PGCFG_PGWT_7 ( 0x80UL << EFUSE_PGCFG_PGWT_Pos ) + +#define EFUSE_PGCFG_PGT_Pos ( 0U ) +#define EFUSE_PGCFG_PGT_Msk ( 0xffUL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT ( EFUSE_PGCFG_PGT_Msk ) +#define EFUSE_PGCFG_PGT_0 ( 0x1UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_1 ( 0x2UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_2 ( 0x4UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_3 ( 0x8UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_4 ( 0x10UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_5 ( 0x20UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_6 ( 0x40UL << EFUSE_PGCFG_PGT_Pos ) +#define EFUSE_PGCFG_PGT_7 ( 0x80UL << EFUSE_PGCFG_PGT_Pos ) + + +/*************** Bits definition for EFUSE_DSRx **********************/ + +#define EFUSE_DSRX_DATA_Pos ( 0U ) +#define EFUSE_DSRX_DATA_Msk ( 0xffUL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA ( EFUSE_DSRX_DATA_Msk ) +#define EFUSE_DSRX_DATA_0 ( 0x1UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_1 ( 0x2UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_2 ( 0x4UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_3 ( 0x8UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_4 ( 0x10UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_5 ( 0x20UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_6 ( 0x40UL << EFUSE_DSRX_DATA_Pos ) +#define EFUSE_DSRX_DATA_7 ( 0x80UL << EFUSE_DSRX_DATA_Pos ) + + +/******************* Bit definition for DLYB_CR register ********************/ + +#define DLYB_CR_SEN_Pos ( 1U ) +#define DLYB_CR_SEN_Msk ( 0x1UL << DLYB_CR_SEN_Pos ) +#define DLYB_CR_SEN ( DLYB_CR_SEN_Msk ) + +#define DLYB_CR_DEN_Pos ( 0U ) +#define DLYB_CR_DEN_Msk ( 0x1UL << DLYB_CR_DEN_Pos ) +#define DLYB_CR_DEN ( DLYB_CR_DEN_Msk ) + + +/******************* Bit definition for DLYB_CFGR register ********************/ + +#define DLYB_CFGR_LENF_Pos ( 31U) +#define DLYB_CFGR_LENF_Msk ( 0x1UL << DLYB_CFGR_LENF_Pos ) +#define DLYB_CFGR_LENF ( DLYB_CFGR_LENF_Msk ) + +#define DLYB_CFGR_LEN_Pos ( 16U ) +#define DLYB_CFGR_LEN_Msk ( 0xFFFUL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN ( DLYB_CFGR_LEN_Msk ) +#define DLYB_CFGR_LEN_0 ( 0x001UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_1 ( 0x002UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_2 ( 0x004UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_3 ( 0x008UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_4 ( 0x010UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_5 ( 0x020UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_6 ( 0x040UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_7 ( 0x080UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_8 ( 0x100UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_9 ( 0x200UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_10 ( 0x400UL << DLYB_CFGR_LEN_Pos ) +#define DLYB_CFGR_LEN_11 ( 0x800UL << DLYB_CFGR_LEN_Pos ) + +#define DLYB_CFGR_UNIT_Pos ( 8U ) +#define DLYB_CFGR_UNIT_Msk ( 0x7FUL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT ( DLYB_CFGR_UNIT_Msk ) +#define DLYB_CFGR_UNIT_0 ( 0x01UL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT_1 ( 0x02UL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT_2 ( 0x04UL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT_3 ( 0x08UL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT_4 ( 0x10UL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT_5 ( 0x20UL << DLYB_CFGR_UNIT_Pos ) +#define DLYB_CFGR_UNIT_6 ( 0x40UL << DLYB_CFGR_UNIT_Pos ) + +#define DLYB_CFGR_SEL_Pos ( 0U ) +#define DLYB_CFGR_SEL_Msk ( 0xFUL << DLYB_CFGR_SEL_Pos ) +#define DLYB_CFGR_SEL ( DLYB_CFGR_SEL_Msk ) +#define DLYB_CFGR_SEL_0 ( 0x1UL << DLYB_CFGR_SEL_Pos ) +#define DLYB_CFGR_SEL_1 ( 0x2UL << DLYB_CFGR_SEL_Pos ) +#define DLYB_CFGR_SEL_2 ( 0x3UL << DLYB_CFGR_SEL_Pos ) +#define DLYB_CFGR_SEL_3 ( 0x8UL << DLYB_CFGR_SEL_Pos ) + +///*----------- Peripheral_Registers_Bits_Definition END -----------------*/ + +#if (USE_RTOS == 1U) + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + + +typedef unsigned char UINT8; +typedef unsigned short int UINT16; +typedef unsigned int UINT32; + + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) +#define CLEAR_REG(REG) ((REG) = (0x0)) +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define READ_REG(REG) ((REG)) +#define MODIFY_REG(REG,MASK,BITS) ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK)))) +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +#endif /* __ACM32H5XX_H__ */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_accelerate.c b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_accelerate.c new file mode 100644 index 0000000000000000000000000000000000000000..12bc77939d81039d600797c55cd9909522646e44 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_accelerate.c @@ -0,0 +1,407 @@ +/* + ****************************************************************************** + * @file System_Accelerate.c + * @author AisinoChip Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief MCU Cache Peripheral Access Layer System Source File. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 AisinoChip. + * All rights reserved. + ****************************************************************************** +*/ +#include "hal.h" + +#include "system_accelerate.h" + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/********************************************************************************* +* Function : System_EnableIAccelerate +* Description : Enable I-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_EnableIAccelerate(void) +{ + if (SCB->CCR & SCB_CCR_IC_Msk) /* return if ICache is already enabled */ + { + return; + } + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_DisableIAccelerate +* Description : Disable I-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_DisableIAccelerate(void) +{ + __DSB(); + __ISB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_InvalidateIAccelerate +* Description : Invalidate I-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_InvalidateIAccelerate(void) +{ + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); +} + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +void System_InvalidateIAccelerate_by_Addr (volatile void *addr, int32_t isize) +{ + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } +} + +/********************************************************************************* +* Function : System_EnableDAccelerate +* Description : Enable D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_EnableDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + }while (ways-- != 0U); + }while(sets-- != 0U); + + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_DisableDAccelerate +* Description : Disable D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_DisableDAccelerate(void) +{ + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + +#if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + __DSB(); + __ISB(); +#endif + + locals.ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do + { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do + { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + }while(locals.ways-- != 0U); + }while(locals.sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_InvalidateDAccelerate +* Description : Invalidate D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_InvalidateDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + }while(ways-- != 0U); + }while(sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_CleanDAccelerate +* Description : Clean D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do + { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do + { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_CleanInvalidateDAccelerate +* Description : Cleans and Invalidates D-Cache +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanInvalidateDAccelerate(void) +{ + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); +} + +/********************************************************************************* +* Function : System_InvalidateDAccelerate +* Description : Invalidate D-Cache by addr +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_InvalidateDAccelerate_by_Addr (volatile void *addr, int32_t dsize) +{ + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } +} + +/********************************************************************************* +* Function : System_CleanDAccelerate_by_Addr +* Description : Cleans D-Cache for the given address +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanDAccelerate_by_Addr (volatile void *addr, int32_t dsize) +{ + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } +} + +/********************************************************************************* +* Function : System_CleanInvalidateDAccelerate_by_Addr +* Description : Cleans and invalidates D_Cache for the given address +* Input : +* Outpu : +* Author : Chris_Kyle Data : 2020 +**********************************************************************************/ +void System_CleanInvalidateDAccelerate_by_Addr (volatile void *addr, int32_t dsize) +{ + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } +} + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_accelerate.h b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_accelerate.h new file mode 100644 index 0000000000000000000000000000000000000000..248bbedff16f89777f5d97132eb0f0327cd7c99c --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_accelerate.h @@ -0,0 +1,56 @@ +/* + ****************************************************************************** + * @file System_Accelerate.h + * @author AisinoChip Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief MCU Accelerate Peripheral Access Layer System header File. + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 AisinoChip. + * All rights reserved. + ****************************************************************************** +*/ +#ifndef __SYSTEM_ACCELERATE_H__ +#define __SYSTEM_ACCELERATE_H__ + +//#include "cmsis_armclang.h" +#include "stdint.h" + +/* System_EnableIAccelerate */ +void System_EnableIAccelerate(void); + +/* System_DisableIAccelerate */ +void System_DisableIAccelerate(void); + +/* System_InvalidateIAccelerate */ +void System_InvalidateIAccelerate(void); + +void System_InvalidateIAccelerate_by_Addr (volatile void *addr, int32_t isize); + +/* System_EnableDAccelerate */ +void System_EnableDAccelerate(void); + +/* System_DisableDAccelerate */ +void System_DisableDAccelerate(void); + +/* System_InvalidateDAccelerate */ +void System_InvalidateDAccelerate(void); + +/* System_CleanDAccelerate */ +void System_CleanDAccelerate(void); + +/* System_CleanInvalidateDAccelerate */ +void System_CleanInvalidateDAccelerate(void); + +/* System_InvalidateDAccelerate_by_Addr */ +void System_InvalidateDAccelerate_by_Addr (volatile void *addr, int32_t dsize); + +void System_CleanDAccelerate_by_Addr (volatile void *addr, int32_t dsize); + +/* System_CleanInvalidateDAccelerate_by_Addr */ +void System_CleanInvalidateDAccelerate_by_Addr (volatile void *addr, int32_t dsize); + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_acm32h5xx.c b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_acm32h5xx.c new file mode 100644 index 0000000000000000000000000000000000000000..5edd890d928c85fd35894adf5f1ce624cd4728c7 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_acm32h5xx.c @@ -0,0 +1,753 @@ + +/****************************************************************************** +*@file : system_acm32h5xx.c +*@brief : CMSIS Cortex-M33 Device Peripheral Access Layer System Source File +******************************************************************************/ + +#include "acm32h5xx_hal_conf.h" + +#ifdef DATA_IN_ExtSRAM + void SystemInit_ExtMemCtl(void); +#endif + +/****************************************************************************** +*@note : g_SystemCoreClock variable is updated in three ways: +* 1) by calling CMSIS function SystemCoreClockUpdate() +* 2) by calling HAL API function HAL_RCC_GetSysCoreClockFreq() +* 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency +* If you use this function to configure the system clock; then there +* is no need to call the 2 first functions listed above, since g_SystemCoreClock +* variable is updated automatically. +******************************************************************************/ +volatile uint32_t SystemCoreClock = 220000000; + +/****************************************************************************** +*@brief : configure FPU and vector table address +* - This function is called at startup just after reset and before branch to main program. +* - This call is made inside the "startup_acm32h5xx.s" file +*@param : none +*@return: none +******************************************************************************/ +__attribute__((weak)) void SystemInit(void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* set CP10 and CP11 Full Access */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); + #endif + + RCC->RCHCR |= RCC_RCHCR_RCHEN; + __NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP(); + while (!(RCC->RCHCR & RCC_RCHCR_RCHRDY)) {}; + RCC->RCHCR &= ~RCC_RCHCR_RCHSEL; + RCC->CCR1 &= ~RCC_CCR1_SYSCLKSEL; + + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1EN; + RCC->PLL1SCR = 0; + RCC->PLL1CR |= RCC_PLL1CR_PLL1SLEEP; + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2EN; + RCC->PLL2SCR = 0; + RCC->PLL2CR |= RCC_PLL2CR_PLL2SLEEP; + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3EN; + RCC->PLL3CR |= RCC_PLL3CR_PLL3SLEEP; + + RCC->RCHCR &= ~RCC_RCHCR_RCHDIV; + + RCC->CCR2 &= ~RCC_CCR2_SYSDIV0; + __NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP(); + while (!(RCC->CCR2 & RCC_CCR2_DIVDONE)) {}; + + RCC->CCR2 &= ~RCC_CCR2_SYSDIV1; + __NOP();__NOP();__NOP();__NOP();__NOP(); + __NOP();__NOP();__NOP();__NOP();__NOP(); + while (!(RCC->CCR2 & RCC_CCR2_DIVDONE)) {}; + + RCC->CCR2 &= ~(RCC_CCR2_PCLK1DIV | RCC_CCR2_PCLK2DIV | RCC_CCR2_PCLK3DIV | RCC_CCR2_PCLK4DIV); + + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + SCB->VTOR = VECT_TAB_ADDR; + + #if (INS_ACCELERATE_ENABLE) + System_EnableIAccelerate(); + #else + System_DisableIAccelerate(); + #endif +} + +/****************************************************************************** +*@brief : Update g_SystemCoreClock variable according to Clock Register Values. +* The SystemCoreClock variable contains the core clock (HCLK), it can +* be used by the user application to setup the SysTick timer or configure +* other parameters. +* +*@note : Each time the core clock (HCLK) changes, this function must be called +* to update SystemCoreClock variable value. Otherwise, any configuration +* based on this variable will be incorrect. +*@param : none +*@return: none +******************************************************************************/ +void SystemCoreClockUpdate(void) +{ + HAL_RCC_GetSysCoreClockFreq(); +} + + +/****************************************************************************** +*@brief : fast config system core clock. +*@param : sysclkSel: system core clk select, see SYSCLK_SelectTypeDef enum +*@param : pclk1Div: pclk1 div select +* @arg RCC_PCLK1_DIV_1 +* @arg RCC_PCLK1_DIV_2 +* @arg RCC_PCLK1_DIV_4 +* @arg RCC_PCLK1_DIV_8 +* @arg RCC_PCLK1_DIV_16 +*@param : pclk2Div: pclk2 div select +* @arg RCC_PCLK2_DIV_1 +* @arg RCC_PCLK2_DIV_2 +* @arg RCC_PCLK2_DIV_4 +* @arg RCC_PCLK2_DIV_8 +* @arg RCC_PCLK2_DIV_16 +*@note : PLLPCLK = Fin * PLLF / PLLN / PLLP +* PLLQCLK = Fin * PLLF / PLLN / PLLQ +* 1MHz <= ( Fin / PLLN ) <= 2MHz +* 100MHz <= ((Fin / PLLN) * PLLF) <= 550MHz +* 30MHz <= ((Fin / PLLN) * PLLF / PLLP) <= 220MHz +* 16MHz <= ((Fin / PLLN) * PLLF / PLLQ) <= 220MHz +*@return: none +******************************************************************************/ +HAL_StatusTypeDef SystemClock_Config(uint32_t sysclkSel, uint32_t pclk1Div, \ + uint32_t pclk2Div, uint32_t pclk3Div, uint32_t pclk4Div) +{ +// uint32_t pllf; +// uint32_t plln; +// uint32_t pllp; +// uint32_t pllq; +// uint32_t sysdiv; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + switch(sysclkSel) + { + case SYSCLK_220M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 330; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_200M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 300; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_180M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 270; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_160M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 240; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_100M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 300; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 4; + RCC_OscInitStruct.PLL1.PLLQ = 4; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_80M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 120; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_64M_SRC_RCH: + case SYSCLK_32M_SRC_RCH: + case SYSCLK_16M_SRC_RCH: + case SYSCLK_8M_SRC_RCH: + case SYSCLK_4M_SRC_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_RCH_DIV16; + RCC_OscInitStruct.PLL1.PLLF = 96; + RCC_OscInitStruct.PLL1.PLLN = 3; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1UL << (sysclkSel - SYSCLK_64M_SRC_RCH); + break; + + case SYSCLK_220M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 330; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_210M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 315; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_200M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 300; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_190M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 285; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_180M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 270; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_170M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 255; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_160M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 240; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_150M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 225; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_140M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 210; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_130M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 195; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_120M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 180; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_110M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 165; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_100M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 300; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 4; + RCC_OscInitStruct.PLL1.PLLQ = 4; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_90M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 270; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 4; + RCC_OscInitStruct.PLL1.PLLQ = 4; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_80M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 120; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_70M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 105; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_64M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 96; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_60M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 90; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_50M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 150; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 4; + RCC_OscInitStruct.PLL1.PLLQ = 4; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_48M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 144; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 4; + RCC_OscInitStruct.PLL1.PLLQ = 4; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_40M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 240; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 8; + RCC_OscInitStruct.PLL1.PLLQ = 8; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_30M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 180; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 8; + RCC_OscInitStruct.PLL1.PLLQ = 8; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_24M_SRC_XTH_12M: + case SYSCLK_12M_SRC_XTH_12M: + case SYSCLK_8M_SRC_XTH_12M: + case SYSCLK_4M_SRC_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_PLL1; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_OscInitStruct.PLL1.PLL = ENABLE; + RCC_OscInitStruct.PLL1.Source = RCC_PLL_SOURCE_XTH; + RCC_OscInitStruct.PLL1.PLLF = 144; + RCC_OscInitStruct.PLL1.PLLN = 9; + RCC_OscInitStruct.PLL1.PLLP = 4; + RCC_OscInitStruct.PLL1.PLLQ = 4; + RCC_OscInitStruct.PLL1.PLLPCLK = ENABLE; + RCC_OscInitStruct.PLL1.PLLQCLK = DISABLE; + RCC_OscInitStruct.PLL1.SSC = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_PLL1PCLK; + if (sysclkSel == SYSCLK_24M_SRC_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 2; + if (sysclkSel == SYSCLK_12M_SRC_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 4; + if (sysclkSel == SYSCLK_8M_SRC_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 6; + if (sysclkSel == SYSCLK_4M_SRC_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 12; + break; + + case SYSCLK_64M_RCH: + case SYSCLK_32M_RCH: + case SYSCLK_16M_RCH: + case SYSCLK_8M_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_RCH; + RCC_ClkInitStruct.SYSCLKDiv0 = 1UL << (sysclkSel - SYSCLK_64M_RCH); + break; + + case SYSCLK_4M_RCH: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_RCH; + RCC_OscInitStruct.RCH = ENABLE; + RCC_OscInitStruct.RCHDiv16 = ENABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_RCH; + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + break; + + case SYSCLK_12M_XTH_12M: + case SYSCLK_6M_XTH_12M: + case SYSCLK_4M_XTH_12M: + RCC_OscInitStruct.OscType = RCC_OSC_TYPE_XTH; + RCC_OscInitStruct.XTH = ENABLE; + RCC_OscInitStruct.XTHBypass = DISABLE; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLK_SOURCE_XTH; + if (sysclkSel == SYSCLK_12M_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 1; + else if (sysclkSel == SYSCLK_6M_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 2; + else if (sysclkSel == SYSCLK_4M_XTH_12M) + RCC_ClkInitStruct.SYSCLKDiv0 = 3; + break; + + default: + return (HAL_ERROR); + } + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + return (HAL_ERROR); + + RCC_ClkInitStruct.ClockType = RCC_CLOCK_TYPE_SYSCLK | \ + RCC_CLOCK_TYPE_SYSDIV0 | RCC_CLOCK_TYPE_SYSDIV1 | \ + RCC_CLOCK_TYPE_PCLK1 | RCC_CLOCK_TYPE_PCLK2 | \ + RCC_CLOCK_TYPE_PCLK3 | RCC_CLOCK_TYPE_PCLK4; + RCC_ClkInitStruct.SYSCLKDiv1 = 1; + RCC_ClkInitStruct.PCLK1Div = pclk1Div; + RCC_ClkInitStruct.PCLK2Div = pclk2Div; + RCC_ClkInitStruct.PCLK3Div = pclk3Div; + RCC_ClkInitStruct.PCLK4Div = pclk4Div; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) + return (HAL_ERROR); + return (HAL_OK); +} + +/********************************************************************************* +* Function : System_Module_Enable +* Description : enable module clock +* Input : module id +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Module_Enable(enum_Enable_ID_t fe_ID_Index) +{ + assert_param(fe_ID_IndexAHB1CKENR))[fe_ID_Index>>5] |= (1UL<<(fe_ID_Index&0x1F)); + + HAL_SimpleDelay(2); +} + +/********************************************************************************* +* Function : System_Module_Disable +* Description : disable module clock +* Input : module id +* Output : none +* Author : Chris_Kyle +**********************************************************************************/ +void System_Module_Disable(enum_Enable_ID_t fe_ID_Index) +{ + assert_param(fe_ID_IndexAHB1CKENR))[fe_ID_Index>>5] &= (~(1UL<<(fe_ID_Index&0x1F))); +} + + +#ifdef DATA_IN_ExtSRAM + +__attribute__((weak)) void SystemInit_ExtMemCtl(void) +{ +} + +#endif /* (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_acm32h5xx.h b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_acm32h5xx.h new file mode 100644 index 0000000000000000000000000000000000000000..d5c3e057db5400631250492ac5b57fdccb17ce28 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/Device/system_acm32h5xx.h @@ -0,0 +1,415 @@ + +/****************************************************************************** +*@file : system_acm32h5xx.h +*@brief : CMSIS Cortex-M33 Device Peripheral Access Layer System Source File +******************************************************************************/ + +#ifndef __SYSTEM_ACM32H5XX_H +#define __SYSTEM_ACM32H5XX_H + +#include "acm32h5xx_hal_conf.h" + +typedef enum +{ + SYSCLK_220M_SRC_RCH = 0, + SYSCLK_200M_SRC_RCH, + SYSCLK_180M_SRC_RCH, + SYSCLK_160M_SRC_RCH, + SYSCLK_100M_SRC_RCH, + SYSCLK_80M_SRC_RCH, + SYSCLK_64M_SRC_RCH, + SYSCLK_32M_SRC_RCH, + SYSCLK_16M_SRC_RCH, + SYSCLK_8M_SRC_RCH, + SYSCLK_4M_SRC_RCH, + + SYSCLK_220M_SRC_XTH_12M, + SYSCLK_210M_SRC_XTH_12M, + SYSCLK_200M_SRC_XTH_12M, + SYSCLK_190M_SRC_XTH_12M, + SYSCLK_180M_SRC_XTH_12M, + SYSCLK_170M_SRC_XTH_12M, + SYSCLK_160M_SRC_XTH_12M, + SYSCLK_150M_SRC_XTH_12M, + SYSCLK_140M_SRC_XTH_12M, + SYSCLK_130M_SRC_XTH_12M, + SYSCLK_120M_SRC_XTH_12M, + SYSCLK_110M_SRC_XTH_12M, + SYSCLK_100M_SRC_XTH_12M, + SYSCLK_90M_SRC_XTH_12M, + SYSCLK_80M_SRC_XTH_12M, + SYSCLK_70M_SRC_XTH_12M, + SYSCLK_64M_SRC_XTH_12M, + SYSCLK_60M_SRC_XTH_12M, + SYSCLK_50M_SRC_XTH_12M, + SYSCLK_48M_SRC_XTH_12M, + SYSCLK_40M_SRC_XTH_12M, + SYSCLK_30M_SRC_XTH_12M, + SYSCLK_24M_SRC_XTH_12M, + SYSCLK_12M_SRC_XTH_12M, + SYSCLK_8M_SRC_XTH_12M, + SYSCLK_4M_SRC_XTH_12M, + + SYSCLK_64M_RCH, + SYSCLK_32M_RCH, + SYSCLK_16M_RCH, + SYSCLK_8M_RCH, + SYSCLK_4M_RCH, + + SYSCLK_12M_XTH_12M, + SYSCLK_6M_XTH_12M, + SYSCLK_4M_XTH_12M, + + SYSCLK_MAX, + +}SYSCLK_SelectTypeDef; + +/* + * @brief Peripheral Enable structures definition + */ +typedef enum +{ + //Peripheral on AHB1 + EN_DMA1 = 0, + EN_DMA2, + EN_CRC = 5, + EN_ETHMAC, + EN_ETHTX, + EN_ETHRX, + EN_DMA2D = 9, + EN_SPI1, + EN_SPI2, + EN_SPI3, + EN_SPI4, + EN_SPI5, + EN_SPI6, + EN_OTG1 = 20, + EN_OTG2 = 21, + EN_FDCAN1, + EN_FDCAN2, + EN_BKPSRAM = 27, + EN_ROM, + EN_SRAM1, + EN_SRAM2, + EN_SRAM3, + + //Peripheral on AHB2 + EN_GPIOA = (32+0), + EN_GPIOB, + EN_GPIOC, + EN_GPIOD, + EN_GPIOE, + EN_GPIOF, + EN_GPIOG, + EN_GPIOH, + EN_GPIOI, + EN_GPIOJ, + EN_GPIOK, + EN_GPIOL, + EN_GPIOM, + EN_GPION, + EN_GPIOO, + EN_GPIOP, + EN_GPIOQ, + EN_ADC12 = (32+17), + EN_ADC3, + EN_DAC1, + EN_DAC2, + EN_DCMI = (32+23), + EN_AESPI1, + EN_AES, + EN_HRNG, + EN_CORDIC, + EN_FDCAN3 = (32+28), + EN_THM = (32+31), + + //Peripheral on AHB3 + EN_QSPI7 = (32*2+0), + EN_QSPI8, + EN_SDMMC = (32*2+4), + EN_OSPI1 = (32*2+8), + EN_OSPI2, + EN_FMC = (32*2+12), + + //Peripheral on APB11 + EN_TIM2 = (32*3+0), + EN_TIM3, + EN_TIM4, + EN_TIM5, + EN_TIM6, + EN_TIM7, + EN_TIM12, + EN_TIM13, + EN_TIM14, + EN_RTC = (32*3+10), + EN_WDT = (32*3+11), + EN_I2S1 = (32*3+14), + EN_I2S2, + EN_I2S3, + EN_UART2, + EN_UART3, + EN_UART4, + EN_UART5, + EN_I2C1, + EN_I2C2, + EN_I2C3, + EN_I2C4, + EN_PMU = (32*3+27), + EN_LPTIM1 = (32*3+30), + EN_LPUART1, + + //Peripheral on APB12 + EN_LPTIM2 = (32*4+1), + EN_UART7, + EN_UART8, + EN_TIM25, + EN_TIM26, + EN_EFUSE1, + EN_EFUSE2, + + //Peripheral on APB2 + EN_SYSCFG = (32*5+0), + EN_CMP1 = (32*5+2), + EN_EXTI = (32*5+4), + EN_TIM1 = (32*5+6), + EN_TIM8 = (32*5+8), + EN_UART1, + EN_UART6, + EN_TIM15, + EN_TIM16, + EN_TIM17, + EN_TIM20 = (32*5+15), + EN_TKEY = (32*5+18), + EN_LTDC, + EN_TIM9 = (32*5+21), + EN_TIM10, + EN_TIM11, + EN_TIM18, + EN_TIM19, + EN_TIM21, + EN_TIM22, + EN_TIM23, + EN_TIM24, + EN_UART9, + EN_UART10, + + //Peripheral on APB3 + EN_LPTIM3 = (32*6+0), + EN_LPTIM4, + EN_LPTIM5, + EN_LPTIM6, + + //Peripheral on APB4 + EN_SPWM1 = (32*7+0), + EN_SPWM2, + EN_DPWM1, + EN_DPWM2, + EN_DPWM3, + EN_DPWM4, + EN_PNDL, + EN_LPT, + EN_MDAC, + EN_SPWM3 = (32*7+12), + EN_SPWM4, + EN_SPWM5, + EN_SPWM6, + EN_DPWM5, + EN_DPWM6, + + EN_MODULE_MAX = (32*8) + +}enum_Enable_ID_t; + + +/* + * @brief Peripheral Reset structures definition + */ +typedef enum +{ + //Peripheral on AHB1 + RST_DMA1 = 0, + RST_DMA2, + RST_CRC = 5, + RST_ETH, + RST_DMA2D = 9, + RST_SPI1, + RST_SPI2, + RST_SPI3, + RST_SPI4, + RST_SPI5, + RST_SPI6, + RST_OTG1 = 20, + RST_OTG2 = 21, + RST_FDCAN1, + RST_FDCAN2, + + //Peripheral on AHB2 + RST_GPIOA = (32+0), + RST_GPIOB, + RST_GPIOC, + RST_GPIOD, + RST_GPIOE, + RST_GPIOF, + RST_GPIOG, + RST_GPIOH, + RST_GPIOI, + RST_GPIOJ, + RST_GPIOK, + RST_GPIOL, + RST_GPIOM, + RST_GPION, + RST_GPIOO, + RST_GPIOP, + RST_GPIOQ, + RST_ADC12 = (32+17), + RST_ADC3, + RST_DAC1, + RST_DAC2, + RST_DCMI = (32+23), + RST_UAC = (32+27), + RST_FDCAN3 = (32+28), + RST_THM = (32+31), + + //Peripheral on AHB3 + RST_QSPI7 = (32*2+0), + RST_QSPI8, + RST_SDMMC = (32*2+4), + RST_OSPI1 = (32*2+8), + RST_OSPI2, + RST_FMC = (32*2+12), + + //Peripheral on APB11 + RST_TIM2 = (32*3+0), + RST_TIM3, + RST_TIM4, + RST_TIM5, + RST_TIM6, + RST_TIM7, + RST_TIM12, + RST_TIM13, + RST_TIM14, + RST_WDT = (32*3+11), + RST_I2S1 = (32*3+14), + RST_I2S2, + RST_I2S3, + RST_UART2, + RST_UART3, + RST_UART4, + RST_UART5, + RST_I2C1, + RST_I2C2, + RST_I2C3, + RST_I2C4, + RST_PMU = (32*3+27), + RST_LPTIM1 = (32*3+30), + RST_LPUART1, + + //Peripheral on APB12 + RST_LPTIM2 = (32*4+1), + RST_UART7, + RST_UART8, + RST_TIM25, + RST_TIM26, + RST_EFUSE1, + RST_EFUSE2, + + //Peripheral on APB2 + RST_SYSCFG = (32*5+0), + RST_CMP1 = (32*5+2), + RST_EXTI = (32*5+4), + RST_TIM1 = (32*5+6), + RST_TIM8 = (32*5+8), + RST_UART1, + RST_UART6, + RST_TIM15, + RST_TIM16, + RST_TIM17, + RST_TIM20 = (32*5+15), + RST_TKEY = (32*5+18), + RST_LTDC, + RST_TIM9 = (32*5+21), + RST_TIM10, + RST_TIM11, + RST_TIM18, + RST_TIM19, + RST_TIM21, + RST_TIM22, + RST_TIM23, + RST_TIM24, + RST_UART9, + RST_UART10, + + //Peripheral on APB3 + RST_LPTIM3 = (32*6+0), + RST_LPTIM4, + RST_LPTIM5, + RST_LPTIM6, + + //Peripheral on APB4 + RST_SPWM1 = (32*7+0), + RST_SPWM2, + RST_DPWM1, + RST_DPWM2, + RST_DPWM3, + RST_DPWM4, + RST_PNDL, + RST_LPT, + RST_MDAC, + RST_SPWM3 = (32*7+12), + RST_SPWM4, + RST_SPWM5, + RST_SPWM6, + RST_DPWM5, + RST_DPWM6, + +}enum_RST_ID_t; + + +/****** system core clock select, uesr config ***********/ +#define SYSCLK_SELECT SYSCLK_220M_SRC_XTH_12M + +/****************************************************************************** +*@brief : PCLK1_DIV_SELECT: pclk1 div select, uesr config +* @arg 1, 2, 4, 8, 16 +******************************************************************************/ +#define PCLK1_DIV_SELECT 2 + +/****************************************************************************** +*@brief : PCLK2_DIV_SELECT: pclk2 div select, uesr config +* @arg 1, 2, 4, 8, 16 +******************************************************************************/ +#define PCLK2_DIV_SELECT 2 + + +/****************************************************************************** +*@brief : PCLK3_DIV_SELECT: pclk3 div select, uesr config +* @arg 1, 2, 4, 8, 16 +******************************************************************************/ +#define PCLK3_DIV_SELECT 2 + + +/****************************************************************************** +*@brief : PCLK4_DIV_SELECT: pclk4 div select, uesr config +* @arg 1, 2, 4, 8, 16 +******************************************************************************/ +#define PCLK4_DIV_SELECT 2 + +/****************************************************************************** +*@note : SystemCoreClock variable is updated in three ways: +* 1) by calling CMSIS function SystemCoreClockUpdate() +* 2) by calling HAL API function HAL_RCC_GetSysClkFreq() +* 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency +* If you use this function to configure the system clock; then there +* is no need to call the 2 first functions listed above, since SystemCoreClock +* variable is updated automatically. +******************************************************************************/ +extern volatile uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); +HAL_StatusTypeDef SystemClock_Config(uint32_t sysclkSel, uint32_t pclk1Div, \ + uint32_t pclk2Div, uint32_t pclk3Div, uint32_t pclk4Div); +void System_Module_Enable(enum_Enable_ID_t fe_ID_Index); +void System_Module_Disable(enum_Enable_ID_t fe_ID_Index); + +#endif /* __SYSTEM_ACM32H5XX_H */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_HCD.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_HCD.h new file mode 100644 index 0000000000000000000000000000000000000000..61fcb94f18d209606ac2801739bad4c9666ff2b9 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_HCD.h @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file hal_hcd.h + * @author MCD Application Team + * @brief Header file of HCD HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 Aisinochip. + * All rights reserved. + * + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef HAL_HCD_H +#define HAL_HCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "LL_USB.h" + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** @addtogroup + * @{ + */ + +/** @addtogroup HCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Types HCD Exported Types + * @{ + */ + +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition + * @{ + */ +typedef enum +{ + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 +} HCD_StateTypeDef; + +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +/** + * @} + */ + +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +typedef struct __HCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +{ + HCD_TypeDef *Instance; /*!< Register base address */ + HCD_InitTypeDef Init; /*!< HCD required parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ + HAL_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +} HCD_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Constants HCD Exported Constants + * @{ + */ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED + +/** + * @} + */ + +/** @defgroup HCD_PHY_Module HCD PHY Module + * @{ + */ +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Macros HCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); + +/* Non-Blocking mode: Interrupt */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros HCD Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_HCD_H */ + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_PCD.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_PCD.h new file mode 100644 index 0000000000000000000000000000000000000000..73bf46f1c176609022aea93fcd37475001dfe113 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_PCD.h @@ -0,0 +1,409 @@ +/** + ****************************************************************************** + * @file ACM32H5xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 Aisinochip. + * All rights reserved. + * + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef HAL_PCD_H +#define HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "HAL_USB_Def.h" + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) + +/** @addtogroup + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "HAL_PCD_EX.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ + ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE + +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + + +/** + * @} + */ +/** + * @} + */ + + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_PCD_H */ + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_PCD_EX.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_PCD_EX.h new file mode 100644 index 0000000000000000000000000000000000000000..199a44294d668b56a487ee447204f61db120f61f --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_PCD_EX.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file ACM32H5xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 Aisinochip. + * All rights reserved. + * + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef ACM32H5xx_HAL_PCD_EX_H +#define ACM32H5xx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "hal.h" + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** @addtogroup + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + + +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); + +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +#ifdef __cplusplus +} +#endif + + +#endif + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_USB_Def.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_USB_Def.h new file mode 100644 index 0000000000000000000000000000000000000000..854e6b84c7cbcdf2f7af82d695c05d8c83c80a48 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/HAL_USB_Def.h @@ -0,0 +1,1471 @@ + +/*********************************************************************** + * Filename : HAL_USB_Def.h + * Description : HAL usb driver header file + * Author(s) : CWT + * version : V1.0 + * Modify date : 2020-04-17 + ***********************************************************************/ + +#ifndef __HAL_USB_DEF_H__ +#define __HAL_USB_DEF_H__ + +#include "hal.h" + + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ********************/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) +#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) +#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ +#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) +#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) +#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ +#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) +#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) +#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ +#define USB_OTG_GOTGCTL_CURR_MODE_Pos (21U) +#define USB_OTG_GOTGCTL_CURR_MODE_Pos_Msk (0x1UL << USB_OTG_GOTGCTL_CURR_MODE_Pos) /*!< 0x00200000 */ +#define USB_OTG_GOTGCTL_CURR_MODE USB_OTG_GOTGCTL_CURR_MODE_Pos_Msk /*!< OTG Current Mode */ + +/******************** Bit definition for USB_OTG_HCFG register ********************/ +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ +#define USB_OTG_GOTGINT_IDCHNG_Pos (20U) +#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYIF_Pos (3U) +#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */ +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U) +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_LPMINT_Pos (27U) +#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDEM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_LPMINTM_Pos (27U) +#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for OTG register ********************/ + +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_DCDET_Pos (0U) +#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */ +#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ +#define USB_OTG_GCCFG_PDET_Pos (1U) +#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */ +#define USB_OTG_GCCFG_SDET_Pos (2U) +#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ +#define USB_OTG_GCCFG_PS2DET_Pos (3U) +#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */ +#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_BCDEN_Pos (17U) +#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ +#define USB_OTG_GCCFG_DCDEN_Pos (18U) +#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define USB_OTG_GCCFG_PDEN_Pos (19U) +#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define USB_OTG_GCCFG_SDEN_Pos (20U) +#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define USB_OTG_GCCFG_VBDEN_Pos (21U) +#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< VBUS mode enable */ +#define USB_OTG_GCCFG_OTGIDEN_Pos (22U) +#define USB_OTG_GCCFG_OTGIDEN_Msk (0x1UL << USB_OTG_GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_GCCFG_OTGIDEN USB_OTG_GCCFG_OTGIDEN_Msk /*!< OTG Id enable */ +#define USB_OTG_GCCFG_PHYHSEN_Pos (23U) +#define USB_OTG_GCCFG_PHYHSEN_Msk (0x1UL << USB_OTG_GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_GCCFG_PHYHSEN USB_OTG_GCCFG_PHYHSEN_Msk /*!< HS PHY enable */ + +/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_GLPMCFG register ********************/ +#define USB_OTG_GLPMCFG_LPMEN_Pos (0U) +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition for USB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!
© Copyright (c) 2024 Aisinochip. + * All rights reserved. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LL_USB_H +#define LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +#include "hal.h" + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** @addtogroup ACM32H5 HAL + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USB Mode definition + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_OTG_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_OTG_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_OTG_HCStateTypeDef; + +/** + * @brief USB OTG Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref USB_Core_PHY_ */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + + uint32_t phy_cfg; /*!< 60M-8BIT or 30M-16BIT */ +} USB_OTG_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_EP_Type_ */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ +} USB_OTG_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type_ */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t last_xfer_count; /*!< last transfer count */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count.*/ + + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HCTypeDef; +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_HS_OTG_ID1 1 +#define USB_HS_OTG_ID2 2 +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +#define USB_OTG_HS_EMBEDDED_PHY 3U + +#if !defined (USB_HS_PHYC_TUNE_VALUE) +#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ +#endif /* USB_HS_PHYC_TUNE_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE_8BIT 9U +#define USBD_HS_TRDT_VALUE_16BIT 5U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define DEP0CTL_MPS_64 0U +#define DEP0CTL_MPS_32 1U +#define DEP0CTL_MPS_16 2U +#define DEP0CTL_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_60_MHZ 0U +#define HCFG_30_MHZ 1U + +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U + +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +#define EP_ADDR_MSK 0xFU +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); + +HAL_StatusTypeDef USBD_EP0_Send_Data(void *hpcd, uint8_t * data, uint16_t length); + +HAL_StatusTypeDef USBD_EPx_Receive_Zero_Packet(uint32_t base_address, uint32_t epnum); + +HAL_StatusTypeDef USBD_EPx_Send_Data(void *hpcd, uint32_t ep_num, uint8_t * data, uint16_t length); + +HAL_StatusTypeDef USBD_EPx_Send_Data_Ex(void *hpcd, uint32_t ep_num, uint32_t ep_max, uint8_t * data, uint16_t length); + +uint32_t USBD_EPx_Has_Receive_Data_Started(void * p_hpcd, uint32_t ep_num); + +uint32_t USBD_EPx_Host_Sent_Data_to_OutEP(void * p_hpcd, uint32_t ep_num); + +void USBD_EPx_Clear_Received_Data(void * p_hpcd, uint32_t ep_num); + +uint32_t USBD_EPx_Get_Out_EP_Error(void * p_hpcd, uint32_t ep_num); + +void USBD_EPx_Clear_Out_EP_Error(void * p_hpcd, uint32_t ep_num); + +uint8_t USB_GetIdStatus(USB_OTG_GlobalTypeDef *USBx); + +HAL_StatusTypeDef USB_SetTestMode(USB_OTG_GlobalTypeDef *USBx, uint32_t value); + +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +#ifdef __cplusplus +} +#endif + + +#endif + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal.h new file mode 100644 index 0000000000000000000000000000000000000000..ff54835af15aa4ab2a64f0e92927fb6b82b42fde --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal.h @@ -0,0 +1,60 @@ +/****************************************************************************** +*@file : hal.h +*@brief : +******************************************************************************/ + +#ifndef __HAL_H +#define __HAL_H + +#include "rtdef.h" +#include "acm32h5xx_hal_conf.h" + +typedef struct +{ + uint32_t clktickLatest; + uint32_t mstickLatest; + uint32_t clkCount; + uint32_t msCount; +} HAL_DelayHandleTypeDef; + +typedef struct +{ + uint32_t intPrio; //жȼ + uint32_t freq; //ʱƵʣλ Hz + uint32_t period; //ʱ + uint32_t clkPerUs; //ÿ΢CLK + uint32_t clkPerMs; //ÿCLK + uint32_t msPeriod; //ÿڵ΢ + uint32_t usPer65536Clk; //65536 clk΢ +} HAL_SysTickHandleTypeDef; + +extern HAL_SysTickHandleTypeDef g_systickHandle; + + +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t intPrio, uint32_t msPeriod); +void HAL_IncTick(void); +extern rt_tick_t rt_tick_get(void); + +#define HAL_GetTick() rt_tick_get() +#define HAL_Delay(msDelay) rt_thread_mdelay(msDelay) + +HAL_StatusTypeDef HAL_SetTickMsPeriod(int msPeriod); +uint32_t HAL_GetTickMsPeriod(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +void HAL_DelayClks(uint32_t clks); +void HAL_DelayUs(uint32_t us); +void HAL_DelayMs(uint32_t ms); +void HAL_SimpleDelay(volatile uint32_t delay); +void HAL_StartDelay(HAL_DelayHandleTypeDef *hdelay); +void HAL_UpdateDelay(HAL_DelayHandleTypeDef *hdelay); +uint32_t HAL_GetClkDelay(HAL_DelayHandleTypeDef *hdelay); +uint32_t HAL_GetUsDelay(HAL_DelayHandleTypeDef *hdelay); +uint32_t HAL_GetMsDelay(HAL_DelayHandleTypeDef *hdelay); +void HAL_GetUID(uint32_t *UID); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_adc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..ff9f2b25e94b208cc9081277f8b21fad44d90541 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_adc.h @@ -0,0 +1,904 @@ +/****************************************************************************** +*@file : hal_adc.h +*@brief : Header file of ADC HAL module. +******************************************************************************/ +#ifndef __HAL_ADC_H__ +#define __HAL_ADC_H__ + + +#include "hal.h" + + +/** + * @brief ADC ExTigger structure definition + */ +typedef struct +{ + uint32_t ExTrigSel; /*!< Configures the regular channel trig mode. */ + + uint32_t JExTrigSel; /*!< Configures the inject channel trig mode. */ + +}ADC_ExTrigTypeDef; + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. */ + +}ADC_OversamplingTypeDef; + + + + +/** + * @brief ADC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specify the ADC clock source. */ + + uint32_t ClockPrescaler; /*!< Specify the ADC clock div from the PCLK. */ + + uint32_t Resolution; /*!< Configure the ADC resolution. */ + + uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). */ + + FunctionalState ConConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for + ADC group regular,after the first ADC conversion start trigger occurred (software start or external trigger). */ + FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence + (main sequence subdivided in successive parts).Discontinuous mode is used only if sequencer is enabled + (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.Discontinuous mode can be enabled only + if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. */ + uint32_t NbrOfDiscConversion; /*!< Regular channel intermittent mode channel count. */ + + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge by default. */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. */ + + uint32_t ChannelEn; /*!< Specify the enable ADC channels. */ + + + uint32_t DMAMode; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) + or in continuous mode (DMA transfer unlimited, whatever number of conversions). */ + uint32_t OverMode; /*!< ADC_OVERMODE_DISABLE,ADC_OVERMODE_ENABLE */ + + uint32_t OverSampMode; /*!< Specify whether the oversampling feature is enabled or disabled. */ + + ADC_OversamplingTypeDef Oversampling; /*!< Specify ADC group regular oversampling structure. */ + + uint32_t AnalogWDGEn; + + + +}ADC_InitTypeDef; + + +typedef struct +{ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. */ + + uint32_t Sq; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank. */ + + uint32_t Smp; /*!< Sampling time value to be set for the selected channel. */ + + uint32_t Diff; /*!< Select differential input.In differential mode: Differential measurement is carried out + between the selected channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured automatically. */ + uint32_t OffsetNumber; /*!< Select the offset number. */ + + uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. + Offset value must be a positive number. */ + + uint32_t OffsetCalculate; /*!< Define if the offset should be substracted (negative sign) + or added (positive sign) from or to the raw converted data. */ + uint32_t Offsetsign; /*!< Define if the offset should be saturated upon under or over flow. */ + +}ADC_ChannelConfTypeDef; + +typedef struct +{ + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. For Analog Watchdog 1: + Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. */ + + uint32_t RegularChannel; /*!< Select the analog watchdog regular channe */ + + uint32_t InjectChannel; /*!< Select the analog watchdog inject channe */ + + uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. */ + + uint32_t Diff; /*!< Select differential input. */ + +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief ADC Injected Conversion Oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. */ + +} ADC_InjOversamplingTypeDef; + + +typedef struct +{ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure */ + + uint32_t InjectedRank; /*!< Rank in the injected group sequencer */ + + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. */ + + uint32_t InjectedDiff; /*!< Selection of differential input. */ + + uint32_t InjectedOffsetNumber; /*!< Selects the offset number. */ + + uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. */ + + uint32_t InjectedOffsetCalculate; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. */ + + uint32_t InjectedOffsetSign; /*!< Define if the offset should be saturated upon under or over flow. */ + + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. */ + + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. */ + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one */ + + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. */ + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. */ + + FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. */ + + ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. */ + +}ADC_InjectionConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. */ + + uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. */ + + uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. */ + +}ADC_MultiModeTypeDef; + +/** + * @brief ADC handle Structure definition + */ +typedef struct __ADC_HandleTypeDef +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ +#endif + uint32_t ChannelNum; /*!< Total enable regular group channel number*/ + + uint32_t *AdcResults; /*!< Point to the convert results*/ + + void (*ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + + void (*GroupCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC regular group conversion complete callback */ + + void (*InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC injected conversion complete callback */ + + void (*InjectedGroupConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC injected Group conversion complete callback */ + + void (*LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog callback */ + +}ADC_HandleTypeDef; + + +/** @defgroup ADC1/ADC2/ADC3 + * @{ + */ +#define IS_ADC_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || ((INSTANCE) == ADC2) || ((INSTANCE) == ADC3)) +/** + * @} + */ + +/** @defgroup ADC Trig source define + * @{ + */ +/* | Trig Source | Regular | Inject | * + * | ADC_EXTERNAL_TIG0 | TIM1_CC1 | TIM1_TRGO | * + * | ADC_EXTERNAL_TIG1 | TIM1_CC2 | TIM1_CC4 | * + * | ADC_EXTERNAL_TIG2 | TIM1_CC3 | TIM2_TRGO | * + * | ADC_EXTERNAL_TIG3 | TIM2_CC2 | TIM2_CC1 | * + * | ADC_EXTERNAL_TIG4 | TIM3_TRGO | TIM3_CC4 | * + * | ADC_EXTERNAL_TIG5 | TIM4_CC4 | TIM4_TRGO | * + * | ADC_EXTERNAL_TIG6 | EXTI Line 11 | EXTI Line 15 | * + * | ADC_EXTERNAL_TIG7 | TIM8_TRGO | TIM8_CC4 | * + * | ADC_EXTERNAL_TIG8 | TIM8_TRGO2 | TIM1_TRGO2 | * + * | ADC_EXTERNAL_TIG9 | TIM1_TRGO | TIM8_TRGO | * + * | ADC_EXTERNAL_TIG10 | TIM1_TRGO2 | TIM8_TRGO2 | * + * | ADC_EXTERNAL_TIG11 | TIM2_TRGO | TIM3_CC3 | * + * | ADC_EXTERNAL_TIG12 | TIM4_TRGO | TIM3_TRGO | * + * | ADC_EXTERNAL_TIG13 | TIM6_TRGO | TIM3_CC1 | * + * | ADC_EXTERNAL_TIG14 | TIM15_TRGO | TIM6_TRGO | * + * | ADC_EXTERNAL_TIG15 | TIM3_CC4 | TIM15_TRGO | * + * | ADC_EXTERNAL_TIG16 | | | * + * | ADC_EXTERNAL_TIG17 | | | * + * | ADC_EXTERNAL_TIG18 | LPTIM1_OUT | LPTIM1_OUT | * + * | ADC_EXTERNAL_TIG19 | LPTIM2_OUT | LPTIM2_OUT | * + * | ADC_EXTERNAL_TIG20 | LPTIM3_OUT | LPTIM3_OUT | */ +#define ADC_EXTERNAL_TIG0 (0U) +#define ADC_EXTERNAL_TIG1 (1U) +#define ADC_EXTERNAL_TIG2 (2U) +#define ADC_EXTERNAL_TIG3 (3U) +#define ADC_EXTERNAL_TIG4 (4U) +#define ADC_EXTERNAL_TIG5 (5U) +#define ADC_EXTERNAL_TIG6 (6U) +#define ADC_EXTERNAL_TIG7 (7U) +#define ADC_EXTERNAL_TIG8 (8U) +#define ADC_EXTERNAL_TIG9 (9U) +#define ADC_EXTERNAL_TIG10 (10U) +#define ADC_EXTERNAL_TIG11 (11U) +#define ADC_EXTERNAL_TIG12 (12U) +#define ADC_EXTERNAL_TIG13 (13U) +#define ADC_EXTERNAL_TIG14 (14U) +#define ADC_EXTERNAL_TIG15 (15U) +#define ADC_EXTERNAL_TIG16 (16U) +#define ADC_EXTERNAL_TIG17 (17U) +#define ADC_EXTERNAL_TIG18 (18U) +#define ADC_EXTERNAL_TIG19 (19U) +#define ADC_EXTERNAL_TIG20 (20U) +#define ADC_SOFTWARE_START (32U) +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNAL_TIG0) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG1) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG2) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG3) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG4) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG5) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG6) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG7) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG8) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG9) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG10) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG11) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG12) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG13) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG14) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG15) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG16) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG17) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG18) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG19) || \ + ((REGTRIG) == ADC_EXTERNAL_TIG20) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC External Trigger Edge + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0U) +#define ADC_EXTERNALTRIGCONVEDGE_RISING (1U) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (2U) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (3U) +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) +/** + * @} + */ + +/** @defgroup ADC Data Align +* @{ +*/ +#define ADC_DATAALIGN_RIGHT (0x00U) +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || ((ALIGN) == ADC_DATAALIGN_LEFT)) +/** + * @} + */ + +/** @defgroup ADC Continuous +* @{ +*/ +#define ADC_CONT_DISABLE (0x00U) +#define ADC_CONT_ENABLE ((uint32_t)ADC_CR1_CONT) +#define IS_ADC_CONT(CONT) (((CONT) == ADC_CONT_DISABLE) || ((CONT) == ADC_CONT_ENABLE)) +/** + * @} + */ + +/** @defgroup ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12B (0x00U) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (ADC_CR2_RES_0) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (ADC_CR2_RES_1) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (ADC_CR2_RES_0 | ADC_CR2_RES_1) /*!< ADC resolution 6 bits */ +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B)) +/** + * @} + */ + +/** @defgroup ADC ClockPrescale + * @{ + */ +#define IS_ADC_CLOCKDIV(CLOCKDIV) (((CLOCKDIV) >= 0x01) && ((CLOCKDIV) <= 0x40)) + +/** + * @} + */ + +/** @defgroup ADC ClockSource + * @{ + */ +#define ADC_CLOCKSOURCE_HCLK (0x00U) +#define ADC_CLOCKSOURCE_PLL3PCLK ((uint32_t)ADC_CCR_CLKMODE) +#define IS_ADC_CLOCKSOURCE(SOURCE) (((SOURCE) == ADC_CLOCKSOURCE_HCLK) || ((SOURCE) == ADC_CLOCKSOURCE_PLL3PCLK)) + +/** + * @} + */ + +/** @defgroup Multimode + * @{ + */ +#define ADC_MODE_INDEPENDENT (0x00U) /*!< ADC dual mode disabled (ADC independent mode) */ +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (ADC_CCR_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (ADC_CCR_DUALMOD_1) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define ADC_DUALMODE_REGINTERL_INJECSIMULT (ADC_CCR_DUALMOD_0 | ADC_CCR_DUALMOD_1) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ +#define ADC_DUALMODE_INJECSIMULT (ADC_CCR_DUALMOD_0 | ADC_CCR_DUALMOD_2) /*!< ADC dual mode enabled: group injected simultaneous */ +#define ADC_DUALMODE_REGSIMULT (ADC_CCR_DUALMOD_1 | ADC_CCR_DUALMOD_2) /*!< ADC dual mode enabled: group regular simultaneous */ +#define ADC_DUALMODE_INTERL (ADC_CCR_DUALMOD_0 | ADC_CCR_DUALMOD_1 | ADC_CCR_DUALMOD_2) /*!< ADC dual mode enabled: Combined group regular interleaved */ +#define ADC_DUALMODE_ALTERTRIG (ADC_CCR_DUALMOD_0 | ADC_CCR_DUALMOD_3) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT) || \ + ((MODE) == ADC_DUALMODE_INTERL) || \ + ((MODE) == ADC_DUALMODE_ALTERTRIG)) +/** + * @} + */ + +/** @defgroup DMA transfer mode depending on ADC resolution + * @{ + */ +#define ADC_DMAACCESSMODE_DISABLED (0x00U) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ +#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_DMADUAL_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ +#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_DMADUAL_0 | ADC_CCR_DMADUAL_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ +#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ + ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \ + ((MODE) == ADC_DMAACCESSMODE_8_6_BITS)) +/** + * @} + */ + +/** @defgroup ADC Delay Between 2 Sampling Phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (0x00U) +#define ADC_TWOSAMPLINGDELAY_6CYCLES (ADC_CCR_DELAY_0) +#define ADC_TWOSAMPLINGDELAY_7CYCLES (ADC_CCR_DELAY_1) +#define ADC_TWOSAMPLINGDELAY_8CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_1) +#define ADC_TWOSAMPLINGDELAY_9CYCLES (ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_10CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_11CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_12CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_13CYCLES (ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_14CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_15CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_16CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_17CYCLES (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_18CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_19CYCLES (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_20CYCLES (ADC_CCR_DELAY_0 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_3) +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) + +/** + * @} + */ + + +/** @defgroup ADC analog watchdog selection + * @{ + */ +#define ADC_ANALOGWATCHDOG_RCH_SINGLE (ADC_CR1_AWDSGL | ADC_CR1_AWDEN) //Single regular channel +#define ADC_ANALOGWATCHDOG_JCH_SINGLE (ADC_CR1_AWDSGL | ADC_CR1_JAWDEN) //Single Inject channel +#define ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE (ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN) //Regular or inject channel +#define ADC_ANALOGWATCHDOG_RCH_ALL (ADC_CR1_AWDEN) //All regular channels +#define ADC_ANALOGWATCHDOG_JCH_ALL (ADC_CR1_JAWDEN) //All inject channels +#define ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL (ADC_CR1_AWDEN | ADC_CR1_JAWDEN) //All regular and inject channels +#define ADC_ANALOGWATCHDOG_NONE (0x00U) +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_RCH_SINGLE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_JCH_SINGLE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_RCH_ALL) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_JCH_ALL) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) +/** + * @} + */ + +/** @defgroup ADC analog watchdog thresholds + * @{ + */ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + +/** @defgroup ADC channel number +* @{ +*/ +#define ADC_CHANNEL_0 (0U) +#define ADC_CHANNEL_1 (1U) +#define ADC_CHANNEL_2 (2U) +#define ADC_CHANNEL_3 (3U) +#define ADC_CHANNEL_4 (4U) +#define ADC_CHANNEL_5 (5U) +#define ADC_CHANNEL_6 (6U) +#define ADC_CHANNEL_7 (7U) +#define ADC_CHANNEL_8 (8U) +#define ADC_CHANNEL_9 (9U) +#define ADC_CHANNEL_10 (10U) +#define ADC_CHANNEL_11 (11U) +#define ADC_CHANNEL_12 (12U) +#define ADC_CHANNEL_13 (13U) +#define ADC_CHANNEL_14 (14U) +#define ADC_CHANNEL_15 (15U) +#define ADC_CHANNEL_16 (16U) +#define ADC_CHANNEL_17 (17U) +#define ADC_CHANNEL_18 (18U) +#define ADC_CHANNEL_19 (19U) +#define ADC_CHANNEL_VREF (13U) +#define ADC_CHANNEL_VBAT (17U) +#define ADC_CHANNEL_TEMP (18U) +#define ADC_CHANNEL_0_EN (1U << ADC_CHANNEL_0) +#define ADC_CHANNEL_1_EN (1U << ADC_CHANNEL_1) +#define ADC_CHANNEL_2_EN (1U << ADC_CHANNEL_2) +#define ADC_CHANNEL_3_EN (1U << ADC_CHANNEL_3) +#define ADC_CHANNEL_4_EN (1U << ADC_CHANNEL_4) +#define ADC_CHANNEL_5_EN (1U << ADC_CHANNEL_5) +#define ADC_CHANNEL_6_EN (1U << ADC_CHANNEL_5) +#define ADC_CHANNEL_7_EN (1U << ADC_CHANNEL_5) +#define ADC_CHANNEL_8_EN (1U << ADC_CHANNEL_8) +#define ADC_CHANNEL_9_EN (1U << ADC_CHANNEL_9) +#define ADC_CHANNEL_10_EN (1U << ADC_CHANNEL_10) +#define ADC_CHANNEL_11_EN (1U << ADC_CHANNEL_11) +#define ADC_CHANNEL_12_EN (1U << ADC_CHANNEL_12) +#define ADC_CHANNEL_13_EN (1U << ADC_CHANNEL_13) +#define ADC_CHANNEL_14_EN (1U << ADC_CHANNEL_14) +#define ADC_CHANNEL_15_EN (1U << ADC_CHANNEL_15) +#define ADC_CHANNEL_16_EN (1U << ADC_CHANNEL_16) +#define ADC_CHANNEL_17_EN (1U << ADC_CHANNEL_17) +#define ADC_CHANNEL_18_EN (1U << ADC_CHANNEL_18) +#define ADC_CHANNEL_19_EN (1U << ADC_CHANNEL_19) +#define ADC_CHANNEL_VREF_EN (1U << ADC_CHANNEL_VREF) +#define ADC_CHANNEL_VBAT_EN (1U << ADC_CHANNEL_VBAT) +#define ADC_CHANNEL_TEMP_EN (1U << ADC_CHANNEL_TEMP) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) < 32)) + +/** + * @} + */ + +/** @defgroup Sampling time + * @{ + */ +#define ADC_SMP_CLOCK_3 (0U) +#define ADC_SMP_CLOCK_5 (1U) +#define ADC_SMP_CLOCK_7 (2U) +#define ADC_SMP_CLOCK_10 (3U) +#define ADC_SMP_CLOCK_13 (4U) +#define ADC_SMP_CLOCK_16 (5U) +#define ADC_SMP_CLOCK_20 (6U) +#define ADC_SMP_CLOCK_30 (7U) +#define ADC_SMP_CLOCK_60 (8U) +#define ADC_SMP_CLOCK_80 (9U) +#define ADC_SMP_CLOCK_100 (10U) +#define ADC_SMP_CLOCK_120 (11U) +#define ADC_SMP_CLOCK_160 (12U) +#define ADC_SMP_CLOCK_260 (13U) +#define ADC_SMP_CLOCK_320 (14U) +#define ADC_SMP_CLOCK_640 (15U) +#define IS_ADC_SMPCLOCK(SMPCLOCK) (((SMPCLOCK) == ADC_SMP_CLOCK_3) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_5) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_7) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_10) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_13) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_16) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_20) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_30) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_60) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_80) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_100) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_120) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_160) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_260) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_320) || \ + ((SMPCLOCK) == ADC_SMP_CLOCK_640)) +/** + * @} + */ + +/** @defgroup ADC sequence number +* @{ +*/ +#define ADC_SEQUENCE_SQ1 (1U) +#define ADC_SEQUENCE_SQ2 (2U) +#define ADC_SEQUENCE_SQ3 (3U) +#define ADC_SEQUENCE_SQ4 (4U) +#define ADC_SEQUENCE_SQ5 (5U) +#define ADC_SEQUENCE_SQ6 (6U) +#define ADC_SEQUENCE_SQ7 (7U) +#define ADC_SEQUENCE_SQ8 (8U) +#define ADC_SEQUENCE_SQ9 (9U) +#define ADC_SEQUENCE_SQ10 (10U) +#define ADC_SEQUENCE_SQ11 (11U) +#define ADC_SEQUENCE_SQ12 (12U) +#define ADC_SEQUENCE_SQ13 (13U) +#define ADC_SEQUENCE_SQ14 (14U) +#define ADC_SEQUENCE_SQ15 (15U) +#define ADC_SEQUENCE_SQ16 (16U) +#define IS_ADC_SEQUENCE(SEQUENCE) (((SEQUENCE) == ADC_SEQUENCE_SQ1) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ2) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ3) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ4) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ5) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ6) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ7) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ8) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ9) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ10) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ11) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ12) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ13) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ14) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ15) || \ + ((SEQUENCE) == ADC_SEQUENCE_SQ16)) +/** + * @} + */ + +/** @defgroup ADC regular length + * @{ + */ +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x01) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC regular discontinuous mode number + * @{ + */ +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) ((NUMBER) <= 0x8) +/** + * @} + */ + +/** @defgroup ADC injected rank + * @{ + */ +#define ADC_INJECTED_RANK_1 (1U) +#define ADC_INJECTED_RANK_2 (2U) +#define ADC_INJECTED_RANK_3 (3U) +#define ADC_INJECTED_RANK_4 (4U) +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) +/** + * @} + */ + +/** @defgroup ADC injected length + * @{ + */ +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) +/** + * @} + */ + +/** @defgroup Offset Number + * @{ + */ +#define ADC_OFR_1 (0U) /*!< ADC offset number 1: ADC_OFR1 */ +#define ADC_OFR_2 (1U) /*!< ADC offset number 2: ADC_OFR2 */ +#define ADC_OFR_3 (2U) /*!< ADC offset number 3: ADC_OFR3 */ +#define ADC_OFR_4 (3U) /*!< ADC offset number 4: ADC_OFR4 */ +#define ADC_OFR_NONE (4U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ +#define IS_ADC_OFFSET_NUMBER(NUMBER) (((NUMBER) < 0x5)) +/** + * @} + */ + +/** @defgroup offset + * @{ + */ +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) +/** + * @} + */ + + /** @defgroup Offset Calculate + * @{ + */ +#define ADC_OFFSET_MINUS (0x00000000UL) /*!< ADC conversion result minus offset */ +#define ADC_OFFSET_PLUS (ADC_OFRX_OFFSETY_POS) /*!< ADC conversion result plus offset */ +#define IS_ADC_OFFSET_CALCULATE(CALCULATE) (((CALCULATE) == ADC_OFFSET_MINUS) || ((CALCULATE) == ADC_OFFSET_PLUS)) +/** + * @} + */ + + +/** @defgroup Offset sign + * @{ + */ +#define ADC_OFFSET_SIGN_SIGNED (0x00000000UL) /*!< The calculation result is a signed number */ +#define ADC_OFFSET_SIGN_UNSIGNED (ADC_OFRX_OFFSETY_SAT) /*!< The calculation result is an unsigned number */ +#define IS_ADC_OFFSET_SIGN(SIGN) (((SIGN) == ADC_OFFSET_SIGN_SIGNED) || ((SIGN) == ADC_OFFSET_SIGN_UNSIGNED)) +/** + * @} + */ + +/** @defgroup JDR Number + * @{ + */ +#define ADC_JDR_1 (0U) /*!< ADC JDR number 1: ADC_JDR1 */ +#define ADC_JDR_2 (1U) /*!< ADC JDR number 2: ADC_JDR2 */ +#define ADC_JDR_3 (2U) /*!< ADC JDR number 3: ADC_JDR3 */ +#define ADC_JDR_4 (3U) /*!< ADC JDR number 4: ADC_JDR4 */ +#define ADC_JDR_NONE (4U) /*!< none */ +#define IS_ADC_JDR_NUMBER(NUMBER) ((NUMBER) < 0x5) +/** + * @} + */ + +/** @defgroup Oversampling Data shift + * @{ + */ +#define ADC_RIGHTBITSHIFT_NONE (0U) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided */ +#define ADC_RIGHTBITSHIFT_1 (1U) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 */ +#define ADC_RIGHTBITSHIFT_2 (2U) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 */ +#define ADC_RIGHTBITSHIFT_3 (3U) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 */ +#define ADC_RIGHTBITSHIFT_4 (4U) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 */ +#define ADC_RIGHTBITSHIFT_5 (5U) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 */ +#define ADC_RIGHTBITSHIFT_6 (6U) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 */ +#define ADC_RIGHTBITSHIFT_7 (7U) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 */ +#define ADC_RIGHTBITSHIFT_8 (8U) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 */ +#define IS_ADC_RIGHTBITSHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_1) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_2) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_3) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_4) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_5) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_6) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_7) || \ + ((SHIFT) == ADC_RIGHTBITSHIFT_8)) +/** + * @} + */ + +/** @defgroup Oversampling Ratio + * @{ + */ +#define ADC_OVERSAMPLING_RATIO_2 (0U) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_4 (1U) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_8 (2U) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_16 (3U) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_32 (4U) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_64 (5U) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_128 (6U) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed */ +#define ADC_OVERSAMPLING_RATIO_256 (7U) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed */ +#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_4) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_8) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_16) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_32) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_64) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_128) || \ + ((RATIO) == ADC_OVERSAMPLING_RATIO_256)) +/** + * @} + */ + +/** @defgroup overflow mode + * @{ + */ +#define ADC_OVERFLOWMODE_LAST (0x00000000UL) /*!< ADC keeps the last sampling data when overflow occurs */ +#define ADC_OVERFLOWMODE_NEW (ADC_CR2_OVRMOD) /*!< ADC saves the new sampling data when overflow occurs */ +#define IS_ADC_OVERFLOW_MODE(MODE) (((MODE) == ADC_OVERFLOWMODE_LAST) || ((MODE) == ADC_OVERFLOWMODE_NEW)) +/** + * @} + */ + +/** @defgroup oversampling triger mode + * @{ + */ +#define ADC_OVERSAMPLING_TRIGER_MORE (0x00000000UL) /*!< One trigger for N ADC conversion */ +#define ADC_OVERSAMPLING_TRIGER_ONCE (ADC_CR2_TROVS) /*!< One trigger for ADC conversion */ +#define IS_ADC_OVERSAMPLING_TRIGER(MODE) (((MODE) == ADC_OVERSAMPLING_TRIGER_MORE) || ((MODE) == ADC_OVERSAMPLING_TRIGER_ONCE)) +/** + * @} + */ + +/** @defgroup ADC interrupts and flag definition + * @{ + */ +#define ADC_FLAG_ADRDY (ADC_SR_ADRDY) +#define ADC_IT_FLAG_EOSMP (ADC_SR_EOSMP) +#define ADC_IT_FLAG_EOC (ADC_SR_EOC) +#define ADC_IT_FLAG_EOG (ADC_SR_EOG) +#define ADC_IT_FLAG_OVERF (ADC_SR_OVERF) +#define ADC_IT_FLAG_JEOC (ADC_SR_JEOC) +#define ADC_IT_FLAG_JEOG (ADC_SR_JEOG) +#define ADC_IT_FLAG_AWD (ADC_SR_AWD) +#define ADC_IT_FLAG_ALL (0x000000FFUL) +#define IS_ADC_IT_FLAG(FLAG) (((FLAG) == ADC_IT_FLAG_EOSMP) || ((FLAG) == ADC_IT_FLAG_EOC) || \ + ((FLAG) == ADC_IT_FLAG_EOG)|| ((FLAG) == ADC_IT_FLAG_OVERF) || \ + ((FLAG) == ADC_IT_FLAG_JEOC)|| ((FLAG) == ADC_IT_FLAG_JEOG) || \ + ((FLAG) == ADC_IT_FLAG_AWD) || ((FLAG) <= ADC_IT_FLAG_ALL)) +#define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_IT_FLAG_EOSMP) || ((FLAG) == ADC_IT_FLAG_EOC) || \ + ((FLAG) == ADC_IT_FLAG_EOG)|| ((FLAG) == ADC_IT_FLAG_OVERF) || \ + ((FLAG) == ADC_IT_FLAG_JEOC)|| ((FLAG) == ADC_IT_FLAG_JEOG) || \ + ((FLAG) == ADC_IT_FLAG_AWD) || ((FLAG) <= ADC_IT_FLAG_ALL) || ((FLAG) == ADC_FLAG_ADRDY)) +/** + * @} + */ + +/** @defgroup Single-ended or differential +* @{ +*/ +#define ADC_DIFF_SINGLE (0U) /*!< ADC channel ending set to single ended */ +#define ADC_DIFF_DIFFERENTIAL (1U) /*!< ADC channel ending set to differential */ +#define IS_ADC_DIFF(MODE) (((MODE) == ADC_DIFF_SINGLE) || ((MODE) == ADC_DIFF_DIFFERENTIAL)) +/** + * @} + */ + + +/** @defgroup Signed or unsigned number selection +* @{ +*/ +#define ADC_SIGN_UNSIGNED (0U) /*!< The result is an unsigned number */ +#define ADC_SIGN_SIGNED (1U) /*!< The result is an signed number */ +#define IS_ADC_SIGN(MODE) (((MODE) == ADC_SIGN_SIGNED) || ((MODE) == ADC_SIGN_UNSIGNED)) +/** + * @} + */ + + +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); + +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); + +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); + +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); + +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); + +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); + +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc); + +uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc); + +HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected); + +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_InjectedStop(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc); + +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); + +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); + +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); + +FlagStatus HAL_ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); + +void HAL_ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); + +void HAL_ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); + +ITStatus HAL_ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +void HAL_ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); + +#endif + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_aes.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..2ec97569dc544a18d0cf047d3f3b078b4bb114e9 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_aes.h @@ -0,0 +1,90 @@ +/****************************************************************************** +*@file : hal_aes.h +*@brief : AES module driver header file. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __AES_H__ +#define __AES_H__ + +#include "hal.h" + +#define AES_ENCRYPTION 1 +#define AES_DECRYPTION 0 +#define AES_ECB_MODE 0 +#define AES_CBC_MODE 1 +#define AES_CTR_MODE 2 + +#define AES_SWAP_ENABLE 1 +#define AES_SWAP_DISABLE 0 + +#define AES_NORMAL_MODE 0x12345678 +#define AES_SECURITY_MODE 0 + +#define AES_ADDR_AUTO_ENABLE 1 +#define AES_ADDR_AUTO_DISABLE 0 + +#define AES_KEY_128 0 +#define AES_KEY_192 1 +#define AES_KEY_256 2 + +#define AES_FAIL 0x00 +#define AES_PASS 0xa59ada68 + +/****************************************************************************** +*@brief : set key for aes +*@param : keyin : pointer to buffer of key +*@param : key_len : select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) +*@param : swap_en : AES_SWAP_ENABLE, AES_SWAP_DISABLE +*@return: None +******************************************************************************/ +void HAL_AES_SetKey(uint32_t *keyin, uint8_t key_len, uint8_t swap_en); +void HAL_AES_SetKey_U8(uint8_t *keyin, uint8_t key_len, uint8_t swap_en); + +/****************************************************************************** +*@brief : function for aes encryption and decryption +*@param : indata : pointer to buffer of input data +*@param : outdata : pointer to buffer of output data +*@param : block_len : block(128bit) length for aes cryption +*@param : operation : AES_ENCRYPTION,AES_DECRYPTION +*@param : mode : AES_ECB_MODE, AES_CBC_MODE +*@param : iv : initial vector for CBC mode +*@param : security_mode : AES_NORMAL_MODE, AES_SECURITY_MDOE +*@return: None +******************************************************************************/ +uint32_t HAL_AES_Crypt( + uint32_t *indata, + uint32_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint32_t *iv, + uint32_t security_mode +); + + +uint32_t HAL_AES_Crypt_U8( + uint8_t *indata, + uint8_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint8_t *iv, + uint32_t security_mode +); + +void HAL_AES_Crypt_CTR( + uint32_t *indata, + uint32_t *outdata, + uint32_t *iv, + uint32_t block_len, +uint8_t auto_en +); + +void HAL_AES_SetKey_CTR(uint32_t *keyin, uint8_t key_len, uint32_t *iv, uint8_t swap_en); + +#endif +/****************************************************************************** + * end of file +*******************************************************************************/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_aes_spi1.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_aes_spi1.h new file mode 100644 index 0000000000000000000000000000000000000000..bc48a1de9b3510708a058107d7febbefc040b633 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_aes_spi1.h @@ -0,0 +1,139 @@ +/****************************************************************************** +*@file : hal_aes.h +*@brief : AES module driver header file. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __AES_SPI_H__ +#define __AES_SPI_H__ + +#include "hal.h" + +#define AES_SPI_ENCRYPTION 1 +#define AES_SPI_DECRYPTION 0 +#define AES_SPI_ECB_MODE 0 +#define AES_SPI_CBC_MODE 1 +#define AES_SPI_CTR_MODE 2 +#define AES_SPI_SWAP_ENABLE 1 +#define AES_SPI_SWAP_DISABLE 0 + +#define AES_SPI_NORMAL_MODE 0x12345678 +#define AES_SPI_SECURITY_MODE 0 + +#define AES_SPI_KEY_128 0 +#define AES_SPI_KEY_192 1 +#define AES_SPI_KEY_256 2 + +#define AES_SPI_FAIL 0x00 +#define AES_SPI_PASS 0xa59ada68 + +#define AES_SPI_ADDR_AUTO_ENABLE 1 +#define AES_SPI_ADDR_AUTO_DISABLE 0 + + + +#define SPI7_MEM_ADDR 0x08000000 + +#define SPI7_MEM_EXE_ADDR 0x08002000 + +//#define SPI_MEM_ADDR 0x63000000 +//#define SPIB_MEM_ADDR 0x08000000 +//#define SPIB_MEM_ADDR 0x04000000 + + +#define SPI8_MEM_ADDR 0x10000000 +#define SPI8_MEM_EXE_ADDR 0x10002000 + +#define OSPI2_MEM_ADDR 0x18000000 +#define OSPI2_MEM_EXE_ADDR 0x18002000 + +#define MEM_ADDR SPI7_MEM_ADDR +#define MEM_EXE_ADDR SPI7_MEM_EXE_ADDR + +//#define MEM_ADDR SPI8_MEM_ADDR +//#define MEM_EXE_ADDR SPI8_MEM_EXE_ADDR + + +//#define MEM_ADDR OSPI2_MEM_ADDR +//#define MEM_EXE_ADDR OSPI2_MEM_EXE_ADDR + + + + + +#define FIRST_SIZE 0x8000 //32K +#define SECOND_SIZE 0x20000 //128K + + + +/****************************************************************************** +*@brief : set key for aes +*@param : keyin : pointer to buffer of key +*@param : key_len : select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) +*@param : swap_en : AES_SWAP_ENABLE, AES_SWAP_DISABLE +*@return: None +******************************************************************************/ +void HAL_AES_SPI_SetKey(uint32_t *keyin, uint8_t key_len, uint8_t swap_en); +void HAL_AES_SPI_SetKey_U8(uint8_t *keyin, uint8_t key_len, uint8_t swap_en); +void HAL_AES_SPI_SetKey_CTR(uint32_t *keyin, uint8_t key_len, uint8_t swap_en); + +/****************************************************************************** +*@brief : function for aes encryption and decryption +*@param : indata : pointer to buffer of input data +*@param : outdata : pointer to buffer of output data +*@param : block_len : block(128bit) length for aes cryption +*@param : operation : AES_ENCRYPTION,AES_DECRYPTION +*@param : mode : AES_ECB_MODE, AES_CBC_MODE +*@param : iv : initial vector for CBC mode +*@param : security_mode : AES_NORMAL_MODE, AES_SECURITY_MDOE +*@return: None +******************************************************************************/ +uint32_t HAL_AES_SPI_Crypt( + uint32_t *indata, + uint32_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint32_t *iv, + uint32_t security_mode +); + + +uint32_t HAL_AES_SPI_Crypt_U8( + uint8_t *indata, + uint8_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint8_t *iv, + uint32_t security_mode +); + +void HAL_AES_SPI_Crypt_CTR( + uint32_t *indata, + uint32_t *outdata, + uint32_t *iv, + uint32_t block_len, + uint8_t auto_en +); + +void HAL_AES_Crypt_soft(uint32_t *datain, uint32_t *dataout, uint32_t *ivin, uint32_t length); + +//write only once after sysreset +void otfdec_uid_set_key(uint32_t *uid, uint32_t *random); +//write only once after sysreset +void otfdec_puf_set_key(uint32_t puf_offset,uint32_t *random); +//otfdec_en : 1: select PUF + RANDOM 3: UID+RANDOM +//write only once after sysreset +void otfdec_en(uint8_t otfdec_en, uint8_t spi_sel); +void otfdec_encrypt(uint32_t *datain, uint32_t start_addr, uint32_t length,uint32_t *dataout); +void otfdec_encrypt1(uint32_t *datain, uint32_t start_addr, uint32_t length,uint32_t *dataout); +void otfdec_uid_set_key2(uint32_t *key2, uint32_t *random); +void otfdec_uid_set_key3(uint32_t *key3); + + +#endif +/****************************************************************************** + * end of file +*******************************************************************************/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cde.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cde.h new file mode 100644 index 0000000000000000000000000000000000000000..fb05cb65d5d3b3151566217966db7a5309a8b41a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cde.h @@ -0,0 +1,430 @@ +/****************************************************************************** +*@file : hal_cde.h +*@brief : cde header file +*@ver : 1.0.0 +*@date : 2023.2.3 +******************************************************************************/ + + +#ifndef _HAL_CDE_H +#define _HAL_CDE_H + +#include "hal.h" + +void HAL_CDE_EnableCPx(int num); + +void HAL_CDE_DisableCPx(int num); + +#define ROTATE_LEFT(n,x) __ROR(x,32-n) +#define SM3_P0(x) x^ ROTATE_LEFT(9,x) ^ ROTATE_LEFT(17,x) +#define SM3_P1(x) x^ ROTATE_LEFT(15,x) ^ ROTATE_LEFT(23,x) +#define SM4_T1(x) x^ ROTATE_LEFT(2,x) ^ ROTATE_LEFT(10,x) ^ ROTATE_LEFT(18,x) ^ ROTATE_LEFT(24,x) +#define SM4_T2(x) x^ ROTATE_LEFT(13,x) ^ ROTATE_LEFT(23,x) + +#define SM3_FF2(x,y,z) (x&y)|(x&z)|(y&z) // Rounds 16-63 x,y,z is word length; +#define SM3_GG2(x,y,z) (x&y)|(~x&z) // Rounds 16-63 x,y,z is word length; + + +/* + Counting the number of ones in a 32 bit register. + The output of this instruction is a 32 bit register, containing + the number of ones + +refrence C-code: + +uint32_t POPCNT(uint32_t a) { + a = (a&0x55555555) + ((a&0xaaaaaaaa)>> 1); + a = (a&0x33333333) + ((a&0xcccccccc)>> 2); + a = (a&0x0f0f0f0f) + ((a&0xf0f0f0f0)>> 4); + a = (a&0x00ff00ff) + ((a&0xff00ff00)>> 8); + a = (a&0x0000ffff) + ((a&0xffff0000)>>16); + return a; +} +*/ +#define __HAL_CDE_POPCNT(a) __arm_cx1a(0, (a), 1) + + +/* + Reverse bit order of byte in a 32 bit register. + For example, 0x112233344 becomes 0x8844cc22 + +refrence C-code: + +UINT8 reverse_byte(UINT8 in_data) +{ + UINT8 temp; + UINT8 i; + + temp = 0; + for(i = 0; i < 8; i++) + { + if(in_data & (1 << i)) + { + temp |= 0x80 >> i; + } + } + + return temp; +} +*/ +#define __HAL_CDE_BYTE_REVERSE(a) __arm_cx1a(0, (a), 2) + +/* + SM3_P0 + +refrence C-code: + +#define SM3_P0(x) x^ ROTATE_LEFT(9,x) ^ ROTATE_LEFT(17,x) +*/ +#define __HAL_CDE_SM3_P0(a) __arm_cx1a(0, (a), 3) + +/* + SM3_P1 + +refrence C-code: + +#define SM3_P1(x) x^ ROTATE_LEFT(15,x) ^ ROTATE_LEFT(23,x) +*/ +#define __HAL_CDE_SM3_P1(a) __arm_cx1a(0, (a), 4) + +/* + SM4_T1 + +refrence C-code: + +#define SM4_T1(x) x^ ROTATE_LEFT(2,x) ^ ROTATE_LEFT(10,x) ^ ROTATE_LEFT(18,x) ^ ROTATE_LEFT(24,x) +*/ +#define __HAL_CDE_SM4_T1(a) __arm_cx1a(0, (a), 5) + + +/* + SM4_T2 + +refrence C-code: + +#define SM4_T2(x) x^ ROTATE_LEFT(13,x) ^ ROTATE_LEFT(23,x) +*/ +#define __HAL_CDE_SM4_T2(a) __arm_cx1a(0, (a), 6) + +/* + CRC32 instruction for updating a 32 bit state register by 8 bit input + data using the ISO 3309 standard. + Polynomial representation (reversed) : 0xEDB88320 + +refrence C-code: + +#define POLYNOMIAL 0xedb88320 +uint32_t CRC32(uint32_t crc, uint32_t d) { + crc = crc ^ (d&0xff); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + if (crc&1) crc = (crc>>1) ^ POLYNOMIAL; else crc = (crc>>1); + return crc; +} +*/ + +/* + SM3_FF2 + +refrence C-code: + +#define SM3_FF2(x,y,z) (x&y)|(x&z)|(y&z) // Rounds 16-63 x,y,z is word length; +*/ +#define __HAL_CDE_SM3_FF2(x, y, z) __arm_cx3a(0,x, y, z,1) + +/* + SM3_GG2 + +refrence C-code: + +#define SM3_GG2(x,y,z) (x&y)|(~x&z) // Rounds 16-63 x,y,z is word length; +*/ +#define __HAL_CDE_SM3_GG2(x, y, z) __arm_cx3a(0,x, y, z,10) + + + +#define __HAL_CDE_CRC32_REVERSE(crc, d) __arm_cx2a(0, (crc), (d), 2) //cpuڲԳʼֵԼз + +/* +CRC module for data[31:0] , crc32[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32; +ʽ0x04C11DB7 +֧һμһ +*/ +#define __HAL_CDE_CRC32_32BIT(crc, d) __arm_cx2a(0, (crc), (d), 1) //ڲd ڵ򣬼d[31:0] תΪ {d[7:0],d[15:8],d[23:16],d[31:24]} + + + +/* This instruction extracts 32 bits from two 32 bit registers. + res[ 0:23] = a[8:31] + res[24:31] = b[0:7] + +refrence C-code: + +uint32_t PACK8(uint32_t a, uint32_t b) { + return (a >> 8) | (b << 24); +} +*/ +#define __HAL_CDE_PACK8(a, b) __arm_cx3(0,(a),(b), 4) + + +/* This instruction extracts 32 bits from two 32 bit registers. + res[ 0:15] = a[16:31] + res[16:31] = b[0:15] + +refrence C-code: + +uint32_t PACK16(uint32_t a, uint32_t b) { + return (a >> 16) | (b << 16); +} +*/ +#define __HAL_CDE_PACK16(a, b) __arm_cx3(0,(a),(b), 5) + +/* Instruction for updating the FIR filter delay line by two 8 bit operands + This instruction extracts 32 bits from two 32 bit registers. + res[ 0:7] = a[24:31] + res[8:31] = b[0:23] + +refrence C-code: + +uint32_t PACK24(uint32_t a, uint32_t b) { + return (a >> 24) | (b << 8); +} +*/ +#define __HAL_CDE_PACK24(a, b) __arm_cx3(0,(a),(b), 6) + + +/* This instruction does four 8x8 bit unsigned multiplicaltions forming + four 16 bit products. + The four products and the accumulator 'a' are added, and the 32 bit + result is returned from the instruction. + +refrence C-code: + +uint32_t UMLAQ(uint32_t a, uint32_t b, uint32_t c) { + uint16_t a0, a1, a2, a3; + a0 = (uint16_t)((b >> 0) & 0xff) * (uint16_t)((c >> 0) & 0xff); + a1 = (uint16_t)((b >> 8) & 0xff) * (uint16_t)((c >> 8) & 0xff); + a2 = (uint16_t)((b >> 16) & 0xff) * (uint16_t)((c >> 16) & 0xff); + a3 = (uint16_t)((b >> 24) & 0xff) * (uint16_t)((c >> 24) & 0xff); + return a + (uint32_t)a0 + (uint32_t)a1 + (uint32_t)a2 + (uint32_t)a3; +} +*/ +#define __HAL_CDE_UMLAQ(a, b, c) __arm_cx3a(0,(a),(b),(c), 2) + + +/* This instruction does four 8x8 bit unsigned multiplicaltions forming + four 16 bit products. + The four products are added, and the 32 bit result is returned from + the instruction. + +uint32_t UMUAQ(uint32_t b, uint32_t c) { + uint16_t a0, a1, a2, a3; + a0 = (uint16_t)((b >> 0) & 0xff) * (uint16_t)((c >> 0) & 0xff); + a1 = (uint16_t)((b >> 8) & 0xff) * (uint16_t)((c >> 8) & 0xff); + a2 = (uint16_t)((b >> 16) & 0xff) * (uint16_t)((c >> 16) & 0xff); + a3 = (uint16_t)((b >> 24) & 0xff) * (uint16_t)((c >> 24) & 0xff); + return (uint32_t)a0 + (uint32_t)a1 + (uint32_t)a2 + (uint32_t)a3; +} +*/ +#define __HAL_CDE_UMUAQ(b, c) __arm_cx3(0,(b),(c), 7) + + +/* This instruction does four 8 bit signed by 8 bit unsigned multi- + plications forming four 16 bit products. + The four products and the accumulator 'a' are added, and the 32 bit + result is returned from the instruction. + +int32_t SUMLAQ(int32_t a, uint32_t b, uint32_t c) { + int16_t a0, a1, a2, a3; + a0 = (int16_t)(int8_t)((b >> 0) & 0xff) * (int16_t)(uint8_t)((c >> 0) & 0xff); + a1 = (int16_t)(int8_t)((b >> 8) & 0xff) * (int16_t)(uint8_t)((c >> 8) & 0xff); + a2 = (int16_t)(int8_t)((b >> 16) & 0xff) * (int16_t)(uint8_t)((c >> 16) & 0xff); + a3 = (int16_t)(int8_t)((b >> 24) & 0xff) * (int16_t)(uint8_t)((c >> 24) & 0xff); + return a + (int32_t)a0 + (int32_t)a1 + (int32_t)a2 + (int32_t)a3; +} +*/ +#define __HAL_CDE_SUMLAQ(a, b, c) __arm_cx3a(0,(a),(b),(c), 3) + + +/* This instruction does four 8 bit signed by 8 bit unsigned multi- + plications forming four 16 bit products. + The four products are added, and the 32 bit result is returned from + the instruction. + +int32_t SUMUAQ(uint32_t b, uint32_t c) { + int16_t a0, a1, a2, a3; + a0 = (int16_t)(int8_t)((b >> 0) & 0xff) * (int16_t)(uint8_t)((c >> 0) & 0xff); + a1 = (int16_t)(int8_t)((b >> 8) & 0xff) * (int16_t)(uint8_t)((c >> 8) & 0xff); + a2 = (int16_t)(int8_t)((b >> 16) & 0xff) * (int16_t)(uint8_t)((c >> 16) & 0xff); + a3 = (int16_t)(int8_t)((b >> 24) & 0xff) * (int16_t)(uint8_t)((c >> 24) & 0xff); + return (int32_t)a0 + (int32_t)a1 + (int32_t)a2 + (int32_t)a3; +} +*/ +#define __HAL_CDE_SUMUAQ(b, c) __arm_cx3(0,(b),(c), 8) + + +/* + This function calculates the hamming distance between two input registers + + Input registers takes any value, valid output values [0:31] + Do not use {A} CDE type, proposed CDE instruction: cx3(p0, a, b, c, #) + +uint32_t HAMMING_DIST(uint32_t b, uint32_t c) { + uint32_t i, a, val; + + val = b ^ c; + a = 0; + for (i = 0; i < 32; i++) { + a = a + (val & 1); + val = val >> 1; + } + + return a; +} +*/ +#define __HAL_CDE_HAMMING_DIST(b, c) __arm_cx3(0,b,c, 9) + +/* + parity of the number of ones in a 32 bit register. + For example, 0x11 : 0 + 0x23 : 1 + 0xffff: 0 +refrence C-code: +__builtin_parity +*/ +#define __HAL_CDE_PARITY(a) __arm_cx1a(0, (a), 7) + +/* + Reverse bit order of u16 in a 32 bit register. + For example, 0x11223344 becomes 0x448822cc + +refrence C-code: + +UINT8 reverse_u16(UINT16 in_data) +{ + UINT8 temp; + UINT8 i; + + temp = 0; + for(i = 0; i < 16; i++) + { + if(in_data & (1 << i)) + { + temp |= 0x8000 >> i; + } + } + + return temp; +} +*/ +#define __HAL_CDE_U16_REVERSE(a) __arm_cx1a(0, (a), 8) + +/* + Counts the number of tailing zeros of a data value. + For example, 0x00 : 32 + 0x11 : 0 + 0x1122 : 1 + 0x80000000: 31 +refrence C-code: +__builtin_ctz + +*/ +#define __HAL_CDE_CTZ(a) __arm_cx2a(0, a, 0, 3) + +/* + from back to front, which position of bit 1 in a data value. + For example, 0x00 : 32 + 0x11 : 1 + 0x1122 : 2 + 0x80000000: 32 +refrence C-code: +__builtin_ffs + +*/ +#define __HAL_CDE_FFS(a) __arm_cx2a(0, a, 1, 3) + + +/* + byte amplification + For example, bit[7:0] a = 01101011 + b=1 : bit[15:0] 00 11 11 00 11 00 11 11 + b=2 : bit[31:0] 00000000 000 111 111 000 111 000 111 111 + b=4 : bit[31:0] 0000 1111 1111 0000 1111 0000 1111 1111 +refrence C-code: + + +*/ +#define __HAL_CDE_BYTE_AMP(a,b) __arm_cx2a(0, a, b, 4) + +/* This instruction extracts 8 bits from two 8 bit registers. + +refrence C-code: +uint8_t BYTE_PACKN(uint8_t a, uint8_t b, uint8_t n) { + return (a >> n) | (b << (8-n)); +} +uint32_t WORD_PACKN(uint32_t a, uint32_t b, uint8_t n) { + uint32_t c,c1,c2,c3,c4; + c1 = ((a&0xff) >> n) | ((b&0xff) << (8-n)); + c2 = ((a&0xff00) >> n) | ((b&0xff00) << (8-n)); + c3 = ((a&0xff0000) >> n) | ((b&0xff0000) << (8-n)); + c4 = ((a&0xff000000) >> n) | ((b&0xff000000) << (8-n)); + c = (c1&0xff) | (c2&0xff00) | (c3&0xff0000) | (c4&0xff000000); + return c; +} +*/ +#define __HAL_CDE_BYTE_PACKN(a, b,n) __arm_cx3a(0,(a),(b), n,11) + +/* This instruction extracts 8 bits from two 8 bit registers. + +refrence C-code: +uint32_t BYTE3_PACKN(uint32_t a, uint8_t n) { + uint8_t c,c1,c2,c3; + uint8_t a1,a2,a3,a4; + a1 = (a&0xff); + a2 = (a&0xff00)>>8; + a3 = (a&0xff0000)>>16; + a4 = (a&0xff000000)>>24; + c1 = (a1 >> n) | (a2 << (8-n)); + c2 = (a2 >> n) | (a3 << (8-n)); + c3 = (a3 >> n) | (a4 << (8-n)); + c = (c1&0xff) | ((c2<<8)&0xff00) | ((c3<<16)&0xff0000); + return c; +} +*/ +#define __HAL_CDE_3BYTE_PACKN(a,n) __arm_cx2a(0,(a),n,5) + +/* This instruction extracts 8 bits from two 8 bit registers. + +refrence C-code: +uint64_t BYTE7_PACKN(uint64_t a, uint8_t n) { + uint64_t c,c1,c2,c3,c4,c5,c6,c7; + uint8_t a1,a2,a3,a4,a5,a6,a7,a8; + a1 = (a&0xff); + a2 = (a&0xff00)>>8; + a3 = (a&0xff0000)>>16; + a4 = (a&0xff000000)>>24; + a5 = (a&0xff00000000)>>32; + a6 = (a&0xff0000000000)>>40; + a7 = (a&0xff000000000000)>>48; + a8 = (a&0xff00000000000000)>>56; + c1 = (a1 >> n) | (a2 << (8-n)); + c2 = (a2 >> n) | (a3 << (8-n)); + c3 = (a3 >> n) | (a4 << (8-n)); + c4 = (a4 >> n) | (a5 << (8-n)); + c5 = (a5 >> n) | (a6 << (8-n)); + c6 = (a6 >> n) | (a7 << (8-n)); + c7 = (a7 >> n) | (a8 << (8-n)); + c = (c1&0xff) | ((c2<<8)&0xff00) | ((c3<<16)&0xff0000) | ((c4<<24)&0xff000000) | ((c5<<32)&0xff00000000) | ((c6<<40)&0xff000000000) | ((c7<<48)&0xff000000000000); + return c; +} +*/ +#define __HAL_CDE_7BYTE_PACKN(a,n) __arm_cx2da(0,(a),n,6) + +#endif + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_comp.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_comp.h new file mode 100644 index 0000000000000000000000000000000000000000..b213f648b6ca60b12fb886b1ec0633d2aa83b70c --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_comp.h @@ -0,0 +1,163 @@ + +/****************************************************************************** +*@file : hal_comp.h +*@brief : COMP HAL module driver header file. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __HAL_COMP_H__ +#define __HAL_COMP_H__ + +#include "acm32h5xx_hal_conf.h" + + +typedef struct +{ + uint32_t InPSel; //input plus select + uint32_t InMSel; //input minus select + uint32_t Polarity; //polarity + uint32_t HYS; //Hysteresis window + uint32_t BlankSel; //blank source select + uint32_t FltEn; //filt enable + uint32_t FltTime; //filt time + uint32_t CrvEn; //reference voltage divide enable + uint32_t CrvSel; //reference voltage source select + uint32_t CrvCfg; //reference voltage divider factor config +}COMP_InitTypeDef; + + +typedef struct +{ + COMP_TypeDef *Instance; // Register base address + COMP_InitTypeDef Init; // COMP required parameters + uint8_t OutputLevelOrg; // COMP OutputLevel original + uint8_t OutputLevel; // COMP OutputLevel with filter +} COMP_HandleTypeDef; + + +#define COMP_CRVSEL_AVDD (0U) +#define COMP_CRVSEL_VREF (COMP_CR_CRV_SEL) + +#define COMP_CRV_DISABLE (0U) +#define COMP_CRV_ENABLE (COMP_CR_CRV_EN) + +#define COMP_POLARITY_NOINVERT (0U) +#define COMP_POLARITY_INVERT (COMP_CR_POLARITY) + +#define COMP_FLT_DISABLE (0U) +#define COMP_FLT_ENABLE (COMP_CR_FLTEN) + +#define COMP_FLTTIME_1CLK (0U) +#define COMP_FLTTIME_2CLK (1U << COMP_CR_FLTTIME_Pos) +#define COMP_FLTTIME_4CLK (2U << COMP_CR_FLTTIME_Pos) +#define COMP_FLTTIME_16CLK (3U << COMP_CR_FLTTIME_Pos) +#define COMP_FLTTIME_64CLK (4U << COMP_CR_FLTTIME_Pos) +#define COMP_FLTTIME_256CLK (5U << COMP_CR_FLTTIME_Pos) +#define COMP_FLTTIME_1024CLK (6U << COMP_CR_FLTTIME_Pos) +#define COMP_FLTTIME_4095CLK (7U << COMP_CR_FLTTIME_Pos) + +#define COMP_BLANKSEL_NONE (0U) +#define COMP_BLANKSEL_S1 (1U << COMP_CR_BLANKSEL_Pos) +#define COMP_BLANKSEL_S2 (2U << COMP_CR_BLANKSEL_Pos) +#define COMP_BLANKSEL_S3 (3U << COMP_CR_BLANKSEL_Pos) +#define COMP_BLANKSEL_S4 (4U << COMP_CR_BLANKSEL_Pos) +#define COMP_BLANKSEL_S5 (5U << COMP_CR_BLANKSEL_Pos) +#define COMP_BLANKSEL_S6 (6U << COMP_CR_BLANKSEL_Pos) +#define COMP_BLANKSEL_S7 (7U << COMP_CR_BLANKSEL_Pos) + +#define COMP1_BLANKSEL_NONE (0U) +#define COMP1_BLANKSEL_TIM1_OC5 (1U << COMP_CR_BLANKSEL_Pos) +#define COMP1_BLANKSEL_TIM1_OC3 (2U << COMP_CR_BLANKSEL_Pos) +#define COMP1_BLANKSEL_TIM3_OC3 (3U << COMP_CR_BLANKSEL_Pos) +#define COMP1_BLANKSEL_TIM3_OC4 (4U << COMP_CR_BLANKSEL_Pos) +#define COMP1_BLANKSEL_TIM8_OC5 (5U << COMP_CR_BLANKSEL_Pos) +#define COMP1_BLANKSEL_TIM15_OC1 (6U << COMP_CR_BLANKSEL_Pos) +#define COMP1_BLANKSEL_ALL (7U << COMP_CR_BLANKSEL_Pos) + +#define COMP_INPSEL_P0 (0U) +#define COMP_INPSEL_P1 (1U << COMP_CR_INPSEL_Pos) + +#define COMP_INMSEL_DACx (0U) +#define COMP_INMSEL_P1 (1U << COMP_CR_INMSEL_Pos) +#define COMP_INMSEL_P2 (2U << COMP_CR_INMSEL_Pos) +#define COMP_INMSEL_VREF_AVDD (3U << COMP_CR_INMSEL_Pos) + +#define COMP1_INPSEL_PB0 (0U) +#define COMP1_INPSEL_PB2 (1U << COMP_CR_INPSEL_Pos) + +#define COMP1_INMSEL_DAC1 (0U) +#define COMP1_INMSEL_PB1 (1U << COMP_CR_INMSEL_Pos) +#define COMP1_INMSEL_PC4 (2U << COMP_CR_INMSEL_Pos) +#define COMP1_INMSEL_VREF_AVDD (3U << COMP_CR_INMSEL_Pos) + +#define COMP_HYS_NONE (0U) +#define COMP_HYS_4 (4U << COMP_CR_HYS_Pos) +#define COMP_HYS_5 (5U << COMP_CR_HYS_Pos) +#define COMP_HYS_6 (6U << COMP_CR_HYS_Pos) +#define COMP_HYS_7 (7U << COMP_CR_HYS_Pos) + + +#define IS_COMP_INSTANCE(_INSTANCE_) ((_INSTANCE_) == COMP1) + + +#define IS_COMP_CRVCFG(_CRVCFG_) ((_CRVCFG_) <= 15U) + +#define IS_COMP_CRVSEL(_CRVSEL_) (((_CRVSEL_) == COMP_CRVSEL_AVDD) || \ + ((_CRVSEL_) == COMP_CRVSEL_VREF)) + +#define IS_COMP_CRVEN(_CRVEN_) (((_CRVEN_) == COMP_CRV_DISABLE) || \ + ((_CRVEN_) == COMP_CRV_ENABLE)) + +#define IS_COMP_POLARITY(_POLARITY_) (((_POLARITY_) == COMP_POLARITY_NOINVERT) || \ + ((_POLARITY_) == COMP_POLARITY_INVERT)) + +#define IS_COMP_FLTEN(_FLTEN_) (((_FLTEN_) == COMP_FLT_DISABLE) || \ + ((_FLTEN_) == COMP_FLT_ENABLE)) + +#define IS_COMP_FLTTIME(_FLTTIME_) (((_FLTTIME_) == COMP_FLTTIME_1CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_2CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_4CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_16CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_64CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_256CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_1024CLK) || \ + ((_FLTTIME_) == COMP_FLTTIME_4095CLK)) + +#define IS_COMP_BLANKSEL(_BLANKSEL_) (((_BLANKSEL_) == COMP_BLANKSEL_NONE) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S1) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S2) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S3) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S4) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S5) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S6) || \ + ((_BLANKSEL_) == COMP_BLANKSEL_S7)) + +#define IS_COMP_INPSEL(_INPSEL_) (((_INPSEL_) == COMP_INPSEL_P0) || \ + ((_INPSEL_) == COMP_INPSEL_P1)) + +#define IS_COMP_INMSEL(_INMSEL_) (((_INMSEL_) == COMP_INMSEL_DACx) || \ + ((_INMSEL_) == COMP_INMSEL_P1) || \ + ((_INMSEL_) == COMP_INMSEL_P2) || \ + ((_INMSEL_) == COMP_INMSEL_VREF_AVDD)) + +#define IS_COMP_HYS(_HYS_) (((_HYS_) == COMP_HYS_NONE) || \ + ((_HYS_) == COMP_HYS_4) || \ + ((_HYS_) == COMP_HYS_5) || \ + ((_HYS_) == COMP_HYS_6) || \ + ((_HYS_) == COMP_HYS_7)) + + +void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp); +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp); + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cordic.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cordic.h new file mode 100644 index 0000000000000000000000000000000000000000..cea216d9654267ba37b1c3905e80b0bb21a63086 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cordic.h @@ -0,0 +1,626 @@ +/****************************************************************************** +*@file : hal_fau.h +*@brief : Header file of FAU module. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __CORDIC_H_ +#define __CORDIC_H_ + +#define RANGE 2147483648U //2^31 +#define CORDIC_F_31 0xD2C90A46 // CORDIC gain F +#define W_INV_Q31 0x6A012206 + +#define PI 3.1415926 + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 1) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_1(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 2) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_2(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 3) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_3(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 4) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_4(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 5) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_5(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 6) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_6(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 7) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_7(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the sin & cos value of the input angle(precision 8) +* +*@param : angle_para: input angle data in radians, divided by ,range[-1,1],Q31 format +*@param : cos_data : the cos value of the input angle,range[-1,1],Q31 format +*@param : sin_data : the sin value of the input angle,range[-1,1],Q31 format +*@return: None +******************************************************************************/ +void HAL_CORDIC_CosSin_8(int angle_para, int* cos_data, int* sin_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 1) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_1(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 2) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_2(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 3) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_3(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 4) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_4(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 5) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_5(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 6) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_6(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 7) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_7(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the atan & sqrt value of the input x,y(precision 8) +* +*@param : x : input x, range[-1,1],Q31 format +*@param : y : input y, range[-1,1],Q31 format +*@param : sqrt_data : the sqrt value of the input x,y,Q31 format +* sqrt_data should devide (CORDIC_F_31>>4) to obtain the value in float +*@param : atan_data : the atan value of the input y/x,Q31 format +* atan_value must be multiplied by to obtain the angle in radians +*@return: None +******************************************************************************/ +void HAL_CORDIC_AtanSqrt_8(int x, int y, int*sqrt_data, int* atan_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 1) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_1(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 2) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_2(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 3) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_3(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 4) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_4(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 5) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_5(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 6) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_6(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 7) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_7(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the sinh & cosh value of the input angle(precision 8) +* +*@param : angle_para : input hyperbolic angle data in radians, range [-0.559 ~0. 559]([-1.118 ~ 1.118]/2),Q31 format +*@param : cosh_data : the hyperbolic cosh value of the input angle,,range[0.5 0.846],Q31 format +* cosh_data must be multiplied by 2 to obtain the correct result +*@param : sinh_data : the hyperbolic sinh value of the input angle,range[[-0.683 0.683],Q31 format +* sinh_data must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_CoshSinh_8(int angle_para, int* cosh_data, int* sinh_data); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 1) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_1(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 27) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_2(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 3) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_3(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 4) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_4(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 5) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_5(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 6) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_6(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 7) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_7(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the hyperbolic arctangent of the input argument(precision 8) +* +*@param : angle_para : input hyperbolic angle data,range [-0.403 0.403]([-0.806 ~ 0.806]/2),Q31 format; +*@param : atanh_value: the atanh value of the input argument,Q31 format + atanh_value must be multiplied by 2 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Atanh_8(int angle_para, int *atanh_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 1) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_1(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 2) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_2(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 3) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_3(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 4) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_4(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 5) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_5(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 6) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_6(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 7) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_7(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the natural logarithm of the input argument(precision 8) +* +*@param : arg : input argument,range [0.054 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.107 x < 1 1 0.0535 ARG1 < 0.5 +* 1 x < 3 2 0.25 ARG1 < 0.75 +* 3 x < 7 3 0.375 ARG1 < 0.875 +* 7 x 9.35 4 0.4375 ARG1 < 0.584 +*@param : ln_value: the natural logarithm value of the input argument,Q31 format +* ln_value must be multiplied by 4 to obtain the correct result. +*@return: None +******************************************************************************/ +void HAL_CORDIC_Ln_8(int arg, int scale, int *ln_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 1) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_1(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 2) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_2(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 3) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_3(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 4) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_4(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 5) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_5(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 6) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_6(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 7) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_7(int arg, int scale, int *sqrt_value); + +/****************************************************************************** +*@brief : calculate the square root value of the input argument(precision 8) +* +*@param : arg : input argument,range [0.027 0.875],Q31 format; +*@param : scale : scaling factor +* ORIGIN RANGE SCALE ARG RANGE +* 0.027 x < 0.75 0 0.027 ARG1 < 0.75 +* 0.75 x < 1.75 1 0.375 ARG1 < 0.875 +* 1.75 x 2.341 2 0.4375 ARG1 0.585 +*@param : sqrt_value: the squart root value of the input argument,Q31 format +* sqrt_value must be multiplied by 2^scale/W_INV_Q31 to obtain the correct result +*@return: None +******************************************************************************/ +void HAL_CORDIC_Sqrt_8(int arg, int scale, int *sqrt_value); + + +#endif \ No newline at end of file diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cortex.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cortex.h new file mode 100644 index 0000000000000000000000000000000000000000..bf9bff098b0be29ab446ec1eca58d044a8f84e27 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_cortex.h @@ -0,0 +1,255 @@ +/****************************************************************************** +*@file : hal_cortex.h +*@brief : Header file of CORTEX HAL module. +******************************************************************************/ + +#ifndef __HAL_CORTEX_H +#define __HAL_CORTEX_H + +#include "hal_def.h" + +#if (__MPU_PRESENT == 1U) +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ + uint8_t AttributesIndex; /*!< Specifies the memory attributes index. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ +} MPU_Region_InitTypeDef; + +typedef struct +{ + uint8_t Number; /*!< Specifies the number of the memory attributes to configure. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + + uint8_t Attributes; /*!< Specifies the memory attributes vue. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + +} MPU_Attributes_InitTypeDef; + +#endif /* __MPU_PRESENT */ + + +/** CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority, 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority, 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority, 0 bits for subpriority */ + +/** CORTEX_SysTick_clock_source CORTEX _SysTick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + + +/** CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control */ +#if (__MPU_PRESENT == 1) +#define MPU_HFNMI_PRIVDEF_NONE 0U +#define MPU_HARDFAULT_NMI 2U +#define MPU_PRIVILEGED_DEFAULT 4U +#define MPU_HFNMI_PRIVDEF 6U + +/** CORTEX_MPU_Region_Enable CORTEX MPU Region Enable */ +#define MPU_REGION_ENABLE 1U +#define MPU_REGION_DISABLE 0U + +/** CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U + +/** CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable */ +#define MPU_ACCESS_NOT_SHAREABLE 0U +#define MPU_ACCESS_OUTER_SHAREABLE 1U +#define MPU_ACCESS_INNER_SHAREABLE 3U + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes */ +#define MPU_REGION_PRIV_RW 0U +#define MPU_REGION_ALL_RW 1U +#define MPU_REGION_PRIV_RO 2U +#define MPU_REGION_ALL_RO 3U + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number */ +#define MPU_REGION_NUMBER0 0U +#define MPU_REGION_NUMBER1 1U +#define MPU_REGION_NUMBER2 2U +#define MPU_REGION_NUMBER3 3U +#define MPU_REGION_NUMBER4 4U +#define MPU_REGION_NUMBER5 5U +#define MPU_REGION_NUMBER6 6U +#define MPU_REGION_NUMBER7 7U + +/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number */ +#define MPU_ATTRIBUTES_NUMBER0 0U +#define MPU_ATTRIBUTES_NUMBER1 1U +#define MPU_ATTRIBUTES_NUMBER2 2U +#define MPU_ATTRIBUTES_NUMBER3 3U +#define MPU_ATTRIBUTES_NUMBER4 4U +#define MPU_ATTRIBUTES_NUMBER5 5U +#define MPU_ATTRIBUTES_NUMBER6 6U +#define MPU_ATTRIBUTES_NUMBER7 7U + +/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ +#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ + +#define OUTER(__ATTR__) ((__ATTR__) << 4U) +#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) + + +//@defgroup MPU_HFNMI_xxxx +//@{ +#define MPU_HFNMI_DISABLE (0) // MPU is disabled during HardFault and NMI handlers +#define MPU_HFNMI_ENABLE (1) // The MPU is enabled during HardFault and NMI handlers +//@} + +//@defgroup MPU_PRIVDEF_xxxx +//@{ +#define MPU_PRIVDEF_DISABLE (0) // Disables use of the default memory map +#define MPU_PRIVDEF_ENABLE (1) // Enables use of the default memory map as a background region for privileged software accesses +//@} + +//@defgroup MPU_ACCESS_xxxx +//@{ +#define MPU_ACCESS_PRIV_READ_WRITE (0) // Read/write by privileged code only +#define MPU_ACCESS_ALL_READ_WRITE (1) // Read/write by any privilege level +#define MPU_ACCESS_PRIV_READ_ONLY (2) // Read-only by privileged code only +#define MPU_ACCESS_ALL_READ_ONLY (3) // Read-only by any privilege level +//@} + +//@defgroup MPU_EXECUTE_xxxx +//@{ +#define MPU_EXECUTE_ENABLE (0) // Enables execution +#define MPU_EXECUTE_DISABLE (1) // Disables execution +//@} + +//@defgroup MPU_ATTR_xxxx +//@{ +#define MPU_ATTR_NO_CACHE (0x44) //normal memory,non-cacheable +#define MPU_ATTR_WRITE_THROUGH (0xAA) //normal memory,write-through,read-allocation +#define MPU_ATTR_WRITE_BACK (0xFF) //normal memory,write-back,read-allocation,write-allocation +#define MPU_ATTR_DEVICE (0x00) //device memory?nGnRnE +//@} + +typedef struct +{ + uint32_t BaseAddr; // the lower inclusive limit of the selected MPU memory region,lower 5 bits fixed to 0b'00000 + uint32_t LimitAddr; // the upper inclusive limit of the selected MPU memory region,lower 5 bits fixed to 0b'11111 + uint8_t Access; // read/write access permissions. @ref MPU_ACCESS_xxxx + uint8_t Execute; // execute permissions. @ref MPU_EXECUTE_xxxx + uint8_t Attr; // attributes, @ref MPU_ATTR_xxxx +}MPU_RegionConfigTypeDef; + +typedef struct +{ + uint8_t HfNmi; // @ref MPU_HFNMI_xxxx + uint8_t PrivDef; // @ref MPU_PRIVDEF_xxxx + uint8_t RegionCount; // region count. + MPU_RegionConfigTypeDef *RegionConfigs; //region configs. +}MPU_ConfigInitTypeDef; + +#endif /* __MPU_PRESENT */ + + +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +HAL_StatusTypeDef HAL_SYSTICK_Config(uint32_t TicksNum); + +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); + +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); +void HAL_MPU_Config(MPU_ConfigInitTypeDef *MPU_configInit); +#endif /* __MPU_PRESENT */ + + +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1U) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_ALL_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_ALL_RO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) +#endif /* __MPU_PRESENT */ + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_crc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..244505bd2f8e56ee2a8e2cc39a99934dcc8c3d90 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_crc.h @@ -0,0 +1,159 @@ + +/****************************************************************************** +*@file : hal_crc.h +*@brief : Header file for CRC module. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __HAL_CRC_H__ +#define __HAL_CRC_H__ + +#include "hal.h" + +/** @defgroup CRC POLY Reverse + * @{ + */ + #define CRC_POLY_REV_EN (0x00000400U) /*!< Poly Reverse Enable */ + #define CRC_POLY_REV_DIS (0x00000000U) /*!< Poly Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC OUTXOR Reverse + * @{ + */ + #define CRC_OUTXOR_REV_EN (0x00000200U) /*!< OUTXOR Reverse Enable */ + #define CRC_OUTXOR_REV_DIS (0x00000000U) /*!< OUTXOR Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC INIT Reverse + * @{ + */ + #define CRC_INIT_REV_EN (0x00000100U) /*!< INIT Reverse Enable */ + #define CRC_INIT_REV_DIS (0x00000000U) /*!< INIT Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC RSLT Reverse + * @{ + */ + #define CRC_RSLT_REV_EN (0x00000080U) /*!< RSLT Reverse Enable */ + #define CRC_RSLT_REV_DIS (0x00000000U) /*!< RSLT Reverse Disable */ +/** + * @} + */ + +/** @defgroup CRC DATA Reverse + * @{ + */ + #define CRC_DATA_REV_DISABLE (0x00000000U) /*!< DATA Reverse Disable */ + #define CRC_DATA_REV_BY_BYTE (0x00000020U) /*!< DATA Reverse By Byte */ + #define CRC_DATA_REV_BY_HALFWORD (0x00000040U) /*!< DATA Reverse By HalfWord */ + #define CRC_DATA_REV_BY_WORD (0x00000060U) /*!< DATA Reverse By Word */ +/** + * @} + */ + +/** @defgroup CRC Poly Len + * @{ + */ + #define CRC_POLTY_LEN_32 (0x00000000U) /*!< POLY len = 32bit */ + #define CRC_POLTY_LEN_16 (0x00000008U) /*!< POLY len = 16bit */ + #define CRC_POLTY_LEN_8 (0x00000010U) /*!< POLY len = 8bit */ + #define CRC_POLTY_LEN_7 (0x00000018U) /*!< POLY len = 7bit */ +/** + * @} + */ + +/** @defgroup CRC Data Len + * @{ + */ + #define CRC_DATA_LEN_1B (0x00000000U) /*!< DATA len = 1 Byte */ + #define CRC_DATA_LEN_2B (0x00000002U) /*!< DATA len = 2 Byte */ + #define CRC_DATA_LEN_3B (0x00000004U) /*!< DATA len = 3 Byte */ + #define CRC_DATA_LEN_4B (0x00000006U) /*!< DATA len = 4 Byte */ +/** + * @} + */ + +/** @defgroup CRC RST + * @{ + */ + #define CRC_RST_EN (0x00000001U) /*!< RST CRC_DATA To CRC_INIT */ + #define CRC_RST_DIS (0x00000000U) /*!< RST CRC_DATA To CRC_INIT */ + +/** + * @} + */ + +/* + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint32_t PolyRev; /*!< Specifies if the Poly is reversed in CRC + This parameter can be a value of @ref CRC POLY Reverse. */ + uint32_t OutxorRev; /*!< Specifies if the Outxor is reversed in CRC + This parameter can be a value of @ref CRC OUTXOR Reverse. */ + uint32_t InitRev; /*!< Specifies if the Init is reversed in CRC + This parameter can be a value of @ref CRC INIT Reverse. */ + uint32_t RsltRev; /*!< Specifies if the Result is reversed in CRC + This parameter can be a value of @ref CRC RSLT Reverse. */ + uint32_t DataRev; /*!< Specifies if the Data is reversed in CRC + This parameter can be a value of @ref CRC DATA Reverse. */ + uint32_t PolyLen; /*!< Specifies the Poly Len in CRC + This parameter can be a value of @ref CRC Poly Len. */ + uint32_t DataLen; /*!< Specifies the Data Len in CRC + This parameter can be a value of @ref CRC Data Len. */ + uint32_t RST; /*!< Specifies if CRC is reset + This parameter can be a value of @ref CRC RST. */ + + uint32_t InitData; /*!< This member configures the InitData. */ + + uint32_t OutXorData; /*!< This member configures the OutXorData. */ + + uint32_t PolyData; /*!< This member configures the PolyData. */ + + uint32_t FData; /*!< This member configures the FData. */ + +}CRC_InitTypeDef; + +/* + * @brief UART handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< CRC registers base address */ + + CRC_InitTypeDef Init; /*!< CRC calculate parameters */ + + void* CRC_Data_Buff; /*!< CRC databuff base address */ + + uint32_t CRC_Data_Len; /*!< amount of CRC data to be calculated */ + +}CRC_HandleTypeDef; + +/****************************************************************************** +*@brief : Calculate the crc calue of input data +*@param : hcrc: pointer to the CRC handle +*@return: CRC value +******************************************************************************/ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc); + +/****************************************************************************** +*@brief : Initialize CRC +*@param : hcrc: pointer to the CRC handle +*@return: None +******************************************************************************/ +void HAL_CRC_Init(CRC_HandleTypeDef *hcrc); + + +#endif + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dac.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..f4aefa7e4fe179b2816e24a2bf55ebde6eba299a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dac.h @@ -0,0 +1,397 @@ +/* + ****************************************************************************** + * @file HAL_DAC.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of DAC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_DAC_H__ +#define __HAL_DAC_H__ + +#include "acm32h5xx_hal_conf.h" + + +/** + * @brief DAC Configuration sample and hold Channel structure definition + */ +typedef struct +{ + uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + + uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + + uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ +}DAC_SampleAndHoldConfTypeDef; + + +typedef struct +{ + uint32_t DAC_Calibration ; /*!< Specifies the Sample time for the selected channel. + This parameter can be a value of @ref DAC_Calibration */ + + uint32_t DAC_Calibration_TRIM ; /*!< Specifies the hold time for the selected channel + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ +}DAC_CalibrationConfTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel. + This parameter can be ENABLE or DISABLE */ + + FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel. + This parameter can be ENABLE or DISABLE */ + + uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. + This parameter can be a value of @ref DAC_SampleAndHold */ + + union{ + uint32_t DAC_Trigger; /*!< DAC normal trigger */ + uint32_t SawtoothResetTrigger; /*!< DAC SawTooth wave reset trigger */ + }; + + uint32_t SawtoothStepTrigger; /*!< DAC SawTooth wave step trigger */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ + + + uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . + This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ + + uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref DAC_UserTrimming + DAC_UserTrimming is either factory or user trimming */ + + uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value + i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ + +}DAC_ChannelConfTypeDef; + +/** + * @brief CAN handle Structure definition + */ +typedef struct +{ + DAC_TypeDef *Instance; /*!< Register base address */ + +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ +#endif + +}DAC_HandleTypeDef; + + +#define IS_DAC_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || ((INSTANCE) == DAC2)) + + + +/** @defgroup DAC_SampleAndHold DAC power mode + * @{ + */ +#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) +#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) + + +/** @defgroup DAC_CHANNEL + * @{ + */ + +#define DAC_CHANNEL_1 0x00000000U +#define DAC_CHANNEL_2 0x00000010U +#define DAC_CHANNEL_Dual 0x00000020U +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2) || \ + ((CHANNEL) == DAC_CHANNEL_Dual)) +/** + * @} + */ + + +#define DAC_CR_WAVE_DISABLE (0U) +#define DAC_CR_WAVE_NOISE (DAC_CR_WAVE1_0) +#define DAC_CR_WAVE_TRIANGLE (DAC_CR_WAVE1_1) +#define DAC_CR_WAVE_SAWTOOTH (DAC_CR_WAVE1_0 | DAC_CR_WAVE1_1) + + +/** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode + * @{ + */ +#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000U /*!< Sawtooth wave generation, polarity is decrement */ +#define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */ +#define IS_DAC_SAWTOOTH_POLARITY(POLARITY) ((POLARITY == DAC_SAWTOOTH_POLARITY_DECREMENT) || \ + (POLARITY == DAC_SAWTOOTH_POLARITY_INCREMENT)) + +/** + * @} + */ + /** @defgroup DAC_trigger + * @{ + */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_SOFTWARE (0x00000000U | DAC_CR_TEN1) /*!< conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPT1_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPT2_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXTI9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXTI10 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ + ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_LPT1_TRGO)|| \ + ((TRIGGER) == DAC_TRIGGER_LPT2_TRGO)|| \ + ((TRIGGER) == DAC_TRIGGER_EXTI9)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None 0x00000000U +#define DAC_WaveGeneration_Noise 0x00000001U +#define DAC_WaveGeneration_Triangle 0x00000002U +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 (DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 (DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 (DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 (DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 (DAC_CR_MAMP1_2| DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 (DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 (DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 (DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 (DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 (DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 (DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 (DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 (DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 (DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) +/** + * @} + */ + + /** @defgroup DAC_MODE + * @{ + */ + +#define DAC_Mode_Normal_BufferEnable_OutPAD 0x00000000U +#define DAC_Mode_Normal_BufferEnable_OutPAD_OutInternal 0x00000001U +#define DAC_Mode_Normal_BufferDisable_OutPAD 0x00000002U +#define DAC_Mode_Normal_BufferDisable_OutPAD_OutInternal 0x00000003U + +#define DAC_Mode_SampleAndHold_BufferEnable_OutPAD 0x00000004U +#define DAC_Mode_SampleAndHold_BufferEnable_OutPAD_OutInternal 0x00000005U +#define DAC_Mode_SampleAndHold_BufferDisable_OutPAD_OutInternal 0x00000006U +#define DAC_Mode_SampleAndHold_BufferDisable_OutInternal 0x00000007U +#define IS_DAC_MODE(MODE) (((MODE) == DAC_Mode_Normal_BufferEnable_OutPAD) || \ + ((MODE) == DAC_Mode_Normal_BufferEnable_OutPAD_OutInternal) || \ + ((MODE) == DAC_Mode_Normal_BufferDisable_OutPAD)|| \ + ((MODE) == DAC_Mode_Normal_BufferDisable_OutPAD_OutInternal)|| \ + ((MODE) == DAC_Mode_SampleAndHold_BufferEnable_OutPAD)|| \ + ((MODE) == DAC_Mode_SampleAndHold_BufferEnable_OutPAD_OutInternal)|| \ + ((MODE) == DAC_Mode_SampleAndHold_BufferDisable_OutPAD_OutInternal)|| \ + ((MODE) == DAC_Mode_SampleAndHold_BufferDisable_OutInternal)) +/** + * @} + */ + + /** @defgroup DAC_SampleAndHold DAC power mode + * @{ + */ +#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U +#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) +#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ + ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) +/** + * @} + */ + + + /** @defgroup DAC_UserTrimming DAC User Trimming +* @{ +*/ + +#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ +#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ +#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ + ((TRIMMING) == DAC_TRIMMING_USER)) +#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) +/** + * @} + */ + + /** @defgroup DAC_Calibration + * @{ + */ + +#define DAC_Calibration_Disable 0x00000000U +#define DAC_Calibration_Enable 0x00000001U +#define IS_DAC_Calibration(Calibration) (((Calibration) == DAC_Calibration_Disable) || \ + ((Calibration) == DAC_Calibration_Enable)) + +#define IS_DAC_Calibration_TRIM(TRIM) ((TRIM) <= 0x1FU) +/** + * @} + */ + /** @defgroup DAC_output_buffer DAC output buffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U +#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) +/** + * @} + */ + + +/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral + * @{ + */ + +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) +#define DAC_CHIPCONNECT_BOTH (1UL << 2) + +#define IS_DAC_CHIP_CONNECTION_BUFON(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \ + ((CONNECT) == DAC_CHIPCONNECT_BOTH)) + +#define IS_DAC_CHIP_CONNECTION_NORMALMODE_BUFOFF(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \ + ((CONNECT) == DAC_CHIPCONNECT_INTERNAL)) + +#define IS_DAC_CHIP_CONNECTION_SHMODE_BUFOFF(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \ + ((CONNECT) == DAC_CHIPCONNECT_BOTH)) +/** + * @} + */ + + + /** @defgroup DAC_data_alignment DAC data alignment + * @{ + */ + +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) + + + +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) + +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) +/** + * @} + */ + + + + +/* Initialization/de-initialization functions *********************************/ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); + +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) ; +HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,uint32_t ResetData, uint32_t StepData); +HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataResetBySoftware(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue); +uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); + + +#endif \ No newline at end of file diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dcmi.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dcmi.h new file mode 100644 index 0000000000000000000000000000000000000000..ff200c4f236e70c85c1afa52737c6f1fe121b281 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dcmi.h @@ -0,0 +1,735 @@ +/****************************************************************************** +* @file hal_uart.h + +* @brief Header file of UART HAL module. +* @version V1.0.0 +* @date 2020 +******************************************************************************/ +#ifndef __HAL_DCMI_H__ +#define __HAL_DCMI_H__ + +#include "acm32h5xx_hal_conf.h" +/** @addtogroup DCMI DCMI + * @brief DCMI HAL module driver + * @{ + */ +#define DCMI_POSITION_ESCR_LSC (uint32_t)DCMI_ESCR_LSC_Pos /*!< Required left shift to set line start delimiter */ +#define DCMI_POSITION_ESCR_LEC (uint32_t)DCMI_ESCR_LEC_Pos /*!< Required left shift to set line end delimiter */ +#define DCMI_POSITION_ESCR_FEC (uint32_t)DCMI_ESCR_FEC_Pos /*!< Required left shift to set frame end delimiter */ + + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +/******************************************************************************/ +/* */ +/* DCMI */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DCMI_CR register ******************/ +#define DCMI_CR_CAPTURE_Pos (0U) +#define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ +#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk +#define DCMI_CR_CM_Pos (1U) +#define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */ +#define DCMI_CR_CM DCMI_CR_CM_Msk +#define DCMI_CR_CROP_Pos (2U) +#define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ +#define DCMI_CR_CROP DCMI_CR_CROP_Msk +#define DCMI_CR_JPEG_Pos (3U) +#define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ +#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk +#define DCMI_CR_ESS_Pos (4U) +#define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ +#define DCMI_CR_ESS DCMI_CR_ESS_Msk +#define DCMI_CR_PCKPOL_Pos (5U) +#define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ +#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk +#define DCMI_CR_HSPOL_Pos (6U) +#define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ +#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk +#define DCMI_CR_VSPOL_Pos (7U) +#define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ +#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk +#define DCMI_CR_FCRC_0 0x00000100U +#define DCMI_CR_FCRC_1 0x00000200U +#define DCMI_CR_EDM_0 0x00000400U +#define DCMI_CR_EDM_1 0x00000800U +//#define DCMI_CR_CRE_Pos (12U) +//#define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ +//#define DCMI_CR_CRE DCMI_CR_CRE_Msk +#define DCMI_CR_ENABLE_Pos (14U) +#define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ +#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk + +/******************** Bits definition for DCMI_SR register ******************/ +#define DCMI_SR_HSYNC_Pos (0U) +#define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ +#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk +#define DCMI_SR_VSYNC_Pos (1U) +#define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ +#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk +#define DCMI_SR_FNE_Pos (2U) +#define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ +#define DCMI_SR_FNE DCMI_SR_FNE_Msk + +/******************** Bits definition for DCMI_RIS register *****************/ +#define DCMI_RIS_FRAME_RIS_Pos (0U) +#define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ +#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk +#define DCMI_RIS_OVR_RIS_Pos (1U) +#define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ +#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk +#define DCMI_RIS_ERR_RIS_Pos (2U) +#define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ +#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk +#define DCMI_RIS_VSYNC_RIS_Pos (3U) +#define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ +#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk +#define DCMI_RIS_LINE_RIS_Pos (4U) +#define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ +#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk +/* Legacy defines */ +#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS +#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS +#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS +#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS +#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS +#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS + +/******************** Bits definition for DCMI_IER register *****************/ +#define DCMI_IER_FRAME_IE_Pos (0U) +#define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ +#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk +#define DCMI_IER_OVR_IE_Pos (1U) +#define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ +#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk +#define DCMI_IER_ERR_IE_Pos (2U) +#define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ +#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk +#define DCMI_IER_VSYNC_IE_Pos (3U) +#define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ +#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk +#define DCMI_IER_LINE_IE_Pos (4U) +#define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ +#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk +/* Legacy defines */ +#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE + +/******************** Bits definition for DCMI_MIS register *****************/ +#define DCMI_MIS_FRAME_MIS_Pos (0U) +#define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ +#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk +#define DCMI_MIS_OVR_MIS_Pos (1U) +#define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ +#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk +#define DCMI_MIS_ERR_MIS_Pos (2U) +#define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ +#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk +#define DCMI_MIS_VSYNC_MIS_Pos (3U) +#define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ +#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk +#define DCMI_MIS_LINE_MIS_Pos (4U) +#define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ +#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk + +/* Legacy defines */ +#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS +#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS +#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS +#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS +#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS + +/******************** Bits definition for DCMI_ICR register *****************/ +#define DCMI_ICR_FRAME_ISC_Pos (0U) +#define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ +#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk +#define DCMI_ICR_OVR_ISC_Pos (1U) +#define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ +#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk +#define DCMI_ICR_ERR_ISC_Pos (2U) +#define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ +#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk +#define DCMI_ICR_VSYNC_ISC_Pos (3U) +#define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ +#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk +#define DCMI_ICR_LINE_ISC_Pos (4U) +#define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ +#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk + +/* Legacy defines */ +#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC + +/******************** Bits definition for DCMI_ESCR register ******************/ +#define DCMI_ESCR_FSC_Pos (0U) +#define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ +#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk +#define DCMI_ESCR_LSC_Pos (8U) +#define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk +#define DCMI_ESCR_LEC_Pos (16U) +#define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk +#define DCMI_ESCR_FEC_Pos (24U) +#define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ +#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk + +/******************** Bits definition for DCMI_ESUR register ******************/ +#define DCMI_ESUR_FSU_Pos (0U) +#define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ +#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk +#define DCMI_ESUR_LSU_Pos (8U) +#define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ +#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk +#define DCMI_ESUR_LEU_Pos (16U) +#define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ +#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk +#define DCMI_ESUR_FEU_Pos (24U) +#define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ +#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk + +/******************** Bits definition for DCMI_CWSTRT register ******************/ +#define DCMI_CWSTRT_HOFFCNT_Pos (0U) +#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk +#define DCMI_CWSTRT_VST_Pos (16U) +#define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ +#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk + +/******************** Bits definition for DCMI_CWSIZE register ******************/ +#define DCMI_CWSIZE_CAPCNT_Pos (0U) +#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ +#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk +#define DCMI_CWSIZE_VLINE_Pos (16U) +#define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ +#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk + +/******************** Bits definition for DCMI_DR register *********************/ +#define DCMI_DR_BYTE0_Pos (0U) +#define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ +#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk +#define DCMI_DR_BYTE1_Pos (8U) +#define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ +#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk +#define DCMI_DR_BYTE2_Pos (16U) +#define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ +#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk +#define DCMI_DR_BYTE3_Pos (24U) +#define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ +#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DCMI_Exported_Types DCMI Exported Types + * @{ + */ +/** + * @brief HAL DCMI State structures definition + */ +typedef enum +{ + HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */ + HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */ + HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */ + HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ + HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ + HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ +}HAL_DCMI_StateTypeDef; + +/** + * @brief DCMIEx Embedded Synchronisation CODE Init structure definition + */ +typedef struct +{ + uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ + uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ + uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ + uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ +}DCMI_CodesInitTypeDef; + +/** + * @brief DCMI Init structure definition + */ +/** + * @brief DCMI Init structure definition + */ +typedef struct +{ + uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. + This parameter can be a value of @ref DCMI_Synchronization_Mode */ + + uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. + This parameter can be a value of @ref DCMI_PIXCK_Polarity */ + + uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_VSYNC_Polarity */ + + uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. + This parameter can be a value of @ref DCMI_HSYNC_Polarity */ + + uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. + This parameter can be a value of @ref DCMI_Capture_Rate */ + + uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. + This parameter can be a value of @ref DCMI_Extended_Data_Mode */ + + DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */ + + uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode + This parameter can be a value of @ref DCMI_MODE_JPEG */ +}DCMI_InitTypeDef; + +/** + * @} + */ +/** + * @brief DCMI handle Structure definition + */ +typedef struct +{ + DCMI_TypeDef *Instance; /*!< DCMI Register base address */ + + DCMI_InitTypeDef Init; /*!< DCMI parameters */ + + HAL_LockTypeDef Lock; /*!< DCMI locking object */ + + __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */ + + __IO uint32_t XferCount; /*!< DMA transfer counter */ + + __IO uint32_t XferSize; /*!< DMA transfer size */ + + uint32_t XferTransferNumber; /*!< DMA transfer number */ + + uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */ + + __IO uint32_t ErrorCode; /*!< DCMI Error code */ + +}DCMI_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DCMI_Exported_Constants DCMI Exported Constants + * @{ + */ + +/** @defgroup DCMI_Error_Code DCMI Error Code + * @{ + */ +#define HAL_DCMI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DCMI_ERROR_OVR 0x00000001U /*!< Overrun error */ +#define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */ +#define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */ +/** + * @} + */ + +/** @defgroup DCMI_Capture_Mode DCMI Capture Mode + * @{ + */ +#define DCMI_MODE_CONTINUOUS 0x00000000U /*!< The received data are transferred continuously + into the destination memory through the DMA */ +#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of + frame and then transfers a single frame through the DMA */ +/** + * @} + */ + +/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode + * @{ + */ +#define DCMI_SYNCHRO_HARDWARE 0x00000000U /*!< Hardware synchronization data capture (frame/line start/stop) + is synchronized with the HSYNC/VSYNC signals */ +#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with + synchronization codes embedded in the data flow */ + +/** + * @} + */ + +/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity + * @{ + */ +#define DCMI_PCKPOLARITY_FALLING 0x00000000U /*!< Pixel clock active on Falling edge */ +#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ + +/** + * @} + */ + +/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity + * @{ + */ +#define DCMI_VSPOLARITY_LOW 0x00000000U /*!< Vertical synchronization active Low */ +#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ + +/** + * @} + */ + +/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity + * @{ + */ +#define DCMI_HSPOLARITY_LOW 0x00000000U /*!< Horizontal synchronization active Low */ +#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ + +/** + * @} + */ + +/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG + * @{ + */ +#define DCMI_JPEG_DISABLE 0x00000000U /*!< Mode JPEG Disabled */ +#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ + +/** + * @} + */ + +/** @defgroup DCMI_Capture_Rate DCMI Capture Rate + * @{ + */ +#define DCMI_CR_ALL_FRAME 0x00000000U /*!< All frames are captured */ +#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ +#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ + +/** + * @} + */ + +/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode + * @{ + */ +#define DCMI_EXTEND_DATA_8B 0x00000000U /*!< Interface captures 8-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ +#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ + +/** + * @} + */ + +/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate + * @{ + */ +#define DCMI_WINDOW_COORDINATE 0x3FFFU /*!< Window coordinate */ + +/** + * @} + */ + +/** @defgroup DCMI_Window_Height DCMI Window Height + * @{ + */ +#define DCMI_WINDOW_HEIGHT 0x1FFFU /*!< Window Height */ + +/** + * @} + */ + +/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line + * @{ + */ +#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */ +#define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */ + +/** + * @} + */ + +/** @defgroup DCMI_interrupt_sources DCMI interrupt sources + * @{ + */ +#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */ +#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */ +#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */ +#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */ +#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */ +/** + * @} + */ + +/** @defgroup DCMI_Flags DCMI Flags + * @{ + */ + +/** + * @brief DCMI SR register + */ +#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */ +#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */ +#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ +/** + * @brief DCMI RIS register + */ +#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) /*!< Frame capture complete interrupt flag */ +#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RISR_OVR_RIS) /*!< Overrun interrupt flag */ +#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) /*!< Synchronization error interrupt flag */ +#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) /*!< VSYNC interrupt flag */ +#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) /*!< Line interrupt flag */ +/** + * @brief DCMI MIS register + */ +#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */ +#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ +#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ +#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ +#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DCMI_Exported_Macros DCMI Exported Macros + * @{ + */ + +/** @brief Reset DCMI handle state + * @param __HANDLE__ specifies the DCMI handle. + * @retval None + */ +#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) + +/** + * @brief Enable the DCMI. + * @param __HANDLE__ DCMI handle + * @retval None + */ +#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) + +/** + * @brief Disable the DCMI. + * @param __HANDLE__ DCMI handle + * @retval None + */ +#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) + +/* Interrupt & Flag management */ +/** + * @brief Get the DCMI pending flag. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ Get the specified flag. + * This parameter can be one of the following values (no combination allowed) + * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) + * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) + * @arg DCMI_FLAG_FNE: FIFO empty flag + * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask + * @arg DCMI_FLAG_OVRRI: Overrun flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask + * @arg DCMI_FLAG_LINERI: Line flag mask + * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status + * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status + * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status + * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status + * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status + * @retval The state of FLAG. + */ +#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ +((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\ + (((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__))) + +/** + * @brief Clear the DCMI pending flags. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask + * @arg DCMI_FLAG_OVRRI: Overrun flag mask + * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask + * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask + * @arg DCMI_FLAG_LINERI: Line flag mask + * @retval None + */ +#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable the specified DCMI interrupts. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVR: Overrun interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval None + */ +#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DCMI interrupts. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVR: Overrun interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval None + */ +#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DCMI interrupt has occurred or not. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt source to check. + * This parameter can be one of the following values: + * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask + * @arg DCMI_IT_OVR: Overrun interrupt mask + * @arg DCMI_IT_ERR: Synchronization error interrupt mask + * @arg DCMI_IT_VSYNC: VSYNC interrupt mask + * @arg DCMI_IT_LINE: Line interrupt mask + * @retval The state of INTERRUPT. + */ +#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions + * @{ + */ + +/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); +void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); +/** + * @} + */ + +/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); +HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); +HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi); +HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi); +void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); +/** + * @} + */ + +/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); +HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); +/** + * @} + */ + +/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DCMI_Private_Constants DCMI Private Constants + * @{ + */ +#define DCMI_MIS_INDEX 0x1000U /*!< DCMI MIS register index */ +#define DCMI_SR_INDEX 0x2000U /*!< DCMI SR register index */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup DCMI_Private_Macros DCMI Private Macros + * @{ + */ +#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \ + ((MODE) == DCMI_MODE_SNAPSHOT)) + +#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ + ((MODE) == DCMI_SYNCHRO_EMBEDDED)) + +#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \ + ((POLARITY) == DCMI_PCKPOLARITY_RISING)) + +#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \ + ((POLARITY) == DCMI_VSPOLARITY_HIGH)) + +#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \ + ((POLARITY) == DCMI_HSPOLARITY_HIGH)) + +#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \ + ((JPEG_MODE) == DCMI_JPEG_ENABLE)) + +#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \ + ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \ + ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) + +#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \ + ((DATA) == DCMI_EXTEND_DATA_10B) || \ + ((DATA) == DCMI_EXTEND_DATA_12B) || \ + ((DATA) == DCMI_EXTEND_DATA_14B)) + +#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) + +#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DCMI_Private_Functions DCMI Private Functions + * @{ + */ + +/** + * @} + */ + +#endif /* __STM32F4xx_HAL_DCMI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_def.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_def.h new file mode 100644 index 0000000000000000000000000000000000000000..ab0479d261b39da19669d173be9be0cec0ae444d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_def.h @@ -0,0 +1,167 @@ + +/****************************************************************************** +*@file : hal_def.h +*@brief : This file contains HAL common defines, enumeration, macros and structures definitions. +******************************************************************************/ + +#ifndef __HAL_DEF_H +#define __HAL_DEF_H + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +typedef enum +{ + RESET = 0U, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; + +#define IS_FUNCTIONAL_STATE(State) (((State) == ENABLE) || ((State) == DISABLE)) + +typedef enum +{ + SUCCESS = 0U, + ERROR = !SUCCESS +} ErrorStatus; + + +/* Exported macro ------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#define UNUSED(x) ((void)(x)) + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5 */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif +#endif + +#ifdef __GNUC__ + #ifndef __weak + #define __weak __WEAK + #endif +#endif +#endif /* __HAL_DEF_H */ + + \ No newline at end of file diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dlyb.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dlyb.h new file mode 100644 index 0000000000000000000000000000000000000000..a329aa808f1dc0901d6b90296906b6ffcb6720e2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dlyb.h @@ -0,0 +1,37 @@ +/* + ****************************************************************************** + * @file HAL_DLYB.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of DLYB HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_DLYB_H__ +#define __HAL_DLYB_H__ + +#include "hal.h" + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + + + +#define DLYB_SEL_MAX 12 +#define DLYB_UINT_MAX 128 + + +#define DEN_ENABLE (1<<0) +#define SEN_ENABLE (1<<1) + + + + +HAL_StatusTypeDef HAL_DLYB_Enable(DLYB_TypeDef *hdlyb); +HAL_StatusTypeDef HAL_DLYB_Disable(DLYB_TypeDef *hdlyb); + + + + + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dma.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..7e0d56ed803910bb60caa322caaa677fa1793ba0 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dma.h @@ -0,0 +1,910 @@ +/****************************************************************************** +*@file : hal_dma.h +*@brief : Header file of DMA HAL module. +******************************************************************************/ + +#ifndef __HAL_DMA_H__ +#define __HAL_DMA_H__ + +#include "hal.h" + + +/** + * @brief DMA Configuration Structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the operation mode of the DMA. + This parameter can be a value of @ref DMA_Mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected channel */ + uint32_t Lock; + + uint32_t DataFlow; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_DataFlow */ + + uint32_t ReqID; /*!< The request number of the source peripheral and the destination peripheral. + This value is invalid when the memory to memory data transfer is configured + on the selected channel. + This parameter can be a value of @ref DMA1_ReqID or DMA2_ReqID */ + + uint32_t SrcIncDec; /*!< Specifies whether the source address register should be incremented or not. + This parameter can be a value of @ref DMA_SrcIncDec */ + + uint32_t DestIncDec; /*!< Specifies whether the destination address register should be incremented or not. + This parameter can be a value of @ref DMA_DestIncDec */ + + uint32_t SrcWidth; /*!< Specifies whether the source data width. + This parameter can be a value of @ref DMA_SrcWidth */ + + uint32_t DestWidth; /*!< Specifies whether the destination data width. + This parameter can be a value of @ref DMA_DestWidth */ + + uint32_t SrcBurst; /*!< Specifies the Burst transfer configuration for the source transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. This parameter can be a value of @ref DMA_SrcBurst. */ + + uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. This parameter can be a value of @ref DMA_DestBurst. */ + + uint32_t SrcMaster; /*!< Specifies the source master. + This parameter can be a value of @ref DMA_SrcMaster */ + + uint32_t DestMaster; /*!< Specifies the destination master. + This parameter can be a value of @ref DMA_DestMaster */ + + uint32_t NextMaster; /*!< Specifies the next master.Valid only in Circular mode. + This parameter can be a value of @ref DMA_NextMaster */ + +}DMA_InitTypeDef; + +/** + * @brief DMA Link List Item Structure + */ + +typedef struct __DMA_NextLink +{ + uint32_t SrcAddr; /*!< source address */ + + uint32_t DestAddr; /*!< desination address */ + + uint32_t Next; /*!< Next Node pointer */ + + uint32_t Ctrl; /*!< Ctrol */ + +}DMA_LinkTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + void *Parent; /*!< Parent object state */ + + void (*XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /* DMA transfer half complete callback */ + + void (*XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /* DMA transfer error callback */ + + void (*XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /* DMA transfer abort callback */ + + DMA_TypeDef *DMA; /*!< DMA channel Base Address */ + + uint32_t Channel; /*!< DMA channel */ + + DMA_LinkTypeDef Link; /*!< DMA Link */ + +}DMA_HandleTypeDef; + +/** + * @brief DMA Link Init Structure + */ + +typedef struct __DMA_LinkInitTypeDef +{ + uint32_t SrcAddr; /* source address */ + + uint32_t DestAddr; /* desination address */ + + uint32_t TransferSize; /* The length of data to be transferred from source to destination. */ + + uint32_t Next; /* Next Node pointer */ + + uint32_t NextMaster; /*!< Specifies the next master.Valid only if LLI is valid. + This parameter can be a value of @ref DMA_NextMaster */ + + uint32_t RawInt ; /*!< Raw interrupt enable. + This parameter can be a value of @ref DMA_RawInt */ + + uint32_t SrcIncDec; /*!< Specifies whether the source address register should be incremented or not. + This parameter can be a value of @ref DMA_SrcIncDec */ + + uint32_t DestIncDec; /*!< Specifies whether the destination address register should be incremented or not. + This parameter can be a value of @ref DMA_DestIncDec */ + + uint32_t SrcWidth; /*!< Specifies whether the source data width. + This parameter can be a value of @ref DMA_SrcWidth */ + + uint32_t DestWidth; /*!< Specifies whether the destination data width. + This parameter can be a value of @ref DMA_DestWidth */ + + uint32_t SrcBurst; /*!< Specifies the Burst transfer configuration for the source transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. This parameter can be a value of @ref DMA_SrcBurst. */ + + uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. This parameter can be a value of @ref DMA_DestBurst. */ + +}DMA_LinkInitTypeDef; + + + + +/** @defgroup DMA_RawInt + * @{ + */ + +#define DMA_RAWINT_DISABLE ( 0U ) +#define DMA_RAWINT_ENABLE ( DMA_CXCTRL_RITEN ) +/** + * @} + */ + +/** @defgroup DMA_SrcInc + * @{ + */ + +#define DMA_SRCINCDEC_DISABLE ( 0U ) +#define DMA_SRCINCDEC_INC ( DMA_CXCTRL_SIORSD_0 ) +#define DMA_SRCINCDEC_DEC ( DMA_CXCTRL_SIORSD_1 ) +#define DMA_SRCINCDEC_DISABLE_1 ( DMA_CXCTRL_SIORSD_1 | DMA_CXCTRL_SIORSD_0 ) +/** + * @} + */ + + +/** @defgroup DMA_DestInc + * @{ + */ + +#define DMA_DESTINCDEC_DISABLE ( 0U ) +#define DMA_DESTINCDEC_INC ( DMA_CXCTRL_DIORDD_0 ) +#define DMA_DESTINCDEC_DEC ( DMA_CXCTRL_DIORDD_1 ) +#define DMA_DESTINCDEC_DISABLE_1 ( DMA_CXCTRL_DIORDD_1 | DMA_CXCTRL_DIORDD_0 ) + +/** + * @} + */ + +/** @defgroup DMA_SrcWidth + * @{ + */ +#define DMA_SRCWIDTH_BYTE ( 0U ) /* 8bit */ +#define DMA_SRCWIDTH_HALFWORD ( DMA_CXCTRL_SWIDTH_0 ) /* 16bit */ +#define DMA_SRCWIDTH_WORD ( DMA_CXCTRL_SWIDTH_1 ) /* 32bit */ +/** + * @} + */ + +/** @defgroup DMA_DestWidth + * @{ + */ +#define DMA_DESTWIDTH_BYTE ( 0U ) /* 8bit */ +#define DMA_DESTWIDTH_HALFWORD ( DMA_CXCTRL_DWIDTH_0 ) /* 16bit */ +#define DMA_DESTWIDTH_WORD ( DMA_CXCTRL_DWIDTH_1 ) /* 32bit */ + +/** + * @} + */ + + /** @defgroup DMA_Mode + * @{ + */ +#define DMA_MODE_NORMAL ( 0U ) /*!< Normal mode */ +#define DMA_MODE_CIRCULAR ( 1U ) /*!< Circular mode */ + +/** + * @} + */ + +/** + * @brief DMA_SrcBurst + */ + +#define DMA_SRCBURST_1 ( 0U ) +#define DMA_SRCBURST_4 ( DMA_CXCTRL_SBSIZE_0 ) +#define DMA_SRCBURST_8 ( DMA_CXCTRL_SBSIZE_1 ) +#define DMA_SRCBURST_16 ( DMA_CXCTRL_SBSIZE_1 | DMA_CXCTRL_SBSIZE_0 ) +#define DMA_SRCBURST_32 ( DMA_CXCTRL_SBSIZE_2 ) +#define DMA_SRCBURST_64 ( DMA_CXCTRL_SBSIZE_2 | DMA_CXCTRL_SBSIZE_0 ) +#define DMA_SRCBURST_128 ( DMA_CXCTRL_SBSIZE_2 | DMA_CXCTRL_SBSIZE_1 ) +#define DMA_SRCBURST_256 ( DMA_CXCTRL_SBSIZE_2 | DMA_CXCTRL_SBSIZE_1 | DMA_CXCTRL_SBSIZE_0 ) + +/** + * @} + */ + +/** + * @brief DMA_DestBurst + */ + +#define DMA_DESTBURST_1 ( 0U ) +#define DMA_DESTBURST_4 ( DMA_CXCTRL_DBSIZE_0 ) +#define DMA_DESTBURST_8 ( DMA_CXCTRL_DBSIZE_1 ) +#define DMA_DESTBURST_16 ( DMA_CXCTRL_DBSIZE_1 | DMA_CXCTRL_DBSIZE_0 ) +#define DMA_DESTBURST_32 ( DMA_CXCTRL_DBSIZE_2 ) +#define DMA_DESTBURST_64 ( DMA_CXCTRL_DBSIZE_2 | DMA_CXCTRL_DBSIZE_0 ) +#define DMA_DESTBURST_128 ( DMA_CXCTRL_DBSIZE_2 | DMA_CXCTRL_DBSIZE_1 ) +#define DMA_DESTBURST_256 ( DMA_CXCTRL_DBSIZE_2 | DMA_CXCTRL_DBSIZE_1 | DMA_CXCTRL_DBSIZE_0 ) + +/** + * @} + */ + +/** + * @brief DMA_SrcMaster + */ + +#define DMA_SRCMASTER_1 ( 0U ) +#define DMA_SRCMASTER_2 ( DMA_CXCONFIG_S ) + +/** + * @} + */ + +/** + * @brief DMA_DestMaster + */ + +#define DMA_DESTMASTER_1 ( 0U ) +#define DMA_DESTMASTER_2 ( DMA_CXCONFIG_D ) + +/** + * @} + */ + +/** + * @brief DMA_Master1Endian + */ + +#define DMA_MASTER1_ENDIAN_LITTLE ( 0U ) +#define DMA_MASTER1_ENDIAN_BIG ( DMA_CONFIG_M1ENDIAN ) + +/** + * @} + */ + +/** + * @brief DMA_Master2Endian + */ + +#define DMA_MASTER2_ENDIAN_LITTLE ( 0U ) +#define DMA_MASTER2_ENDIAN_BIG ( DMA_CONFIG_M2ENDIAN ) + +/** + * @} + */ + +/** + * @brief DMA_NextMaster + */ + +#define DMA_NEXTMASTER_1 ( 0U ) +#define DMA_NEXTMASTER_2 ( DMA_CXLLI_LM ) + +/** + * @} + */ + +/** + * @brief DMA transfer max number + */ + +#define DMA_TRANSFER_SIZE ( 0xFFFFU ) + + +/** @defgroup DMA_DataFlow + * @{ + */ + +#define DMA_DATAFLOW_M2M ( 0U ) +#define DMA_DATAFLOW_M2P ( DMA_CXCONFIG_FLOWCTRL_0 ) +#define DMA_DATAFLOW_P2M ( DMA_CXCONFIG_FLOWCTRL_1 ) + +/** + * @} + */ + + +/** @defgroup DMA1_ReqID + * @{ + */ + +#define DMA1_REQ_M2M ( 0U ) +#define DMA1_REQ_ADC1 ( 0U ) +#define DMA1_REQ_SPI1_TX ( 1U ) +#define DMA1_REQ_SPI1_RX ( 2U ) +#define DMA1_REQ_SPI2_TX ( 3U ) +#define DMA1_REQ_SPI2_RX ( 4U ) +#define DMA1_REQ_USART1_TX ( 5U ) +#define DMA1_REQ_USART1_RX ( 6U ) +#define DMA1_REQ_USART2_TX ( 7U ) +#define DMA1_REQ_USART2_RX ( 8U ) +#define DMA1_REQ_I2C1_TX ( 9U ) +#define DMA1_REQ_I2C1_RX ( 10U ) +#define DMA1_REQ_I2C2_TX ( 11U ) +#define DMA1_REQ_I2C2_RX ( 12U ) +#define DMA1_REQ_TIM1_CH1 ( 13U ) +#define DMA1_REQ_TIM1_CH2 ( 14U ) +#define DMA1_REQ_TIM1_CH3 ( 15U ) +#define DMA1_REQ_TIM1_CH4 ( 16U ) +#define DMA1_REQ_TIM1_UP ( 17U ) +#define DMA1_REQ_TIM1_TRIG ( 18U ) +#define DMA1_REQ_TIM1_COM ( 19U ) +#define DMA1_REQ_TIM2_CH1 ( 20U ) +#define DMA1_REQ_TIM2_CH2 ( 21U ) +#define DMA1_REQ_TIM2_CH3 ( 22U ) +#define DMA1_REQ_TIM2_CH4 ( 23U ) +#define DMA1_REQ_TIM2_UP ( 24U ) +#define DMA1_REQ_TIM2_TRIG ( 25U ) +#define DMA1_REQ_ADC2 ( 26U ) +#define DMA1_REQ_ADC3 ( 27U ) +#define DMA1_REQ_USART3_TX ( 28U ) +#define DMA1_REQ_USART3_RX ( 29U ) +#define DMA1_REQ_LPUART_TX ( 30U ) +#define DMA1_REQ_LPUART_RX ( 31U ) +#define DMA1_REQ_TIM15_CH1 ( 32U ) +#define DMA1_REQ_TIM15_CH2 ( 33U ) +#define DMA1_REQ_TIM15_UP ( 34U ) +#define DMA1_REQ_TIM15_TRIG ( 35U ) +#define DMA1_REQ_TIM15_COM ( 36U ) +#define DMA1_REQ_I2S1_TX ( 37U ) +#define DMA1_REQ_I2S1_RX ( 38U ) +#define DMA1_REQ_DAC1_CH1 ( 39U ) +#define DMA1_REQ_DAC1_CH2 ( 40U ) +#define DMA1_REQ_I2S2_TX ( 41U ) +#define DMA1_REQ_I2S2_RX ( 42U ) +#define DMA1_REQ_I2S3_TX ( 43U ) +#define DMA1_REQ_I2S3_RX ( 44U ) +#define DMA1_REQ_USART4_TX ( 45U ) +#define DMA1_REQ_USART4_RX ( 46U ) +#define DMA1_REQ_SPI3_TX ( 47U ) +#define DMA1_REQ_SPI3_RX ( 48U ) +#define DMA1_REQ_TIM4_CH1 ( 49U ) +#define DMA1_REQ_TIM4_CH2 ( 50U ) +#define DMA1_REQ_TIM4_CH3 ( 51U ) +#define DMA1_REQ_TIM4_CH4 ( 52U ) +#define DMA1_REQ_TIM4_UP ( 53U ) +#define DMA1_REQ_TIM4_TRIG ( 54U ) +#define DMA1_REQ_NDL ( 55U ) +#define DMA1_REQ_STM1_PWM ( 56U ) +#define DMA1_REQ_STM2_PWM ( 57U ) +#define DMA1_REQ_DCMI ( 58U ) +#define DMA1_REQ_SPI7_RX ( 59U ) +#define DMA1_REQ_SPI7_TX ( 60U ) +#define DMA1_REQ_SPI8_RX ( 61U ) +#define DMA1_REQ_SPI8_TX ( 62U ) +#define DMA1_REQ_STM3_PWM ( 63U ) +#define DMA1_REQ_STM4_PWM ( 64U ) +#define DMA1_REQ_STM5_PWM ( 65U ) +#define DMA1_REQ_STM6_PWM ( 66U ) +#define DMA1_REQ_LPT ( 67U ) +#define DMA1_REQ_TIM5_UP ( 68U ) +#define DMA1_REQ_TIM5_CH1 ( 69U ) +#define DMA1_REQ_TIM5_CH2 ( 70U ) +#define DMA1_REQ_TIM5_CH3 ( 71U ) +#define DMA1_REQ_TIM5_CH4 ( 72U ) +#define DMA1_REQ_TIM5_TRIG ( 73U ) +#define DMA1_REQ_TIM5_COM ( 74U ) +#define DMA1_REQ_TIM25_UP ( 75U ) +#define DMA1_REQ_TIM25_CH1 ( 76U ) +#define DMA1_REQ_TIM25_CH2 ( 77U ) +#define DMA1_REQ_TIM25_TRIG ( 78U ) +#define DMA1_REQ_TIM25_COM ( 79U ) +#define DMA1_REQ_TIM20_UP ( 80U ) +#define DMA1_REQ_TIM20_CH1 ( 81U ) +#define DMA1_REQ_TIM20_CH2 ( 82U ) +#define DMA1_REQ_TIM20_CH3 ( 83U ) +#define DMA1_REQ_TIM20_CH4 ( 84U ) +#define DMA1_REQ_TIM20_CH5 ( 85U ) +#define DMA1_REQ_TIM20_CH6 ( 86U ) +#define DMA1_REQ_TIM20_TRIG ( 87U ) +#define DMA1_REQ_TIM20_COM ( 88U ) +#define DMA1_REQ_TIM18_UP ( 89U ) +#define DMA1_REQ_TIM18_CH1 ( 90U ) +#define DMA1_REQ_TIM18_TRIG ( 91U ) +#define DMA1_REQ_TIM18_COM ( 92U ) +#define DMA1_REQ_TIM19_UP ( 93U ) +#define DMA1_REQ_TIM19_CH1 ( 94U ) +#define DMA1_REQ_TIM19_TRIG ( 95U ) +#define DMA1_REQ_TIM19_COM ( 96U ) +#define DMA1_REQ_TIM21_UP ( 97U ) +#define DMA1_REQ_TIM22_UP ( 98U ) +#define DMA1_REQ_TIM23_UP ( 99U ) +#define DMA1_REQ_TIM23_CH1 ( 100U ) +#define DMA1_REQ_TIM23_CH2 ( 101U ) +#define DMA1_REQ_TIM23_CH3 ( 102U ) +#define DMA1_REQ_TIM23_CH4 ( 103U ) +#define DMA1_REQ_TIM23_TRIG ( 104U ) +#define DMA1_REQ_TIM23_COM ( 105U ) +#define DMA1_REQ_TIM24_UP ( 106U ) +#define DMA1_REQ_TIM24_CH1 ( 107U ) +#define DMA1_REQ_TIM24_CH2 ( 108U ) +#define DMA1_REQ_TIM24_CH3 ( 109U ) +#define DMA1_REQ_TIM24_CH4 ( 110U ) +#define DMA1_REQ_TIM24_TRIG ( 111U ) +#define DMA1_REQ_TIM24_COM ( 112U ) +#define DMA1_REQ_SPI4_RX ( 113U ) +#define DMA1_REQ_SPI4_TX ( 114U ) +#define DMA1_REQ_SPI5_RX ( 115U ) +#define DMA1_REQ_SPI5_TX ( 116U ) +#define DMA1_REQ_DAC2_CH1 ( 117U ) +#define DMA1_REQ_DAC2_CH2 ( 118U ) +#define DMA1_REQ_OSPI1_RX ( 119U ) +#define DMA1_REQ_OSPI1_TX ( 120U ) +#define DMA1_REQ_OSPI2_RX ( 121U ) +#define DMA1_REQ_OSPI2_TX ( 122U ) +#define DMA1_REQ_I2C3_TX ( 123U ) +#define DMA1_REQ_I2C3_RX ( 124U ) +#define DMA1_REQ_I2C4_TX ( 125U ) +#define DMA1_REQ_I2C4_RX ( 126U ) +#define DMA1_REQ_USART5_TX ( 127U ) +#define DMA1_REQ_USART5_RX ( 128U ) +#define DMA1_REQ_USART6_TX ( 129U ) +#define DMA1_REQ_USART6_RX ( 130U ) +#define DMA1_REQ_USART7_TX ( 131U ) +#define DMA1_REQ_USART7_RX ( 132U ) +#define DMA1_REQ_USART8_TX ( 133U ) +#define DMA1_REQ_USART8_RX ( 134U ) +#define DMA1_REQ_USART9_TX ( 135U ) +#define DMA1_REQ_USART9_RX ( 136U ) +#define DMA1_REQ_USART10_TX ( 137U ) +#define DMA1_REQ_USART10_RX ( 138U ) +#define DMA1_REQ_FDCAN1_TX ( 139U ) +#define DMA1_REQ_FDCAN1_RX ( 140U ) +#define DMA1_REQ_FDCAN2_TX ( 141U ) +#define DMA1_REQ_FDCAN2_RX ( 142U ) +#define DMA1_REQ_FDCAN3_TX ( 143U ) +#define DMA1_REQ_FDCAN3_RX ( 144U ) +#define DMA1_REQ_SPI6_RX ( 145U ) +#define DMA1_REQ_SPI6_TX ( 146U ) +#define DMA1_REQ_MAX ( 147U ) + +/** + * @} + */ + +/** @defgroup DMA2_ReqID + * @{ + */ + +#define DMA2_REQ_M2M ( 0U ) +#define DMA2_REQ_ADC1 ( 0U ) +#define DMA2_REQ_SPI1_TX ( 1U ) +#define DMA2_REQ_SPI1_RX ( 2U ) +#define DMA2_REQ_SPI2_TX ( 3U ) +#define DMA2_REQ_SPI2_RX ( 4U ) +#define DMA2_REQ_USART1_TX ( 5U ) +#define DMA2_REQ_USART1_RX ( 6U ) +#define DMA2_REQ_USART2_TX ( 7U ) +#define DMA2_REQ_USART2_RX ( 8U ) +#define DMA2_REQ_I2C1_TX ( 9U ) +#define DMA2_REQ_I2C1_RX ( 10U ) +#define DMA2_REQ_I2C2_TX ( 11U ) +#define DMA2_REQ_I2C2_RX ( 12U ) +#define DMA2_REQ_TIM8_CH1 ( 13U ) +#define DMA2_REQ_TIM8_CH2 ( 14U ) +#define DMA2_REQ_TIM8_CH3 ( 15U ) +#define DMA2_REQ_TIM8_CH4 ( 16U ) +#define DMA2_REQ_TIM8_UP ( 17U ) +#define DMA2_REQ_TIM8_TRIG ( 18U ) +#define DMA2_REQ_TIM8_COM ( 19U ) +#define DMA2_REQ_TIM3_CH1 ( 20U ) +#define DMA2_REQ_TIM3_CH2 ( 21U ) +#define DMA2_REQ_TIM3_CH3 ( 22U ) +#define DMA2_REQ_TIM3_CH4 ( 23U ) +#define DMA2_REQ_TIM3_UP ( 24U ) +#define DMA2_REQ_TIM3_TRIG ( 25U ) +#define DMA2_REQ_ADC2 ( 26U ) +#define DMA2_REQ_ADC3 ( 27U ) +#define DMA2_REQ_USART3_TX ( 28U ) +#define DMA2_REQ_USART3_RX ( 29U ) +#define DMA2_REQ_LPUART_TX ( 30U ) +#define DMA2_REQ_LPUART_RX ( 31U ) +#define DMA2_REQ_TIM16_CH1 ( 32U ) +#define DMA2_REQ_TIM16_UP ( 33U ) +#define DMA2_REQ_TIM17_CH1 ( 34U ) +#define DMA2_REQ_TIM17_UP ( 35U ) +#define DMA2_REQ_TIM6_UP ( 36U ) +#define DMA2_REQ_I2S1_TX ( 37U ) +#define DMA2_REQ_I2S1_RX ( 38U ) +#define DMA2_REQ_DAC1_CH1 ( 39U ) +#define DMA2_REQ_DAC1_CH2 ( 40U ) +#define DMA2_REQ_I2S2_TX ( 41U ) +#define DMA2_REQ_I2S2_RX ( 42U ) +#define DMA2_REQ_I2S3_TX ( 43U ) +#define DMA2_REQ_I2S3_RX ( 44U ) +#define DMA2_REQ_USART4_TX ( 45U ) +#define DMA2_REQ_USART4_RX ( 46U ) +#define DMA2_REQ_SPI3_TX ( 47U ) +#define DMA2_REQ_SPI3_RX ( 48U ) +#define DMA2_REQ_TIM7_UP ( 49U ) +#define DMA2_REQ_NDL ( 55U ) +#define DMA2_REQ_STM1_PWM ( 56U ) +#define DMA2_REQ_STM2_PWM ( 57U ) +#define DMA2_REQ_DCMI ( 58U ) +#define DMA2_REQ_SPI7_RX ( 59U ) +#define DMA2_REQ_SPI7_TX ( 60U ) +#define DMA2_REQ_SPI8_RX ( 61U ) +#define DMA2_REQ_SPI8_TX ( 62U ) +#define DMA2_REQ_STM3_PWM ( 63U ) +#define DMA2_REQ_STM4_PWM ( 64U ) +#define DMA2_REQ_STM5_PWM ( 65U ) +#define DMA2_REQ_STM6_PWM ( 66U ) +#define DMA2_REQ_LPT ( 67U ) +#define DMA2_REQ_TIM5_UP ( 68U ) +#define DMA2_REQ_TIM5_CH1 ( 69U ) +#define DMA2_REQ_TIM5_CH2 ( 70U ) +#define DMA2_REQ_TIM5_CH3 ( 71U ) +#define DMA2_REQ_TIM5_CH4 ( 72U ) +#define DMA2_REQ_TIM5_TRIG ( 73U ) +#define DMA2_REQ_TIM5_COM ( 74U ) +#define DMA2_REQ_TIM25_UP ( 75U ) +#define DMA2_REQ_TIM25_CH1 ( 76U ) +#define DMA2_REQ_TIM25_CH2 ( 77U ) +#define DMA2_REQ_TIM25_TRIG ( 78U ) +#define DMA2_REQ_TIM25_COM ( 79U ) +#define DMA2_REQ_TIM20_UP ( 80U ) +#define DMA2_REQ_TIM20_CH1 ( 81U ) +#define DMA2_REQ_TIM20_CH2 ( 82U ) +#define DMA2_REQ_TIM20_CH3 ( 83U ) +#define DMA2_REQ_TIM20_CH4 ( 84U ) +#define DMA2_REQ_TIM20_CH5 ( 85U ) +#define DMA2_REQ_TIM20_CH6 ( 86U ) +#define DMA2_REQ_TIM20_TRIG ( 87U ) +#define DMA2_REQ_TIM20_COM ( 88U ) +#define DMA2_REQ_TIM18_UP ( 89U ) +#define DMA2_REQ_TIM18_CH1 ( 90U ) +#define DMA2_REQ_TIM18_TRIG ( 91U ) +#define DMA2_REQ_TIM18_COM ( 92U ) +#define DMA2_REQ_TIM19_UP ( 93U ) +#define DMA2_REQ_TIM19_CH1 ( 94U ) +#define DMA2_REQ_TIM19_TRIG ( 95U ) +#define DMA2_REQ_TIM19_COM ( 96U ) +#define DMA2_REQ_TIM21_UP ( 97U ) +#define DMA2_REQ_TIM22_UP ( 98U ) +#define DMA2_REQ_TIM23_UP ( 99U ) +#define DMA2_REQ_TIM23_CH1 ( 100U ) +#define DMA2_REQ_TIM23_CH2 ( 101U ) +#define DMA2_REQ_TIM23_CH3 ( 102U ) +#define DMA2_REQ_TIM23_CH4 ( 103U ) +#define DMA2_REQ_TIM23_TRIG ( 104U ) +#define DMA2_REQ_TIM23_COM ( 105U ) +#define DMA2_REQ_TIM24_UP ( 106U ) +#define DMA2_REQ_TIM24_CH1 ( 107U ) +#define DMA2_REQ_TIM24_CH2 ( 108U ) +#define DMA2_REQ_TIM24_CH3 ( 109U ) +#define DMA2_REQ_TIM24_CH4 ( 110U ) +#define DMA2_REQ_TIM24_TRIG ( 111U ) +#define DMA2_REQ_TIM24_COM ( 112U ) +#define DMA2_REQ_SPI4_RX ( 113U ) +#define DMA2_REQ_SPI4_TX ( 114U ) +#define DMA2_REQ_SPI5_RX ( 115U ) +#define DMA2_REQ_SPI5_TX ( 116U ) +#define DMA2_REQ_DAC2_CH1 ( 117U ) +#define DMA2_REQ_DAC2_CH2 ( 118U ) +#define DMA2_REQ_OSPI1_RX ( 119U ) +#define DMA2_REQ_OSPI1_TX ( 120U ) +#define DMA2_REQ_OSPI2_RX ( 121U ) +#define DMA2_REQ_OSPI2_TX ( 122U ) +#define DMA2_REQ_I2C3_TX ( 123U ) +#define DMA2_REQ_I2C3_RX ( 124U ) +#define DMA2_REQ_I2C4_TX ( 125U ) +#define DMA2_REQ_I2C4_RX ( 126U ) +#define DMA2_REQ_USART5_TX ( 127U ) +#define DMA2_REQ_USART5_RX ( 128U ) +#define DMA2_REQ_USART6_TX ( 129U ) +#define DMA2_REQ_USART6_RX ( 130U ) +#define DMA2_REQ_USART7_TX ( 131U ) +#define DMA2_REQ_USART7_RX ( 132U ) +#define DMA2_REQ_USART8_TX ( 133U ) +#define DMA2_REQ_USART8_RX ( 134U ) +#define DMA2_REQ_USART9_TX ( 135U ) +#define DMA2_REQ_USART9_RX ( 136U ) +#define DMA2_REQ_USART10_TX ( 137U ) +#define DMA2_REQ_USART10_RX ( 138U ) +#define DMA2_REQ_FDCAN1_TX ( 139U ) +#define DMA2_REQ_FDCAN1_RX ( 140U ) +#define DMA2_REQ_FDCAN2_TX ( 141U ) +#define DMA2_REQ_FDCAN2_RX ( 142U ) +#define DMA2_REQ_FDCAN3_TX ( 143U ) +#define DMA2_REQ_FDCAN3_RX ( 144U ) +#define DMA2_REQ_SPI6_RX ( 145U ) +#define DMA2_REQ_SPI6_TX ( 146U ) +#define DMA2_REQ_MAX ( 147U ) + +/** + * @} + */ + +/** + * @brief DMA_XfeCallbackID + */ + +#define DMA_CALLBACKID_CPLT ( 0U ) +#define DMA_CALLBACKID_HALFCPLT ( 1U ) +#define DMA_CALLBACKID_ERROR ( 2U ) +#define DMA_CALLBACKID_ABORT ( 3U ) +#define DMA_CALLBACKID_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup DMA_Flag + * @{ + */ +#define DMA_FLAG_TC ( 0x01U ) /*!< Flag, indicating transmission completion interrupt occur */ +#define DMA_FLAG_HTC ( 0x02U ) /*!< Flag, indicating half transmission completion interrupt occur */ +#define DMA_FLAG_ERR ( 0x04U ) /*!< Flag, indicating error interrupt occur */ +#define DMA_FLAG_RTC ( 0x08U ) /*!< Flag, indicating raw transmission completion interrupt occur */ +#define DMA_FLAG_RHTC ( 0x10U ) /*!< Flag, indicating raw half transmission completion interrupt occur */ +#define DMA_FLAG_RERR ( 0x20U ) /*!< Flag, indicating raw error interrupt occur */ + +/** + * @} + */ + +/** + * @brief DMA FLAG mask for assert test + */ + +#define DMA_FLAG_MASK ( DMA_FLAG_TC | DMA_FLAG_HTC | DMA_FLAG_ERR | DMA_FLAG_RTC | DMA_FLAG_RHTC | DMA_FLAG_RERR ) + + +/** @defgroup DMA_IT + * @{ + */ +#define DMA_IT_TC ( DMA_CXCONFIG_ITC ) /*!< transmission completion interrupt */ +#define DMA_IT_HTC ( DMA_CXCONFIG_IHFTC ) /*!< indicating half transmission completion interrupt */ +#define DMA_IT_ERR ( DMA_CXCONFIG_IE ) /*!< error interrupt */ + +/** + * @} + */ + +/** + * @brief DMA IT mask for assert test + */ + +#define DMA_IT_MASK ( DMA_IT_TC | DMA_IT_HTC | DMA_IT_ERR ) + +/** + * @brief DMA TIMEOUT + */ + +#define DMA_ABORT_TIMEOUT ( 0xFFFFU ) + + +/* Exported functions --------------------------------------------------------*/ + +#define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_) (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_) + +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->DMA->CONFIG |= DMA_CONFIG_EN) + +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->DMA->CONFIG &= ~DMA_CONFIG_EN) + +#define __HAL_DMA_MASTER1_BIG_ENDIAN(__HANDLE__) ((__HANDLE__)->DMA->CONFIG |= DMA_CONFIG_M1ENDIAN) + +#define __HAL_DMA_MASTER1_LITTLE_ENDIAN(__HANDLE__) ((__HANDLE__)->DMA->CONFIG &= ~DMA_CONFIG_M1ENDIAN) + +#define __HAL_DMA_MASTER2_BIG_ENDIAN(__HANDLE__) ((__HANDLE__)->DMA->CONFIG |= DMA_CONFIG_M2ENDIAN) + +#define __HAL_DMA_MASTER2_LITTLE_ENDIAN(__HANDLE__) ((__HANDLE__)->DMA->CONFIG &= ~DMA_CONFIG_M2ENDIAN) + +#define __HAL_DMA_RAWINT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CXCTRL |= DMA_CXCTRL_RITEN) + +#define __HAL_DMA_RAWINT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CXCTRL &= ~DMA_CXCTRL_RITEN) + +#define __HAL_DMA_LOCK_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CXCONFIG |= DMA_CXCONFIG_LOCK) + +#define __HAL_DMA_LOCK_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CXCONFIG &= ~DMA_CXCONFIG_LOCK) + +#define __HAL_DMA_GET_HFTC_IT_SOURCE(__HANDLE__) ((__HANDLE__)->Instance->CXCONFIG & DMA_CXCONFIG_IHFTC) + +#define __HAL_DMA_GET_TC_IT_SOURCE(__HANDLE__) ((__HANDLE__)->Instance->CXCONFIG & DMA_CXCONFIG_ITC) + +#define __HAL_DMA_GET_ERR_IT_SOURCE(__HANDLE__) ((__HANDLE__)->Instance->CXCONFIG & DMA_CXCONFIG_IE) + +#define __HAL_DMA_GET_TRANSFER_SIZE(__HANDLE__) ((__HANDLE__)->Instance->CXCTRL & 0xFFFFU) + +#define __HAL_DMA_GET_LINK(__HANDLE__) ((__HANDLE__)->Instance->CXLLI & DMA_CXLLI_LLI) + + + +/** @defgroup DMA Private Macros + * @{ + */ +#define IS_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +#define IS_DMA_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Channel0) || \ + ((__INSTANCE__) == DMA1_Channel1) || \ + ((__INSTANCE__) == DMA1_Channel2) || \ + ((__INSTANCE__) == DMA1_Channel3) || \ + ((__INSTANCE__) == DMA1_Channel4) || \ + ((__INSTANCE__) == DMA1_Channel5) || \ + ((__INSTANCE__) == DMA1_Channel6) || \ + ((__INSTANCE__) == DMA1_Channel7) || \ + ((__INSTANCE__) == DMA2_Channel0) || \ + ((__INSTANCE__) == DMA2_Channel1) || \ + ((__INSTANCE__) == DMA2_Channel2) || \ + ((__INSTANCE__) == DMA2_Channel3) || \ + ((__INSTANCE__) == DMA2_Channel4) || \ + ((__INSTANCE__) == DMA2_Channel5) || \ + ((__INSTANCE__) == DMA2_Channel6) || \ + ((__INSTANCE__) == DMA2_Channel7)) + +#define IS_DMA_MODE(__MODE__) (((__MODE__) == DMA_MODE_NORMAL ) || \ + ((__MODE__) == DMA_MODE_CIRCULAR)) + +#define IS_DMA_DATAFLOW(__DATAFLOW__) (((__DATAFLOW__) == DMA_DATAFLOW_M2M) || \ + ((__DATAFLOW__) == DMA_DATAFLOW_M2P) || \ + ((__DATAFLOW__) == DMA_DATAFLOW_P2M)) + +#define IS_DMA_REQ1ID(__DATAFLOW__, __REQID__) ((__DATAFLOW__ == DMA_DATAFLOW_M2M) ? SET : \ + ((__REQID__) < DMA1_REQ_MAX)) + +#define IS_DMA_REQ2ID(__DATAFLOW__, __REQID__) ((__DATAFLOW__ == DMA_DATAFLOW_M2M) ? SET : \ + ((__REQID__) < DMA2_REQ_MAX)) + +#define IS_DMA_SRCINCDEC(__INCDEC__) (((__INCDEC__) == DMA_SRCINCDEC_DISABLE ) || \ + ((__INCDEC__) == DMA_SRCINCDEC_INC) || \ + ((__INCDEC__) == DMA_SRCINCDEC_DEC)) + +#define IS_DMA_DESTINCDEC(__INCDEC__) (((__INCDEC__) == DMA_DESTINCDEC_DISABLE ) || \ + ((__INCDEC__) == DMA_DESTINCDEC_INC) || \ + ((__INCDEC__) == DMA_DESTINCDEC_DEC)) + +#define IS_DMA_SRCWIDTH(__WIDTH__) (((__WIDTH__) == DMA_SRCWIDTH_BYTE) || \ + ((__WIDTH__) == DMA_SRCWIDTH_HALFWORD) || \ + ((__WIDTH__) == DMA_SRCWIDTH_WORD)) + +#define IS_DMA_DESTWIDTH(__WIDTH__) (((__WIDTH__) == DMA_DESTWIDTH_BYTE) || \ + ((__WIDTH__) == DMA_DESTWIDTH_HALFWORD) || \ + ((__WIDTH__) == DMA_DESTWIDTH_WORD)) + +#define IS_DMA_SRCBURST(__BURST__) (((__BURST__) == DMA_SRCBURST_1) || \ + ((__BURST__) == DMA_SRCBURST_4) || \ + ((__BURST__) == DMA_SRCBURST_8) || \ + ((__BURST__) == DMA_SRCBURST_16) || \ + ((__BURST__) == DMA_SRCBURST_32) || \ + ((__BURST__) == DMA_SRCBURST_64) || \ + ((__BURST__) == DMA_SRCBURST_128) || \ + ((__BURST__) == DMA_SRCBURST_256)) + +#define IS_DMA_DESTBURST(__BURST__) (((__BURST__) == DMA_DESTBURST_1) || \ + ((__BURST__) == DMA_DESTBURST_4) || \ + ((__BURST__) == DMA_DESTBURST_8) || \ + ((__BURST__) == DMA_DESTBURST_16) || \ + ((__BURST__) == DMA_DESTBURST_32) || \ + ((__BURST__) == DMA_DESTBURST_64) || \ + ((__BURST__) == DMA_DESTBURST_128) || \ + ((__BURST__) == DMA_DESTBURST_256)) + +#define IS_DMA_SRCMASTER(__MASTER__) (((__MASTER__) == DMA_SRCMASTER_1) || \ + ((__MASTER__) == DMA_SRCMASTER_2)) + +#define IS_DMA_DESTMASTER(__MASTER__) (((__MASTER__) == DMA_DESTMASTER_1) || \ + ((__MASTER__) == DMA_DESTMASTER_2)) + +#define IS_DMA_MASTER1_ENDIAN(__ENDIAN__) (((__ENDIAN__) == DMA_MASTER1_ENDIAN_LITTLE) || \ + ((__ENDIAN__) == DMA_MASTER1_ENDIAN_BIG)) + +#define IS_DMA_MASTER2_ENDIAN(__ENDIAN__) (((__ENDIAN__) == DMA_MASTER2_ENDIAN_LITTLE) || \ + ((__ENDIAN__) == DMA_MASTER2_ENDIAN_BIG)) + +#define IS_DMA_NEXTMASTER(__MASTER__) (((__MASTER__) == DMA_NEXTMASTER_1) || \ + ((__MASTER__) == DMA_NEXTMASTER_2)) + +#define IS_DMA_CALLBACK(__CALLBACK__) ((__CALLBACK__) < DMA_CALLBACKID_MAX) + +#define IS_DMA_RAWIT(__RAWIT__) (((__RAWIT__) == DMA_RAWINT_DISABLE) || \ + ((__RAWIT__) == DMA_RAWINT_ENABLE)) + +#define IS_DMA_SRCADDR(__ADDR__) ( SET ) + +#define IS_DMA_DESTADDR(__ADDR__) ( SET ) + +#define IS_DMA_NEXT(__NEXT__) ((((uint32_t)(__NEXT__)) & 0x03U) == 0) + +#define IS_DMA_TRANSFERSIZE(__SIZE__) (((__SIZE__) != 0) && ((__SIZE__) <= 0xFFFFU)) + +#define IS_DMA_STATE(__FLAG__) (((__FLAG__) == DMA_FLAG_TC) || \ + ((__FLAG__) == DMA_FLAG_HTC) || \ + ((__FLAG__) == DMA_FLAG_ERR) || \ + ((__FLAG__) == DMA_FLAG_RTC) || \ + ((__FLAG__) == DMA_FLAG_RHTC) || \ + ((__FLAG__) == DMA_FLAG_RERR)) + +#define IS_DMA_FLAG(__FLAG__) ((((uint32_t)(__FLAG__) & DMA_FLAG_MASK) != 0) && \ + (((uint32_t)(__FLAG__) & ~DMA_FLAG_MASK) == 0)) + +#define IS_DMA_IT(__IT__) ((((uint32_t)(__IT__) & DMA_IT_MASK) != 0) && \ + (((uint32_t)(__IT__) & ~DMA_IT_MASK) == 0)) + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ + +/* This function handles DMA interrupt request. */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); + +/* Initialize the DMA according to the specified. */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); + +/* DeInitializes the DMA peripheral. */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); + +/* Initialize the DMA MSP. */ +void HAL_DMA_MspInit(DMA_HandleTypeDef *hdma); + +/* DeInitialize the DMA MSP. */ +void HAL_DMA_MspDeInit(DMA_HandleTypeDef *hdma); + +/* Register callbacks. */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, uint32_t CallbackID, \ + void (* pCallback)(struct __DMA_HandleTypeDef * hdma)); + +/* UnRegister callbacks. */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, uint32_t CallbackID); + +/* Starts the DMA Transfer. */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DestAddr, uint32_t TransferSize); + +/* Start the DMA Transfer with interrupt enabled. */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DestAddr, uint32_t TransferSize); + +/* Initialize linked list. */ +HAL_StatusTypeDef HAL_DMA_InitLink(DMA_LinkTypeDef *Link, DMA_LinkInitTypeDef *Link_Init); + +/* Set the next node of the linked node. */ +HAL_StatusTypeDef HAL_DMA_SetLinkNext(DMA_LinkTypeDef *Curr, DMA_LinkTypeDef *Next); + +/* DMA link transfer start. */ +HAL_StatusTypeDef HAL_DMA_Start_Link(DMA_HandleTypeDef *hdma, DMA_LinkTypeDef *Link); + +/* DMA link transfer start with interrupt enabled. */ +HAL_StatusTypeDef HAL_DMA_Start_Link_IT(DMA_HandleTypeDef *hdma, DMA_LinkTypeDef *Link); + +/* Abort the DMA Transfer. */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); + +/* Get interrupt source. */ +FunctionalState HAL_DMA_GetITSource(DMA_HandleTypeDef *hdma, uint32_t IT); + +/* Enable interrupt. */ +HAL_StatusTypeDef HAL_DMA_EnableIT(DMA_HandleTypeDef *hdma, uint32_t IT); + +/* Disable interrupt. */ +HAL_StatusTypeDef HAL_DMA_DisableIT(DMA_HandleTypeDef *hdma, uint32_t IT); + +/* Clear the DMA flag. */ +HAL_StatusTypeDef HAL_DMA_ClearFlag(DMA_HandleTypeDef *hdma, uint32_t Flag); + +/* Returns the DMA flag. */ +FlagStatus HAL_DMA_GetFlag(DMA_HandleTypeDef *hdma, uint32_t Flag); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dma2d.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dma2d.h new file mode 100644 index 0000000000000000000000000000000000000000..1e8b7c0a553b8c1b5c33632c9363a32ceb44d359 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dma2d.h @@ -0,0 +1,858 @@ +/****************************************************************************** +*@file : hal_dma2d.h +*@brief : GPIO HAL module driver. +******************************************************************************/ + +#ifndef __HAL_DMA2D_H__ +#define __HAL_DMA2D_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "hal.h" + + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Types DMA2D Exported Types + * @{ + */ +#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ + + +/******************** Bit definition for DMA2D_CR register ******************/ +#define DMA2D_CR_START_Pos (0U) +#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */ +#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */ +#define DMA2D_CR_SUSP_Pos (1U) +#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */ +#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */ +#define DMA2D_CR_ABORT_Pos (2U) +#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */ +#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */ +#define DMA2D_CR_TEIE_Pos (8U) +#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */ +#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ +#define DMA2D_CR_TCIE_Pos (9U) +#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */ +#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ +#define DMA2D_CR_TWIE_Pos (10U) +#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */ +#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */ +#define DMA2D_CR_CAEIE_Pos (11U) +#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */ +#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */ +#define DMA2D_CR_CTCIE_Pos (12U) +#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */ +#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */ +#define DMA2D_CR_CEIE_Pos (13U) +#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */ +#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */ +#define DMA2D_CR_MODE_Pos (16U) +#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */ +#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */ +#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */ +#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */ +#define DMA2D_CR_AHB_LOCK_Pos (18U) +#define DMA2D_CR_AHB_LOCK_Msk (0x1UL << DMA2D_CR_AHB_LOCK_Pos) /*!< 0x00040000 */ +#define DMA2D_CR_AHB_LOCK DMA2D_CR_AHB_LOCK_Msk /*!< AHB lock Enable */ + + +/******************** Bit definition for DMA2D_ISR register *****************/ +#define DMA2D_ISR_TEIF_Pos (0U) +#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */ +#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */ +#define DMA2D_ISR_TCIF_Pos (1U) +#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */ +#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */ +#define DMA2D_ISR_TWIF_Pos (2U) +#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */ +#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */ +#define DMA2D_ISR_CAEIF_Pos (3U) +#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */ +#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */ +#define DMA2D_ISR_CTCIF_Pos (4U) +#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */ +#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_ISR_CEIF_Pos (5U) +#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */ +#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */ + +/******************** Bit definition for DMA2D_IFCR register ****************/ +#define DMA2D_IFCR_CTEIF_Pos (0U) +#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */ +#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */ +#define DMA2D_IFCR_CTCIF_Pos (1U) +#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */ +#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */ +#define DMA2D_IFCR_CTWIF_Pos (2U) +#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */ +#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */ +#define DMA2D_IFCR_CAECIF_Pos (3U) +#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */ +#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */ +#define DMA2D_IFCR_CCTCIF_Pos (4U) +#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */ +#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_IFCR_CCEIF_Pos (5U) +#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */ +#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */ + +/******************** Bit definition for DMA2D_FGMAR register ***************/ +#define DMA2D_FGMAR_MA_Pos (0U) +#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */ + +/******************** Bit definition for DMA2D_FGOR register ****************/ +#define DMA2D_FGOR_LO_Pos (0U) +#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */ +#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */ + +/******************** Bit definition for DMA2D_BGMAR register ***************/ +#define DMA2D_BGMAR_MA_Pos (0U) +#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */ + +/******************** Bit definition for DMA2D_BGOR register ****************/ +#define DMA2D_BGOR_LO_Pos (0U) +#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */ +#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */ + +/******************** Bit definition for DMA2D_FGPFCCR register *************/ +#define DMA2D_FGPFCCR_CM_Pos (0U) +#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */ +#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ +#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */ +#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */ +#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */ +#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */ +#define DMA2D_FGPFCCR_CCM_Pos (4U) +#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */ +#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */ +#define DMA2D_FGPFCCR_START_Pos (5U) +#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */ +#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */ +#define DMA2D_FGPFCCR_CS_Pos (8U) +#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */ +#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */ +#define DMA2D_FGPFCCR_AM_Pos (16U) +#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */ +#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ +#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */ +#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */ +#define DMA2D_FGPFCCR_CSS_Pos (18U) +#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */ +#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */ +#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */ +#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */ +#define DMA2D_FGPFCCR_AI_Pos (20U) +#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */ +#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */ +#define DMA2D_FGPFCCR_RBS_Pos (21U) +#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */ +#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */ +#define DMA2D_FGPFCCR_ALPHA_Pos (24U) +#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ +#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */ + +/******************** Bit definition for DMA2D_FGCOLR register **************/ +#define DMA2D_FGCOLR_BLUE_Pos (0U) +#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */ +#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */ +#define DMA2D_FGCOLR_GREEN_Pos (8U) +#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ +#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */ +#define DMA2D_FGCOLR_RED_Pos (16U) +#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */ +#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */ + +/******************** Bit definition for DMA2D_BGPFCCR register *************/ +#define DMA2D_BGPFCCR_CM_Pos (0U) +#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */ +#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ +#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */ +#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */ +#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */ +#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */ +#define DMA2D_BGPFCCR_CCM_Pos (4U) +#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */ +#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */ +#define DMA2D_BGPFCCR_START_Pos (5U) +#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */ +#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */ +#define DMA2D_BGPFCCR_CS_Pos (8U) +#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */ +#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */ +#define DMA2D_BGPFCCR_AM_Pos (16U) +#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */ +#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ +#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */ +#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */ +#define DMA2D_BGPFCCR_AI_Pos (20U) +#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */ +#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */ +#define DMA2D_BGPFCCR_RBS_Pos (21U) +#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */ +#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */ +#define DMA2D_BGPFCCR_ALPHA_Pos (24U) +#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ +#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */ + +/******************** Bit definition for DMA2D_BGCOLR register **************/ +#define DMA2D_BGCOLR_BLUE_Pos (0U) +#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */ +#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */ +#define DMA2D_BGCOLR_GREEN_Pos (8U) +#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ +#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */ +#define DMA2D_BGCOLR_RED_Pos (16U) +#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */ +#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */ + +/******************** Bit definition for DMA2D_FGCMAR register **************/ +#define DMA2D_FGCMAR_MA_Pos (0U) +#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */ + +/******************** Bit definition for DMA2D_BGCMAR register **************/ +#define DMA2D_BGCMAR_MA_Pos (0U) +#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */ + +/******************** Bit definition for DMA2D_OPFCCR register **************/ +#define DMA2D_OPFCCR_CM_Pos (0U) +#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */ +#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */ +#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */ +#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */ +#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */ +#define DMA2D_OPFCCR_AI_Pos (20U) +#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */ +#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */ +#define DMA2D_OPFCCR_RBS_Pos (21U) +#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */ +#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */ + +/******************** Bit definition for DMA2D_OCOLR register ***************/ +/*!State = HAL_DMA2D_STATE_RESET) + +/** + * @brief Enable the DMA2D. + * @param __HANDLE__: DMA2D handle + * @retval None. + */ +#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) + + +/* Interrupt & Flag management */ +/** + * @brief Get the DMA2D pending flags. + * @param __HANDLE__: DMA2D handle + * @param __FLAG__: flag to check. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag + * @arg DMA2D_FLAG_TW: Transfer Watermark flag + * @arg DMA2D_FLAG_TC: Transfer complete flag + * @arg DMA2D_FLAG_TE: Transfer error flag + * @retval The state of FLAG. + */ +#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clear the DMA2D pending flags. + * @param __HANDLE__: DMA2D handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA2D_FLAG_CE: Configuration error flag + * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag + * @arg DMA2D_FLAG_CAE: CLUT access error flag + * @arg DMA2D_FLAG_TW: Transfer Watermark flag + * @arg DMA2D_FLAG_TC: Transfer complete flag + * @arg DMA2D_FLAG_TE: Transfer error flag + * @retval None + */ +#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA2D interrupts. + * @param __HANDLE__: DMA2D handle + * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA2D interrupts. + * @param __HANDLE__: DMA2D handle + * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA2D interrupt source is enabled or not. + * @param __HANDLE__: DMA2D handle + * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA2D_IT_CE: Configuration error interrupt mask + * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask + * @arg DMA2D_IT_CAE: CLUT access error interrupt mask + * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask + * @arg DMA2D_IT_TC: Transfer complete interrupt mask + * @arg DMA2D_IT_TE: Transfer error interrupt mask + * @retval The state of INTERRUPT source. + */ +#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); + +/** + * @} + */ + + +/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); + +/** + * @} + */ + +/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State functions ***************************************************/ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark + * @{ + */ +#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ +/** + * @} + */ + +/** @defgroup DMA2D_Color_Value DMA2D Color Value + * @{ + */ +#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */ +/** + * @} + */ + +/** @defgroup DMA2D_Offset DMA2D Offset + * @{ + */ +#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ +/** + * @} + */ + +/** @defgroup DMA2D_Size DMA2D Size + * @{ + */ +#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ +#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ +/** + * @} + */ + +/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size + * @{ + */ +#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D maximum CLUT size */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA2D_Private_Macros DMA2D Private Macros + * @{ + */ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) +#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER) +#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ + ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) +#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) +#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) +#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) +#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ + ((INPUT_CM) == DMA2D_INPUT_A4)) +#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ + ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ + ((AlphaMode) == DMA2D_COMBINE_ALPHA)) + +#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ + ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) + +#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ + ((RB_Swap) == DMA2D_RB_SWAP)) + +#define IS_DMA2D_CHROMA_SUB_SAMPLING (CSS) (((CSS) == DMA2D_NO_CSS) || \ + ((CSS) == DMA2D_CSS_422) || \ + ((CSS) == DMA2D_CSS_420)) + +#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) +#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) +#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) +#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) +#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif //#ifdef __HAL_DMA2D_H__ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dwt.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dwt.h new file mode 100644 index 0000000000000000000000000000000000000000..78b15bc51aab1ad1f3bc453d56cfb7fe84367688 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_dwt.h @@ -0,0 +1,36 @@ +/****************************************************************************** +*@file : hal_dwt.h +*@brief : header file +******************************************************************************/ +#ifndef __HAL_DWT_H__ +#define __HAL_DWT_H__ + +#include "hal.h" + +extern uint32_t HAL_DWT_clkPerUs, HAL_DWT_clkPerMs; + +#define _HAL_DWT_GET_CLK_TICK() (DWT->CYCCNT) +#define _HAL_DWT_GET_CLK_DELAY(startClkTick) (DWT->CYCCNT - (startClkTick)) +#define _HAL_DWT_DELAY_CLKS(startClkTick,clks) while(DWT->CYCCNT - (startClkTick) < (clks)) + +void HAL_DWT_Init(void); + + +__STATIC_FORCEINLINE uint32_t HAL_DWT_GetClkTick(void) +{ + return DWT->CYCCNT; +} + +uint32_t HAL_DWT_GetClkDelay(uint32_t startClkTick); + +uint32_t HAL_DWT_GetUsDelay(uint32_t startClkTick); + +uint32_t HAL_DWT_GetMsDelay(uint32_t startClkTick); + +void HAL_DWT_DelayClks(uint32_t clks); + +void HAL_DWT_DelayUs(uint32_t us); + +void HAL_DWT_DelayMs(uint32_t ms); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_efuse.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_efuse.h new file mode 100644 index 0000000000000000000000000000000000000000..1400c99f1f6b2e781d221d5b5d4b79b2a468ca2d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_efuse.h @@ -0,0 +1,84 @@ +/****************************************************************************** +*@file : hal_efuse.h +*@brief : Header file of EFUSE HAL module. +******************************************************************************/ + +#ifndef __HAL_EFUSE_H__ +#define __HAL_EFUSE_H__ + +#include "hal.h" + +#define EFUSE_1US_TIMES 1000 + +/** @defgroup EFUSE FLAG + * @{ + */ + +#define EFUSE_PREREAD_FLAG EFUSE_SR_PREREAD_DONE +#define EFUSE_UNPG_FLAG EFUSE_SR_UNPG +#define EFUSE_DONE_FLAG EFUSE_SR_DONE + +/** + * @} + */ + +/** @defgroup EFUSE MODE + * @{ + */ + + +#define EFUSE_RBYTE (0U << EFUSE_CTRL_MODE_Pos) +#define EFUSE_WBYTE (1U << EFUSE_CTRL_MODE_Pos) + +/** + * @} + */ + + +/** @defgroup EFUSE Private Macros + * @{ + */ + +#define IS_EFUSE_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == EFUSE1) || ((__INSTANCE__) == EFUSE2)) + +#define IS_EFUSE_BYTE_ADDR(__ADDR__) ((__ADDR__ )< 0x100) + +#define IS_EFUSE_BIT_ADDR(__ADDR__) ((__ADDR__)<0x800) + +#define IS_EFUSE_FLAG(__FLAG__) ((__FLAG__) == EFUSE_PREREAD_FLAG || \ + (__FLAG__) == EFUSE_UNPG_FLAG || \ + (__FLAG__) == EFUSE_DONE_FLAG ) + +#define IS_EFUSE_CLR_FLAG(__FLAG__) ((__FLAG__) == EFUSE_UNPG_FLAG || \ + (__FLAG__) == EFUSE_DONE_FLAG ) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/* HAL_EFUSE_Init */ +HAL_StatusTypeDef HAL_EFUSE_Init(EFUSE_TypeDef *EFUSEx); + +/* HAL_EFUSE_DeInit */ +void HAL_EFUSE_DeInit(EFUSE_TypeDef *EFUSEx); + +HAL_StatusTypeDef HAL_EFUSE_ReadByte(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t* data,uint32_t timeout); +HAL_StatusTypeDef HAL_EFUSE_ReadBytes(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t* data,uint32_t len,uint32_t timeout); +HAL_StatusTypeDef HAL_EFUSE_WriteByte(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t data,uint32_t timeout); +HAL_StatusTypeDef HAL_EFUSE_WriteBytes(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t* data,uint32_t len,uint32_t timeout); + +void HAL_EFUSE_ReadDsr(EFUSE_TypeDef *EFUSEx,uint8_t str_addr,uint8_t len,uint8_t* data); +void HAL_EFUSE_RpEnable(EFUSE_TypeDef *EFUSEx); +void HAL_EFUSE_ByteWpEnable(EFUSE_TypeDef *EFUSEx); +void HAL_EFUSE_WpEnable(EFUSE_TypeDef *EFUSEx); + +FlagStatus HAL_EFUSE_GetState(EFUSE_TypeDef *EFUSEx, uint32_t flag); +void HAL_EFUSE_ClrState(EFUSE_TypeDef *EFUSEx, uint32_t flag); + +void HAL_EFUSE_PowerUpSpTimeCfg(EFUSE_TypeDef *EFUSEx, uint32_t us); +void HAL_EFUSE_PowerDownHdCfg(EFUSE_TypeDef *EFUSEx, uint32_t us); +void HAL_EFUSE_ProWaitTimeCfg(EFUSE_TypeDef *EFUSEx, uint32_t us); +void HAL_EFUSE_ProTimeCfg(EFUSE_TypeDef *EFUSEx, uint32_t us); +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_eth.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_eth.h new file mode 100644 index 0000000000000000000000000000000000000000..f526e026e275013f2eaaa69a38b4e98facd8c009 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_eth.h @@ -0,0 +1,1593 @@ +/****************************************************************************** +*@file : hal_ethmac.h +*@brief : Header file of RCC HAL module. +******************************************************************************/ + + +#ifndef __HAL_ETH_H__ +#define __HAL_ETH_H__ + +#include "acm32h5xx_hal_conf.h" + + +/** @defgroup ETH_Buffs_setting ETH Buffs setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1536U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ + + +#define ETH_PTP_TIMEOUT 0xffffu +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ + HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ + HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_ETH_StateTypeDef; + + /** + * @} + */ + +/** @defgroup ETH_Error_Code ETH Error Code + * @{ + */ +#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */ +#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */ +#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ +#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ +#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */ + +/** + * @} + */ + +typedef enum +{ + ETH_MEDIA_INTERFACE_MII = 0, // MII + ETH_MEDIA_INTERFACE_RMII // RMII +}ETH_MediaInterfaceTypeDef; + +typedef enum +{ + ETH_SPEED_100M = 0, // 100M + ETH_SPEED_10M // 10M +}ETH_SpeedTypeDef; + +typedef enum +{ + ETH_MODE_FULL_DUPLEX = 0, // ȫ˫ + ETH_MODE_HALF_DUPLEX // ˫ +}ETH_ModeTypeDef; + +typedef enum +{ + ETH_DESC_LIST_MODE_RING = 0, // νṹ + ETH_DESC_LIST_MODE_LIST // ӽṹ +}ETH_DescListModeTypeDef; + +#define ETH_TX_MODE_DATA_COPY BIT0 +#define ETH_TX_MODE_TIMESTAMP BIT1 +#define ETH_TX_MODE_WAIT_TX_COMPLETE BIT2 + +/** + * + */ + +typedef struct __ETH_BufferTypeDef +{ + uint8_t *Buff; + uint32_t Len; + struct __ETH_BufferTypeDef *next; +} __attribute__((aligned(4))) ETH_BuffTypeDef; + +/** + * @brief ETH DMA Descriptors data structure definition + */ + +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + __IO uint32_t DESC4; + __IO uint32_t DESC5; + __IO uint32_t DESC6; + __IO uint32_t DESC7; + __IO uint32_t Buff1; + __IO uint32_t Buff2; +} __attribute__((aligned(4))) ETH_DMADescTypeDef; + + +/** + * @brief DMA Transmit Descriptors Wrapper structure definition + */ +typedef struct +{ + ETH_DMADescTypeDef *TxDescTab; /*Instance->MACIMR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACIMR &( __INTERRUPT__)) == ( __INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval The state of ETHERNET MAC flag. + */ +#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) + +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +//#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR =(__FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. +* @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) + + + + + +#define IS_ETH_SOURCE_ADDR_CONTROL(para) (((para) == ETH_SOURCE_ADDRESS_DISABLE) || \ + ((para) == ETH_SOURCE_ADDRESS_INSERT_ADDR0) || \ + ((para) == ETH_SOURCE_ADDRESS_INSERT_ADDR1) || \ + ((para) == ETH_SOURCE_ADDRESS_REPLACE_ADDR0) || \ + ((para) == ETH_SOURCE_ADDRESS_REPLACE_ADDR1)) + +#define IS_ETH_INTERFRAME_GAP(para) (((para) == ETH_INTERFRAME_GAP_96BIT) || \ + ((para) == ETH_INTERFRAME_GAP_88BIT) || \ + ((para) == ETH_INTERFRAME_GAP_80BIT) || \ + ((para) == ETH_INTERFRAME_GAP_72BIT) || \ + ((para) == ETH_INTERFRAME_GAP_64BIT) || \ + ((para) == ETH_INTERFRAME_GAP_56BIT) || \ + ((para) == ETH_INTERFRAME_GAP_48BIT) || \ + ((para) == ETH_INTERFRAME_GAP_40BIT)) + +#define IS_ETH_SPEED(para) (((para) == ETH_SPEED_10M) || \ + ((para) == ETH_SPEED_100M)) + +#define IS_ETH_DUPLEX_MODE(para) (((para) == ETH_MODE_FULL_DUPLEX) || \ + ((para) == ETH_MODE_HALF_DUPLEX)) + +#define IS_ETH_MAC_SPEED(para) (((para) == ETH_MAC_SPEED_10M) || \ + ((para) == ETH_MAC_SPEED_100M)) + +#define IS_ETH_MODE(para) (((para) == ETH_MODE_HALF_DUPLEX) || \ + ((para) == ETH_MODE_FULL_DUPLEX)) + +#define IS_ETH_BACK_OFF_LIMIT(para) (((para) == ETH_BACK_OFF_LIMIT_10) || \ + ((para) == ETH_BACK_OFF_LIMIT_8) || \ + ((para) == ETH_BACK_OFF_LIMIT_4) || \ + ((para) == ETH_BACK_OFF_LIMIT_1)) + +#define IS_ETH_PREAMBLE_LEN(para) (((para) == ETH_PREAMBLE_LEN_7B) || \ + ((para) == ETH_PREAMBLE_LEN_5B) || \ + ((para) == ETH_PREAMBLE_LEN_3B)) + +#define IS_ETH_PASS_CONTROL_PACKETS(para) (((para) == ETH_PASS_CONTROL_BLOCK_ALL) || \ + ((para) == ETH_PASS_CONTROL_FORWARD_ALL_EXCEPT_PAUSE_FRAME) || \ + ((para) == ETH_PASS_CONTROL_FORWARD_ALL) || \ + ((para) == ETH_PASS_CONTROL_FORWARD_PASSED_ADDR_FILTER)) + +#define IS_ETH_PAUSE_TIME(para) ((para) <= 0xFFFFUL) + +#define IS_ETH_PAUSE_LOW_THRESHOLD(para) (((para) == ETH_PAUSE_LOW_THRESHOLD_MINUS_4) || \ + ((para) == ETH_PAUSE_LOW_THRESHOLD_MINUS_28) || \ + ((para) == ETH_PAUSE_LOW_THRESHOLD_MINUS_144) || \ + ((para) == ETH_PAUSE_LOW_THRESHOLD_MINUS_256)) + +#define IS_ETH_VLAN_TAG(para) ((para) <= 0x0000FFFFUL) + + +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(para) (((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_64BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_128BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_192BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_256BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_40BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_32BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_24BYTES) || \ + ((para) == ETH_TRANSMIT_THRESHOLD_CONTROL_16BYTES)) + +#define IS_ETH_RECEIVED_THRESHOLD_CONTROL(para) (((para) == ETH_RECEIVED_THRESHOLD_CONTROL_64BYTES) || \ + ((para) == ETH_RECEIVED_THRESHOLD_CONTROL_32BYTES) || \ + ((para) == ETH_RECEIVED_THRESHOLD_CONTROL_96BYTES) || \ + ((para) == ETH_RECEIVED_THRESHOLD_CONTROL_128BYTES)) + +#define IS_ETH_RX_DMA_BURST_LEN(para) (((para) == ETH_RX_DMA_BURST_LEN_1BEAT) || \ + ((para) == ETH_RX_DMA_BURST_LEN_2BEAT) || \ + ((para) == ETH_RX_DMA_BURST_LEN_4BEAT) || \ + ((para) == ETH_RX_DMA_BURST_LEN_8BEAT) || \ + ((para) == ETH_RX_DMA_BURST_LEN_16BEAT) || \ + ((para) == ETH_RX_DMA_BURST_LEN_32BEAT)) + +#define IS_ETH_RX_TX_PRIORITY_RATIO(para) (((para) == ETH_RX_TX_PRIORITY_RATIO_1_1) || \ + ((para) == ETH_RX_TX_PRIORITY_RATIO_2_1) || \ + ((para) == ETH_RX_TX_PRIORITY_RATIO_3_1) || \ + ((para) == ETH_RX_TX_PRIORITY_RATIO_4_1)) + +#define IS_ETH_TX_DMA_BURST_LEN(para) (((para) == ETH_TX_DMA_BURST_LEN_1BEAT) || \ + ((para) == ETH_TX_DMA_BURST_LEN_2BEAT) || \ + ((para) == ETH_TX_DMA_BURST_LEN_4BEAT) || \ + ((para) == ETH_TX_DMA_BURST_LEN_8BEAT) || \ + ((para) == ETH_TX_DMA_BURST_LEN_16BEAT) || \ + ((para) == ETH_TX_DMA_BURST_LEN_32BEAT)) + +#define IS_ETH_DESCRIPTOR_SKIP_LEN(para) ((para) <= 31U) + +#define IS_ETH_DMA_ARBITRATION(para) (((para) == ETH_DMA_ARBITRATION_ROUNDROBIN) || \ + ((para) == ETH_DMA_ARBITRATION_RX_PRIOR_TX)) + + + + + +#define IS_ETH_ADDR_FILTER_GROUP_MASK(para) (((para) & ~(ETH_MACA1HR_MBC >> ETH_MACA1HR_MBC_Pos)) == 0) + +#define IS_ETH_VLAN_HASH_TABLE(para) ((para) <= 0xFFFFU) + +#define IS_ETH_VLAN_MODE(para) (((para) == ETH_VLAN_MODE_NONE) || \ + ((para) == ETH_VLAN_MODE_DELETE) || \ + ((para) == ETH_VLAN_MODE_INSERT) || \ + ((para) == ETH_VLAN_MODE_REPLACE)) + +#define IS_ETH_IPV6_ADDR_MASK(para) ((para) <= 127U) + +#define IS_ETH_IPV4_SOUR_ADDR_MASK(para) ((para) <= 31U) + +#define IS_ETH_IPV4_DEST_ADDR_MASK(para) ((para) <= 31U) + +#define IS_ETH_SOUR_PORT(para) ((para) <= 0xFFFFU) + +#define IS_ETH_DEST_PORT(para) ((para) <= 0xFFFFU) + + + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitDefaultParamter(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitSpeedDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetSpeedConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetSpeedConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetSpeedDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitDuplexModeDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetDuplexModeConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetDuplexModeConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetDuplexModeDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitMACAddrDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetMACAddrConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetMACAddrConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetMACAddrDefaultConfig(ETH_HandleTypeDef *heth); + + +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeupIRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_LPISendEntryCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_LPISendExitCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_LPIRecvEntryCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_LPIRecvExitCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeupCallback(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_GetTxBuff(ETH_HandleTypeDef *heth, ETH_BuffTypeDef **buff); +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_BuffTypeDef *buff, uint32_t mode, ETH_TxStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_ETH_Receive(ETH_HandleTypeDef *heth, ETH_BuffTypeDef **buff, ETH_RxStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_ETH_ReleaseRxDescriptors(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitAddrFilterDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetAddrFilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetAddrFilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetAddrFilterDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitVLANFilterDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetVLANFilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetVLANFilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetVLANFilterDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitL3L4FilterDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetL3L4FilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetL3L4FilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetL3L4FilterDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitFilterDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetFilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetFilterConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetFilterDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitVLANDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetVLANConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetVLANConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetVLANDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitMACDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetMACDefaultConfig(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitDMADefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetDMADefaultConfig(ETH_HandleTypeDef *heth); + +uint32_t HAL_ETH_GetFlowCtrlStatus(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_RecvFlowCtrlEnable(ETH_HandleTypeDef *heth, uint32_t pausetime); +HAL_StatusTypeDef HAL_ETH_RecvFlowCtrlDisable(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SendFlowCtrlEnable(ETH_HandleTypeDef *heth, uint32_t unicast_pause_frame_detect); +HAL_StatusTypeDef HAL_ETH_SendFlowCtrlDisable(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetBackPressureStatus(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_BackPressureEnable(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_BackPressureDisable(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitMMCDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetMMCCounter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetMMCConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetMMCConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetMMCDefaultConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_MMCFreezeCounter(ETH_HandleTypeDef *heth, FunctionalState cmd); +HAL_StatusTypeDef HAL_ETH_MMCResetCounter(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitLPIDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetLPIConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetLPIConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetLPIDefaultConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_EnterLPIMode(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ExitLPIMode(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_InitPMTDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetPMTConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetPMTConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetPMTDefaultConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, uint32_t WakeupMode, uint32_t WakeupFrameEnable, uint32_t MagicPacketEnable); + +HAL_StatusTypeDef HAL_ETH_InitPTPDefaultParamter(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetPTPConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetPTPConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetPTPDefaultConfig(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTPStart(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTPStop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTPAdjFreq(ETH_HandleTypeDef *heth, int32_t freq); +HAL_StatusTypeDef HAL_ETH_PTPUpdateOffset(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTPTimeSetTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTPGetSystemTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTPGetTargetTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTPSetTargetTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTPGetAuxiliaryTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp); +uint32_t HAL_ETH_PTPGetAuxiTimeStatus(ETH_HandleTypeDef *heth, ETH_PTPAuxiTimeStatusTypeDef *status); + + + +HAL_StatusTypeDef HAL_ETH_ConfigSMI(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *RegValue); +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); + +HAL_StatusTypeDef HAL_ETH_RxClockDelayConfig(ETH_HandleTypeDef *heth, uint32_t uint, uint32_t len); + + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_exti.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_exti.h new file mode 100644 index 0000000000000000000000000000000000000000..81e8655ce59ba13c9b159d9721ed156930f750e3 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_exti.h @@ -0,0 +1,174 @@ +/****************************************************************************** +*@file : hal_exti.h +*@brief : Header file of EXTI HAL module. +******************************************************************************/ + +#ifndef __HAL_EXTI_H__ +#define __HAL_EXTI_H__ + +#include "hal.h" +#include "hal_gpio.h" + + +/** @defgroup EXTI_Line + * @brief When line is 0-15, its definition is the same as GPIO_pins + * @{ + */ + +#define EXTI_LINE_0 ( 0U ) +#define EXTI_LINE_1 ( 1U ) +#define EXTI_LINE_2 ( 2U ) +#define EXTI_LINE_3 ( 3U ) +#define EXTI_LINE_4 ( 4U ) +#define EXTI_LINE_5 ( 5U ) +#define EXTI_LINE_6 ( 6U ) +#define EXTI_LINE_7 ( 7U ) +#define EXTI_LINE_8 ( 8U ) +#define EXTI_LINE_9 ( 9U ) +#define EXTI_LINE_10 ( 10U ) +#define EXTI_LINE_11 ( 11U ) +#define EXTI_LINE_12 ( 12U ) +#define EXTI_LINE_13 ( 13U ) +#define EXTI_LINE_14 ( 14U ) +#define EXTI_LINE_15 ( 15U ) +#define EXTI_LINE_LVD ( 16U ) +#define EXTI_LINE_RTC ( 17U ) +#define EXTI_LINE_IWDT ( 18U ) +#define EXTI_LINE_COMP1 ( 19U ) +#define EXTI_LINE_COMP2 ( 20U ) +#define EXTI_LINE_COMP3 ( 21U ) +#define EXTI_LINE_COMP4 ( 22U ) +#define EXTI_LINE_USB1 ( 23U ) +#define EXTI_LINE_USB2 ( 24U ) +#define EXTI_LINE_LPTIM1 ( 25U ) +#define EXTI_LINE_LPTIM2 ( 26U ) +#define EXTI_LINE_LPTIM3 ( 27U ) +#define EXTI_LINE_LPTIM4 ( 28U ) +#define EXTI_LINE_LPTIM5 ( 29U ) +#define EXTI_LINE_LPTIM6 ( 30U ) +#define EXTI_LINE_LPUART1 ( 31U ) +#define EXTI_LINE_LPUART2 ( 32U ) +#define EXTI_LINE_ETH_WAKEUP ( 33U ) +#define EXTI_LINE_TKEY ( 34U ) + + +/** + * @} + */ + +/** @brief PIN mask for assert test + */ + +#define EXTI_ALL_LINE_MASK ( 0x003FFFFFU ) /* PIN mask for assert test */ +#define EXTI_GPIO_LINE_MASK ( 0x0000FFFFU ) /* PIN mask */ +#define EXTI_GPIOA_LINE_MASK ( 0x0000FF3FU ) /* PIN mask for assert test */ +#define EXTI_GPIOB_LINE_MASK ( 0x000000FFU ) /* PIN mask for assert test */ +#define EXTI_GPIOC_LINE_MASK ( 0x0000E1FFU ) /* PIN mask for assert test */ + +/** @defgroup EXTI_Mode + * @brief its definition is the same as that of GPIO_MODE_IT_RISINGGPIO_MODE_IT_FALLING + * GPIO_MODE_IT_RISING_FALLINGGPIO_MODE_EVT_RISINGGPIO_MODE_EVT_RISING + * GPIO_MODE_EVT_RISING in GPIO_Mode + * @{ + */ + +#define EXTI_MODE_IT_RISING ( 0x10110000U ) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define EXTI_MODE_IT_FALLING ( 0x10210000U ) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define EXTI_MODE_IT_RISING_FALLING ( 0x10310000U ) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define EXTI_MODE_EVT_RISING ( 0x10120000U ) /*!< External Event Mode with Rising edge trigger detection */ +#define EXTI_MODE_EVT_FALLING ( 0x10220000U ) /*!< External Event Mode with Falling edge trigger detection */ +#define EXTI_MODE_EVT_RISING_FALLING ( 0x10320000U ) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ + +#define EXTI_GPIOA ( 0U ) +#define EXTI_GPIOB ( 1U ) +#define EXTI_GPIOC ( 2U ) +#define EXTI_GPIOD ( 3U ) +#define EXTI_GPIOE ( 4U ) +#define EXTI_GPIOF ( 5U ) +#define EXTI_GPIOG ( 6U ) +#define EXTI_GPIOH ( 7U ) +#define EXTI_GPIOI ( 8U ) +#define EXTI_GPIOJ ( 9U ) +#define EXTI_GPIOK ( 10U ) +#define EXTI_GPIOL ( 11U ) +#define EXTI_GPIOM ( 12U ) +#define EXTI_GPION ( 13U ) +#define EXTI_GPIOO ( 14U ) +#define EXTI_GPIOP ( 15U ) +#define EXTI_GPIOQ ( 16U ) + +/** + * @} + */ + + + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t u32_Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t u32_Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t u32_GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +}EXTI_HandleTypeDef; + + +/** @defgroup EXTI Private Macros + * @{ + */ + +#define IS_EXTI_GPIO(__GPIO__) (((__GPIO__) == GPIOA) || ((__GPIO__) == GPIOB) || \ + ((__GPIO__) == GPIOC) || ((__GPIO__) == GPIOD) || \ + ((__GPIO__) == GPIOE) || ((__GPIO__) == GPIOF) || \ + ((__GPIO__) == GPIOG) || ((__GPIO__) == GPIOH) || \ + ((__GPIO__) == GPIOI) || ((__GPIO__) == GPIOJ) || \ + ((__GPIO__) == GPIOK) || ((__GPIO__) == GPIOL) || \ + ((__GPIO__) == GPIOM) || ((__GPIO__) == GPION) || \ + ((__GPIO__) == GPIOO) || ((__GPIO__) == GPIOP) || \ + ((__GPIO__) == GPIOQ)) + +#define IS_EXTI_SINGLE_GPIO_LINE(__LINE__) ((__LINE__) <= EXTI_LINE_15) + +#define IS_EXTI_SINGLE_LINE(__LINE__) ((__LINE__) <= EXTI_LINE_TKEY) + +#define IS_EXTI_MODE(__MODE__) (((__MODE__) == EXTI_MODE_IT_RISING) || \ + ((__MODE__) == EXTI_MODE_IT_FALLING) || \ + ((__MODE__) == EXTI_MODE_IT_RISING_FALLING) || \ + ((__MODE__) == EXTI_MODE_EVT_RISING) || \ + ((__MODE__) == EXTI_MODE_EVT_FALLING) || \ + ((__MODE__) == EXTI_MODE_EVT_RISING_FALLING)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_EXTI_IRQHandler(uint32_t Line); +void HAL_EXTI_LineCallback(uint32_t Line); +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(GPIO_TypeDef *GPIOx, uint32_t Line, uint32_t Mode); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(uint32_t Line); +FunctionalState HAL_EXTI_IsConfigLine(GPIO_TypeDef *GPIOx, uint32_t Line); +void HAL_EXTI_GenerateSWI(uint32_t Line); +FlagStatus HAL_EXTI_GetPending(uint32_t Line); +void HAL_EXTI_ClearPending(uint32_t Line); +void HAL_EXTI_ClearAllPending(void); + + + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_fdcan.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_fdcan.h new file mode 100644 index 0000000000000000000000000000000000000000..ad19ebeb7a14a27e32ec87408a872ecde82e26e5 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_fdcan.h @@ -0,0 +1,930 @@ +#ifndef __HAL_FDCAN_H__ +#define __HAL_FDCAN_H__ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "acm32h5xx_hal_conf.h" + +typedef enum +{ + HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ + HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ + HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ + HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ +} HAL_FDCAN_StateTypeDef; + +/** + * @brief FDCAN Init structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the FDCAN mode. + This parameter can be a value of @ref FDCAN_operating_mode */ + + uint32_t FrameISOType; /*!< Specifies the FDCAN frame ISO Type. + This parameter can be a value of @ref FDCAN_frame_ISOType */ + + uint32_t RxBufOverFlowMode; /*!< Specifies the FDCAN Receive buffer Overflow Mode. + This parameter can be a value of @ref FDCAN_Rx_FIFO_operation_mode. */ + FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the nominal bit time quanta. */ + + uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a bit to perform + resynchronization. */ + + uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. */ + + uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. */ + + uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the data bit time quanta. */ + + uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a data bit to + perform resynchronization. */ + + uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. */ + + uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. */ + +} FDCAN_InitTypeDef; + + +/** + * @brief FDCAN filter structure definition + */ +typedef struct +{ + uint32_t IdType; /*!< Specifies the identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. + This parameter must be a number less than NR_OF_ACF - 1 */ + uint32_t FilerMask; + + uint32_t FilerCode; + + uint32_t FilterType; /*!< Specifies the filter type. + This parameter can be a value of @ref FDCAN_filter_type. + The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted + only when IdType is FDCAN_EXTENDED_ID. + This parameter is ignored if FilterConfig is set to + FDCAN_FILTER_TO_RXBUFFER */ +} FDCAN_FilterTypeDef; + + +typedef enum +{ + FDCAN_FILTER_TYPE0 = 0, + FDCAN_FILTER_TYPE1, + FDCAN_FILTER_TYPE2, + FDCAN_FILTER_TYPE3, +}FDCAN_Filter_enum; + +typedef union +{ + struct + { + uint32_t r0:1; + uint32_t RTR:1; + uint32_t IDE:1; + uint32_t EXTID0_17:18; + uint32_t id:11; + }b; + + struct + { + uint32_t r0:1; + uint32_t RTR:1; + uint32_t IDE:1; + uint32_t id:29; + }ext; + + uint32_t w; +}FDCAN_Filter32_Map_u; + +typedef union +{ + struct + { + uint16_t EXTID15_17:3; + uint16_t IDE:1; + uint16_t RTR:1; + uint16_t id:11; + }b; + uint16_t hw; +}FDCAN_Filter16_Map_u; + +typedef union +{ + struct + { + FDCAN_Filter32_Map_u code32; //acode; + FDCAN_Filter32_Map_u mask32; //amask; + }type0; + + struct + { + FDCAN_Filter32_Map_u code32; + FDCAN_Filter32_Map_u code32_2; + }type1; + + struct + { + FDCAN_Filter16_Map_u code16; + FDCAN_Filter16_Map_u mask16; + FDCAN_Filter16_Map_u code16_2; + FDCAN_Filter16_Map_u mask16_2; + }type2; + + struct + { + FDCAN_Filter16_Map_u code16; + FDCAN_Filter16_Map_u code16_2; + FDCAN_Filter16_Map_u code16_3; + FDCAN_Filter16_Map_u code16_4; + }type3; + +}FDCAN_Filter_u; + +typedef struct +{ + uint32_t FilterIndex; + FDCAN_Filter_enum FilterType; + FDCAN_Filter_u Filter; + +}FDCAN_NewFilterTypeDef; + + +typedef union +{ + struct{ + __IO uint32_t ID:29; + __IO uint32_t RSV:2; + __IO uint32_t TTSEN:1; + }b; + __IO uint32_t w; +}FDCAN_TX_ID_u; + +typedef union +{ + struct{ + __IO uint32_t DLC:4; + __IO uint32_t BRS:1; + __IO uint32_t FDF:1; + __IO uint32_t RTR:1; + __IO uint32_t IDE:1; + __IO uint32_t RSV0:8; + __IO uint32_t RSV1:8; + __IO uint32_t RSV2:8; + + }b; + __IO uint32_t w; +}FDCAN_TX_FrameInfo_u; + + +typedef union +{ + struct{ + __IO uint32_t ID:29; + __IO uint32_t RSV:2; + __IO uint32_t ESI:1; //error state indicator + }b; + __IO uint32_t w; +}FDCAN_RX_ID_u; + + +typedef union +{ + struct{ + __IO uint32_t DLC:4; + __IO uint32_t BRS:1; + __IO uint32_t FDF:1; + __IO uint32_t RTR:1; + __IO uint32_t IDE:1; + __IO uint32_t RSV0:4; + __IO uint32_t TX:1; + __IO uint32_t KOER:3; + __IO uint32_t CycleTime:16; + }b; + __IO uint32_t w; +}FDCAN_RX_FrameInfo_u; + + +typedef fdcan_ecc_u FDCAN_ErrorInfo_u; + +/** + * @brief FDCAN Tx header structure definition + */ +typedef struct +{ + FDCAN_TX_ID_u ID; + + FDCAN_TX_FrameInfo_u FrameInfo; + +} FDCAN_TxHeaderTypeDef; + +/** + * @brief FDCAN Rx header structure definition + */ +typedef struct +{ + FDCAN_RX_ID_u ID; + + FDCAN_RX_FrameInfo_u FrameInfo; + + uint32_t RxTimestampLow; + + uint32_t RxTimestampHigh; + +} FDCAN_RxHeaderTypeDef; + + +typedef struct{ + uint32_t tts_h; + uint32_t tts_l; +}FDCAN_TTSTypeDef; + +/** + * @brief FDCAN Trigger structure definition + */ +typedef struct +{ +// uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. +// This parameter must be a number between 0 and 63 */ + + uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. + This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ + + uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. + This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + This parameter must be a number between 0 and RepeatFactor */ + + uint32_t TriggerType; /*!< Specifies the trigger type. + This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ + + uint32_t TTPtr; /*!< Specifies the index of the Tx buffer for which the trigger is valid. + This parameter can be a value of @ref FDCAN_Tx_location. + This parameter is taken in consideration only if the trigger is configured for + transmission. */ + + uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. + This parameter is taken in consideration only if the trigger is configured for + reception. + This parameter must be a number between: + - 0 and 127, if FilterType is FDCAN_STANDARD_ID + - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ + + uint32_t TxEnWindow; /* transmit enalbe window */ + +} FDCAN_TriggerTypeDef; + + +/** + * @brief FDCAN handle structure definition + */ +typedef struct __FDCAN_HandleTypeDef +{ + FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ + +// TTCAN_TypeDef *ttcan; /*!< TT register base address */ + + FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ + +// FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ + + uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index + of latest Tx FIFO/Queue request */ + + __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ + + HAL_LockTypeDef Lock; /*!< FDCAN locking object */ + + __IO uint32_t ErrorCode; /*!< FDCAN Error code */ + + __IO FDCAN_ErrorInfo_u CANErrorInfo; + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */ + void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ + void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ + void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ + void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ + void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ + void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ + void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Rx Buffer New Message callback */ + void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ + void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ + void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ + void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ + void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ + void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */ + void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< FDCAN TT Time Mark callback */ + void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback */ + void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< FDCAN TT Global Time callback */ + + void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ + void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ +#endif + +} FDCAN_HandleTypeDef; + + +/* Transmition buffer type enum */ +typedef enum { + FDCAN_TRANSMIT_PTB = 0, + FDCAN_TRANSMIT_STB_ONE = 1, + FDCAN_TRANSMIT_STB_ALL = 2 +}TransmitType_enum; + +typedef enum { + FDCAN_ABORT_PTB = 0, + FDCAN_ABORT_STB = 1, +}TransmitAbortType_enum; + + +typedef enum { + FDCAN_RXBUF_EMPTY = 0, + FDCAN_RXBUF_LESS_AFWL = 1, + FDCAN_RXBUF_AFWL = 2, + FDCAN_RXBUF_FULL = 3, + FDCAN_RXBUF_OV, +}FDCAN_RXBUF_FILL_STATE_enum; + +typedef enum { + FDCAN_TXBUF_EMPTY = 0, + FDCAN_TXBUF_HALF_LESSHF = 1, + FDCAN_TXBUF_MORE_HALF = 2, + FDCAN_TXBUF_FULL = 3, +}FDCAN_TXBUF_FILL_STATE_enum; + +typedef enum +{ + FDCAN_MAC_NONE_ERR = 0, + FDCAN_MAC_BIT_ERR, + FDCAN_MAC_FORM_ERR, + FDCAN_MAC_STUFF_ERR, + FDCAN_MAC_ACK_ERR, + FDCAN_MAC_CRC_ERR, + FDCAN_MAC_OTHER_ERRS +}FDCAN_MAC_ERR_enum; + + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL FDCAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ + HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */ + HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */ + HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */ + HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */ + HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */ + + HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */ + HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */ + +} HAL_FDCAN_CallbackIDTypeDef; + +/** + * @brief HAL FDCAN Callback pointer definition + */ +typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ +typedef void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< pointer to Clock Calibration FDCAN callback function */ +typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ +typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ +typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ +typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ +typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ +typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ +typedef void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< pointer to TT Schedule Synchronization FDCAN callback function */ +typedef void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< pointer to TT Time Mark FDCAN callback function */ +typedef void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function */ +typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< pointer to TT Global Time FDCAN callback function */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants + * @{ + */ + +#define NR_OF_ACF (16) + +/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code + * @{ + */ +#define ERR_FDCAN_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ +#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ +#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ +#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ +#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ +#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ +#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ +#define ERR_FDCAN_RXBUF_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ +#define ERR_FDCAN_TXBUF_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define ERR_FDCAN_TBSLOT_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define ERR_FDCAN_PTB_LOCKED ((uint32_t)0x00000400U) +#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ +#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ +#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ +#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ +#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ +#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ +#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ +#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ +#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ +#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ +#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ +#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ +#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ +#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_format FDCAN Frame Format + * @{ + */ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_ISOType FDCAN Frame ISO Type + * @{ + */ +#define FDCAN_FRAME_ISO (FDCAN_CR_FD_ISO) +#define FDCAN_FRAME_NONISO (0) +/** + * @} + */ + +#define FDCAN_TIMESTAMP_DISABLE (0) +#define FDCAN_TIMESTAMP_ENABLE (1) + + +/** @defgroup FDCAN_operating_mode FDCAN Operating Mode + * @{ + */ + +#define FDCAN_MODE_NORMAL (0) /*!< Normal mode */ +#define FDCAN_MODE_LOM (FDCAN_CR_LOM) /*!< Listen only Mode. same as bus monitoring mode */ +#define FDCAN_MODE_LBMI (FDCAN_CR_LBMI) /*!< LoopBack mode internal */ +#define FDCAN_MODE_LBME (FDCAN_CR_LBME) /*!< LoopBack mode External */ +#define FDCAN_MODE_LBME_SACK (FDCAN_CR_LBME | FDCAN_CR_SACK) /*!< LoopBack mode External with self-ACK */ +#define FDCAN_MODE_LOM_LBME (FDCAN_CR_LOM | FDCAN_CR_LBME) /*!< Listen only mode combined LBME */ +#define FDCAN_MODE_LOM_LBME_SACK (FDCAN_CR_LOM | FDCAN_MODE_LBME_SACK) /*!< Listen only mode combined LBME with self-ACK */ + + +/** + * @} + */ + + +/** @defgroup FDCAN_id_type FDCAN ID Type + * @{ + */ +#define FDCAN_STANDARD_ID ((uint32_t)0) /*!< Standard ID element */ +#define FDCAN_EXTENDED_ID ((uint32_t)1) /*!< Extended ID element */ +#define FDCAN_BOTH_ID ((uint32_t)2) /*!< Extended ID element */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_type FDCAN Frame Type + * @{ + */ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ +#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup FDCAN_data_length_code FDCAN Data Length Code + * @{ + */ +#define FDCAN_DLC_BYTES_0 (0x0) /*!< 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 (0x1) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 (0x2) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 (0x3) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 (0x4) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 (0x5) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 (0x6) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 (0x7) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 (0x8) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 (0x9) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 (0xA) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 (0xB) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 (0xC) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 (0xD) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 (0xE) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 (0xF) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator + * @{ + */ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ +#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ +/** + * @} + */ + + +/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code + * @{ + */ +#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ +#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ +#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ +#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ +#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ +#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ +#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ +#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ +/** + * @} + */ + +/** @defgroup FDCAN_communication_state FDCAN communication state + * @{ + */ +#define FDCAN_BUS_IDLE ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ +#define FDCAN_BUS_RACTIVE ((uint32_t)0x00000004U) /*!< Node is neither receiver nor transmitter */ +#define FDCAN_BUS_TACTIVE ((uint32_t)0x00000002U) /*!< Node is operating as receiver */ +#define FDCAN_BUS_OFF ((uint32_t)0x00000001U) /*!< Node is operating as transmitter */ +/** + * @} + */ + + +/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode + * @{ + */ +#define FDCAN_RX_BUF_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ +#define FDCAN_RX_BUF_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */ +/** + * @} + */ + + +/** @defgroup tt_presc_selection TTCAN Timer PRESCaler + * @{ + */ +#define FDCAN_TT_TPRESC_1 ((uint32_t)0x00000000U) +#define FDCAN_TT_TPRESC_2 ((uint32_t)0x00000001U) +#define FDCAN_TT_TPRESC_4 ((uint32_t)0x00000002U) +#define FDCAN_TT_TPRESC_8 ((uint32_t)0x00000003U) +#define IS_FDCAN_TT_TPRESC(PRESC) (((PRESC) == FDCAN_TT_TPRESC_1) || \ + ((PRESC) == FDCAN_TT_TPRESC_2) || \ + ((PRESC) == FDCAN_TT_TPRESC_4) || \ + ((PRESC) == FDCAN_TT_TPRESC_8)) + +#define FDCAN_TT_TX_IMMEDIATE_TRIGGER ((uint32_t)0x00000000U) /*!< For immediate transmission */ +#define FDCAN_TT_RX_TIME_TRIGGER ((uint32_t)0x00000001U) /*!< For receive triggers */ +#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< For exclusive time windows */ +#define FDCAN_TT_TX_TRIGGER_MERGED_START ((uint32_t)0x00000003U) /*!< For merged arbitrating time windows */ +#define FDCAN_TT_TX_TRIGGER_MERGED_STOP ((uint32_t)0x00000004U) /*!< For merged arbitrating time windows */ +#define FDCAN_TT_TRIGGER_NOCATION ((uint32_t)0x00000005U) /*!< For merged arbitrating time windows */ +//#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ +#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_IMMEDIATE_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_RX_TIME_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED_START ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED_STOP)) + +#define FDCAN_TIMESTAMP_SOF 0 +#define FDCAN_TIMESTAMP_EOF 1 +#define IS_FDCAN_TIMESTAMP_POSITION(pos) ((pos) == FDCAN_TIMESTAMP_SOF) || ((pos) == FDCAN_TIMESTAMP_EOF) + +#define FDCAN_IR_MASK (0x2A00FE) /*!< FDCAN interrupts mask */ +#define FDCAN_ERR_IR_MASK (0x2A) /*!< FDCAN error interrupts mask */ + +#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE (FDCAN_IR_RIF ) /*!< At least one received message stored into a Rx Buffer */ +#define FDCAN_FLAG_RX_BUFFER_OVERRUN (FDCAN_IR_ROIF ) /*!< At least one received message stored into a Rx Buffer */ +#define FDCAN_FLAG_RX_BUFFER_FULL (FDCAN_IR_RFIF ) +#define FDCAN_FLAG_RX_BUFFER_ALMOSTFULL (FDCAN_IR_RAFIF ) +#define FDCAN_FLAG_TX_PTB_COMPLETE (FDCAN_IR_TPIF ) +#define FDCAN_FLAG_TX_STB_COMPLETE (FDCAN_IR_TSIF ) +#define FDCAN_FLAG_ERROR (FDCAN_IR_EIF ) +#define FDCAN_FLAG_TX_ABORT_COMPLETE (FDCAN_IR_AIF ) +#define FDCAN_FLAG_BUS_ERROR (FDCAN_IR_BEIF ) +#define FDCAN_FLAG_ARBITRATION_LOST (FDCAN_IR_ALIF ) +#define FDCAN_FLAG_ERROR_PASSIVE (FDCAN_IR_EPIF ) +#define FDCAN_FLAG_ERRPASSMD_ACTIVE (FDCAN_IR_EPASS ) +#define FDCAN_FLAG_ERRWARN_LIMIT (FDCAN_IR_EWARN ) + +#define FDCAN_IE_RX_BUFFER_NEW_MESSAGE (FDCAN_IR_RIE ) /*!< At least one received message stored into a Rx Buffer */ +#define FDCAN_IE_RX_BUFFER_OVERRUN (FDCAN_IR_ROIE ) /*!< At least one received message stored into a Rx Buffer */ +#define FDCAN_IE_RX_BUFFER_FULL (FDCAN_IR_RFIE ) +#define FDCAN_IE_RX_BUFFER_ALMOSTFULL (FDCAN_IR_RAFIE ) +#define FDCAN_IE_TX_PTB_COMPLETE (FDCAN_IR_TPIE ) +#define FDCAN_IE_TX_STB_COMPLETE (FDCAN_IR_TSIE ) +#define FDCAN_IE_ERROR (FDCAN_IR_EIE ) +#define FDCAN_IE_BUS_ERROR (FDCAN_IR_BEIE ) +#define FDCAN_IE_ARBITRATION_LOST (FDCAN_IR_ALIE ) +#define FDCAN_IE_ERROR_PASSIVE (FDCAN_IR_EPIE ) + + +#define __HAL_FDCAN_ENTER_RESET_STATE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, FDCAN_CR_RESET) +#define __HAL_FDCAN_EXIT_RESET_STATE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, FDCAN_CR_RESET) + +#define __HAL_FDCAN_DLC2LEN(DLC) ( DLC < 9 ? DLC : DLC < 13 ? 8 + (DLC - 8) * 4 : 32 + (DLC - 13) * 16 ) +#define __HAL_FDCAN_LEN2DLC(LEN) ( LEN < 9 ? LEN : LEN < 32 ? 8 + (LEN - 8) / 4 : 13 + (LEN - 32) / 16 ) + + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->IR = ((__HANDLE__)->Instance->IR & FDCAN_IR_MASK ) | (__INTERRUPT__) +#define __HAL_FDCAN_ENABLE_IT_ALL(__HANDLE__) ((__HANDLE__)->Instance->IR = FDCAN_IR_MASK) + +#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->IR &= ~((__INTERRUPT__) & FDCAN_IR_MASK) +#define __HAL_FDCAN_DISABLE_IT_ALL(__HANDLE__) ((__HANDLE__)->Instance->IR = 0) + +#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__)) +#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +do{ \ + ((__HANDLE__)->Instance->IR) = (((__HANDLE__)->Instance->IR) & (FDCAN_IR_MASK) ) | (__FLAG__); \ + }while(0) + +#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->TTCFG) = (((__HANDLE__)->Instance->TTCFG) & ~0x16800) | (__INTERRUPT__)) +#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->TTCFG) = (((__HANDLE__)->Instance->TTCFG) & ~0x16800) & (~__INTERRUPT__)) + +#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->TTCFG) & (__FLAG__)) +#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->TTCFG) = ((__HANDLE__)->Instance->TTCFG & ~0x16800) | (__FLAG__)) + +#define __HAL_FDCAN_DISABLE_ALL_FILTERS(__HANDLE__) ((__HANDLE__)->Instance->ACFCR.b.AE = 0) + + +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); +//HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); +//HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_NewConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_NewFilterTypeDef *sFilterConfig); + +HAL_StatusTypeDef HAL_FDCAN_ConfigRxBufOverwriteMode(FDCAN_HandleTypeDef *hfdcan, uint32_t OverwriteMode); +HAL_StatusTypeDef HAL_FDCAN_TransceiverEnterSTBY(FDCAN_HandleTypeDef *hfdcan); + +HAL_StatusTypeDef HAL_FDCAN_EnableTimestamp(FDCAN_HandleTypeDef *hfdcan, uint32_t ts_position); +HAL_StatusTypeDef HAL_FDCAN_DisableTimestamp(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_GetTTS(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTSTypeDef *tts); + +HAL_StatusTypeDef HAL_FDCAN_TT_EnableWatchTrigger(FDCAN_HandleTypeDef *hfdcan, uint32_t cycle_time); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableWatchTrigger(FDCAN_HandleTypeDef *hfdcan); + +uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); + +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); + +HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, TransmitType_enum type); +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, TransmitAbortType_enum type); + +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); + + +bool HAL_FDCAN_GetTxReqCompleted(FDCAN_HandleTypeDef *hfdcan, TransmitType_enum type); +HAL_StatusTypeDef HAL_FDCAN_WaitTxCompleted(FDCAN_HandleTypeDef *hfdcan, TransmitType_enum type, uint32_t timeout); +uint32_t HAL_FDCAN_GetBusStatus(FDCAN_HandleTypeDef *hfdcan); + +HAL_StatusTypeDef HAL_FDCAN_ClearEntireSTB(FDCAN_HandleTypeDef *hfdcan); + +void HAL_FDCAN_PTBTranmistSingleShot(FDCAN_HandleTypeDef *hfdcan, FunctionalState state); +void HAL_FDCAN_STBTranmistSingleShot(FDCAN_HandleTypeDef *hfdcan, FunctionalState state); + + +FDCAN_RXBUF_FILL_STATE_enum HAL_FDCAN_GetRxBufFillState(FDCAN_HandleTypeDef *hfdcan); +FDCAN_TXBUF_FILL_STATE_enum HAL_FDCAN_GetTxBufFillState(FDCAN_HandleTypeDef *hfdcan); + +HAL_StatusTypeDef HAL_FDCAN_AddMessageToSTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToPTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); + +HAL_StatusTypeDef HAL_FDCAN_EnableSTBPriorityMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableSTBPriorityMode(FDCAN_HandleTypeDef *hfdcan); + +HAL_StatusTypeDef HAL_FDCAN_TransmitMessageBySTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); +HAL_StatusTypeDef HAL_FDCAN_TransmitMessageByPTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); + + +HAL_StatusTypeDef HAL_FDCAN_ConfigRxBufWarnningLimit(FDCAN_HandleTypeDef *hfdcan, uint8_t afwl); +uint8_t HAL_FDCAN_GetRxBufWarnningLimit(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigErrCntWarnningLimit(FDCAN_HandleTypeDef *hfdcan, uint8_t ecnt); +uint8_t HAL_FDCAN_GetErrCntWarnningLimit(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_GetErrorInfo(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorInfo_u *errinfo); +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_RxBufferAFCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_RxBufferFullCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_RxBufferOVCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TXPTBCompletedCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TXSTBCompletedCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxAbortCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_BusErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorPassiveCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ArbitrationLostCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); +void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); + + +void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); +void HAL_FDCAN_TT_TimerTriggerCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_Config(FDCAN_HandleTypeDef *hfdcan, uint32_t TT_Presc); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig); +void HAL_FDCAN_TT_ImmediateTrigger(FDCAN_HandleTypeDef *hfdcan, uint8_t TTPtr); +HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_AddMessageByTBPtr(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint8_t TBPtr); +HAL_StatusTypeDef HAL_FDCAN_TT_AddMessageByTBPtr_NOTBF(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint8_t TBPtr); + + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group7 + * @{ + */ +/* Peripheral State functions *************************************************/ +uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ +#define STB_SLOTS_NUM (16) +#define IS_FDCAN_STB_SLOTS_INDEX(INDEX) ((INDEX) > 0 && INDEX <= STB_SLOTS_NUM) +#define IS_FDCAN_TT_SLOTS_INDEX(INDEX) ((INDEX) <= STB_SLOTS_NUM) + +#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \ + ((__INSTANCE__) == FDCAN2) || \ + ((__INSTANCE__) == FDCAN3)) + +#define IS_FDCAN_AFWL(AWFL) ((AWFL) < STB_SLOTS_NUM) + +#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \ + ((__INSTANCE__) == FDCAN2) || \ + ((__INSTANCE__) == FDCAN3)) + +#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ + ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ + ((FORMAT) == FDCAN_FRAME_FD_BRS )) + +#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ + ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ + ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ + ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ + ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) + +#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) +#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) +#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) +#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) +#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) +#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) +#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) +#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) +#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) +#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) +#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ + ((SIZE) == FDCAN_DATA_BYTES_12) || \ + ((SIZE) == FDCAN_DATA_BYTES_16) || \ + ((SIZE) == FDCAN_DATA_BYTES_20) || \ + ((SIZE) == FDCAN_DATA_BYTES_24) || \ + ((SIZE) == FDCAN_DATA_BYTES_32) || \ + ((SIZE) == FDCAN_DATA_BYTES_48) || \ + ((SIZE) == FDCAN_DATA_BYTES_64)) + +#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ + ((ID_TYPE) == FDCAN_EXTENDED_ID)) + +#define IS_FILTER_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ + ((ID_TYPE) == FDCAN_EXTENDED_ID) || \ + ((ID_TYPE) == FDCAN_BOTH_ID)) + +#define IS_VALID_FILTER_INDEX(FILTER_INDEX) ((FILTER_INDEX) < (NR_OF_ACF) ) + +#define IS_FDCAN_RX_BUF_MODE(MODE) (((MODE) == FDCAN_RX_BUF_BLOCKING ) || \ + ((MODE) == FDCAN_RX_BUF_OVERWRITE)) + +#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ + ((TYPE) == FDCAN_REMOTE_FRAME)) + +#define IS_FDCAN_TRANSMIT_TYPE(TYPE) (((TYPE) == FDCAN_TRANSMIT_PTB ) || \ + ((TYPE) == FDCAN_TRANSMIT_STB_ONE ) || \ + ((TYPE) == FDCAN_TRANSMIT_STB_ALL)) + +#define IS_FDCAN_ABORT_TYPE(TYPE) (((TYPE) == FDCAN_ABORT_PTB ) || \ + ((TYPE) == FDCAN_ABORT_STB)) + +#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ + ((DLC) == FDCAN_DLC_BYTES_1 ) || \ + ((DLC) == FDCAN_DLC_BYTES_2 ) || \ + ((DLC) == FDCAN_DLC_BYTES_3 ) || \ + ((DLC) == FDCAN_DLC_BYTES_4 ) || \ + ((DLC) == FDCAN_DLC_BYTES_5 ) || \ + ((DLC) == FDCAN_DLC_BYTES_6 ) || \ + ((DLC) == FDCAN_DLC_BYTES_7 ) || \ + ((DLC) == FDCAN_DLC_BYTES_8 ) || \ + ((DLC) == FDCAN_DLC_BYTES_12) || \ + ((DLC) == FDCAN_DLC_BYTES_16) || \ + ((DLC) == FDCAN_DLC_BYTES_20) || \ + ((DLC) == FDCAN_DLC_BYTES_24) || \ + ((DLC) == FDCAN_DLC_BYTES_32) || \ + ((DLC) == FDCAN_DLC_BYTES_48) || \ + ((DLC) == FDCAN_DLC_BYTES_64)) + +#ifdef __cplusplus +} +#endif + + +#endif /* __HAL_FDCAN_H__ */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_fmc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_fmc.h new file mode 100644 index 0000000000000000000000000000000000000000..e66b18a05f9ff2121543ce71f8710e06ff45f351 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_fmc.h @@ -0,0 +1,755 @@ +/* + ****************************************************************************** + * @file HAL_FMC.h + * @version V1.0.0 + * @date 2022 + * @brief Header file of FMC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_FMC_H__ +#define __HAL_FMC_H__ + +#include "hal.h" + + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, + expressed in number of HCLK cycles. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. */ + +}FMC_NORSRAMTimingInitTypeDef; +/** + * @} + */ + + +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NOR/SRAM memory bank that will be used. */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. */ + + uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. */ + + uint32_t CRAMPageSize; /*!< Specifies the CRAM page size. */ + + uint32_t WriteMode; /*!< Synchronous or asynchronous write mode. */ + +}FMC_NORSRAMInitTypeDef; +/** + * @} + */ + +/** + * @brief FMC SDRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. */ + + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. */ + + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. */ + + uint32_t MemoryDataWidth; /*!< Defines the memory device width. */ + + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. */ + + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. */ + + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. */ + + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + to disable the clock before changing frequency. */ + + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + commands during the CAS latency and stores data in the Read FIFO. */ + + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. */ + +}FMC_SDRAMInitTypeDef; +/** + * @} + */ + +/** + * @brief FMC SDRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. */ + + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. */ + + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. */ + + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. */ + + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. */ + + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. */ + + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. */ +}FMC_SDRAMTimingInitTypeDef; +/** + * @} + */ + +/** +* @brief SDRAM command parameters structure definition +*/ +typedef struct +{ + uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. */ + + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. */ + + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. */ + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ + +}FMC_SDRAMCommandTypeDef; +/** + * @} + */ + +/** @defgroup FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) +#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ + ((BANK) == FMC_NORSRAM_BANK2) || \ + ((BANK) == FMC_NORSRAM_BANK3) || \ + ((BANK) == FMC_NORSRAM_BANK4)) +/** + * @} + */ + + +/** @defgroup FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) +#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) +#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) || \ + ((MEMORY) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((MEMORY) == FMC_MEMORY_TYPE_NOR)) +/** + * @} + */ + +/** @defgroup FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) +#define IS_FMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +/** + * @} + */ + +/** @defgroup FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +/** + * @} + */ + + +/** @defgroup FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) +#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((STATE) == FMC_BURST_ACCESS_MODE_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) +#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +/** + * @} + */ + +/** @defgroup FMC Wrap Mode + * @{ + */ +#define FMC_WRAP_MODE_DISABLE (0x00000000U) +#define FMC_WRAP_MODE_ENABLE (0x00000400U) +#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) || \ + ((MODE) == FMC_WRAP_MODE_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC Wait Timing + * @{ + */ +#define FMC_WAITSIGNALACTIVE_BEFOREWAITSTATE (0x00000000U) +#define FMC_WAITSIGNALACTIVE_DURINGWAITSTATE (0x00000800U) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAITSIGNALACTIVE_BEFOREWAITSTATE) || \ + ((ACTIVE) == FMC_WAITSIGNALACTIVE_DURINGWAITSTATE)) +/** + * @} + */ + +/** @defgroup FMC Write Operation + * @{ + */ +#define FMC_WRITEOPERATION_DISABLE (0x00000000U) +#define FMC_WRITEOPERATION_ENABLE (0x00001000U) +#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITEOPERATION_DISABLE) || \ + ((OPERATION) == FMC_WRITEOPERATION_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) +#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) +#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) || \ + ((MODE) == FMC_EXTENDED_MODE_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) +#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC CRAM Page Size + * @{ + */ +#define FMC_CRAMPAGE_SIZE_AUTO (0x00000000U) +#define FMC_CRAMPPAGE_SIZE_128 (0x00010000U) +#define FMC_CRAMPPAGE_SIZE_256 (0x00020000U) +#define FMC_CRAMPPAGE_SIZE_512 (0x00030000U) +#define FMC_CRAMPPAGE_SIZE_1024 (0x00040000U) +#define IS_FMC_CRAMPPAGE_SIZE(SIZE) (((SIZE) == FMC_CRAMPAGE_SIZE_AUTO) || \ + ((SIZE) == FMC_CRAMPPAGE_SIZE_128) || \ + ((SIZE) == FMC_CRAMPPAGE_SIZE_256) || \ + ((SIZE) == FMC_CRAMPPAGE_SIZE_512) || \ + ((SIZE) == FMC_CRAMPPAGE_SIZE_1024)) +/** + * @} + */ + +/** @defgroup FMC Write Mode + * @{ + */ +#define FMC_WRITE_ASY_MODE (0x00000000U) +#define FMC_WRITE_SY_MODE (0x00080000U) +#define IS_FMC_WRITE_MODE(MODE) (((MODE) == FMC_WRITE_ASY_MODE) || \ + ((MODE) == FMC_WRITE_SY_MODE)) +/** + * @} + */ + +/** @defgroup FMC Address Setup Time + * @{ + */ +#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FMC Address Hold Time + * @{ + */ +#define IS_FMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FMC Data Setup Time + * @{ + */ +#define IS_FMC_DATASETUP_TIME(TIME) ((TIME) <= 0xFF) +/** + * @} + */ + +/** @defgroup FMC Bus Turn around Duration + * @{ + */ +#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) +/** + * @} + */ + +/** @defgroup FMC CLK Division + * @{ + */ +#define IS_FMC_CLK_DIV(DIV) ((DIV) <= 0xF) +/** + * @} + */ + +/** @defgroup FMC Data Latency + * @{ + */ +#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) +/** + * @} + */ + +/** @defgroup FMC_Access_Mode FMC Access Mode +* @{ +*/ +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) +#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) || \ + ((MODE) == FMC_ACCESS_MODE_B) || \ + ((MODE) == FMC_ACCESS_MODE_C) || \ + ((MODE) == FMC_ACCESS_MODE_D)) +/** +* @} +*/ + + + +/** @defgroup FMC SDRAM Bank + * @{ + */ +#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U) +#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U) +#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ + ((BANK) == FMC_SDRAM_BANK2)) +/** + * @} + */ + + /** @defgroup FMC SDRAM Column Bits number + * @{ + */ +#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U) +#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Row Bits number + * @{ + */ +#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U) +#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Memory Bus Width + * @{ + */ +#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Internal Banks Number + * @{ + */ +#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U) +#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) +/** + * @} + */ + +/** @defgroup FMC SDRAM CAS Latency + * @{ + */ +#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U) +#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Write Protection + * @{ + */ +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U) +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Clock Period + * @{ + */ +#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U) +#define FMC_SDRAM_CLOCK_PERIOD_4 ((uint32_t)0x00000400U) +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_4)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Read Burst + * @{ + */ +#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U) +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Read Pipe Delay + * @{ + */ +#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U) +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) +/** + * @} + */ + +/** @defgroup FMC SDRAM write to read delay + * @{ + */ +#define FMC_SDRAM_W2R_DELAY_0 ((uint32_t)0x00000000U) +#define FMC_SDRAM_W2R_DELAY_HALF_SDCLK ((uint32_t)0x00008000U) +#define IS_FMC_W2R_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_W2R_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_W2R_DELAY_HALF_SDCLK)) +/** + * @} + */ + +/** @defgroup FMC SDRAM burst read fifo length + * @{ + */ +#define FMC_SDRAM_BURST_READ_FIFO_LEN_0 ((uint32_t)0x00000000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_1 ((uint32_t)0x00010000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_2 ((uint32_t)0x00020000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_3 ((uint32_t)0x00030000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_4 ((uint32_t)0x00040000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_5 ((uint32_t)0x00050000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_6 ((uint32_t)0x00060000U) +#define FMC_SDRAM_BURST_READ_FIFO_LEN_7 ((uint32_t)0x00070000U) +#define IS_FMC_BURST_READ_FIFO_LEN(__LEN__) (((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_0) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_1) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_2) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_3) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_4) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_5) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_6) || \ + ((__LEN__) == FMC_SDRAM_BURST_READ_FIFO_LEN_7)) +/** + * @} + */ + + +/** @defgroup FMC SDRAM Command Mode + * @{ + */ +#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U) +#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U) +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) +/** + * @} + */ + +/** + * @brief FMC SDRAM Load Mode Register + */ +#define FMC_SDRAM_LOAD_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDRAM_LOAD_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDRAM_LOAD_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDRAM_LOAD_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDRAM_LOAD_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDRAM_LOAD_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDRAM_LOAD_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDRAM_LOAD_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDRAM_LOAD_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDRAM_LOAD_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDRAM_LOAD_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) +/** + * @} + */ + +/** @defgroup FMC SDRAM Command Target + * @{ + */ +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDRCMD_CTD2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDRCMD_CTD1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U) +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Mode Status + * @{ + */ +#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE ((uint32_t)0x00000001U) +#define FMC_SDRAM_POWER_DOWN_MODE ((uint32_t)0x00000002U) + + +/** @defgroup FMC SDRAM LoadToActive Delay + * @{ + */ +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM ExitSelfRefresh Delay + * @{ + */ +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM SelfRefresh Time + * @{ + */ +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM RowCycle Delay + * @{ + */ +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM Write Recovery Time + * @{ + */ +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM RP Delay + * @{ + */ +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM RCD Delay + * @{ + */ +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM AutoRefresh Number + * @{ + */ +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) +/** + * @} + */ + +/** @defgroup FMC SDRAM ModeRegister Definition + * @{ + */ +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) +/** + * @} + */ + +/** @defgroup FMC SDRAM Refresh rate + * @{ + */ +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) +/** + * @} + */ + + + + +HAL_StatusTypeDef HAL_FMC_NORSRAM_Init(FMC_NORSRAMInitTypeDef *hFMC); + +HAL_StatusTypeDef HAL_FMC_NORSRAM_DeInit(FMC_NORSRAMInitTypeDef *hFMC); + +HAL_StatusTypeDef HAL_FMC_NORSRAM_Timing_Init(FMC_NORSRAMTimingInitTypeDef *Timing, uint32_t Bank); + +HAL_StatusTypeDef HAL_FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAMTimingInitTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); + +HAL_StatusTypeDef HAL_FMC_SDRAM_Init(FMC_SDRAMInitTypeDef *Init); + +HAL_StatusTypeDef HAL_FMC_SDRAM_Timing_Init(FMC_SDRAMTimingInitTypeDef *Timing, uint32_t Bank); + +HAL_StatusTypeDef HAL_FMC_SDRAM_DeInit(uint32_t Bank); + +HAL_StatusTypeDef HAL_FMC_SDRAM_SendCommand(FMC_SDRAMCommandTypeDef *Command, uint32_t Timeout); + +HAL_StatusTypeDef HAL_FMC_SDRAM_ProgramRefreshRate(uint32_t RefreshRate); + +HAL_StatusTypeDef HAL_FMC_SDRAM_SetAutoRefreshNumber(uint32_t AutoRefreshNumber); + +uint32_t HAL_FMC_SDRAM_GetBankModeStatus(uint32_t Bank); + +uint32_t HAL_FMC_SDRAM_GetStatus(void); + +void HAL_FMC_SDRAM_ITConfig(FunctionalState NewState); + +FlagStatus HAL_FMC_SDRAM_GetITStatus(void); + +void HAL_FMC_SDRAM_ClearITPendingBit(void); + +void HAL_FMC_SDRAM_BurstReadFifoLength(uint32_t FifoLen, uint32_t Bank); + +void HAL_FMC_SDRAM_W2RDelay(uint32_t W2RDelay, uint32_t Bank); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_gpio.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..08f759b7a67cc2741b7f6f6491a6c4bd938505e7 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_gpio.h @@ -0,0 +1,289 @@ +/****************************************************************************** +*@file : hal_gpio.h +*@brief : Header file of GPIO HAL module. +******************************************************************************/ + +#ifndef __HAL_GPIO_H__ +#define __HAL_GPIO_H__ + +#include "hal.h" + + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Drive; /*!< Specifies the Output drive capability for the selected pins. + This parameter can be a value of @ref GPIO_drive */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_function_selection */ +} GPIO_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup GPIO_PORT Index + * @{ + */ +typedef enum +{ + GPIO_PORTA, + GPIO_PORTB, + GPIO_PORTC, + GPIO_PORTD, + GPIO_PORTE, + GPIO_PORTF, + GPIO_PORTG, + GPIO_PORTH, + GPIO_PORTI, + GPIO_PORTJ, + GPIO_PORTK, + GPIO_PORTL, + GPIO_PORTM, + GPIO_PORTN, + GPIO_PORTO, + GPIO_PORTP, + GPIO_PORTQ, +}enum_GPIOx_t; +/** + * @} + */ + + +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; + + +/** @defgroup GPIO_pins GPIO pins + * @{ + */ + +#define GPIO_PIN_0 ( (uint16_t)0x0001 ) /* Pin 0 selected */ +#define GPIO_PIN_1 ( (uint16_t)0x0002 ) /* Pin 1 selected */ +#define GPIO_PIN_2 ( (uint16_t)0x0004 ) /* Pin 2 selected */ +#define GPIO_PIN_3 ( (uint16_t)0x0008 ) /* Pin 3 selected */ +#define GPIO_PIN_4 ( (uint16_t)0x0010 ) /* Pin 4 selected */ +#define GPIO_PIN_5 ( (uint16_t)0x0020 ) /* Pin 5 selected */ +#define GPIO_PIN_6 ( (uint16_t)0x0040 ) /* Pin 6 selected */ +#define GPIO_PIN_7 ( (uint16_t)0x0080 ) /* Pin 7 selected */ +#define GPIO_PIN_8 ( (uint16_t)0x0100 ) /* Pin 8 selected */ +#define GPIO_PIN_9 ( (uint16_t)0x0200 ) /* Pin 9 selected */ +#define GPIO_PIN_10 ( (uint16_t)0x0400 ) /* Pin 10 selected */ +#define GPIO_PIN_11 ( (uint16_t)0x0800 ) /* Pin 11 selected */ +#define GPIO_PIN_12 ( (uint16_t)0x1000 ) /* Pin 12 selected */ +#define GPIO_PIN_13 ( (uint16_t)0x2000 ) /* Pin 13 selected */ +#define GPIO_PIN_14 ( (uint16_t)0x4000 ) /* Pin 14 selected */ +#define GPIO_PIN_15 ( (uint16_t)0x8000 ) /* Pin 15 selected */ + +/** + * @} + */ + +/** @brief PIN mask for assert test + */ + +#define GPIO_ALL_PIN_MASK ( 0x0000FFFFU ) /* PIN mask for assert test */ + +/** @defgroup GPIO_mode + * @{ + */ +#define GPIO_MODE_INPUT ( 0x00000000U ) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP ( 0x00000001U ) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD ( 0x00000011U ) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ( 0x00000002U ) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ( 0x00000012U ) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG_SWITCH_OFF ( 0x00000003U ) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG_SWITCH_ON ( 0x00000013U ) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING ( 0x10110000U ) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING ( 0x10210000U ) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING ( 0x10310000U ) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING ( 0x10120000U ) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING ( 0x10220000U ) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING ( 0x10320000U ) /*!< External Event Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_GPIO_MASK ( 0x00000003u ) /*!< GPIO interrupt Mask */ +#define GPIO_MODE_GPIO_OUTPUT_TYPE_MASK ( 0x00000010u ) /*!< GPIO interrupt Mask */ +#define GPIO_MODE_EXTI_MASK ( 0x10000000u ) /*!< GPIO interrupt Mask */ + +/** + * @} + */ + +/** @defgroup GPIO_drive + * @brief GPIO Output drive capability + * @{ + */ +#define GPIO_DRIVE_LEVEL0 ( 0x00000000U ) /*!< Output drive capability up to 2mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL1 ( 0x00000001U ) /*!< Output drive capability up to 4mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL2 ( 0x00000002U ) /*!< Output drive capability up to 6mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL3 ( 0x00000003U ) /*!< Output drive capability up to 8mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL4 ( 0x00000004U ) /*!< Output drive capability up to 8mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL5 ( 0x00000005U ) /*!< Output drive capability up to 8mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL6 ( 0x00000006U ) /*!< Output drive capability up to 8mA, please refer to the product datasheet */ +#define GPIO_DRIVE_LEVEL7 ( 0x00000007U ) /*!< Output drive capability up to 8mA, please refer to the product datasheet */ + +/** + * @} + */ + +/** @defgroup GPIO_pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL ( 0x00000000U ) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ( 0x00000001U ) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ( 0x00000002U ) /*!< Pull-down activation */ + +/** + * @} + */ + + +/** @defgroup GPIOEx_function_selection + * @{ + */ +#define GPIO_FUNCTION_0 ( 0x00000000U ) +#define GPIO_FUNCTION_1 ( 0x00000001U ) +#define GPIO_FUNCTION_2 ( 0x00000002U ) +#define GPIO_FUNCTION_3 ( 0x00000003U ) +#define GPIO_FUNCTION_4 ( 0x00000004U ) +#define GPIO_FUNCTION_5 ( 0x00000005U ) +#define GPIO_FUNCTION_6 ( 0x00000006U ) +#define GPIO_FUNCTION_7 ( 0x00000007U ) +#define GPIO_FUNCTION_8 ( 0x00000008U ) +#define GPIO_FUNCTION_9 ( 0x00000009U ) +#define GPIO_FUNCTION_10 ( 0x0000000AU ) +#define GPIO_FUNCTION_11 ( 0x0000000BU ) +#define GPIO_FUNCTION_12 ( 0x0000000CU ) +#define GPIO_FUNCTION_13 ( 0x0000000DU ) +#define GPIO_FUNCTION_14 ( 0x0000000EU ) +#define GPIO_FUNCTION_15 ( 0x0000000FU ) + +/** + * @} + */ + +/** @defgroup GPIO Private Macros + * @{ + */ + +#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || ((__INSTANCE__) == GPIOB) || \ + ((__INSTANCE__) == GPIOC) || ((__INSTANCE__) == GPIOD) || \ + ((__INSTANCE__) == GPIOE) || ((__INSTANCE__) == GPIOF) || \ + ((__INSTANCE__) == GPIOG) || ((__INSTANCE__) == GPIOH) || \ + ((__INSTANCE__) == GPIOI) || ((__INSTANCE__) == GPIOJ) || \ + ((__INSTANCE__) == GPIOK) || ((__INSTANCE__) == GPIOL) || \ + ((__INSTANCE__) == GPIOM) || ((__INSTANCE__) == GPION) || \ + ((__INSTANCE__) == GPIOO) || ((__INSTANCE__) == GPIOP) || \ + ((__INSTANCE__) == GPIOQ)) + +#define IS_GPIO_ALL_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_ALL_PIN_MASK) != 0) && \ + (((uint32_t)(__PIN__) & ~GPIO_ALL_PIN_MASK) == 0)) + +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + +#define IS_GPIO_MODE(__GPIO__, __MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG_SWITCH_OFF) ||\ + ((__MODE__) == GPIO_MODE_ANALOG_SWITCH_ON)) + + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) ||\ + ((__PULL__) == GPIO_PULLDOWN)) + +#define IS_GPIO_DRIVE(__DRIVE__) (((__DRIVE__) == GPIO_DRIVE_LEVEL0) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL1) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL2) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL3) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL4) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL5) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL6) ||\ + ((__DRIVE__) == GPIO_DRIVE_LEVEL7)) + +#define IS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || \ + ((__ACTION__) == GPIO_PIN_SET)) + +#define IS_GPIO_FUNCTION(__FUNCTION__) (((__FUNCTION__) == GPIO_FUNCTION_0) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_1) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_2) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_3) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_4) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_5) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_6) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_7) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_8) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_9) ||\ + ((__FUNCTION__) == GPIO_FUNCTION_10)||\ + ((__FUNCTION__) == GPIO_FUNCTION_11)||\ + ((__FUNCTION__) == GPIO_FUNCTION_12)||\ + ((__FUNCTION__) == GPIO_FUNCTION_13)||\ + ((__FUNCTION__) == GPIO_FUNCTION_14)||\ + ((__FUNCTION__) == GPIO_FUNCTION_15)) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/* HAL_GPIO_Init */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); + +/* HAL_GPIO_DeInit */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/* HAL_GPIO_WritePin */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIO_PinState PinState); + +/* HAL_GPIO_ReadPin */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/* HAL_GPIO_TogglePin */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_hrng.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_hrng.h new file mode 100644 index 0000000000000000000000000000000000000000..9af91144a18547d16d8adc1e0fbc251a79329263 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_hrng.h @@ -0,0 +1,54 @@ +/****************************************************************************** +*@file : hal_hrng.h +*@brief : HRNG module driver header file. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __HRNG_H__ +#define __HRNG_H__ + +#include "hal.h" + +/****************************************************************************** +*@brief : Initialize the hrng module +* +*@return: None +******************************************************************************/ +void HAL_HRNG_Init(void); + +/****************************************************************************** +*@brief : DeInitializes the hrng module +* +*@return: None +******************************************************************************/ +void HAL_HRNG_DeInit(void); + +/****************************************************************************** +*@brief : get 8bit random number +* +*@return: 8 bit random number +******************************************************************************/ +uint8_t HAL_HRNG_GetHrng_8(void); + +/****************************************************************************** +*@brief : get 32bit random number +* +*@return: 32 bit random number +******************************************************************************/ +uint32_t HAL_HRNG_GetHrng_32(void); + +/****************************************************************************** +*@brief : get random number +* +*@param : hdata : the start address of random number +*@param : byte_len the byte length of random number +*@return: 0 : hrng data is ok +* 1 : hrng data is bad +******************************************************************************/ +uint8_t HAL_HRNG_GetHrng(uint8_t *hdata, uint32_t byte_len); + +#endif + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_i2c.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..6e5143fb1ae2f3b54cd1ec1dac16d810729ba7e4 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_i2c.h @@ -0,0 +1,208 @@ +/****************************************************************************** +*@file : hal_i2c.h +*@brief : Header file of I2C HAL module. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __HAL_I2C_H__ +#define __HAL_I2C_H__ + +#include "acm32h5xx_hal_conf.h" + +/** @defgroup I2C_MODE + * @{ + */ +#define I2C_MODE_SLAVE (0U) +#define I2C_MODE_MASTER (1U) +/** + * @} + */ + +/** @defgroup CLOCK_SPEED + * @{ + */ +#define CLOCK_SPEED_STANDARD (100000U) +#define CLOCK_SPEED_FAST (400000U) +#define CLOCK_SPEED_FAST_PLUS (1000000U) +/** + * @} + */ + + +/** @defgroup TX_AUTO_EN + * @{ + */ +#define TX_AUTO_DISABLE (0U) +#define TX_AUTO_ENABLE (1U) +/** + * @} + */ + + +/** @defgroup STRETCH_MODE + * @{ + */ +#define STRETCH_MODE_ENABLE (0U) +#define STRETCH_MODE_DISABLE (1U) +/** + * @} + */ + +/** @defgroup FILTER_ALGO_ENABLE + * @{ + */ +#define FILTER_ALGO_DISABLE (0U) +#define FILTER_ALGO_ENABLE (1U) +/** + * @} + */ + +/** @defgroup SLAVE State machine + * @{ + */ +#define I2C_STATE_IDLE (0U) +#define I2C_STATE_TX_DATA (1U) +#define I2C_STATE_RX_DATA (2U) +#define I2C_STATE_REQ_ADDR (3U) +#define I2C_STATE_RX_ADDR (4U) +/** + * @} + */ + + /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0U) +#define I2C_MEMADD_SIZE_16BIT (1U) +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) + +/** + * @brief I2C Configuration Structure definition + */ + +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__) ) ? 1 : 0) + + +typedef struct +{ + uint32_t I2C_Mode; /* This parameter can be a value of @ref I2C_MODE */ + + uint32_t Tx_Auto_En; /* This parameter can be a value of @ref TX_AUTO_EN */ + + uint32_t Stretch_Mode; /* This parameter can be a value of @ref STRETCH_MODE */ + + uint32_t Own_Address; /* This parameter can be a 7-bit address */ + + uint32_t Clock_Speed; /* This parameter can be a value of @ref CLOCK_SPEED */ + + uint32_t filter_enable; /* This parameter can be a value of @ref FILTER_ALGO_DISABLE */ +} I2C_InitTypeDef; + +/******************************** Check I2C Parameter *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ + ((INSTANCE) == I2C2) || \ + ((INSTANCE) == I2C3) || \ + ((INSTANCE) == I2C4) ) + +#define IS_I2C_ALL_MODE(I2C_MODE) (((I2C_MODE) == I2C_MODE_SLAVE) || \ + ((I2C_MODE) == I2C_MODE_MASTER)) + +#define IS_I2C_CLOCK_SPEED(CLOCK_SPEED) (((CLOCK_SPEED) > 0U) && ((CLOCK_SPEED) <=1000000U)) + +#define IS_I2C_TX_AUTO_EN(TX_AUTO_EN) (((TX_AUTO_EN) == TX_AUTO_DISABLE) || \ + ((TX_AUTO_EN) == TX_AUTO_ENABLE)) + +#define IS_I2C_STRETCH_EN(STRETCH_EN) (((STRETCH_EN) == STRETCH_MODE_ENABLE) || \ + ((STRETCH_EN) == STRETCH_MODE_DISABLE)) + +/** + * @brief I2C handle Structure definition + */ +typedef struct _I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /* I2C registers base address */ + + I2C_InitTypeDef Init; /* I2C communication parameters */ + + volatile uint32_t state; /* the I2C state machine */ + + uint8_t *Rx_Buffer; /* I2C Rx Buffer */ + uint8_t *Tx_Buffer; /* I2C Tx Buffer */ + + uint32_t Rx_Size; /* I2C Rx Size */ + uint32_t Tx_Size; /* I2C Tx Size */ + + uint32_t Rx_Count; /* I2C Rx Count */ + uint32_t Tx_Count; /* I2C Tx Count */ +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *HDMA_Rx; /* I2C Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* I2C Tx DMA handle parameters */ +#endif + void (*I2C_STOPF_Callback)(struct _I2C_HandleTypeDef* hi2c); /* I2C STOP flag interrupt callback */ + +}I2C_HandleTypeDef; + +/* Function : HAL_I2C_IRQHandler */ +void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_MspInit */ +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_MspDeInit */ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_Init */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_DeInit */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_Master_Transmit */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Master_Receive */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Transmit */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Slave_Receive */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); + + +/* Function : HAL_I2C_Slave_Receive_IT */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); + +#ifdef HAL_DMA_MODULE_ENABLED +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size); +#endif + +/* Function : HAL_I2C_Mem_Write */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_Mem_Read */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Function : HAL_I2C_GetSlaveRxState */ +uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c); + +/* Function : HAL_I2C_GetSlaveTxState */ +uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_i2s.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..71d8c3f38bbc816b83c46e38ac7869df54f857bd --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_i2s.h @@ -0,0 +1,487 @@ + +/****************************************************************************** +*@file : hal_i2s.h +*@brief : Header file of I2S HAL module. +******************************************************************************/ + +#ifndef __HAL_I2S_H__ +#define __HAL_I2S_H__ + +#include "hal.h" + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_DataFormat */ + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_ClockPolarity */ + + uint32_t IOSwitch; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_IOSwitch */ + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. */ + +}I2S_InitTypeDef; + + + +/** + * @brief I2S handle Structure definition + */ +typedef struct __I2S_HandleTypeDef +{ + I2S_TypeDef *Instance; /*!< I2S registers base address */ + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + DMA_HandleTypeDef *hdmactx; /*!< Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmacrx; /*!< Rx DMA Handle parameters */ + + uint32_t State; /*!< Tx state */ + uint32_t Error; /*!< Tx Error */ + uint32_t Abort; /*!< Tx abort flag in blocking mode */ + uint32_t *pTxBuf; /*!< Tx buffer pointer */ + uint32_t TxCount; /*!< Tx size not transfer */ + uint32_t *pRxBuf; /*!< Rx buffer pointer */ + uint32_t RxCount; /*!< Rx size not transfer */ + + uint32_t (*TxCpltCallback)(struct __I2S_HandleTypeDef *); /* send complete callback */ + uint32_t (*RxCpltCallback)(struct __I2S_HandleTypeDef *); /* send complete callback */ + uint32_t (*TxEmptyCallback)(struct __I2S_HandleTypeDef *); /* send complete callback */ + uint32_t (*MsuspCallback)(struct __I2S_HandleTypeDef *); /* send complete callback */ + uint32_t (*SvtcCallback)(struct __I2S_HandleTypeDef *); /* send complete callback */ + uint32_t (*DMATxCpltCallback)(struct __I2S_HandleTypeDef *); /* send complete callback */ + uint32_t (*DMATxHalfCpltCallback)(struct __I2S_HandleTypeDef *); /* send half complete callback in DMA mode */ + uint32_t (*DMARxCpltCallback)(struct __I2S_HandleTypeDef *); /* recv complete callback */ + uint32_t (*DMARxHalfCpltCallback)(struct __I2S_HandleTypeDef *); /* recv half complete callback in DMA mode */ + uint32_t (*ErrorCallback)(struct __I2S_HandleTypeDef *); /* error callback */ + +}I2S_HandleTypeDef; + + +/** + * @brief HAL I2S Callback pointer definition + */ + +typedef uint32_t (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hlpuart); /*!< pointer to the I2S callback function */ + + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_MODE_MASTER ( I2S_CR_MODE ) +#define I2S_MODE_SLAVE ( 0U ) + +/** + * @} + */ + + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_STANDARD_PHILIPS ( 0U ) +#define I2S_STANDARD_MSB ( I2S_CR_STD_0 ) +#define I2S_STANDARD_LSB ( I2S_CR_STD_1 ) +#define I2S_STANDARD_PCM_SHORT ( I2S_CR_STD_1 | I2S_CR_STD_0 ) +#define I2S_STANDARD_PCM_LONG ( I2S_CR_PCMMODE | I2S_CR_STD_1 | I2S_CR_STD_0 ) + +/** + * @} + */ + + +/** @defgroup I2S_DataFormat + * @{ + */ + +#define I2S_DATA_FORMAT_16B_EXTENDED_TO_16B ( 0U ) +#define I2S_DATA_FORMAT_16B_EXTENDED_TO_32B ( I2S_CR_CHLEN ) +#define I2S_DATA_FORMAT_24B_EXTENDED_TO_32B ( I2S_CR_CHLEN | I2S_CR_DLEN_0 ) +#define I2S_DATA_FORMAT_32B_EXTENDED_TO_32B ( I2S_CR_CHLEN | I2S_CR_DLEN_1 ) +/** + * @} + */ + + +/** @defgroup I2S_MCLKOut + * @{ + */ +#define I2S_MCLKOUT_ENABLE ( I2S_PR_MCKOE ) +#define I2S_MCLKOUT_DISABLE ( 0U ) +/** + * @} + */ + + +/** @defgroup I2S_ClockPolarity + * @{ + */ + +#define I2S_CLOCK_POLARITY_LOW ( 0U ) +#define I2S_CLOCK_POLARITY_HIGH ( I2S_CR_CKPL ) + +/** + * @} + */ + + +/** @defgroup I2S_IOSwitch + * @{ + */ + +#define I2S_IO_SWITCH_ENABLE ( I2S_CR_IOSWP ) +#define I2S_IO_SWITCH_DISABLE ( 0U ) + +/** + * @} + */ + +/** @defgroup I2S_CallbackID + * @{ + */ + +#define I2S_CALLBACKID_TX_CPLT ( 0U ) +#define I2S_CALLBACKID_RX_CPLT ( 1U ) +#define I2S_CALLBACKID_TX_EMPTY ( 2U ) +#define I2S_CALLBACKID_MSUSP ( 3U ) +#define I2S_CALLBACKID_SVTC ( 4U ) +#define I2S_CALLBACKID_DMA_TX_CPLT ( 5U ) +#define I2S_CALLBACKID_DMA_TX_HALF_CPLT ( 6U ) +#define I2S_CALLBACKID_DMA_RX_CPLT ( 7U ) +#define I2S_CALLBACKID_DMA_RX_HALF_CPLT ( 8U ) +#define I2S_CALLBACKID_ERROR ( 9U ) +#define I2S_CALLBACKID_MAX ( 10U ) + +/** + * @} + */ + +/** @defgroup I2S_IT + * @{ + */ +#define I2S_IT_TXE ( I2S_DIER_TXEIE ) +#define I2S_IT_RXNE ( I2S_DIER_RXNEIE ) +#define I2S_IT_ERR ( I2S_DIER_ERRIE ) +#define I2S_IT_MSUSP ( I2S_DIER_MSUSPIE ) +#define I2S_IT_SVTC ( I2S_DIER_SVTCIE ) + +/** + * @} + */ + +/** + * @brief + */ + +#define I2S_IT_MASK ( I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR | I2S_IT_MSUSP | I2S_IT_SVTC ) + +/** @defgroup I2S_Flags + * @{ + */ + +#define I2S_FLAG_SVTC ( I2S_SR_SVTC ) +#define I2S_FLAG_MSUSP ( I2S_SR_MSUSP ) +#define I2S_FLAG_FE ( I2S_SR_FE ) +#define I2S_FLAG_OVR ( I2S_SR_OVR ) +#define I2S_FLAG_UDR ( I2S_SR_UDR ) +#define I2S_FLAG_CH ( I2S_SR_CH ) +#define I2S_FLAG_TXE ( I2S_SR_TXE ) +#define I2S_FLAG_RXNE ( I2S_SR_RXNE ) + +/** + * @} + */ + +/** + * @brief + */ + +#define I2S_FLAG_MASK ( I2S_FLAG_SVTC | I2S_FLAG_MSUSP | I2S_FLAG_FE | I2S_FLAG_OVR | \ + I2S_FLAG_UDR | I2S_FLAG_CH | I2S_FLAG_TXE | I2S_FLAG_RXNE ) + + +/** + * @brief I2S_State + */ + +#define I2S_STATE_READY ( 0U ) +#define I2S_STATE_BUSY ( 1U ) +#define I2S_STATE_BUSY_IT ( 2U ) +#define I2S_STATE_BUSY_DMA ( 3U ) +#define I2S_STATE_BUSY_DMA_LINK ( 4U ) + +/** + * @brief I2S DMA error + */ + +#define I2S_DMA_ERROR ( 1U << 31 ) +#define I2S_DMA_TX_ERROR ( 1U << 31 ) +#define I2S_DMA_RX_ERROR ( 1U << 31 ) + + + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup I2S_Exported_Macros + * @{ + */ + +/** + * @brief Enable the I2S peripheral. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_EN) + +/** + * @brief Disable the I2S peripheral. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_EN)) + +#define __HAL_I2S_TX_RX_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_TEN | I2S_CR_REN) + +#define __HAL_I2S_TX_RX_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_TEN | I2S_CR_REN)) + +#define __HAL_I2S_TX_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_TEN) + +#define __HAL_I2S_TX_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_TEN)) + +#define __HAL_I2S_RX_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_REN) + +#define __HAL_I2S_RX_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_REN)) + +#define __HAL_I2S_START_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_START) + +#define __HAL_I2S_START_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_START)) + +#define __HAL_I2S_STOP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_STOP) + +#define __HAL_I2S_STOP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_STOP)) + +#define __HAL_I2S_WRITE_DATA(__HANDLE__, __DATA__) ((__HANDLE__)->Instance->TXDR = (__DATA__)) + +#define __HAL_I2S_READ_DATA(__HANDLE__) ((__HANDLE__)->Instance->RXDR) + +/** + * @brief Enable the TX DMA. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_TX_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_TXDMAEN) + +/** + * @brief Disable the TX DMA. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_TX_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_TXDMAEN)) + + +/** + * @brief Enable the RX DMA. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_RX_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_RXDMAEN) + +/** + * @brief Disable the RX DMA. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_RX_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_RXDMAEN)) + +/** + * @brief Enable the TX RX DMA. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_TX_RX_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= I2S_CR_TXDMAEN | I2S_CR_RXDMAEN) + +/** + * @brief Disable the TX RX DMA. + * @param __HANDLE__ I2S handle + * @retval None + */ + +#define __HAL_I2S_TX_RX_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(I2S_CR_TXDMAEN | I2S_CR_RXDMAEN)) + + +/** + * @brief Enable the specified I2S interrupt. + * @param __HANDLE__ I2S handle. + * @param __INTERRUPT__ I2S interrupt to set. + * This parameter can be a combination of: + * @arg I2S_IT_TXE : Tx buffer empty Interrupt. + * @arg I2S_IT_RXNE : Rx buffer non empty Interrupt. + * @arg I2S_IT_ERR : Error Interrupt. + * @retval None. + */ + +#define __HAL_I2S_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified I2S interrupt. + * @param __HANDLE__ I2S handle. + * @param __INTERRUPT__ I2S interrupt to set. + * This parameter can be a combination of: + * @arg I2S_IT_TXE : Tx buffer empty Interrupt. + * @arg I2S_IT_RXNE : Rx buffer non empty Interrupt. + * @arg I2S_IT_ERR : Error Interrupt. + * @retval None. + */ + +#define __HAL_I2S_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= (~(__INTERRUPT__))) + +/** + * @brief Check whether the specified I2S flag is set or not. + * @param __HANDLE__ I2S handle + * @param __FLAG__ I2S flag to check + * This parameter can be a value of: + * @arg I2S_FLAG_FE : frame error flag. + * @arg I2S_FLAG_BUSY : busy flag. + * @arg I2S_FLAG_RXOVE : rx buffer overflow flag. + * @arg I2S_FLAG_TXUDE : rx buffer uderflow flag. + * @arg I2S_FLAG_CHF : which channel data is the next data. + * @arg I2S_FLAGR_TXE : tx buffer empty flag. + * @arg I2S_FLAG_RXNE : rx buffer non empty flag. + * @retval The state of the specified flag (SET or RESET). + */ + +#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) + + +#define __HAL_I2S_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = 0xffffffff & ~(__FLAG__)) + + +/** + * @brief Check whether the specified I2S interrupt source is enabled or not. + * @param __HANDLE__ I2S handle. + * @param __INTERRUPT__ I2S interrupt to check. + * This parameter can be a value of: + * @arg I2S_IT_TXE : Tx buffer empty Interrupt. + * @arg I2S_IT_RXNE : Rx buffer non empty Interrupt. + * @arg I2S_IT_ERR : Error Interrupt. + * @retval Interrupt status. + */ + +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) + +/** + * @} + */ + + +/** @defgroup I2S Private Macros + * @{ + */ + +#define IS_I2S_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +#define IS_I2S_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2S1) || \ + ((__INSTANCE__) == I2S2) || \ + ((__INSTANCE__) == I2S3)) + +#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_MASTER) || \ + ((__MODE__) == I2S_MODE_SLAVE)) + +#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ + ((__STANDARD__) == I2S_STANDARD_MSB) || \ + ((__STANDARD__) == I2S_STANDARD_LSB) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ + ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATAFORMAT(__DATAFORMAT__) (((__DATAFORMAT__) == I2S_DATA_FORMAT_16B_EXTENDED_TO_16B) || \ + ((__DATAFORMAT__) == I2S_DATA_FORMAT_16B_EXTENDED_TO_32B) || \ + ((__DATAFORMAT__) == I2S_DATA_FORMAT_24B_EXTENDED_TO_32B) || \ + ((__DATAFORMAT__) == I2S_DATA_FORMAT_32B_EXTENDED_TO_32B)) + + +#define IS_I2S_MCLKOUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUT_ENABLE) || \ + ((__OUTPUT__) == I2S_MCLKOUT_DISABLE)) + +#define IS_I2S_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == I2S_CLOCK_POLARITY_LOW) || \ + ((__POLARITY__) == I2S_CLOCK_POLARITY_HIGH)) + +#define IS_I2S_IOSWITCH(__SWITCH__) (((__SWITCH__) == I2S_IO_SWITCH_ENABLE) || \ + ((__SWITCH__) == I2S_IO_SWITCH_DISABLE)) + + +#define IS_I2S_CALLBACKID(__CALLBACKID__) ((__CALLBACKID__) < I2S_CALLBACKID_MAX) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_I2S_IRQHander(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, uint32_t id, pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, uint32_t id); + +HAL_StatusTypeDef HAL_I2S_TxData(I2S_HandleTypeDef *hi2s, uint32_t Data); +HAL_StatusTypeDef HAL_I2S_RxData(I2S_HandleTypeDef *hi2s, uint32_t *pdata); + +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_I2S_Transmit_Receive(I2S_HandleTypeDef *hi2s, uint32_t *prxdata, uint32_t *ptxdata, uint32_t size, uint32_t timeout); + +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size); +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size); +HAL_StatusTypeDef HAL_I2S_Transmit_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *prxdata, uint32_t *ptxdata, uint32_t size); + +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint16_t size); +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint16_t size); +HAL_StatusTypeDef HAL_I2S_Transmit_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *prxdata, uint32_t *ptxdata, uint16_t size); + +HAL_StatusTypeDef HAL_I2S_Abort(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); + +void HAL_I2S_TxEmptyCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_TxCompleteCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_MsuspCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_SvtcCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_RxNonEmptyCallback(I2S_HandleTypeDef *hi2s); +void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); + +void HAL_I2S_DMATxCpltCallback(DMA_HandleTypeDef *hdmac); +void HAL_I2S_DMATxHalfCpltCallback(DMA_HandleTypeDef *hdmac); +void HAL_I2S_DMARxCpltCallback(DMA_HandleTypeDef *hdmac); +void HAL_I2S_DMARxHalfCpltCallback(DMA_HandleTypeDef *hdmac); +void HAL_I2S_DMAErrorCallback(DMA_HandleTypeDef *hdmac); + + + + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_iwdt.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_iwdt.h new file mode 100644 index 0000000000000000000000000000000000000000..7a1fba4261e475a14af59b9b4c1681be9ade4836 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_iwdt.h @@ -0,0 +1,180 @@ + +/****************************************************************************** +*@file : hal_iwdt.h +*@brief : Header file of IWDT HAL module. +******************************************************************************/ + +#ifndef __HAL_IWDT_H__ +#define __HAL_IWDT_H__ + +#include "hal.h" + + +/** + * @brief IWDT Init structure definition + */ + +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the IWDT. + This parameter can be any value of @ref IWDT_Clock_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDT down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Wakeup; /*!< Specifies the wakeup value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t WakeupMode; /*!< Configure the wake-up mode of IWDT. + This parameter can be any value of @ref IWDT_Wakeup_Mode */ + +} IWDT_InitTypeDef; + +/** + * @brief IWDT Handle Structure definition + */ + +typedef struct +{ + IWDT_TypeDef *Instance; /*!< Register base address */ + + IWDT_InitTypeDef Init; /*!< IWDT required parameters */ + +} IWDT_HandleTypeDef; + + +/** @defgroup IWDT_Cmd + * @{ + */ + +#define IWDT_CMD_ENABLE ( 0xCCCCU ) +#define IWDT_CMD_WRITE_ENABLE ( 0x5555U ) +#define IWDT_CMD_WAKEUP_ENABLE ( 0x6666U ) +#define IWDT_CMD_WAKEUP_DISABLE ( 0x9999U ) +#define IWDT_CMD_RELOAD ( 0xAAAAU ) +#define IWDT_CMD_DISABLE ( 0xEF01ABCDU ) + +/** + * @} + */ +/** @defgroup IWDT_Clock_Prescaler + * @{ + */ + +#define IWDT_CLOCK_PRESCALER_4 ( 0U ) +#define IWDT_CLOCK_PRESCALER_8 ( 1U ) +#define IWDT_CLOCK_PRESCALER_16 ( 2U ) +#define IWDT_CLOCK_PRESCALER_32 ( 3U ) +#define IWDT_CLOCK_PRESCALER_64 ( 4U ) +#define IWDT_CLOCK_PRESCALER_128 ( 5U ) +#define IWDT_CLOCK_PRESCALER_256 ( 6U ) +#define IWDT_CLOCK_PRESCALER_256_1 ( 7U ) + +/** + * @} + */ + +/** @defgroup IWDT_Wakeup_Mode + * @{ + */ + +#define IWDT_WAKEUP_MODE_IT ( EXTI_MODE_IT_RISING ) +#define IWDT_WAKEUP_MODE_EVENT ( EXTI_MODE_EVT_RISING ) + +/** + * @} + */ + +/** @defgroup IWDT_Flag + * @{ + */ + +#define IWDT_FLAG_PVU ( IWDT_SR_PVU ) +#define IWDT_FLAG_RVU ( IWDT_SR_RVU ) +#define IWDT_FLAG_WVU ( IWDT_SR_WVU ) +#define IWDT_FLAG_WTU ( IWDT_SR_WTU ) +#define IWDT_FLAG_RLF ( IWDT_SR_RLF ) + +/** + * @} + */ + +/** + * @brief IWDT EXTI Line number + */ + +#define IWDT_EXTI_LINE ( EXTI_LINE_IWDT ) + +/** + * @brief IWDT down-counter reload max value + */ + +#define IWDT_RELOAD_MAX_VALUE ( 0x0FFFU ) + + +/** @defgroup IWDT_TIMEOUT + * @{ + */ + +#define IWDT_PVU_TIMEOUT ( 30U ) +#define IWDT_RVU_TIMEOUT ( 30U ) +#define IWDT_WVU_TIMEOUT ( 30U ) +#define IWDT_WTU_TIMEOUT ( 30U ) +#define IWDT_RLF_TIMEOUT ( 30U ) + +/** + * @} + */ + + +/** @defgroup IWDT Private Macros + * @{ + */ + +#define IS_IWDT_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) +#define IS_IWDT_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDT) + +#define IS_IWDT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDT_CLOCK_PRESCALER_4) || \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_8) || \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_16) || \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_32) || \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_64) || \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_256)|| \ + ((__PRESCALER__) == IWDT_CLOCK_PRESCALER_256_1)) + +#define IS_IWDT_WAKEUPMODE(__MODE__) (((__MODE__) == IWDT_WAKEUP_MODE_IT) || \ + ((__MODE__) == IWDT_WAKEUP_MODE_EVENT)) + +#define IS_IWDT_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDT_RELOAD_MAX_VALUE) + +#define IS_IWDT_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDT_RELOAD_MAX_VALUE) + +#define IS_IWDT_WAKEUP(__WAKEUP__) ((__WAKEUP__) <= IWDT_RELOAD_MAX_VALUE) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_IWDT_IRQHandler(IWDT_HandleTypeDef *hiwdt); + +void HAL_IWDT_Callback(IWDT_HandleTypeDef *hiwdt); + +HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt); + +void HAL_IWDT_MspInit(IWDT_HandleTypeDef * hiwdt); + +HAL_StatusTypeDef HAL_IWDT_Refresh(IWDT_HandleTypeDef *hiwdt); + +FlagStatus HAL_IWDT_GetPending(void); + +void HAL_IWDT_ClearPending(void); + + + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_lptim.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_lptim.h new file mode 100644 index 0000000000000000000000000000000000000000..309d24097be3f2b1c5aa3819d4d95f86caedd80a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_lptim.h @@ -0,0 +1,755 @@ +/* + ****************************************************************************** + * @file hal_lptim.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of LPTIM HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_LPTIM_H__ +#define __HAL_LPTIM_H__ + +#include "hal.h" + +/** + * @brief LPTIM Initialization Structure definition + */ + +typedef struct +{ + uint32_t ClockSource; /*!< Selects the clock source. + This parameter can be a value of @ref LPTIM_ClockSource */ + + uint32_t ClockPrescaler; /*!< Specifies the counter clock Prescaler. + Note: This parameter is invalid when the internal clock source is + selected and the external input1 is selected as the count signal. + Note: This parameter is invalid when encoder mode is selected. + This parameter can be a value of @ref LPTIM_ClockPrescaler */ + + + uint32_t TriggerSource; /*!< Selects the Trigger source. + This parameter can be a value of @ref LPTIM_TriggerSource */ + + + uint32_t TriggerFilter; /*!< Selects the trigger sampling time to configure the clock glitch filter. + Note: This parameter is used only when the internal clock source is + selected and an external trigger is used. + This parameter can be a value of @ref LPTIM_TriggerFilter */ + + + uint32_t TriggerPolarity; /*!< Selects the Trigger active edge. + Note: This parameter is used only when the internal clock source is + selected and an external trigger is used. + This parameter can be a value of @ref LPTIM_TriggerPolarity */ + + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + Note: When external clock source is selected, this parameter is invalid, + and external events are forced to be selected + This parameter can be a value of @ref LPTIM_CounterSource */ + + uint32_t CounterFilter; /*!< Selects the clock sampling time to configure the clock glitch filter. + Note: This parameter is only used when the internal clock source is + selected and the external input1 is selected as the count signal. + This parameter can be a value of @ref LPTIM_CounterFilter */ + + + uint32_t CounterPolarity; /*!< Selects the polarity of the active edge for the counter unit + if the external input1 is selected. + Note: This parameter is used in two cases: one is to select an internal + clock source and external input1 as the count signal, and the + other is to select an external clock source. The 'both edge' is + only available in the first case. + This parameter can be a value of @ref LPTIM_CounterPolarity */ + + uint32_t Input1Source; /*!< Specifies source selected for input1. + This parameter can be a value of @ref LPTIM_Input1Source */ + + uint32_t Input2Source; /*!< Specifies source selected for input2. + Note: This parameter is used only for encoder feature. + This parameter can be a value of @ref LPTIM_Input2Source */ + + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare values and + repetition counter values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_UpdatingMode */ + + uint32_t WaveformPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_WaveformPolarity */ + +} LPTIM_InitTypeDef; + + + +/** + * @brief LPTIM handle Structure definition + */ + +typedef struct __LPTIM_HandleTypeDef +{ + LPTIM_TypeDef *Instance; /*!< Register base address */ + uint32_t WakeUpLine; + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + + void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ + void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ + void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ + void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ + void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ + void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ + void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ + void (* RepetitionUpdateCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter Update event occurs Callback */ + void (* RepetitionWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */ + + uint32_t RepetitionCounter; + uint32_t AutoReload; + uint32_t Compare; +} LPTIM_HandleTypeDef; + +/** + * @defgroup LPTIM_CallbackID + * @{ + */ + +#define LPTIM_CALLBACKID_COMPARE_MATCH ( 0U ) /*!< Compare match Callback ID */ +#define LPTIM_CALLBACKID_AUTORELOAD_MATCH ( 1U ) /*!< Auto-reload match Callback ID */ +#define LPTIM_CALLBACKID_TRIGGER ( 2U ) /*!< External trigger event detection Callback ID */ +#define LPTIM_CALLBACKID_COMPARE_WRITE ( 3U ) /*!< Compare register write complete Callback ID */ +#define LPTIM_CALLBACKID_AUTORELOAD_WRITE ( 4U ) /*!< Auto-reload register write complete Callback ID */ +#define LPTIM_CALLBACKID_DIRECTION_UP ( 5U ) /*!< Up-counting direction change Callback ID */ +#define LPTIM_CALLBACKID_DIRECTION_DOWN ( 6U ) /*!< Down-counting direction change Callback ID */ +#define LPTIM_CALLBACKID_REPETITION_UPDATE ( 7U ) /*!< Update event occurs Callback ID */ +#define LPTIM_CALLBACKID_REPETITION_WRITE ( 8U ) /*!< Repeat register write complete Callback ID */ + +/** + * @} + */ + +/** + * @brief HAL TIM Callback pointer definition + */ + +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ + + +/** + * @defgroup LPTIM_State + * @{ + */ + +#define HAL_LPTIM_STATE_READY ( 0U ) +#define HAL_LPTIM_STATE_BUSY ( 1U ) + +/** + * @} + */ + + + + + +/** @defgroup LPTIM_ClockSource + * @{ + */ + +#define LPTIM_CLOCKSOURCE_INTERNAL_PCLK ( 0 ) +#define LPTIM_CLOCKSOURCE_INTERNAL_RCL ( 1 ) +#define LPTIM_CLOCKSOURCE_INTERNAL_RCH ( 2 ) +#define LPTIM_CLOCKSOURCE_INTERNAL_XTL ( 3 ) +#define LPTIM_CLOCKSOURCE_EXTERNAL_INPUT1 ( 4 ) + +/** + * @} + */ + +/** @defgroup LPTIM_ClockPrescaler + * @{ + */ + +#define LPTIM_CLOCKPRESCALER_DIV1 ( 0U ) +#define LPTIM_CLOCKPRESCALER_DIV2 ( LPTIM_CFGR1_PRESC_0 ) +#define LPTIM_CLOCKPRESCALER_DIV4 ( LPTIM_CFGR1_PRESC_1 ) +#define LPTIM_CLOCKPRESCALER_DIV8 ( LPTIM_CFGR1_PRESC_0 | LPTIM_CFGR1_PRESC_1 ) +#define LPTIM_CLOCKPRESCALER_DIV16 ( LPTIM_CFGR1_PRESC_2 ) +#define LPTIM_CLOCKPRESCALER_DIV32 ( LPTIM_CFGR1_PRESC_0 | LPTIM_CFGR1_PRESC_2 ) +#define LPTIM_CLOCKPRESCALER_DIV64 ( LPTIM_CFGR1_PRESC_1 | LPTIM_CFGR1_PRESC_2 ) +#define LPTIM_CLOCKPRESCALER_DIV128 ( LPTIM_CFGR1_PRESC ) + +/** + * @} + */ + +/** @defgroup LPTIM_CounterPolarity + * @{ + */ + +#define LPTIM_COUNTERPOLARITY_RISING ( 0U ) +#define LPTIM_COUNTERPOLARITY_FALLING ( LPTIM_CFGR1_CKPOL_0 ) +#define LPTIM_COUNTERPOLARITY_RISING_FALLING ( LPTIM_CFGR1_CKPOL_1 ) + +/** + * @} + */ + +/** @defgroup LPTIM_CounterFilter + * @{ + */ + +#define LPTIM_COUNTERFILTER_DISABLE ( 0U ) +#define LPTIM_COUNTERFILTER_CLK2 ( LPTIM_CFGR1_CKFLT_0 ) +#define LPTIM_COUNTERFILTER_CLK4 ( LPTIM_CFGR1_CKFLT_1 ) +#define LPTIM_COUNTERFILTER_CLK8 ( LPTIM_CFGR1_CKFLT ) + +/** + * @} + */ + +/** @defgroup LPTIM_TriggerSource + * @{ + */ + +#define LPTIM_TRIGSOURCE_SOFTWARE ( 0x0000FFFFU ) +#define LPTIM_TRIGSOURCE_0 ( 0U ) +#define LPTIM_TRIGSOURCE_1 ( LPTIM_CFGR1_TRIGSEL_0 ) +#define LPTIM_TRIGSOURCE_2 ( LPTIM_CFGR1_TRIGSEL_1 ) +#define LPTIM_TRIGSOURCE_3 ( LPTIM_CFGR1_TRIGSEL_1 | LPTIM_CFGR1_TRIGSEL_0 ) + +#define LPTIM_TRIGSOURCE_4 ( LPTIM_CFGR1_TRIGSEL_2 ) +#define LPTIM_TRIGSOURCE_5 ( LPTIM_CFGR1_TRIGSEL_2 | LPTIM_CFGR1_TRIGSEL_0 ) +#define LPTIM_TRIGSOURCE_6 ( LPTIM_CFGR1_TRIGSEL_2 | LPTIM_CFGR1_TRIGSEL_1 ) +#define LPTIM_TRIGSOURCE_7 ( LPTIM_CFGR1_TRIGSEL_2 | LPTIM_CFGR1_TRIGSEL_1 | LPTIM_CFGR1_TRIGSEL_0 ) + +#define LPTIM_TRIGSOURCE_8 ( LPTIM_CFGR1_TRIGSEL_3 ) +#define LPTIM_TRIGSOURCE_9 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_0 ) +#define LPTIM_TRIGSOURCE_10 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_1 ) +#define LPTIM_TRIGSOURCE_11 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_1 | LPTIM_CFGR1_TRIGSEL_0 ) +#define LPTIM_TRIGSOURCE_12 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_2 ) +#define LPTIM_TRIGSOURCE_13 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_2 |LPTIM_CFGR1_TRIGSEL_0) +#define LPTIM_TRIGSOURCE_14 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_2 |LPTIM_CFGR1_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_15 ( LPTIM_CFGR1_TRIGSEL_3 | LPTIM_CFGR1_TRIGSEL_2 |LPTIM_CFGR1_TRIGSEL_1|LPTIM_CFGR1_TRIGSEL_0) + + +/** + * @} + */ + +/** @defgroup LPTIM_TriggerPolarity + * @{ + */ + +#define LPTIM_TRIGPOLARITY_RISING ( LPTIM_CFGR1_TRIGEN_0 ) +#define LPTIM_TRIGPOLARITY_FALLING ( LPTIM_CFGR1_TRIGEN_1 ) +#define LPTIM_TRIGPOLARITY_RISING_FALLING ( LPTIM_CFGR1_TRIGEN_1 | LPTIM_CFGR1_TRIGEN_0 ) + +/** + * @} + */ + +/** @defgroup LPTIM_TriggerFilter + * @{ + */ + +#define LPTIM_TRIGFILTER_DISABLE ( 0U ) +#define LPTIM_TRIGFILTER_2CLK ( LPTIM_CFGR1_TRGFLT_0 ) +#define LPTIM_TRIGFILTER_4CLK ( LPTIM_CFGR1_TRGFLT_1 ) +#define LPTIM_TRIGFILTER_8CLK ( LPTIM_CFGR1_TRGFLT_1 | LPTIM_CFGR1_TRGFLT_0 ) + +/** + * @} + */ + + +/** @defgroup LPTIM_WaveformPolarity + * @{ + */ + +#define LPTIM_WAVEFORMPOLARITY_HIGH ( 0U ) +#define LPTIM_WAVEFORMPOLARITY_LOW ( LPTIM_CFGR1_WAVPOL ) + +/** + * @} + */ + +/** @defgroup LPTIM_UpdatingMode + * @{ + */ + +#define LPTIM_UPDATE_IMMEDIATE ( 0U ) +#define LPTIM_UPDATE_ENDOFPERIOD ( LPTIM_CFGR1_PRELOAD ) + +/** + * @} + */ + +/** @defgroup LPTIM_CounterSource + * @{ + */ + +#define LPTIM_COUNTERSOURCE_INTERNAL ( 0U ) +#define LPTIM_COUNTERSOURCE_EXTERNAL ( LPTIM_CFGR1_COUNTMODE ) + +/** + * @} + */ + +/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source + * @{ + */ + +#define LPTIM_INPUT1SOURCE_0 ( 0U ) +#define LPTIM_INPUT1SOURCE_1 ( LPTIM_CFGR2_IN1SEL_0 ) +#define LPTIM_INPUT1SOURCE_2 ( LPTIM_CFGR2_IN1SEL_1 ) +#define LPTIM_INPUT1SOURCE_3 ( LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0 ) + +#define LPTIM_INPUT1SOURCE_4 ( LPTIM_CFGR2_IN1SEL_2 ) +#define LPTIM_INPUT1SOURCE_5 ( LPTIM_CFGR2_IN1SEL_2 | LPTIM_CFGR2_IN1SEL_0 ) +#define LPTIM_INPUT1SOURCE_6 ( LPTIM_CFGR2_IN1SEL_2 | LPTIM_CFGR2_IN1SEL_1 ) +#define LPTIM_INPUT1SOURCE_7 ( LPTIM_CFGR2_IN1SEL_2 | LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0 ) + +#define LPTIM_INPUT1SOURCE_8 ( LPTIM_CFGR2_IN1SEL_3 ) +#define LPTIM_INPUT1SOURCE_9 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_0 ) +#define LPTIM_INPUT1SOURCE_10 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_1 ) +#define LPTIM_INPUT1SOURCE_11 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0 ) +#define LPTIM_INPUT1SOURCE_12 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_2 ) +#define LPTIM_INPUT1SOURCE_13 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_2 | LPTIM_CFGR2_IN1SEL_0 ) +#define LPTIM_INPUT1SOURCE_14 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_2 | LPTIM_CFGR2_IN1SEL_1 ) +#define LPTIM_INPUT1SOURCE_15 ( LPTIM_CFGR2_IN1SEL_3 | LPTIM_CFGR2_IN1SEL_2 | LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0 ) + +/** + * @} + */ + +/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source + * @{ + */ + +#define LPTIM_INPUT2SOURCE_0 ( 0U ) +#define LPTIM_INPUT2SOURCE_1 ( LPTIM_CFGR2_IN2SEL_0 ) +#define LPTIM_INPUT2SOURCE_2 ( LPTIM_CFGR2_IN2SEL_1 ) +#define LPTIM_INPUT2SOURCE_3 ( LPTIM_CFGR2_IN2SEL_1 | LPTIM_CFGR2_IN2SEL_0 ) + +#define LPTIM_INPUT2SOURCE_4 ( LPTIM_CFGR2_IN2SEL_2 ) +#define LPTIM_INPUT2SOURCE_5 ( LPTIM_CFGR2_IN2SEL_2 | LPTIM_CFGR2_IN2SEL_0 ) +#define LPTIM_INPUT2SOURCE_6 ( LPTIM_CFGR2_IN2SEL_2 | LPTIM_CFGR2_IN2SEL_1 ) +#define LPTIM_INPUT2SOURCE_7 ( LPTIM_CFGR2_IN2SEL_2 | LPTIM_CFGR2_IN2SEL_1 | LPTIM_CFGR2_IN2SEL_0 ) + +#define LPTIM_INPUT2SOURCE_8 ( LPTIM_CFGR2_IN2SEL_3 ) +#define LPTIM_INPUT2SOURCE_9 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_0 ) +#define LPTIM_INPUT2SOURCE_10 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_1 ) +#define LPTIM_INPUT2SOURCE_11 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_1 | LPTIM_CFGR2_IN2SEL_0 ) +#define LPTIM_INPUT2SOURCE_12 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_2 ) +#define LPTIM_INPUT2SOURCE_13 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_2 | LPTIM_CFGR2_IN2SEL_0 ) +#define LPTIM_INPUT2SOURCE_14 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_2 | LPTIM_CFGR2_IN2SEL_1 ) +#define LPTIM_INPUT2SOURCE_15 ( LPTIM_CFGR2_IN2SEL_3 | LPTIM_CFGR2_IN2SEL_2 | LPTIM_CFGR2_IN2SEL_1 | LPTIM_CFGR2_IN2SEL_0 ) + + +/** + * @} + */ + + +/** @defgroup LPTIM_Flags + * @{ + */ + +#define LPTIM_FLAG_REPOK ( LPTIM_ISR_REPOK ) +#define LPTIM_FLAG_REPUE ( LPTIM_ISR_REPUE ) +#define LPTIM_FLAG_DOWN ( LPTIM_ISR_DOWN ) +#define LPTIM_FLAG_UP ( LPTIM_ISR_UP ) +#define LPTIM_FLAG_ARROK ( LPTIM_ISR_ARROK ) +#define LPTIM_FLAG_CMPOK ( LPTIM_ISR_CMPOK ) +#define LPTIM_FLAG_EXTTRIG ( LPTIM_ISR_EXTTRIG ) +#define LPTIM_FLAG_ARRM ( LPTIM_ISR_ARRM ) +#define LPTIM_FLAG_CMPM ( LPTIM_ISR_CMPM ) + +/** + * @} + */ + +/** @defgroup LPTIM_IT + * @{ + */ + +#define LPTIM_IT_REPOK ( LPTIM_IER_REPOKIE ) +#define LPTIM_IT_REPUE ( LPTIM_IER_REPUEIE ) +#define LPTIM_IT_DOWN ( LPTIM_IER_DOWNIE ) +#define LPTIM_IT_UP ( LPTIM_IER_UPIE ) +#define LPTIM_IT_ARROK ( LPTIM_IER_ARROKIE ) +#define LPTIM_IT_CMPOK ( LPTIM_IER_CMPOKIE ) +#define LPTIM_IT_EXTTRIG ( LPTIM_IER_EXTTRIGIE ) +#define LPTIM_IT_ARRM ( LPTIM_IER_ARRMIE ) +#define LPTIM_IT_CMPM ( LPTIM_IER_CMPMIE ) + +/** + * @} + */ + +/** @brief IT mask for assert test + */ +#define LPTIM_IT_MASK ( LPTIM_IT_REPOK | LPTIM_IT_REPUE | LPTIM_IT_DOWN | \ + LPTIM_IT_UP | LPTIM_IT_ARROK | LPTIM_IT_CMPOK | \ + LPTIM_IT_EXTTRIG | LPTIM_IT_ARRM | LPTIM_IT_CMPM ) + + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros + * @{ + */ + +/** + * @brief Enable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle + * @retval None + */ + +#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) + +/** + * @brief Disable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle. + * @retval None + */ + +#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) + +/** + * @brief Start the LPTIM peripheral in Continuous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ + +#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) + +/** + * @brief Start the LPTIM peripheral in single mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ + +#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) + +/** + * @brief Reset the LPTIM Counter register in synchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ + +#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST) + +/** + * @brief Enable Reset after read of the LPTIM Counter register in asynchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ + +#define __HAL_LPTIM_RESET_COUNTER_AFTER_READ_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE) + +/** + * @brief Disable Reset after read of the LPTIM Counter register in asynchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ + +#define __HAL_LPTIM_RESET_COUNTER_AFTER_READ_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~LPTIM_CR_RSTARE) + +/** + * @brief Return the current Autoreload (Period) value. + * @param __HANDLE__ LPTIM handle + * @retval Autoreload value + */ + +#define __HAL_LPTIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Write the passed parameter in the Autoreload register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Autoreload value + * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. + */ + +#define __HAL_LPTIM_SET_AUTORELOAD(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) + +/** + * @brief Return the current Compare (Pulse/Timeout) value. + * @param __HANDLE__ LPTIM handle + * @retval Compare value + * @note The CMP register can only be modified when the LPTIM instance is enabled. + */ + +#define __HAL_LPTIM_GET_COMPARE(__HANDLE__) ((__HANDLE__)->Instance->CMP) + +/** + * @brief Write the passed parameter in the Compare register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Compare value + * @retval None + * @note The CMP register can only be modified when the LPTIM instance is enabled. + */ + +#define __HAL_LPTIM_SET_COMPARE(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) + +/** + * @brief Return the current Repetition Counter value. + * @param __HANDLE__ LPTIM handle + * @retval Repetition Counter value + */ + +#define __HAL_LPTIM_GET_REPETITION_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->RCR) + +/** + * @brief Write the passed parameter in the repetition counter register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Repetition counter value + * @retval None + * @note The RCR register can only be modified when the LPTIM instance is enabled. + */ + +#define __HAL_LPTIM_SET_REPETITION_COUNTER(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->RCR = (__VALUE__)) + +/** + * @brief Return the current Counter value. + * @param __HANDLE__ LPTIM handle + * @retval Counter value + */ + +#define __HAL_LPTIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->RCR) + +/** + * @brief Check whether the specified LPTIM flag is set or not. + * @param __HANDLE__ LPTIM handle + * @param __FLAG__ LPTIM flag to check + * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repeat register update OK up Flag. + * @arg LPTIM_FLAG_REPUE : Update events occurs up Flag. + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CMPM : Compare match Flag. + * @retval The state of the specified flag (SET or RESET). + */ + +#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR &(__FLAG__)) + +/** + * @brief Clear the specified LPTIM flag. + * @param __HANDLE__ LPTIM handle. + * @param __FLAG__ LPTIM flag to clear. + * This parameter can be a combination of: + * @arg LPTIM_FLAG_REPOK : Repeat register update OK up Flag. + * @arg LPTIM_FLAG_REPUE : Update events occurs up Flag. + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CMPM : Compare match Flag. + * @retval None. + */ + +#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable the specified LPTIM interrupt. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. + * This parameter can be a combination of: + * @arg LPTIM_IT_REPOK : Repeat register update OK up Interrupt. + * @arg LPTIM_IT_REPUE : Update events occurs up Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. + */ + +#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified LPTIM interrupt. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. + * This parameter can be a combination of: + * @arg LPTIM_IT_REPOK : Repeat register update OK up Interrupt. + * @arg LPTIM_IT_REPUE : Update events occurs up Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. + */ + +#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** + * @brief Check whether the specified LPTIM interrupt source is enabled or not. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repeat register update OK up Interrupt. + * @arg LPTIM_IT_REPUE : Update events occurs up Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CMPM : Compare match Interrupt. + * @retval Interrupt status. + */ + +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) + +/** + * @} + */ + + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Macros LPTIM Private Macros + * @{ + */ + +#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1||\ + (__INSTANCE__) == LPTIM2||\ + (__INSTANCE__) == LPTIM3||\ + (__INSTANCE__) == LPTIM4||\ + (__INSTANCE__) == LPTIM5||\ + (__INSTANCE__) == LPTIM6) + +#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_INTERNAL_PCLK) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_INTERNAL_RCL) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_INTERNAL_RCH) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_INTERNAL_XTL) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_EXTERNAL_INPUT1)) + +#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV8) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV16) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV32) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV64) || \ + ((__PRESCALER__) == LPTIM_CLOCKPRESCALER_DIV128)) + +#define IS_LPTIM_TRIG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) >= LPTIM_TRIGSOURCE_0) && \ + ((__TRIG__) <= LPTIM_TRIGSOURCE_15)) + + +#define IS_LPTIM_TRIG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_TRIGPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_TRIGPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_TRIGPOLARITY_RISING_FALLING)) + + +#define IS_LPTIM_TRIG_FILTER(__FILTER__) (((__FILTER__) == LPTIM_TRIGFILTER_DISABLE) || \ + ((__FILTER__) == LPTIM_TRIGFILTER_2CLK) || \ + ((__FILTER__) == LPTIM_TRIGFILTER_4CLK) || \ + ((__FILTER__) == LPTIM_TRIGFILTER_8CLK)) + +#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) + + +#define IS_LPTIM_COUNTER_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_COUNTERPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_COUNTERPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_COUNTERPOLARITY_RISING_FALLING)) + + + +#define IS_LPTIM_COUNTER_FILTER(__FILTER__) (((__FILTER__) == LPTIM_COUNTERFILTER_DISABLE) || \ + ((__FILTER__) == LPTIM_COUNTERFILTER_CLK2) || \ + ((__FILTER__) == LPTIM_COUNTERFILTER_CLK4) || \ + ((__FILTER__) == LPTIM_COUNTERFILTER_CLK8)) + +#define IS_LPTIM_WAVEFORM_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_WAVEFORMPOLARITY_LOW) || \ + ((__POLARITY__) == LPTIM_WAVEFORMPOLARITY_HIGH)) + + +#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ + ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) + +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) (((__AUTORELOAD__) <= 0x0000FFFFUL) && ((__AUTORELOAD__) != 0UL)) + +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) < 0x0000FFFFUL) + +#define IS_LPTIM_PERIOD(__PERIOD__) IS_LPTIM_AUTORELOAD(__PERIOD__) + +#define IS_LPTIM_PULSE(__PULSE__) IS_LPTIM_COMPARE(__PULSE__) + +#define IS_LPTIM_TIMEOUT(__TIMEOUT__) IS_LPTIM_COMPARE(__TIMEOUT__) + +#define IS_LPTIM_REPETITION_COUNTER(__COUNTER__) ((__COUNTER__) <= 0xFFUL) + +#define IS_LPTIM_INPUT1_SOURCE(__SOURCE__) (((__SOURCE__) >= LPTIM_INPUT1SOURCE_0) || \ + ((__SOURCE__) <= LPTIM_INPUT1SOURCE_15)) + + +#define IS_LPTIM_INPUT2_SOURCE(__SOURCE__) (((__SOURCE__) >= LPTIM_INPUT2SOURCE_0) && \ + ((__SOURCE__) <= LPTIM_INPUT2SOURCE_15)) + +#define IS_LPTIM_IT(__IT__) ((((uint32_t)(__IT__) & LPTIM_IT_MASK) != 0x00u) && \ + (((uint32_t)(__IT__) & ~LPTIM_IT_MASK) == 0x00u)) + + +#define IS_LPTIM_CALLBACKID(__CALLBACKID__) (((__CALLBACKID__) == HAL_LPTIM_COMPARE_MATCH_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_AUTORELOAD_MATCH_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_TRIGGER_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_COMPARE_WRITE_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_AUTORELOAD_WRITE_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_DIRECTION_UP_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_DIRECTION_DOWN_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_REPETITION_UPDATE_CB_ID) ||\ + ((__CALLBACKID__) == HAL_LPTIM_REPETITION_WRITE_CB_ID)) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_ConfigCountValue(LPTIM_HandleTypeDef *hlptim, uint8_t RepetitionCounter, \ + uint16_t Period, uint16_t PulseOrTimeout); +HAL_StatusTypeDef HAL_LPTIM_EnableIT(LPTIM_HandleTypeDef *hlptim, uint32_t IT); +HAL_StatusTypeDef HAL_LPTIM_DisableIT(LPTIM_HandleTypeDef *hlptim, uint32_t IT); +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Timeout_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Timeout_Stop(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); + +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + uint32_t CallbackID, + pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + uint32_t CallbackID); + + +#endif // #ifndef __HAL_LPTIM_H__ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_lpuart.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_lpuart.h new file mode 100644 index 0000000000000000000000000000000000000000..f874db08fcb4e0f66c7f1de0f7f6c582f0a895df --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_lpuart.h @@ -0,0 +1,412 @@ + +/****************************************************************************** +*@file : hal_lpuart.h +*@brief : Header file of LPUART HAL module. +******************************************************************************/ + +#ifndef __HAL_LPUART_H__ +#define __HAL_LPUART_H__ + +#include "hal.h" + +/** + * @brief LPUART Init structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + This parameter can be a value of @ref LPUART_BaudRate. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_WordLength. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_StopBits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_Parity*/ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_Mode. */ + + uint32_t ClockSource; /*!< Specifies the clock source of LPUART. + This parameter can be a value of @ref LPUART_ClockSource. */ + + uint32_t WakeupMode; /*!< Specifies the wakeup Mode. + This parameter can be a value of @ref LPUART_WakeupMode. */ + + uint32_t WakeupAddr; /*!< Specifies the address of the wakeup matching. + This parameter can be a value of @ref LPUART_WakeupAddr. */ + +} LPUART_InitTypeDef; + + +/** + * @brief LPUART handle structure definition + */ + +typedef struct __LPUART_HandleTypeDef +{ + LPUART_TypeDef *Instance; /*!< Register base address */ + LPUART_InitTypeDef Init; /*!< communication parameters */ + DMA_HandleTypeDef *hdmatx; /*!< Tx DMA Handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< Rx DMA Handle parameters */ + + uint32_t TxState; /*!< Tx state */ + uint32_t TxError; /*!< Tx Error flag */ + uint8_t *pTxBuf; /*!< Tx buffer pointer */ + uint32_t TxCount; /*!< Tx size not transfer */ + uint32_t TxAbort; /*!< Tx abort flag in block mode*/ + + uint32_t RxState; /*!< Rx state */ + uint32_t RxError; /*!< Rx Error flag */ + uint8_t *pRxBuf; /*!< Rx buffer pointer */ + uint32_t RxCount; /*!< Rx size not transfer */ + uint32_t RxAbort; /*!< Rx abort flag in block mode*/ + + void (*TxCpltCallback)(struct __LPUART_HandleTypeDef *); /* tx complete callback */ + void (*TxHalfCpltCallback)(struct __LPUART_HandleTypeDef *); /* tx complete callback */ + void (*TxErrorCallback)(struct __LPUART_HandleTypeDef *); /* error callback */ + void (*RxCpltCallback)(struct __LPUART_HandleTypeDef *); /* rx recv complete callback */ + void (*RxHalfCpltCallback)(struct __LPUART_HandleTypeDef *); /* rx recv complete callback */ + void (*RxErrorCallback)(struct __LPUART_HandleTypeDef *); /* error callback */ + void (*WakeupCallback)(struct __LPUART_HandleTypeDef *); /* wakeup callback */ + void (*BcntCallback)(struct __LPUART_HandleTypeDef *); /* bit count callback */ + void (*IdleCallback)(struct __LPUART_HandleTypeDef *); /* idle callback */ + +}LPUART_HandleTypeDef; + + +/** + * @brief HAL LPUART Callback pointer definition + */ + +typedef void (*pLPUART_CallbackTypeDef)(LPUART_HandleTypeDef *hlpuart); /*!< pointer to the LPUART callback function */ + +/****************************************************************************** +*@brief : LPUART receive mode enum +* +*@note : the enum is used in receive function: HAL_LPUART_Receive_To_Idle_BCNT +******************************************************************************/ +typedef enum +{ + LPUART_RECEIVE_TOIDLE, /*!< end of receiving data by idle line checked */ + LPUART_RECEIVE_TOBCNT, /*!< end of receiving data by bit count value reached */ +}LPUART_Receive_Mode_Enum; + + +/** @defgroup LPUART_WordLength + * @{ + */ + +#define LPUART_WORDLENGTH_7B ( LPUART_LCR_WLEN ) +#define LPUART_WORDLENGTH_8B ( 0U ) + +/** + * @} + */ + +/** @defgroup LPUART_StopBits + * @{ + */ + +#define LPUART_STOPBITS_1B ( 0U ) +#define LPUART_STOPBITS_2B ( LPUART_LCR_STP2 ) + +/** + * @} + */ + +/** @defgroup LPUART_Parity + * @{ + */ + +#define LPUART_PARITY_NONE ( 0U ) +#define LPUART_PARITY_ODD ( LPUART_LCR_PEN ) +#define LPUART_PARITY_EVEN ( LPUART_LCR_PEN | LPUART_LCR_EPS ) +#define LPUART_PARITY_0 ( LPUART_LCR_PEN | LPUART_LCR_SPS | LPUART_LCR_EPS) +#define LPUART_PARITY_1 ( LPUART_LCR_PEN | LPUART_LCR_SPS ) + +/** + * @} + */ + +/** @defgroup LPUART_ClockSource + * @{ + */ + +#define LPUART_CLOCKSOURCE_RCL ( RCC_LPUART1_CLK_SOURCE_RCL ) +#define LPUART_CLOCKSOURCE_XTL ( RCC_LPUART1_CLK_SOURCE_XTL ) +#define LPUART_CLOCKSOURCE_PCLK_DIV4 ( RCC_LPUART1_CLK_SOURCE_PCLK1_DIV4) +#define LPUART_CLOCKSOURCE_PCLK_DIV8 ( RCC_LPUART1_CLK_SOURCE_PCLK1_DIV8) +#define LPUART_CLOCKSOURCE_PCLK_DIV16 ( RCC_LPUART1_CLK_SOURCE_PCLK1_DIV16) +#define LPUART_CLOCKSOURCE_PCLK_DIV32 ( RCC_LPUART1_CLK_SOURCE_PCLK1_DIV32) + +/** + * @} + */ + +/** @defgroup LPUART_Mode + * @{ + */ + +#define LPUART_MODE_TX ( LPUART_CR_TX_EN ) +#define LPUART_MODE_RX ( LPUART_CR_RX_EN ) +#define LPUART_MODE_TXRX ( LPUART_CR_TX_EN | LPUART_CR_RX_EN ) + +/** + * @} + */ + +/** @defgroup LPUART_WakeupMode + * @{ + */ + +#define LPUART_WAKEUPMODE_NONE ( LPUART_LCR_RXWKS ) +#define LPUART_WAKEUPMODE_STARTBIT ( 0U ) +#define LPUART_WAKEUPMODE_ONEBYTENOCHECK ( LPUART_LCR_RXWKS_0 ) +#define LPUART_WAKEUPMODE_ONEBYTECHECK ( LPUART_LCR_RXWKS_0 | LPUART_LCR_WKCK ) +#define LPUART_WAKEUPMODE_ADDRNOCHECK ( LPUART_LCR_RXWKS_1 ) +#define LPUART_WAKEUPMODE_ADDRCHECK ( LPUART_LCR_RXWKS_1 | LPUART_LCR_WKCK) + +/** + * @} + */ + +/** @defgroup LPUART_CallbackID + * @{ + */ + +#define LPUART_CALLBACKID_TXCPLT ( 0U ) +#define LPUART_CALLBACKID_TXHALFCPLT ( 1U ) +#define LPUART_CALLBACKID_TXERROR ( 2U ) +#define LPUART_CALLBACKID_RXCPLT ( 3U ) +#define LPUART_CALLBACKID_RXHALFCPLT ( 4U ) +#define LPUART_CALLBACKID_RXERROR ( 5U ) +#define LPUART_CALLBACKID_WAKEUP ( 6U ) +#define LPUART_CALLBACKID_BCNT ( 7U ) +#define LPUART_CALLBACKID_IDLE ( 8U ) + +/** + * @} + */ + +/** @defgroup LPUART_IT + * @{ + */ + +#define LPUART_IT_START ( LPUART_IE_STARTIE ) +#define LPUART_IT_MATCH ( LPUART_IE_MATCHIE ) +#define LPUART_IT_RXOV ( LPUART_IE_RXOVIE ) +#define LPUART_IT_FE ( LPUART_IE_FEIE ) +#define LPUART_IT_PE ( LPUART_IE_PEIE ) +#define LPUART_IT_TXE ( LPUART_IE_TXEIE ) +#define LPUART_IT_TC ( LPUART_IE_TCIE ) +#define LPUART_IT_RX ( LPUART_IE_RXIE ) +#define LPUART_IT_IDLE ( LPUART_IE_IDLEIE ) +#define LPUART_IT_BCNT ( LPUART_IE_BCNTIE ) +/** + * @} + */ + +/** + * @brief + */ + +#define LPUART_IT_MASK ( LPUART_IT_START | LPUART_IT_MATCH | \ + LPUART_IT_RXOV | LPUART_IT_FE | \ + LPUART_IT_PE | LPUART_IT_TXE | \ + LPUART_IT_TC | LPUART_IT_RX | \ + LPUART_IE_BCNTIE | LPUART_IE_IDLEIE) + +/** @defgroup LPUART_Flags + * @{ + */ + +#define LPUART_FLAG_TXE ( LPUART_SR_TXE ) +#define LPUART_FLAG_STARTIF ( LPUART_SR_STARTIF ) +#define LPUART_FLAG_MATCHIF ( LPUART_SR_MATCHIF ) +#define LPUART_FLAG_TXOVF ( LPUART_SR_TXOVF ) +#define LPUART_FLAG_RXF ( LPUART_SR_RXF ) +#define LPUART_FLAG_RXOVIF ( LPUART_SR_RXOVIF ) +#define LPUART_FLAG_FEIF ( LPUART_SR_FEIF ) +#define LPUART_FLAG_PEIF ( LPUART_SR_PEIF ) +#define LPUART_FLAG_TXEIF ( LPUART_SR_TXEIF ) +#define LPUART_FLAG_TCIF ( LPUART_SR_TCIF ) +#define LPUART_FLAG_RXIF ( LPUART_SR_RXIF ) +#define LPUART_FLAG_IDLEIF ( LPUART_SR_IDLEIF ) +#define LPUART_FLAG_BCNTIF ( LPUART_SR_BCNTIF ) +/** + * @} + */ + +/** + * @brief + */ + +#define LPUART_IT_FLAG_MASK ( LPUART_FLAG_STARTIF | LPUART_FLAG_MATCHIF | \ + LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | \ + LPUART_FLAG_PEIF | LPUART_FLAG_TXEIF | \ + LPUART_FLAG_TCIF | LPUART_FLAG_RXIF |\ + LPUART_FLAG_IDLEIF | LPUART_FLAG_BCNTIF) + +#define LPUART_FLAG_MASK ( LPUART_FLAG_TXE | LPUART_FLAG_TXOVF | \ + LPUART_FLAG_RXF | LPUART_IT_FLAG_MASK) + +#define LPUART_CLEAR_FLAG_MASK ( LPUART_FLAG_STARTIF | LPUART_FLAG_MATCHIF | \ + LPUART_FLAG_TXOVF | LPUART_FLAG_RXOVIF | \ + LPUART_FLAG_FEIF | LPUART_FLAG_PEIF | \ + LPUART_FLAG_TCIF | LPUART_FLAG_RXIF |\ + LPUART_FLAG_IDLEIF | LPUART_FLAG_BCNTIF) + +/** + * @brief LPUART_State + */ + +#define LPUART_STATE_READY ( 0U ) +#define LPUART_STATE_BUSY ( 1U ) +#define LPUART_STATE_BUSY_IT ( 2U ) +#define LPUART_STATE_BUSY_DMA ( 3U ) + +/** + * @brief LPUART DMA error + */ + +#define LPUART_DMA_TX_ERROR ( 1U << 31 ) +#define LPUART_DMA_RX_ERROR ( 1U << 31 ) + + + + +/** @defgroup LPUART Private Macros + * @{ + */ + +#define __HAL_LPUART_WRITE_TXDATA(__HANDLE__, __TXDATA__) ((__HANDLE__)->Instance->TXDR = __TXDATA__) + +#define __HAL_LPUART_READ_RXDATA(__HANDLE__, __RXDATA__) ((__HANDLE__)->Instance->RXDR) + +#define __HAL_LPUART_ENABLE_DMA(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPUART_CR_DMA_EN) + +#define __HAL_LPUART_DISABLE_DMA(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~LPUART_CR_DMA_EN) + +#define __HAL_LPUART_ENABLE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPUART_CR_TX_EN) + +#define __HAL_LPUART_DISABLE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~LPUART_CR_TX_EN) + +#define __HAL_LPUART_ENABLE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPUART_CR_RX_EN) + +#define __HAL_LPUART_DISABLE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~LPUART_CR_RX_EN) + +#define __HAL_LPUART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE |= (__INTERRUPT__) & LPUART_IT_MASK) + +#define __HAL_LPUART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE &= ~((__INTERRUPT__) & LPUART_IT_MASK)) + +#define __HAL_LPUART_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & ((__FLAG__) & LPUART_FLAG_MASK)) + +#define __HAL_LPUART_GET_IT_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & ((__FLAG__) & LPUART_IT_FLAG_MASK)) + +#define __HAL_LPUART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & ((__INTERRUPT__) & LPUART_IT_MASK)) + +#define __HAL_LPUART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ((__FLAG__) & LPUART_CLEAR_FLAG_MASK)) + + +/** @defgroup LPUART Private Macros + * @{ + */ + +#define IS_LPUART_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +#define IS_LPUART_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPUART1) + +#define IS_LPUART_WORDLENGTH(__WORDLENGTH__) (((__WORDLENGTH__) == LPUART_WORDLENGTH_7B) ||\ + ((__WORDLENGTH__) == LPUART_WORDLENGTH_8B)) + +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == LPUART_STOPBITS_1B) ||\ + ((__STOPBITS__) == LPUART_STOPBITS_2B)) + +#define IS_LPUART_PARITY(__PARITY__) (((__PARITY__) == LPUART_PARITY_NONE) ||\ + ((__PARITY__) == LPUART_PARITY_ODD) ||\ + ((__PARITY__) == LPUART_PARITY_EVEN) ||\ + ((__PARITY__) == LPUART_PARITY_0) ||\ + ((__PARITY__) == LPUART_PARITY_1)) + +#define IS_LPUART_MODE(__MODE__) (((__MODE__) == LPUART_MODE_TX) ||\ + ((__MODE__) == LPUART_MODE_RX) ||\ + ((__MODE__) == LPUART_MODE_TXRX)) + +#define IS_LPUART_WAKEUPMODE(__WAKEUPMODE__) (((__WAKEUPMODE__) == LPUART_WAKEUPMODE_NONE) ||\ + ((__WAKEUPMODE__) == LPUART_WAKEUPMODE_STARTBIT) ||\ + ((__WAKEUPMODE__) == LPUART_WAKEUPMODE_ONEBYTENOCHECK) ||\ + ((__WAKEUPMODE__) == LPUART_WAKEUPMODE_ONEBYTECHECK) ||\ + ((__WAKEUPMODE__) == LPUART_WAKEUPMODE_ADDRNOCHECK) ||\ + ((__WAKEUPMODE__) == LPUART_WAKEUPMODE_ADDRCHECK)) + +#define IS_LPUART_CALLBACKID(__CALLBACKID__) (((__CALLBACKID__) == LPUART_CALLBACKID_TXCPLT) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_TXHALFCPLT) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_TXERROR) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_RXCPLT) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_RXHALFCPLT) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_RXERROR) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_WAKEUP) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_BCNT) ||\ + ((__CALLBACKID__) == LPUART_CALLBACKID_IDLE)) + +#define IS_LPUART_CLOCKSOURCE(__CLOCKSOURCE__) (((__CLOCKSOURCE__) == LPUART_CLOCKSOURCE_XTL) || \ + ((__CLOCKSOURCE__) == LPUART_CLOCKSOURCE_RCL) || \ + ((__CLOCKSOURCE__) == LPUART_CLOCKSOURCE_PCLK_DIV4) || \ + ((__CLOCKSOURCE__) == LPUART_CLOCKSOURCE_PCLK_DIV8) || \ + ((__CLOCKSOURCE__) == LPUART_CLOCKSOURCE_PCLK_DIV16) || \ + ((__CLOCKSOURCE__) == LPUART_CLOCKSOURCE_PCLK_DIV32)) + + + +#define IS_LPUART_WAKEUPADDR(__WAKEUPADDR__) ((__WAKEUPADDR__) <= 0xFFU) + +#define IS_LPUART_DMASIZE(__DMASIZE__) ((__DMASIZE__) <= 0xFFFFU) + +#define IS_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) >= 2U) && ((__BAUDRATE__) <= 254U)) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart); +HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart); +HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_MspInit(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart); +HAL_StatusTypeDef HAL_LPUART_SetBaudRate(LPUART_HandleTypeDef *hlpuart, uint32_t baudRate); +HAL_StatusTypeDef HAL_LPUART_RegisterCallback(LPUART_HandleTypeDef *hlpuart, uint32_t id, pLPUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPUART_UnRegisterCallback(LPUART_HandleTypeDef *hlpuart, uint32_t id); +HAL_StatusTypeDef HAL_LPUART_Transmit(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_LPUART_Receive(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_LPUART_Transmit_IT(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size); +HAL_StatusTypeDef HAL_LPUART_Receive_IT(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size); +HAL_StatusTypeDef HAL_LPUART_Transmit_DMA(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size); +HAL_StatusTypeDef HAL_LPUART_Receive_DMA(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size); +HAL_StatusTypeDef HAL_LPUART_AbortTransmit(LPUART_HandleTypeDef *hlpuart); +HAL_StatusTypeDef HAL_LPUART_AbortReceive(LPUART_HandleTypeDef *hlpuart); +uint32_t HAL_LPUART_GetTxState(LPUART_HandleTypeDef *hlpuart); +uint32_t HAL_LPUART_GetRxState(LPUART_HandleTypeDef *hlpuart); +HAL_StatusTypeDef HAL_LPUART_Receive_To_IDLEorBCNT(LPUART_HandleTypeDef *hlpuart, uint8_t *buf, uint32_t size, + LPUART_Receive_Mode_Enum rece_mode, uint32_t timeout); + + +void HAL_LPUART_TxEmptyCallback(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_TxCompleteCallback(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_RxCompleteCallback(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_WakeupCallback(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_DMATxCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_LPUART_DMATxHalfCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_LPUART_DMATxErrorCallback(DMA_HandleTypeDef *hdma); +void HAL_LPUART_DMARxCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_LPUART_DMARxHalfCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_LPUART_DMARxErrorCallback(DMA_HandleTypeDef *hdma); +void HAL_LPUART_IdleCallback(LPUART_HandleTypeDef *hlpuart); +void HAL_LPUART_BcntCallback(LPUART_HandleTypeDef *hlpuart); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_ltdc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_ltdc.h new file mode 100644 index 0000000000000000000000000000000000000000..42358175960a787812cd0be5404ccaf2c3115af8 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_ltdc.h @@ -0,0 +1,925 @@ +/****************************************************************************** +*@file : hal_ltdc.h +*@brief : GPIO HAL module driver. +******************************************************************************/ + +#ifndef __HAL_LTDC_H__ +#define __HAL_LTDC_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "hal.h" + + + +/** @addtogroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + + +/******************** Bit definition for LTDC_SSCR register *****************/ +#define LTDC_SSCR_VSH_Pos (0U) +#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */ +#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */ +#define LTDC_SSCR_HSW_Pos (16U) +#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */ +#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */ + +/******************** Bit definition for LTDC_BPCR register *****************/ +#define LTDC_BPCR_AVBP_Pos (0U) +#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */ +#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */ +#define LTDC_BPCR_AHBP_Pos (16U) +#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */ +#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */ + +/******************** Bit definition for LTDC_AWCR register *****************/ +#define LTDC_AWCR_AAH_Pos (0U) +#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */ +#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */ +#define LTDC_AWCR_AAW_Pos (16U) +#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */ +#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */ + +/******************** Bit definition for LTDC_TWCR register *****************/ +#define LTDC_TWCR_TOTALH_Pos (0U) +#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */ +#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */ +#define LTDC_TWCR_TOTALW_Pos (16U) +#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */ +#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */ + +/******************** Bit definition for LTDC_GCR register ******************/ +#define LTDC_GCR_LTDCEN_Pos (0U) +#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */ +#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */ +#define LTDC_GCR_DBW_Pos (4U) +#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */ +#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */ +#define LTDC_GCR_DGW_Pos (8U) +#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */ +#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */ +#define LTDC_GCR_DRW_Pos (12U) +#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */ +#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */ +#define LTDC_GCR_DEN_Pos (16U) +#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */ +#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */ +#define LTDC_GCR_AHB_LOCK_Pos (17U) +#define LTDC_GCR_AHB_LOCK_Msk (0x1UL << LTDC_GCR_AHB_LOCK_Pos) /*!< 0x00020000 */ +#define LTDC_GCR_AHB_LOCK LTDC_GCR_AHB_LOCK_Msk /*!< AHB lock Enable */ +#define LTDC_GCR_PCPOL_Pos (28U) +#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */ +#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */ +#define LTDC_GCR_DEPOL_Pos (29U) +#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */ +#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */ +#define LTDC_GCR_VSPOL_Pos (30U) +#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */ +#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */ +#define LTDC_GCR_HSPOL_Pos (31U) +#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */ +#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */ + +/******************** Bit definition for LTDC_SRCR register *****************/ +#define LTDC_SRCR_IMR_Pos (0U) +#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */ +#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */ +#define LTDC_SRCR_VBR_Pos (1U) +#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */ +#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */ + +/******************** Bit definition for LTDC_BCCR register *****************/ +#define LTDC_BCCR_BCBLUE_Pos (0U) +#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */ +#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */ +#define LTDC_BCCR_BCGREEN_Pos (8U) +#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */ +#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */ +#define LTDC_BCCR_BCRED_Pos (16U) +#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */ +#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */ + +/******************** Bit definition for LTDC_IER register ******************/ +#define LTDC_IER_LIE_Pos (0U) +#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */ +#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */ +#define LTDC_IER_FUIE_Pos (1U) +#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */ +#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */ +#define LTDC_IER_TERRIE_Pos (2U) +#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */ +#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */ +#define LTDC_IER_RRIE_Pos (3U) +#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */ +#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */ + +/******************** Bit definition for LTDC_ISR register ******************/ +#define LTDC_ISR_LIF_Pos (0U) +#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */ +#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */ +#define LTDC_ISR_FUIF_Pos (1U) +#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */ +#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */ +#define LTDC_ISR_TERRIF_Pos (2U) +#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */ +#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */ +#define LTDC_ISR_RRIF_Pos (3U) +#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */ +#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */ + +/******************** Bit definition for LTDC_ICR register ******************/ +#define LTDC_ICR_CLIF_Pos (0U) +#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */ +#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */ +#define LTDC_ICR_CFUIF_Pos (1U) +#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */ +#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */ +#define LTDC_ICR_CTERRIF_Pos (2U) +#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */ +#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */ +#define LTDC_ICR_CRRIF_Pos (3U) +#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */ +#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */ + +/******************** Bit definition for LTDC_LIPCR register ****************/ +#define LTDC_LIPCR_LIPOS_Pos (0U) +#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */ +#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */ + +/******************** Bit definition for LTDC_CPSR register *****************/ +#define LTDC_CPSR_CYPOS_Pos (0U) +#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */ +#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */ +#define LTDC_CPSR_CXPOS_Pos (16U) +#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */ +#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */ + +/******************** Bit definition for LTDC_CDSR register *****************/ +#define LTDC_CDSR_VDES_Pos (0U) +#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */ +#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */ +#define LTDC_CDSR_HDES_Pos (1U) +#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */ +#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */ +#define LTDC_CDSR_VSYNCS_Pos (2U) +#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */ +#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */ +#define LTDC_CDSR_HSYNCS_Pos (3U) +#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */ +#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */ + +/******************** Bit definition for LTDC_LxCR register *****************/ +#define LTDC_LxCR_LEN_Pos (0U) +#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */ +#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */ +#define LTDC_LxCR_COLKEN_Pos (1U) +#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */ +#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */ +#define LTDC_LxCR_CLUTEN_Pos (4U) +#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */ +#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */ + +/******************** Bit definition for LTDC_LxWHPCR register **************/ +#define LTDC_LxWHPCR_WHSTPOS_Pos (0U) +#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */ +#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */ +#define LTDC_LxWHPCR_WHSPPOS_Pos (16U) +#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */ +#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */ + +/******************** Bit definition for LTDC_LxWVPCR register **************/ +#define LTDC_LxWVPCR_WVSTPOS_Pos (0U) +#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */ +#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */ +#define LTDC_LxWVPCR_WVSPPOS_Pos (16U) +#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */ +#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */ + +/******************** Bit definition for LTDC_LxCKCR register ***************/ +#define LTDC_LxCKCR_CKBLUE_Pos (0U) +#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */ +#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */ +#define LTDC_LxCKCR_CKGREEN_Pos (8U) +#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */ +#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */ +#define LTDC_LxCKCR_CKRED_Pos (16U) +#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */ +#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */ + +/******************** Bit definition for LTDC_LxPFCR register ***************/ +#define LTDC_LxPFCR_PF_Pos (0U) +#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */ +#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */ + +/******************** Bit definition for LTDC_LxCACR register ***************/ +#define LTDC_LxCACR_CONSTA_Pos (0U) +#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */ +#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */ + +/******************** Bit definition for LTDC_LxDCCR register ***************/ +#define LTDC_LxDCCR_DCBLUE_Pos (0U) +#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */ +#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */ +#define LTDC_LxDCCR_DCGREEN_Pos (8U) +#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */ +#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */ +#define LTDC_LxDCCR_DCRED_Pos (16U) +#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */ +#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */ +#define LTDC_LxDCCR_DCALPHA_Pos (24U) +#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */ +#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */ + +/******************** Bit definition for LTDC_LxBFCR register ***************/ +#define LTDC_LxBFCR_BF2_Pos (0U) +#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */ +#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */ +#define LTDC_LxBFCR_BF1_Pos (8U) +#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */ +#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */ + +/******************** Bit definition for LTDC_LxCFBAR register **************/ +#define LTDC_LxCFBAR_CFBADD_Pos (0U) +#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */ +#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */ + +/******************** Bit definition for LTDC_LxCFBLR register **************/ +#define LTDC_LxCFBLR_CFBLL_Pos (0U) +#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */ +#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */ +#define LTDC_LxCFBLR_CFBP_Pos (16U) +#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */ +#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */ + +/******************** Bit definition for LTDC_LxCFBLNR register *************/ +#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U) +#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */ +#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */ + +/******************** Bit definition for LTDC_LxCLUTWR register *************/ +#define LTDC_LxCLUTWR_BLUE_Pos (0U) +#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */ +#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */ +#define LTDC_LxCLUTWR_GREEN_Pos (8U) +#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */ +#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */ +#define LTDC_LxCLUTWR_RED_Pos (16U) +#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */ +#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */ +#define LTDC_LxCLUTWR_CLUTADD_Pos (24U) +#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ +#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ + + +/******************** Bit definition for RCC_PLL2CFR register *************/ +#define RCC_PLL2CR_Q_DIV_1 1 +#define RCC_PLL2CR_Q_DIV_2 2 +#define RCC_PLL2CR_Q_DIV_3 3 +#define RCC_PLL2CR_Q_DIV_4 4 +#define RCC_PLL2CR_Q_DIV_5 5 +#define RCC_PLL2CR_Q_DIV_6 6 +#define RCC_PLL2CR_Q_DIV_7 7 +#define RCC_PLL2CR_Q_DIV_8 8 +#define RCC_PLL2CR_Q_DIV_9 9 +#define RCC_PLL2CR_Q_DIV_10 10 +#define RCC_PLL2CR_Q_DIV_11 11 +#define RCC_PLL2CR_Q_DIV_12 12 +#define RCC_PLL2CR_Q_DIV_13 13 +#define RCC_PLL2CR_Q_DIV_14 14 +#define RCC_PLL2CR_Q_DIV_15 15 + + +/******************** Bit definition for RCC_DCKCFG register *************/ +#define RCC_DCKCFG_DIV_2 2 +#define RCC_DCKCFG_DIV_4 4 +#define RCC_DCKCFG_DIV_8 8 +#define RCC_DCKCFG_DIV_16 16 + + + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State enumeration definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +}HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +typedef struct +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +} LTDC_HandleTypeDef; +/** + * @} + */ + +typedef struct +{ + GPIO_TypeDef *pGPIO_Port; + uint16_t GPIO_Pin; + uint16_t GPIO_Alt; +}GPIO_CfgDef; + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE (0x00000000U) /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE (0x00000001U) /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU (0x00000002U) /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT (0x00000020U) /*!< LTDC Timeout error */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 (0x00000000U) /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 (0x00000001U) /*!< LTDC Layer 2 */ +/** + * @} + */ + + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL (0x00000000U) /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL (0x00000000U) /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL (0x00000000U) /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC (0x00000000U) /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR (0x000000FFU) /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA (0x00000400U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA (0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA (0x00000005U) /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA (0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 (0x00000000U) /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 (0x00000001U) /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 (0x00000002U) /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 (0x00000003U) /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 (0x00000004U) /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 (0x00000005U) /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 (0x00000006U) /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 (0x00000007U) /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE +#define LTDC_IT_FU LTDC_IER_FUIE +#define LTDC_IT_TE LTDC_IER_TERRIE +#define LTDC_IT_RR LTDC_IER_RRIE +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF +#define LTDC_FLAG_FU LTDC_ISR_FUIF +#define LTDC_FLAG_TE LTDC_ISR_TERRIF +#define LTDC_FLAG_RR LTDC_ISR_RRIF +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) + +/** + * @brief Enable the LTDC. + * @param __HANDLE__: LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__: LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__: LTDC handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__: LTDC handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__: LTDC handle + * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__: LTDC handle + * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__: LTDC handle + * @param __INTERRUPT__: specifies the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Clk_Div(uint8_t PLL2Q, uint8_t DckCfg); +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ERR_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Types LTDC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Variables LTDC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Constants LTDC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR2__) (((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_PAxCA)) + +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) + +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif //#ifdef __HAL_LTDC_H__ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_mdac.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_mdac.h new file mode 100644 index 0000000000000000000000000000000000000000..23f7acaf8db5bf2ef10070a6ff52606ad4a8d9ed --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_mdac.h @@ -0,0 +1,126 @@ +/* + ****************************************************************************** + * @file HAL_DAC.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of DAC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_DAC_H__ +#define __HAL_DAC_H__ + +#include "acm32h5xx_hal_conf.h" + + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + FunctionalState SelfCalibrateEn; + + FunctionalState SampleEn; /*!< Specifies voltage DAC sample and hold mode. + This parameter can be ENABLE or DISABLE */ +//use the trimvalue in NVR +// uint32_t TrimValue; /*!< Specifies the offset trimming value +// This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint32_t BufferMode; /*!< Specifies if voltage DAC output buffer is enabled or not. + This parameter can be MDAC_VDAC_BUFFER_ENABLE or MDAC_VDAC_BUFFER_DISABLE */ + +}VDAC_ChannelConfigTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + uint32_t ITurn; + +}IDAC_ChannelConfigTypeDef; + + +/** + * @brief MDAC handle Structure definition + */ +typedef struct +{ + MDAC_TypeDef *Instance; /*!< Register base address */ +}MDAC_HandleTypeDef; + + +#define MDAC_VDAC_BUFFER_ENABLE (0) +#define MDAC_VDAC_BUFFER_DISABLE (2) + +#define IS_MDAC_INSTANCE(INSTANCE) ((INSTANCE) == MDAC) + +#define IS_VDAC_CHANNEL_NUM(CH) ((CH) < 12) + +#define IS_VDAC_BUFFER_MODE(MODE) (((MODE) == MDAC_VDAC_BUFFER_ENABLE) || \ + (MODE) == MDAC_VDAC_BUFFER_DISABLE) + +#define IS_VDAC_TRIM_VALUE(VAL) ((VAL) < 31) + +#define IS_IDAC_CHANNEL_NUM(CH) ((CH) < 4) + +#define ITURN_FACTORY (32) + +#define IS_IDAC_ITURN(T) ((T) <= ITURN_FACTORY) + +#define MDAC_MAX_V_CHANNEL_NUM (12) +#define MDAC_MAX_I_CHANNEL_NUM (4) + + + + + /** @defgroup DAC_UserTrimming DAC User Trimming +* @{ +*/ + +#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ +#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ +#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ + ((TRIMMING) == DAC_TRIMMING_USER)) +#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) +/** + * @} + */ + + /** @defgroup DAC_Calibration + * @{ + */ + +#define DAC_Calibration_Disable 0x00000000U +#define DAC_Calibration_Enable 0x00000001U +#define IS_DAC_Calibration(Calibration) (((Calibration) == DAC_Calibration_Disable) || \ + ((Calibration) == DAC_Calibration_Enable)) + +#define IS_DAC_Calibration_TRIM(TRIM) ((TRIM) <= 0x1FU) +/** + * @} + */ + +/** + * @} + */ + + +void HAL_MDAC_MspInit(MDAC_HandleTypeDef *hMDAC); +__weak void HAL_MDAC_MspDeInit(MDAC_HandleTypeDef* hMDAC); + +HAL_StatusTypeDef HAL_MDAC_Init(MDAC_HandleTypeDef *hMDAC); +HAL_StatusTypeDef HAL_MDAC_DeInit(MDAC_HandleTypeDef *hMDAC); + +HAL_StatusTypeDef HAL_MDAC_ConfigVoltageChannel(MDAC_HandleTypeDef* hmdac, uint32_t Channel, VDAC_ChannelConfigTypeDef* Config); +HAL_StatusTypeDef HAL_MDAC_SetVoltageValue(MDAC_HandleTypeDef *hMDAC, uint32_t Channel, uint32_t Data); +uint32_t HAL_MDAC_GetVoltageValue(MDAC_HandleTypeDef* hMDAC, uint32_t Channel); + +HAL_StatusTypeDef HAL_MDAC_ConfigCurrentChannel(MDAC_HandleTypeDef* hmdac, uint32_t Channel, IDAC_ChannelConfigTypeDef* Config); +HAL_StatusTypeDef HAL_MDAC_SetCurrentValue(MDAC_HandleTypeDef *hMDAC, uint32_t Channel, uint32_t Data); +uint32_t HAL_MDAC_GetCurrentValue(MDAC_HandleTypeDef* hMDAC, uint32_t Channel); + +HAL_StatusTypeDef HAL_MDAC_SetVoltageTrim(MDAC_HandleTypeDef *hmdac, uint32_t Channel, uint32_t TrimVal); +uint32_t HAL_MDAC_GetVoltageTrimValue(MDAC_HandleTypeDef *hmdac, uint32_t Channel); + +HAL_StatusTypeDef HAL_MDAC_VoltageSelfcalibrate(MDAC_HandleTypeDef *hmdac, uint32_t Channel); +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_nand.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_nand.h new file mode 100644 index 0000000000000000000000000000000000000000..16e2a715affa0bf95ae1d48bdea9fc9fa978826b --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_nand.h @@ -0,0 +1,630 @@ + +/****************************************************************************** +*@file : hal_nand.h +*@brief : Header file for Nand module. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __HAL_NAND_H__ +#define __HAL_NAND_H__ + +#include "hal.h" + +/** @defgroup GPIO PORT + * @{ + */ + +/*Data Ports*/ +#define FMC_NAND_D0_GPIO_PORT GPIOD +#define FMC_NAND_D0_GPIO_PIN GPIO_PIN_14 + +#define FMC_NAND_D1_GPIO_PORT GPIOD +#define FMC_NAND_D1_GPIO_PIN GPIO_PIN_15 + +#define FMC_NAND_D2_GPIO_PORT GPIOD +#define FMC_NAND_D2_GPIO_PIN GPIO_PIN_0 + +#define FMC_NAND_D3_GPIO_PORT GPIOD +#define FMC_NAND_D3_GPIO_PIN GPIO_PIN_1 + +#define FMC_NAND_D4_GPIO_PORT GPIOE +#define FMC_NAND_D4_GPIO_PIN GPIO_PIN_7 + +#define FMC_NAND_D5_GPIO_PORT GPIOE +#define FMC_NAND_D5_GPIO_PIN GPIO_PIN_8 + +#define FMC_NAND_D6_GPIO_PORT GPIOE +#define FMC_NAND_D6_GPIO_PIN GPIO_PIN_9 + +#define FMC_NAND_D7_GPIO_PORT GPIOE +#define FMC_NAND_D7_GPIO_PIN GPIO_PIN_10 + +/*Control Ports*/ +#define FMC_NAND_CEN_GPIO_PORT GPIOG +#define FMC_NAND_CEN_GPIO_PIN GPIO_PIN_9 + +#define FMC_NAND_WEN_GPIO_PORT GPIOD +#define FMC_NAND_WEN_GPIO_PIN GPIO_PIN_5 + +#define FMC_NAND_REN_GPIO_PORT GPIOD +#define FMC_NAND_REN_GPIO_PIN GPIO_PIN_4 + +#define FMC_NAND_CLE_GPIO_PORT GPIOD +#define FMC_NAND_CLE_GPIO_PIN GPIO_PIN_11 + +#define FMC_NAND_ALE_GPIO_PORT GPIOD +#define FMC_NAND_ALE_GPIO_PIN GPIO_PIN_12 + +#define FMC_NAND_RBN_GPIO_PORT GPIOG +#define FMC_NAND_RBN_GPIO_PIN GPIO_PIN_7 +/** + * @} + */ + +/** @defgroup FMC_NAND CMD + * @{ + */ + +#define FMC_NAND_CMD_READ1 0x00 +#define FMC_NAND_CMD_READ2 0x30 +#define FMC_NAND_CMD_ID 0x90 +#define FMC_NAND_CMD_STATUS 0x70 +#define FMC_NAND_CMD_RESET 0xFF +#define FMC_NAND_CMD_PROGRAM1 0x80 +#define FMC_NAND_CMD_PROGRAM2 0x10 +#define FMC_NAND_CMD_ERASE1 0x60 +#define FMC_NAND_CMD_ERASE2 0xD0 +#define FMC_NAND_CMD_RANDOMINPUT 0x85 +#define FMC_NAND_CMD_RANDOMOUTPUT1 0x05 +#define FMC_NAND_CMD_RANDOMOUTPUT2 0xE0 +#define FMC_NAND_CMD_FEATURE 0xEF +/** + * @} + */ + +/** @defgroup FMC_NAND Private Macros + * @{ + */ + +#define IS_FMC_NAND_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND) + +/** + * @} + */ + +/** @defgroup FMC_NAND EDO_EN + * @{ + */ + #define FMC_NAND_EDO_EN (0x00000080U) /*!< EDO Enable */ + #define FMC_NAND_EDO_DIS (0x00000000U) /*!< EDO Disable */ + #define IS_FMC_NAND_EDO_EN(EN) (((EN) == FMC_NAND_EDO_EN || \ + ((EN) <= FMC_NAND_EDO_DIS))) +/** + * @} + */ + +/** @defgroup FMC_NAND RBN_INT EN + * @{ + */ + #define FMC_NAND_RBN_INT_EN (0x00000040U) /*!< RBN INT Enable */ + #define FMC_NAND_RBN_INT_DIS (0x00000000U) /*!< RBN INT Disable */ + #define IS_FMC_NAND_RBNINT_EN(EN) (((EN) == FMC_NAND_RBN_INT_EN || \ + ((EN) <= FMC_NAND_RBN_INT_DIS))) +/** + * @} + */ + +/** @defgroup FMC_NAND ENDIAN + * @{ + */ + #define FMC_NAND_ENDIAN_BIG (0x00000020U) /*!< Big Endian */ + #define FMC_NAND_ENDIAN_LITTLE (0x00000000U) /*!< Little Endian */ + #define IS_FMC_NAND_ENDIAN_EN(ENDIAN) (((ENDIAN) == FMC_NAND_ENDIAN_BIG || \ + ((ENDIAN) <= FMC_NAND_ENDIAN_LITTLE))) +/** + * @} + */ + +/** @defgroup FMC_NAND FWP + * @{ + */ + #define FMC_NAND_FWP_EN (0x00000000U) /*!< FWP Enable */ + #define FMC_NAND_FWP_DIS (0x00000010U) /*!< FWP Disable */ + #define IS_FMC_NAND_FWP_EN(FWP) (((FWP) == FMC_NAND_FWP_EN || \ + ((FWP) <= FMC_NAND_FWP_DIS))) +/** + * @} + */ + +/** @defgroup FMC_NAND FCE + * @{ + */ + #define FMC_NAND_FCE_EN (0x0000000eU) /*!< FCE Enable */ + #define FMC_NAND_FCE_DIS (0x0000000fU) /*!< FCE Disable */ + #define IS_FMC_NAND_FCE_EN(FCE) (((FCE) == FMC_NAND_FCE_EN || \ + ((FCE) <= FMC_NAND_FCE_DIS))) +/** + * @} + */ + +/** @defgroup tADL_Clock + * @{ + */ +#define FMC_NAND_TADL_NONE (0U) +#define FMC_NAND_TADL_1CLOCK (FMC_NAND_WST_TADL_0) +#define FMC_NAND_TADL_2CLOCK (FMC_NAND_WST_TADL_1) +#define FMC_NAND_TADL_3CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL_1) +#define FMC_NAND_TADL_4CLOCK (FMC_NAND_WST_TADL_2) +#define FMC_NAND_TADL_5CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL2) +#define FMC_NAND_TADL_6CLOCK (FMC_NAND_WST_TADL_1 | FMC_NAND_WST_TADL2) +#define FMC_NAND_TADL_7CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL1 | FMC_NAND_WST_TADL2) +#define FMC_NAND_TADL_8CLOCK (FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_9CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_10CLOCK (FMC_NAND_WST_TADL_1 | FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_11CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL_1 | FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_12CLOCK (FMC_NAND_WST_TADL_2 | FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_13CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL_2 | FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_14CLOCK (FMC_NAND_WST_TADL_1 | FMC_NAND_WST_TADL_2 | FMC_NAND_WST_TADL_3) +#define FMC_NAND_TADL_15CLOCK (FMC_NAND_WST_TADL_0 | FMC_NAND_WST_TADL_1 | FMC_NAND_WST_TADL_2 | FMC_NAND_WST_TADL_3) + +#define IS_FMC_NAND_TADL_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TADL_NONE || \ + ((CLOCK) == FMC_NAND_TADL_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TADL_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TADL_15CLOCK))) +/** + * @} + */ + +/** @defgroup tRHW_Clock + * @{ + */ +#define FMC_NAND_TRHW_NONE (0U) +#define FMC_NAND_TRHW_1CLOCK (FMC_NAND_WST_TRHW_0) +#define FMC_NAND_TRHW_2CLOCK (FMC_NAND_WST_TRHW_1) +#define FMC_NAND_TRHW_3CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_1) +#define FMC_NAND_TRHW_4CLOCK (FMC_NAND_WST_TRHW_2) +#define FMC_NAND_TRHW_5CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_2) +#define FMC_NAND_TRHW_6CLOCK (FMC_NAND_WST_TRHW_1 | FMC_NAND_WST_TRHW_2) +#define FMC_NAND_TRHW_7CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_1 | FMC_NAND_WST_TRHW_2) +#define FMC_NAND_TRHW_8CLOCK (FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_9CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_10CLOCK (FMC_NAND_WST_TRHW_1 | FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_11CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_1 | FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_12CLOCK (FMC_NAND_WST_TRHW_2 | FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_13CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_2 | FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_14CLOCK (FMC_NAND_WST_TRHW_1 | FMC_NAND_WST_TRHW_2 | FMC_NAND_WST_TRHW_3) +#define FMC_NAND_TRHW_15CLOCK (FMC_NAND_WST_TRHW_0 | FMC_NAND_WST_TRHW_1 | FMC_NAND_WST_TRHW_2 | FMC_NAND_WST_TRHW_3) + +#define IS_FMC_NAND_TRHW_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TRHW_NONE || \ + ((CLOCK) == FMC_NAND_TRHW_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TRHW_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TRHW_15CLOCK))) +/** + * @} + */ + +/** @defgroup tWHR_Clock + * @{ + */ +#define FMC_NAND_TWHR_NONE (0U) +#define FMC_NAND_TWHR_1CLOCK (FMC_NAND_WST_TWHR_0) +#define FMC_NAND_TWHR_2CLOCK (FMC_NAND_WST_TWHR_1) +#define FMC_NAND_TWHR_3CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_1) +#define FMC_NAND_TWHR_4CLOCK (FMC_NAND_WST_TWHR_2) +#define FMC_NAND_TWHR_5CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_2) +#define FMC_NAND_TWHR_6CLOCK (FMC_NAND_WST_TWHR_1 | FMC_NAND_WST_TWHR_2) +#define FMC_NAND_TWHR_7CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_1 | FMC_NAND_WST_TWHR_2) +#define FMC_NAND_TWHR_8CLOCK (FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_9CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_10CLOCK (FMC_NAND_WST_TWHR_1 | FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_11CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_1 | FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_12CLOCK (FMC_NAND_WST_TWHR_2 | FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_13CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_2 | FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_14CLOCK (FMC_NAND_WST_TWHR_1 | FMC_NAND_WST_TWHR_2 | FMC_NAND_WST_TWHR_3) +#define FMC_NAND_TWHR_15CLOCK (FMC_NAND_WST_TWHR_0 | FMC_NAND_WST_TWHR_1 | FMC_NAND_WST_TWHR_2 | FMC_NAND_WST_TWHR_3) + +#define IS_FMC_NAND_TWHR_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TWHR_NONE || \ + ((CLOCK) == FMC_NAND_TWHR_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TWHR_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TWHR_15CLOCK))) +/** + * @} + */ + + +/** @defgroup tREH_Clock + * @{ + */ +#define FMC_NAND_TREH_NONE (0U) +#define FMC_NAND_TREH_1CLOCK (FMC_NAND_WST_TREH_0) +#define FMC_NAND_TREH_2CLOCK (FMC_NAND_WST_TREH_1) +#define FMC_NAND_TREH_3CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_1) +#define FMC_NAND_TREH_4CLOCK (FMC_NAND_WST_TREH_2) +#define FMC_NAND_TREH_5CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_2) +#define FMC_NAND_TREH_6CLOCK (FMC_NAND_WST_TREH_1 | FMC_NAND_WST_TREH_2) +#define FMC_NAND_TREH_7CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_1 | FMC_NAND_WST_TREH_2) +#define FMC_NAND_TREH_8CLOCK (FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_9CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_10CLOCK (FMC_NAND_WST_TREH_1 | FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_11CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_1 | FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_12CLOCK (FMC_NAND_WST_TREH_2 | FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_13CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_2 | FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_14CLOCK (FMC_NAND_WST_TREH_1 | FMC_NAND_WST_TREH_2 | FMC_NAND_WST_TREH_3) +#define FMC_NAND_TREH_15CLOCK (FMC_NAND_WST_TREH_0 | FMC_NAND_WST_TREH_1 | FMC_NAND_WST_TREH_2 | FMC_NAND_WST_TREH_3) + +#define IS_FMC_NAND_TREH_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TREH_NONE || \ + ((CLOCK) == FMC_NAND_TREH_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TREH_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TREH_15CLOCK))) +/** + * @} + */ + + +/** @defgroup tRP_Clock + * @{ + */ +#define FMC_NAND_TRP_NONE (0U) +#define FMC_NAND_TRP_1CLOCK (FMC_NAND_WST_TRP_0) +#define FMC_NAND_TRP_2CLOCK (FMC_NAND_WST_TRP_1) +#define FMC_NAND_TRP_3CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_1) +#define FMC_NAND_TRP_4CLOCK (FMC_NAND_WST_TRP_2) +#define FMC_NAND_TRP_5CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_2) +#define FMC_NAND_TRP_6CLOCK (FMC_NAND_WST_TRP_1 | FMC_NAND_WST_TRP_2) +#define FMC_NAND_TRP_7CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_1 | FMC_NAND_WST_TRP_2) +#define FMC_NAND_TRP_8CLOCK (FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_9CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_10CLOCK (FMC_NAND_WST_TRP_1 | FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_11CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_1 | FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_12CLOCK (FMC_NAND_WST_TRP_2 | FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_13CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_2 | FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_14CLOCK (FMC_NAND_WST_TRP_1 | FMC_NAND_WST_TRP_2 | FMC_NAND_WST_TRP_3) +#define FMC_NAND_TRP_15CLOCK (FMC_NAND_WST_TRP_0 | FMC_NAND_WST_TRP_1 | FMC_NAND_WST_TRP_2 | FMC_NAND_WST_TRP_3) + +#define IS_FMC_NAND_TRP_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TRP_NONE || \ + ((CLOCK) == FMC_NAND_TRP_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TRP_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TRP_15CLOCK))) +/** + * @} + */ + +/** @defgroup tWH_Clock + * @{ + */ +#define FMC_NAND_TWH_NONE (0U) +#define FMC_NAND_TWH_1CLOCK (FMC_NAND_WST_TWH_0) +#define FMC_NAND_TWH_2CLOCK (FMC_NAND_WST_TWH_1) +#define FMC_NAND_TWH_3CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_1) +#define FMC_NAND_TWH_4CLOCK (FMC_NAND_WST_TWH_2) +#define FMC_NAND_TWH_5CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_2) +#define FMC_NAND_TWH_6CLOCK (FMC_NAND_WST_TWH_1 | FMC_NAND_WST_TWH_2) +#define FMC_NAND_TWH_7CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_1 | FMC_NAND_WST_TWH_2) +#define FMC_NAND_TWH_8CLOCK (FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_9CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_10CLOCK (FMC_NAND_WST_TWH_1 | FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_11CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_1 | FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_12CLOCK (FMC_NAND_WST_TWH_2 | FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_13CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_2 | FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_14CLOCK (FMC_NAND_WST_TWH_1 | FMC_NAND_WST_TWH_2 | FMC_NAND_WST_TWH_3) +#define FMC_NAND_TWH_15CLOCK (FMC_NAND_WST_TWH_0 | FMC_NAND_WST_TWH_1 | FMC_NAND_WST_TWH_2 | FMC_NAND_WST_TWH_3) + +#define IS_FMC_NAND_TWH_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TWH_NONE || \ + ((CLOCK) == FMC_NAND_TWH_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TWH_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TWH_15CLOCK))) +/** + * @} + */ + +/** @defgroup tWP_Clock + * @{ + */ +#define FMC_NAND_TWP_NONE (0U) +#define FMC_NAND_TWP_1CLOCK (FMC_NAND_WST_TWP_0) +#define FMC_NAND_TWP_2CLOCK (FMC_NAND_WST_TWP_1) +#define FMC_NAND_TWP_3CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_1) +#define FMC_NAND_TWP_4CLOCK (FMC_NAND_WST_TWP_2) +#define FMC_NAND_TWP_5CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_2) +#define FMC_NAND_TWP_6CLOCK (FMC_NAND_WST_TWP_1 | FMC_NAND_WST_TWP_2) +#define FMC_NAND_TWP_7CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_1 | FMC_NAND_WST_TWP_2) +#define FMC_NAND_TWP_8CLOCK (FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_9CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_10CLOCK (FMC_NAND_WST_TWP_1 | FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_11CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_1 | FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_12CLOCK (FMC_NAND_WST_TWP_2 | FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_13CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_2 | FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_14CLOCK (FMC_NAND_WST_TWP_1 | FMC_NAND_WST_TWP_2 | FMC_NAND_WST_TWP_3) +#define FMC_NAND_TWP_15CLOCK (FMC_NAND_WST_TWP_0 | FMC_NAND_WST_TWP_1 | FMC_NAND_WST_TWP_2 | FMC_NAND_WST_TWP_3) + +#define IS_FMC_NAND_TWP_CLOCK(CLOCK) (((CLOCK) == FMC_NAND_TWP_NONE || \ + ((CLOCK) == FMC_NAND_TWP_1CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_2CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_3CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_4CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_5CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_6CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_7CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_8CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_9CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_10CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_11CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_12CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_13CLOCK) || \ + ((CLOCK) == FMC_NAND_TWP_14CLOCK) || \ + ((CLOCK) <= FMC_NAND_TWP_15CLOCK))) +/** + * @} + */ + +/** @defgroup FMC_NAND CMD + * @{ + */ + +#define FMC_NAND_CMD_READ1 0x00 +#define FMC_NAND_CMD_READ2 0x30 +#define FMC_NAND_CMD_ID 0x90 +#define FMC_NAND_CMD_STATUS 0x70 +#define FMC_NAND_CMD_RESET 0xFF +#define FMC_NAND_CMD_PROGRAM1 0x80 +#define FMC_NAND_CMD_PROGRAM2 0x10 +#define FMC_NAND_CMD_ERASE1 0x60 +#define FMC_NAND_CMD_ERASE2 0xD0 +#define FMC_NAND_CMD_RANDOMINPUT 0x85 +#define FMC_NAND_CMD_RANDOMOUTPUT1 0x05 +#define FMC_NAND_CMD_RANDOMOUTPUT2 0xE0 +#define FMC_NAND_CMD_FEATURE 0xEF + +/** + * @} + */ + + +/** @defgroup BCH DATA LEN + * @{ + */ + +#define BCH_SECTOR_SIZE 0x200 +#define BCH_INF_SIZE 0x3 +#define BCH_ECC_SIZE 0xD + +/** + * @} + */ + +/** @defgroup BCH ECC MODE + * @{ + */ + +#define BCH_ECC_MODE_EN 0x1 +#define BCH_ECC_MODE_DIS 0x0 + +/** + * @} + */ + +/** @defgroup BCH CHANNEL RST + * @{ + */ + +#define BCH_CHANNEL_RST 0x1 + +/** + * @} + */ + + +/* + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t EDO_EN; /*!< This member controls the EDO mode. */ + + uint32_t RBN_INTEN; /*!< This member controls the RBN INT. */ + + uint32_t ENDIAN; /*!< This member controls Big/Little endian. */ + + uint32_t FWP; /*!< This member controls the FWP mode. */ + + uint32_t FCE; /*!< This member controls the FCE mode. */ + + uint32_t TADL; /*!< Specifies the tADL value*/ + + uint32_t TRHW; /*!< Specifies the tRHW value*/ + + uint32_t TWHR; /*!< Specifies the tWHR value*/ + + uint32_t TREH; /*!< Specifies the tREH value*/ + + uint32_t TRP; /*!< Specifies the tRP value*/ + + uint32_t TWH; /*!< Specifies the tTWH value*/ + + uint32_t TWP; /*!< Specifies the tWP value*/ + +}FMC_NAND_InitTypeDef; + +/* + * @brief UART handle Structure definition + */ +typedef struct +{ + FMC_NAND_TypeDef *Instance; /*!< FMA Nand registers base address */ + + FMC_NAND_InitTypeDef Init; /*!< FMA Nand parameters */ + + void* FMC_NAND_Data_Buff; /*!< FMA Nand databuff base address */ + + uint32_t FMC_NAND_Data_Len; /*!< amount of CRC data to be calculated */ + +}FMC_NAND_HandleTypeDef; + +/****************************************************************************** +*@brief : Initialize nand MSP: CLK, GPIO, NVIC +* +*@param : hnand: handle with nand parameters. +*@return: None +******************************************************************************/ +void HAL_FMC_NAND_MspInit(FMC_NAND_HandleTypeDef *hnand); + +/****************************************************************************** +*@brief : Initialize nandaccording to the specified parameters in hnand. +* +*@param : hnand: handle with nand parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Init(FMC_NAND_HandleTypeDef *hnand); + +/****************************************************************************** +*@brief : Reset Nand Flash +* +*@param : hnand: handle with nand Nand parameters. +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashReset(FMC_NAND_HandleTypeDef *hnand); + +/****************************************************************************** +*@brief : Read ID from Nand Flash +* +*@param : hnand: handle with nand parameters. +*@param : rdata: start address to store ID +*@param : lenth: ID length +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashGetID(FMC_NAND_HandleTypeDef *hnand, uint8_t rdata[], uint8_t lenth); + +/****************************************************************************** +*@brief : Erase a block +* +*@param : hnand: handle with nand parameters. +*@param : BlockAddr: start address of the block to erase +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashErase(FMC_NAND_HandleTypeDef *hnand, uint32_t PageAddr); + +/****************************************************************************** +*@brief : Program one sector(512 bytes) +* +*@param : hnand: handle with nand parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : wdata: start address of data to program +*@param : ecc_en:select the mode of program + BCH_ECC_MODE_EN : program with ecc mode + BCH_ECC_MODE_DIS: progran with no ecc mode +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Flash_Program(FMC_NAND_HandleTypeDef *hnand, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t wdata[], uint8_t ecc_en); + +/****************************************************************************** +*@brief : Program one sector(512 bytes) using necc channel and ecc data +* +*@param : hnand: handle with nand parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : wdata: start address of data to program +*@param : pEccByte: input ecc data +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Flash_Program_NECC_with_ECC_CODE(FMC_NAND_HandleTypeDef *hnand, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t wdata[], uint8_t pEccByte[]); + +/****************************************************************************** +*@brief : Read one sector(512 bytes) +* +*@param : hnand: handle with nand parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : rdata: start address of read data +*@param : ecc_en:select the mode of read + BCH_ECC_MODE_EN : read with ecc mode + BCH_ECC_MODE_DIS: read with no ecc mode +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashRead(FMC_NAND_HandleTypeDef *hnand, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t rdata[], uint8_t ecc_en); + + +/****************************************************************************** +*@brief : Reset ECC Channel +* +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Reset_ECC_Channel(FMC_NAND_HandleTypeDef *hnand); +#endif + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_nfm.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_nfm.h new file mode 100644 index 0000000000000000000000000000000000000000..988cc44337706520e4c075f2a798f9dc3e10df3b --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_nfm.h @@ -0,0 +1,602 @@ + +/****************************************************************************** +*@file : hal_nfm.h +*@brief : Header file for NFM module. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#ifndef __HAL_NFM_H__ +#define __HAL_NFM_H__ + +#include "hal.h" + +/** @defgroup GPIO PORT + * @{ + */ + +/*Data Ports*/ +#define FMC_D0_GPIO_PORT GPIOD +#define FMC_D0_GPIO_PIN GPIO_PIN_14 + +#define FMC_D1_GPIO_PORT GPIOD +#define FMC_D1_GPIO_PIN GPIO_PIN_15 + +#define FMC_D2_GPIO_PORT GPIOD +#define FMC_D2_GPIO_PIN GPIO_PIN_0 + +#define FMC_D3_GPIO_PORT GPIOD +#define FMC_D3_GPIO_PIN GPIO_PIN_1 + +#define FMC_D4_GPIO_PORT GPIOE +#define FMC_D4_GPIO_PIN GPIO_PIN_7 + +#define FMC_D5_GPIO_PORT GPIOE +#define FMC_D5_GPIO_PIN GPIO_PIN_8 + +#define FMC_D6_GPIO_PORT GPIOE +#define FMC_D6_GPIO_PIN GPIO_PIN_9 + +#define FMC_D7_GPIO_PORT GPIOE +#define FMC_D7_GPIO_PIN GPIO_PIN_10 + +/*Control Ports*/ +#define FMC_CEN_GPIO_PORT GPIOG +#define FMC_CEN_GPIO_PIN GPIO_PIN_9 + +#define FMC_WEN_GPIO_PORT GPIOD +#define FMC_WEN_GPIO_PIN GPIO_PIN_5 + +#define FMC_REN_GPIO_PORT GPIOD +#define FMC_REN_GPIO_PIN GPIO_PIN_4 + +#define FMC_CLE_GPIO_PORT GPIOD +#define FMC_CLE_GPIO_PIN GPIO_PIN_11 + +#define FMC_ALE_GPIO_PORT GPIOD +#define FMC_ALE_GPIO_PIN GPIO_PIN_12 + +#define FMC_RBN_GPIO_PORT GPIOG +#define FMC_RBN_GPIO_PIN GPIO_PIN_7 +/** + * @} + */ + +/** @defgroup NFM CMD + * @{ + */ + +#define NFM_CMD_READ1 0x00 +#define NFM_CMD_READ2 0x30 +#define NFM_CMD_ID 0x90 +#define NFM_CMD_STATUS 0x70 +#define NFM_CMD_RESET 0xFF +#define NFM_CMD_PROGRAM1 0x80 +#define NFM_CMD_PROGRAM2 0x10 +#define NFM_CMD_ERASE1 0x60 +#define NFM_CMD_ERASE2 0xD0 +#define NFM_CMD_RANDOMINPUT 0x85 +#define NFM_CMD_RANDOMOUTPUT1 0x05 +#define NFM_CMD_RANDOMOUTPUT2 0xE0 +#define NFM_CMD_FEATURE 0xEF +/** + * @} + */ + +/** @defgroup NFM Private Macros + * @{ + */ + +#define IS_NFM_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == NFM) + +/** + * @} + */ + +/** @defgroup NFM EDO_EN + * @{ + */ + #define NFM_EDO_EN (0x00000080U) /*!< EDO Enable */ + #define NFM_EDO_DIS (0x00000000U) /*!< EDO Disable */ + #define IS_NFM_EDO_EN(EN) (((EN) == NFM_EDO_EN || \ + ((EN) <= NFM_EDO_DIS))) +/** + * @} + */ + +/** @defgroup NFM RBN_INT EN + * @{ + */ + #define NFM_RBN_INT_EN (0x00000040U) /*!< RBN INT Enable */ + #define NFM_RBN_INT_DIS (0x00000000U) /*!< RBN INT Disable */ + #define IS_NFM_RBNINT_EN(EN) (((EN) == NFM_RBN_INT_EN || \ + ((EN) <= NFM_RBN_INT_DIS))) +/** + * @} + */ + +/** @defgroup NFM ENDIAN + * @{ + */ + #define NFM_ENDIAN_BIG (0x00000020U) /*!< Big Endian */ + #define NFM_ENDIAN_LITTLE (0x00000000U) /*!< Little Endian */ + #define IS_NFM_ENDIAN_EN(ENDIAN) (((ENDIAN) == NFM_ENDIAN_BIG || \ + ((ENDIAN) <= NFM_ENDIAN_LITTLE))) +/** + * @} + */ + +/** @defgroup NFM FWP + * @{ + */ + #define NFM_FWP_EN (0x00000000U) /*!< FWP Enable */ + #define NFM_FWP_DIS (0x00000010U) /*!< FWP Disable */ + #define IS_NFM_FWP_EN(FWP) (((FWP) == NFM_FWP_EN || \ + ((FWP) <= NFM_FWP_DIS))) +/** + * @} + */ + +/** @defgroup NFM FCE + * @{ + */ + #define NFM_FCE_EN (0x0000000eU) /*!< FCE Enable */ + #define NFM_FCE_DIS (0x0000000fU) /*!< FCE Disable */ + #define IS_NFM_FCE_EN(FCE) (((FCE) == NFM_FCE_EN || \ + ((FCE) <= NFM_FCE_DIS))) +/** + * @} + */ + +/** @defgroup tADL_Clock + * @{ + */ +#define NFM_TADL_NONE (0U) +#define NFM_TADL_1CLOCK (NFM_NFMWST_TADL_0) +#define NFM_TADL_2CLOCK (NFM_NFMWST_TADL_1) +#define NFM_TADL_3CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_1) +#define NFM_TADL_4CLOCK (NFM_NFMWST_TADL_2) +#define NFM_TADL_5CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_2) +#define NFM_TADL_6CLOCK (NFM_NFMWST_TADL_1 | NFM_NFMWST_TADL_2) +#define NFM_TADL_7CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_1 | NFM_NFMWST_TADL_2) +#define NFM_TADL_8CLOCK (NFM_NFMWST_TADL_3) +#define NFM_TADL_9CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_3) +#define NFM_TADL_10CLOCK (NFM_NFMWST_TADL_1 | NFM_NFMWST_TADL_3) +#define NFM_TADL_11CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_1 | NFM_NFMWST_TADL_3) +#define NFM_TADL_12CLOCK (NFM_NFMWST_TADL_2 | NFM_NFMWST_TADL_3) +#define NFM_TADL_13CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_2 | NFM_NFMWST_TADL_3) +#define NFM_TADL_14CLOCK (NFM_NFMWST_TADL_1 | NFM_NFMWST_TADL_2 | NFM_NFMWST_TADL_3) +#define NFM_TADL_15CLOCK (NFM_NFMWST_TADL_0 | NFM_NFMWST_TADL_1 | NFM_NFMWST_TADL_2 | NFM_NFMWST_TADL_3) + +#define IS_NFM_TADL_CLOCK(CLOCK) (((CLOCK) == NFM_TADL_NONE || \ + ((CLOCK) == NFM_TADL_1CLOCK) || \ + ((CLOCK) == NFM_TADL_2CLOCK) || \ + ((CLOCK) == NFM_TADL_3CLOCK) || \ + ((CLOCK) == NFM_TADL_4CLOCK) || \ + ((CLOCK) == NFM_TADL_5CLOCK) || \ + ((CLOCK) == NFM_TADL_6CLOCK) || \ + ((CLOCK) == NFM_TADL_7CLOCK) || \ + ((CLOCK) == NFM_TADL_8CLOCK) || \ + ((CLOCK) == NFM_TADL_9CLOCK) || \ + ((CLOCK) == NFM_TADL_10CLOCK) || \ + ((CLOCK) == NFM_TADL_11CLOCK) || \ + ((CLOCK) == NFM_TADL_12CLOCK) || \ + ((CLOCK) == NFM_TADL_13CLOCK) || \ + ((CLOCK) == NFM_TADL_14CLOCK) || \ + ((CLOCK) <= NFM_TADL_15CLOCK))) +/** + * @} + */ + +/** @defgroup tRHW_Clock + * @{ + */ +#define NFM_TRHW_NONE (0U) +#define NFM_TRHW_1CLOCK (NFM_NFMWST_TRHW_0) +#define NFM_TRHW_2CLOCK (NFM_NFMWST_TRHW_1) +#define NFM_TRHW_3CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_1) +#define NFM_TRHW_4CLOCK (NFM_NFMWST_TRHW_2) +#define NFM_TRHW_5CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_2) +#define NFM_TRHW_6CLOCK (NFM_NFMWST_TRHW_1 | NFM_NFMWST_TRHW_2) +#define NFM_TRHW_7CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_1 | NFM_NFMWST_TRHW_2) +#define NFM_TRHW_8CLOCK (NFM_NFMWST_TRHW_3) +#define NFM_TRHW_9CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_3) +#define NFM_TRHW_10CLOCK (NFM_NFMWST_TRHW_1 | NFM_NFMWST_TRHW_3) +#define NFM_TRHW_11CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_1 | NFM_NFMWST_TRHW_3) +#define NFM_TRHW_12CLOCK (NFM_NFMWST_TRHW_2 | NFM_NFMWST_TRHW_3) +#define NFM_TRHW_13CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_2 | NFM_NFMWST_TRHW_3) +#define NFM_TRHW_14CLOCK (NFM_NFMWST_TRHW_1 | NFM_NFMWST_TRHW_2 | NFM_NFMWST_TRHW_3) +#define NFM_TRHW_15CLOCK (NFM_NFMWST_TRHW_0 | NFM_NFMWST_TRHW_1 | NFM_NFMWST_TRHW_2 | NFM_NFMWST_TRHW_3) + +#define IS_NFM_TRHW_CLOCK(CLOCK) (((CLOCK) == NFM_TRHW_NONE || \ + ((CLOCK) == NFM_TRHW_1CLOCK) || \ + ((CLOCK) == NFM_TRHW_2CLOCK) || \ + ((CLOCK) == NFM_TRHW_3CLOCK) || \ + ((CLOCK) == NFM_TRHW_4CLOCK) || \ + ((CLOCK) == NFM_TRHW_5CLOCK) || \ + ((CLOCK) == NFM_TRHW_6CLOCK) || \ + ((CLOCK) == NFM_TRHW_7CLOCK) || \ + ((CLOCK) == NFM_TRHW_8CLOCK) || \ + ((CLOCK) == NFM_TRHW_9CLOCK) || \ + ((CLOCK) == NFM_TRHW_10CLOCK) || \ + ((CLOCK) == NFM_TRHW_11CLOCK) || \ + ((CLOCK) == NFM_TRHW_12CLOCK) || \ + ((CLOCK) == NFM_TRHW_13CLOCK) || \ + ((CLOCK) == NFM_TRHW_14CLOCK) || \ + ((CLOCK) <= NFM_TRHW_15CLOCK))) +/** + * @} + */ + +/** @defgroup tWHR_Clock + * @{ + */ +#define NFM_TWHR_NONE (0U) +#define NFM_TWHR_1CLOCK (NFM_NFMWST_TWHR_0) +#define NFM_TWHR_2CLOCK (NFM_NFMWST_TWHR_1) +#define NFM_TWHR_3CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_1) +#define NFM_TWHR_4CLOCK (NFM_NFMWST_TWHR_2) +#define NFM_TWHR_5CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_2) +#define NFM_TWHR_6CLOCK (NFM_NFMWST_TWHR_1 | NFM_NFMWST_TWHR_2) +#define NFM_TWHR_7CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_1 | NFM_NFMWST_TWHR_2) +#define NFM_TWHR_8CLOCK (NFM_NFMWST_TWHR_3) +#define NFM_TWHR_9CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_3) +#define NFM_TWHR_10CLOCK (NFM_NFMWST_TWHR_1 | NFM_NFMWST_TWHR_3) +#define NFM_TWHR_11CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_1 | NFM_NFMWST_TWHR_3) +#define NFM_TWHR_12CLOCK (NFM_NFMWST_TWHR_2 | NFM_NFMWST_TWHR_3) +#define NFM_TWHR_13CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_2 | NFM_NFMWST_TWHR_3) +#define NFM_TWHR_14CLOCK (NFM_NFMWST_TWHR_1 | NFM_NFMWST_TWHR_2 | NFM_NFMWST_TWHR_3) +#define NFM_TWHR_15CLOCK (NFM_NFMWST_TWHR_0 | NFM_NFMWST_TWHR_1 | NFM_NFMWST_TWHR_2 | NFM_NFMWST_TWHR_3) + +#define IS_NFM_TWHR_CLOCK(CLOCK) (((CLOCK) == NFM_TWHR_NONE || \ + ((CLOCK) == NFM_TWHR_1CLOCK) || \ + ((CLOCK) == NFM_TWHR_2CLOCK) || \ + ((CLOCK) == NFM_TWHR_3CLOCK) || \ + ((CLOCK) == NFM_TWHR_4CLOCK) || \ + ((CLOCK) == NFM_TWHR_5CLOCK) || \ + ((CLOCK) == NFM_TWHR_6CLOCK) || \ + ((CLOCK) == NFM_TWHR_7CLOCK) || \ + ((CLOCK) == NFM_TWHR_8CLOCK) || \ + ((CLOCK) == NFM_TWHR_9CLOCK) || \ + ((CLOCK) == NFM_TWHR_10CLOCK) || \ + ((CLOCK) == NFM_TWHR_11CLOCK) || \ + ((CLOCK) == NFM_TWHR_12CLOCK) || \ + ((CLOCK) == NFM_TWHR_13CLOCK) || \ + ((CLOCK) == NFM_TWHR_14CLOCK) || \ + ((CLOCK) <= NFM_TWHR_15CLOCK))) +/** + * @} + */ + + +/** @defgroup tREH_Clock + * @{ + */ +#define NFM_TREH_NONE (0U) +#define NFM_TREH_1CLOCK (NFM_NFMWST_TREH_0) +#define NFM_TREH_2CLOCK (NFM_NFMWST_TREH_1) +#define NFM_TREH_3CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_1) +#define NFM_TREH_4CLOCK (NFM_NFMWST_TREH_2) +#define NFM_TREH_5CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_2) +#define NFM_TREH_6CLOCK (NFM_NFMWST_TREH_1 | NFM_NFMWST_TREH_2) +#define NFM_TREH_7CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_1 | NFM_NFMWST_TREH_2) +#define NFM_TREH_8CLOCK (NFM_NFMWST_TREH_3) +#define NFM_TREH_9CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_3) +#define NFM_TREH_10CLOCK (NFM_NFMWST_TREH_1 | NFM_NFMWST_TREH_3) +#define NFM_TREH_11CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_1 | NFM_NFMWST_TREH_3) +#define NFM_TREH_12CLOCK (NFM_NFMWST_TREH_2 | NFM_NFMWST_TREH_3) +#define NFM_TREH_13CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_2 | NFM_NFMWST_TREH_3) +#define NFM_TREH_14CLOCK (NFM_NFMWST_TREH_1 | NFM_NFMWST_TREH_2 | NFM_NFMWST_TREH_3) +#define NFM_TREH_15CLOCK (NFM_NFMWST_TREH_0 | NFM_NFMWST_TREH_1 | NFM_NFMWST_TREH_2 | NFM_NFMWST_TREH_3) + +#define IS_NFM_TREH_CLOCK(CLOCK) (((CLOCK) == NFM_TREH_NONE || \ + ((CLOCK) == NFM_TREH_1CLOCK) || \ + ((CLOCK) == NFM_TREH_2CLOCK) || \ + ((CLOCK) == NFM_TREH_3CLOCK) || \ + ((CLOCK) == NFM_TREH_4CLOCK) || \ + ((CLOCK) == NFM_TREH_5CLOCK) || \ + ((CLOCK) == NFM_TREH_6CLOCK) || \ + ((CLOCK) == NFM_TREH_7CLOCK) || \ + ((CLOCK) == NFM_TREH_8CLOCK) || \ + ((CLOCK) == NFM_TREH_9CLOCK) || \ + ((CLOCK) == NFM_TREH_10CLOCK) || \ + ((CLOCK) == NFM_TREH_11CLOCK) || \ + ((CLOCK) == NFM_TREH_12CLOCK) || \ + ((CLOCK) == NFM_TREH_13CLOCK) || \ + ((CLOCK) == NFM_TREH_14CLOCK) || \ + ((CLOCK) <= NFM_TREH_15CLOCK))) +/** + * @} + */ + + +/** @defgroup tRP_Clock + * @{ + */ +#define NFM_TRP_NONE (0U) +#define NFM_TRP_1CLOCK (NFM_NFMWST_TRP_0) +#define NFM_TRP_2CLOCK (NFM_NFMWST_TRP_1) +#define NFM_TRP_3CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_1) +#define NFM_TRP_4CLOCK (NFM_NFMWST_TRP_2) +#define NFM_TRP_5CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_2) +#define NFM_TRP_6CLOCK (NFM_NFMWST_TRP_1 | NFM_NFMWST_TRP_2) +#define NFM_TRP_7CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_1 | NFM_NFMWST_TRP_2) +#define NFM_TRP_8CLOCK (NFM_NFMWST_TRP_3) +#define NFM_TRP_9CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_3) +#define NFM_TRP_10CLOCK (NFM_NFMWST_TRP_1 | NFM_NFMWST_TRP_3) +#define NFM_TRP_11CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_1 | NFM_NFMWST_TRP_3) +#define NFM_TRP_12CLOCK (NFM_NFMWST_TRP_2 | NFM_NFMWST_TRP_3) +#define NFM_TRP_13CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_2 | NFM_NFMWST_TRP_3) +#define NFM_TRP_14CLOCK (NFM_NFMWST_TRP_1 | NFM_NFMWST_TRP_2 | NFM_NFMWST_TRP_3) +#define NFM_TRP_15CLOCK (NFM_NFMWST_TRP_0 | NFM_NFMWST_TRP_1 | NFM_NFMWST_TRP_2 | NFM_NFMWST_TRP_3) + +#define IS_NFM_TRP_CLOCK(CLOCK) (((CLOCK) == NFM_TRP_NONE || \ + ((CLOCK) == NFM_TRP_1CLOCK) || \ + ((CLOCK) == NFM_TRP_2CLOCK) || \ + ((CLOCK) == NFM_TRP_3CLOCK) || \ + ((CLOCK) == NFM_TRP_4CLOCK) || \ + ((CLOCK) == NFM_TRP_5CLOCK) || \ + ((CLOCK) == NFM_TRP_6CLOCK) || \ + ((CLOCK) == NFM_TRP_7CLOCK) || \ + ((CLOCK) == NFM_TRP_8CLOCK) || \ + ((CLOCK) == NFM_TRP_9CLOCK) || \ + ((CLOCK) == NFM_TRP_10CLOCK) || \ + ((CLOCK) == NFM_TRP_11CLOCK) || \ + ((CLOCK) == NFM_TRP_12CLOCK) || \ + ((CLOCK) == NFM_TRP_13CLOCK) || \ + ((CLOCK) == NFM_TRP_14CLOCK) || \ + ((CLOCK) <= NFM_TRP_15CLOCK))) +/** + * @} + */ + +/** @defgroup tWH_Clock + * @{ + */ +#define NFM_TWH_NONE (0U) +#define NFM_TWH_1CLOCK (NFM_NFMWST_TWH_0) +#define NFM_TWH_2CLOCK (NFM_NFMWST_TWH_1) +#define NFM_TWH_3CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_1) +#define NFM_TWH_4CLOCK (NFM_NFMWST_TWH_2) +#define NFM_TWH_5CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_2) +#define NFM_TWH_6CLOCK (NFM_NFMWST_TWH_1 | NFM_NFMWST_TWH_2) +#define NFM_TWH_7CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_1 | NFM_NFMWST_TWH_2) +#define NFM_TWH_8CLOCK (NFM_NFMWST_TWH_3) +#define NFM_TWH_9CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_3) +#define NFM_TWH_10CLOCK (NFM_NFMWST_TWH_1 | NFM_NFMWST_TWH_3) +#define NFM_TWH_11CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_1 | NFM_NFMWST_TWH_3) +#define NFM_TWH_12CLOCK (NFM_NFMWST_TWH_2 | NFM_NFMWST_TWH_3) +#define NFM_TWH_13CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_2 | NFM_NFMWST_TWH_3) +#define NFM_TWH_14CLOCK (NFM_NFMWST_TWH_1 | NFM_NFMWST_TWH_2 | NFM_NFMWST_TWH_3) +#define NFM_TWH_15CLOCK (NFM_NFMWST_TWH_0 | NFM_NFMWST_TWH_1 | NFM_NFMWST_TWH_2 | NFM_NFMWST_TWH_3) + +#define IS_NFM_TWH_CLOCK(CLOCK) (((CLOCK) == NFM_TWH_NONE || \ + ((CLOCK) == NFM_TWH_1CLOCK) || \ + ((CLOCK) == NFM_TWH_2CLOCK) || \ + ((CLOCK) == NFM_TWH_3CLOCK) || \ + ((CLOCK) == NFM_TWH_4CLOCK) || \ + ((CLOCK) == NFM_TWH_5CLOCK) || \ + ((CLOCK) == NFM_TWH_6CLOCK) || \ + ((CLOCK) == NFM_TWH_7CLOCK) || \ + ((CLOCK) == NFM_TWH_8CLOCK) || \ + ((CLOCK) == NFM_TWH_9CLOCK) || \ + ((CLOCK) == NFM_TWH_10CLOCK) || \ + ((CLOCK) == NFM_TWH_11CLOCK) || \ + ((CLOCK) == NFM_TWH_12CLOCK) || \ + ((CLOCK) == NFM_TWH_13CLOCK) || \ + ((CLOCK) == NFM_TWH_14CLOCK) || \ + ((CLOCK) <= NFM_TWH_15CLOCK))) +/** + * @} + */ + +/** @defgroup tWP_Clock + * @{ + */ +#define NFM_TWP_NONE (0U) +#define NFM_TWP_1CLOCK (NFM_NFMWST_TWP_0) +#define NFM_TWP_2CLOCK (NFM_NFMWST_TWP_1) +#define NFM_TWP_3CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_1) +#define NFM_TWP_4CLOCK (NFM_NFMWST_TWP_2) +#define NFM_TWP_5CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_2) +#define NFM_TWP_6CLOCK (NFM_NFMWST_TWP_1 | NFM_NFMWST_TWP_2) +#define NFM_TWP_7CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_1 | NFM_NFMWST_TWP_2) +#define NFM_TWP_8CLOCK (NFM_NFMWST_TWP_3) +#define NFM_TWP_9CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_3) +#define NFM_TWP_10CLOCK (NFM_NFMWST_TWP_1 | NFM_NFMWST_TWP_3) +#define NFM_TWP_11CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_1 | NFM_NFMWST_TWP_3) +#define NFM_TWP_12CLOCK (NFM_NFMWST_TWP_2 | NFM_NFMWST_TWP_3) +#define NFM_TWP_13CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_2 | NFM_NFMWST_TWP_3) +#define NFM_TWP_14CLOCK (NFM_NFMWST_TWP_1 | NFM_NFMWST_TWP_2 | NFM_NFMWST_TWP_3) +#define NFM_TWP_15CLOCK (NFM_NFMWST_TWP_0 | NFM_NFMWST_TWP_1 | NFM_NFMWST_TWP_2 | NFM_NFMWST_TWP_3) + +#define IS_NFM_TWP_CLOCK(CLOCK) (((CLOCK) == NFM_TWP_NONE || \ + ((CLOCK) == NFM_TWP_1CLOCK) || \ + ((CLOCK) == NFM_TWP_2CLOCK) || \ + ((CLOCK) == NFM_TWP_3CLOCK) || \ + ((CLOCK) == NFM_TWP_4CLOCK) || \ + ((CLOCK) == NFM_TWP_5CLOCK) || \ + ((CLOCK) == NFM_TWP_6CLOCK) || \ + ((CLOCK) == NFM_TWP_7CLOCK) || \ + ((CLOCK) == NFM_TWP_8CLOCK) || \ + ((CLOCK) == NFM_TWP_9CLOCK) || \ + ((CLOCK) == NFM_TWP_10CLOCK) || \ + ((CLOCK) == NFM_TWP_11CLOCK) || \ + ((CLOCK) == NFM_TWP_12CLOCK) || \ + ((CLOCK) == NFM_TWP_13CLOCK) || \ + ((CLOCK) == NFM_TWP_14CLOCK) || \ + ((CLOCK) <= NFM_TWP_15CLOCK))) +/** + * @} + */ + +/** @defgroup NFM CMD + * @{ + */ + +#define NFM_CMD_READ1 0x00 +#define NFM_CMD_READ2 0x30 +#define NFM_CMD_ID 0x90 +#define NFM_CMD_STATUS 0x70 +#define NFM_CMD_RESET 0xFF +#define NFM_CMD_PROGRAM1 0x80 +#define NFM_CMD_PROGRAM2 0x10 +#define NFM_CMD_ERASE1 0x60 +#define NFM_CMD_ERASE2 0xD0 +#define NFM_CMD_RANDOMINPUT 0x85 +#define NFM_CMD_RANDOMOUTPUT1 0x05 +#define NFM_CMD_RANDOMOUTPUT2 0xE0 +#define NFM_CMD_FEATURE 0xEF + +/** + * @} + */ + + +/** @defgroup BCH DATA LEN + * @{ + */ + +#define BCH_SECTOR_SIZE 0x200 +#define BCH_INF_SIZE 0x3 +#define BCH_ECC_SIZE 0xD + +/** + * @} + */ + +/** @defgroup BCH ECC MODE + * @{ + */ + +#define BCH_ECC_MODE_EN 0x1 +#define BCH_ECC_MODE_DIS 0x0 + +/** + * @} + */ + + +/* + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t EDO_EN; /*!< This member controls the EDO mode. */ + + uint32_t RBN_INTEN; /*!< This member controls the RBN INT. */ + + uint32_t ENDIAN; /*!< This member controls Big/Little endian. */ + + uint32_t FWP; /*!< This member controls the FWP mode. */ + + uint32_t FCE; /*!< This member controls the FCE mode. */ + + uint32_t TADL; /*!< Specifies the tADL value*/ + + uint32_t TRHW; /*!< Specifies the tRHW value*/ + + uint32_t TWHR; /*!< Specifies the tWHR value*/ + + uint32_t TREH; /*!< Specifies the tREH value*/ + + uint32_t TRP; /*!< Specifies the tRP value*/ + + uint32_t TWH; /*!< Specifies the tTWH value*/ + + uint32_t TWP; /*!< Specifies the tWP value*/ + +}NFM_InitTypeDef; + +/* + * @brief UART handle Structure definition + */ +typedef struct +{ + FMC_NAND_TypeDef *Instance; /*!< NFM registers base address */ + + NFM_InitTypeDef Init; /*!< NFM parameters */ + + void* NFM_Data_Buff; /*!< NFM databuff base address */ + + uint32_t NFM_Data_Len; /*!< amount of CRC data to be calculated */ + +}NFM_HandleTypeDef; + +/****************************************************************************** +*@brief : Initialize the NFM MSP: CLK, GPIO, NVIC +* +*@param : hnfm: nfm handle with NFM parameters. +*@return: None +******************************************************************************/ +void HAL_NFM_MspInit(NFM_HandleTypeDef *hnfm); + +/****************************************************************************** +*@brief : Initialize the NFM according to the specified parameters in hnfm. +* +*@param : hnfm: nfm handle with NFM parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_NFM_Init(NFM_HandleTypeDef *hnfm); + +/****************************************************************************** +*@brief : Reset Nand Flash +* +*@param : hnfm: nfm handle with NFM parameters. +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_NFM_FlashReset(NFM_HandleTypeDef *hnfm); + +/****************************************************************************** +*@brief : Read ID from Nand Flash +* +*@param : hnfm: nfm handle with NFM parameters. +*@param : rdata: start address to store ID +*@param : lenth: ID length +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_NFM_FlashGetID(NFM_HandleTypeDef *hnfm, uint8_t rdata[], uint8_t lenth); + +/****************************************************************************** +*@brief : Erase a block +* +*@param : hnfm: nfm handle with NFM parameters. +*@param : BlockAddr: start address of the block to erase +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_NFM_FlashErase(NFM_HandleTypeDef *hnfm, uint32_t PageAddr); + +/****************************************************************************** +*@brief : Program one sector(512 bytes) +* +*@param : hnfm: nfm handle with NFM parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : wdata: start address of data to program +*@param : ecc_en:select the mode of program + BCH_ECC_MODE_EN : program with ecc mode + BCH_ECC_MODE_DIS: progran with no ecc mode +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_NFM_Flash_Program(NFM_HandleTypeDef *hnfm, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t wdata[], uint8_t ecc_en); + +/****************************************************************************** +*@brief : Read one sector(512 bytes) +* +*@param : hnfm: nfm handle with NFM parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : rdata: start address of read data +*@param : ecc_en:select the mode of read + BCH_ECC_MODE_EN : read with ecc mode + BCH_ECC_MODE_DIS: read with no ecc mode +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_NFM_FlashRead(NFM_HandleTypeDef *hnfm, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t rdata[], uint8_t ecc_en); + + +#endif + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_norflash.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_norflash.h new file mode 100644 index 0000000000000000000000000000000000000000..671bfbe1ac0a4415b1781568edb609acb0c2c97f --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_norflash.h @@ -0,0 +1,199 @@ +/***************************************************************** +Copyright(C) 2008 - 2021, Shanghai AisinoChip Co.,Ltd. +@ļ: hal_norflash.h +@: norFlash header file +@Ա: bobzhang +@: 2021.1.18 +@ǰ汾: 1.0 +@޸ļ¼: +޸ ޸ ޸˵ + +******************************************************************/ + +/***************************************************************** +ע⣺ʹHAL_NORFLASH_ModifyDataҪջ6KBϡ +ΪHAL_NORFLASH_ModifyDataڲʹ4KBջռ䣬ݡ +******************************************************************/ + +#ifndef _HAL_NORFLASH_H +#define _HAL_NORFLASH_H + +#include "acm32h5xx_hal_conf.h" + + + +typedef enum +{ + SPI_CMD_ID_NOT_CARE = 0x00, + + SPI_READ_REGISTER_1S0S1S = 0x01, + + SPI_WRITE_REGISTER1_1S1S1S, + + SPI_WRITE_REGISTER2_1S1S1S, + + SPI_WRITE_REGISTER3_1S1S1S, + + SPI_READ_ID_1S0S1S, + + SPI_READ_DATA_1S1S1S_24, // 0x03, STR, xSPI + SPI_READ_DATA_1S1S1S_32, // 0x13, STR, xSPI + + SPI_READ_DATA_1S1S4S_24, // 0x6B, STR, xSPI + SPI_READ_DATA_1S4S4S_24, // 0xEB, STR, xSPI + + SPI_ERASE_SECTOR_1S1S_24, // 0x20, STR, xSPI + SPI_ERASE_SECTOR_1S1S_32, // 0x21, STR, xSPI + + + SPI_ERASE_BLOCK1_1S1S_24, // 0x52, STR, xSPI + SPI_ERASE_BLOCK1_1S1S_32, // 0x5C, STR, xSPI + + SPI_ERASE_BLOCK2_1S1S_24, // 0xD8, STR, xSPI + SPI_ERASE_BLOCK2_1S1S_32, // 0xDC, STR, xSPI + + + SPI_PROG_DATA_1S1S1S_24, // 0x02, STR, xSPI + SPI_PROG_DATA_1S1S1S_32, // 0x12, STR, xSPI + SPI_PROG_DATA_1S1S4S_24, // 0x32, STR, xSPI + + SPI_ENTER_ADDR_32_1S, // 0xB7, STR, xSPI + + SPI_EXIT_ADDR_32_1S, // 0xE9, STR, xSPI + + SPI_READ_UNIQUE_ID = 0x4B, + +}SPI_READ_CMD; + +typedef struct +{ + uint32_t SPI_Instance; + + uint8_t Command; //must + uint8_t Delay; //must + uint8_t Cont_MID; //must + uint8_t Dummy_clks; //must + + uint32_t Addr; //must + uint32_t Operation_length; //must + uint32_t Input_data_Addr; //must + uint32_t Output_data_Addr; //must + +}SPI_Flash_Parameter; + +typedef uint8_t (*SPI_Nor_Func)(SPI_Flash_Parameter *); + +#define SPI_NORFLASH_FUNC_ADDR 0x1FF07FD0 +#define SPI_Nor_Read_MID_DID (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[0]) +#define SPI_Nor_Read_Unique_ID (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[1]) +#define SPI_Nor_WriteRegister (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[2]) +#define SPI_Nor_ReadRegister (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[3]) +#define SPI_Nor_Read (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[4]) +#define SPI_Nor_PageProgram (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[5]) +#define SPI_Nor_Erase (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[6]) +#define SPI_SwitchToFIFOMode (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[8]) +#define SPI_SwitchToXIPMode (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[9]) +#define SPI_Nor_ModifyValue (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[10]) +#define SPI_SetEncrytionKey (((SPI_Nor_Func *)SPI_NORFLASH_FUNC_ADDR)[11]) + +#define SPI_Nor_Encrypt_Data ((SPI_Nor_Func )0x1FF07C01) + +#define READ_DATA (0x03) //1-1-1 +#define READ_DATA_FAST (0x0B) //1-1-1 +#define DUAL_OUTPUT_FAST_READ (0x3B) //1-1-2 +#define QUAD_OUTPUT_FAST_READ (0x6B) //1-1-4 +#define DUAL_IO_FAST_READ (0xBB) //1-2-2 +#define QUAD_IO_FAST_READ (0xEB) //1-4-4 + +#define SET_BURST_WITH_WRAP (0x77) + +#define PAGE_PROGARM (0x02) //1-1-1 +#define DUAL_PAGE_PROGARM (0xA2) //1-1-2 +#define EXT_DUAL_PAGE_PROGARM (0xD2) //1-2-2 +#define QUAD_PAGE_PROGRAM (0x32) //1-1-4 +#define EXT_QUAD_PAGE_PROGRAM (0x38) //1-4-4 + + +#define SECTOR_ERASE (0x20) +#define BLOCK_ERASE_32K (0x52) +#define BLOCK_ERASE_64K (0xd8) +#define CHIP_ERASE (0xC7) + +#define READ_DEVICE_ID (0x90) +#define READ_ID (0x9F) +#define READ_UNIQUE_ID (0x4B) + + +#define SPI_SHIFT_ZERO 0 +#define SPI_SHIFT_1HCLK 1 +#define SPI_SHIFT_1P5HCLK 2 +#define SPI_SHIFT_2HCLK 3 +#define SPI_SHIFT_2P5HCLK 4 +#define SPI_SHIFT_3HCLK 5 + +typedef struct +{ + uint32_t chipSize; + uint8_t readCmd; + uint8_t readDummyBytes; + uint8_t programCmd; +}NORFLASH_ParamTypeDef; + + +#define NORFLASH_PAGE_SIZE (256) +#define NORFLASH_PAGE_SIZE_MASK (NORFLASH_PAGE_SIZE-1) + +#define NORFLASH_SECTOR_SIZE (4096) +#define NORFLASH_SECTOR_SIZE_MASK (NORFLASH_SECTOR_SIZE-1) + +#define NORFLASH_BLOCK_32K_SIZE (32*1024) +#define NORFLASH_BLOCK_32K_SIZE_MASK (NORFLASH_BLOCK_32K_SIZE-1) + +#define NORFLASH_BLOCK_64K_SIZE (64*1024) +#define NORFLASH_BLOCK_64K_SIZE_MASK (NORFLASH_BLOCK_64K_SIZE-1) + + +void HAL_NORFLASH_CfgSpiShift1_Insram(void); +void HAL_NORFLASH_CfgSpiDiv4Shift0_Insram(void); +void HAL_NORFLASH_XipPlainReadBytes_Insram(uint32_t addr, void *buff, uint32_t bytelen); +void HAL_NORFLASH_XipPlainReadWords_Insram(uint32_t addr, void *buff, uint32_t wordlen); + + +uint32_t HAL_NORFLASH_EnterCritical(void); +void HAL_NORFLASH_ExitCritical(uint32_t sr); + + +//uint8_t HAL_NORFLASH_Init(void); + +uint8_t HAL_NORFLASH_ReadUniqueID(uint8_t *buff,uint32_t len); + +//ֽڵManufacture ID Device ID +uint8_t HAL_NORFLASH_ReadID(uint8_t *buff); + +//ݣֿ֧ +uint8_t HAL_NORFLASH_Erase(uint32_t addr, uint32_t len); + +//ֽڶֿ֧ҳ +uint8_t HAL_NORFLASH_Read(uint32_t addr, uint8_t *buff, uint32_t len); + +//ݣֿ֧ҳ +uint8_t HAL_NORFLASH_Program(uint32_t addr, uint8_t *buff, uint32_t len); + +//дֽݡʱԶдδʱԶݲдڲʹ4KBջռ䣬ݡ +uint8_t HAL_NORFLASH_ModifyData(uint32_t addr, uint8_t *buff, uint32_t len); + +uint8_t HAL_NORFLASH_EraseBootFlag(void); + +uint8_t HAL_NORFLASH_SetEncryptionKey(uint8_t * key_input); +uint8_t HAL_NORFLASH_EncryptProgram(uint32_t addr, uint32_t *data_in, uint32_t len, uint32_t *data_out); + +uint8_t HAL_NORFLASH_ModifySPIControllerParam(uint32_t write_addr, uint32_t * p_value, uint32_t len); + +uint8_t HAL_NORFLASH_SetLowPowerMode(uint8_t mode); +void HAL_NORFLASH_ResetMcu(void); + +uint8_t HAL_NORFLASH_ModifyDivShift(uint32_t div, uint32_t shift_clk); + +#endif + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_ospi.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_ospi.h new file mode 100644 index 0000000000000000000000000000000000000000..2661b5bd1fc84f6c34b758db958192d08c6975fe --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_ospi.h @@ -0,0 +1,902 @@ +/****************************************************************************** +*@file : hal_ospi.h +*@brief : Header file of OSPI HAL module. +*@ver : 1.0.0 +*@date : 2023.06.16 +******************************************************************************/ + +#ifndef __HAL_OSPI_H__ +#define __HAL_OSPI_H__ + +#include "hal.h" + + +/** @defgroup OSPI State machine + * @{ + */ +#define OSPI_RX_STATE_IDLE (0U) +#define OSPI_RX_STATE_RECEIVING (1U) +#define OSPI_TX_STATE_IDLE (0U) +#define OSPI_TX_STATE_SENDING (1U) +/** + * @} + */ + +/** @defgroup OSPI_Instances + * @{ + */ +#define IS_OSPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OSPI1) || ((__INSTANCE__) == OSPI2)) +/** + * @} + */ + +/** @defgroup OSPI_WORK_MODE + * @{ + */ +#define OSPI_WORK_MODE_0 (0U) +#define OSPI_WORK_MODE_1 (OSPI_CTL_CPHA) +#define OSPI_WORK_MODE_2 (OSPI_CTL_CPOL) +#define OSPI_WORK_MODE_3 (OSPI_CTL_CPHA | OSPI_CTL_CPOL) +#define IS_OSPI_WORK_MODE(__WORKMODE__) (((__WORKMODE__) == OSPI_WORK_MODE_0) || \ + ((__WORKMODE__) == OSPI_WORK_MODE_1) || \ + ((__WORKMODE__) == OSPI_WORK_MODE_2) || \ + ((__WORKMODE__) == OSPI_WORK_MODE_3)) +/** + * @} + */ + + +/** @defgroup OSPI_X_MODE + * @{ + */ +#define OSPI_1X_MODE (0U) +#define OSPI_2X_MODE (OSPI_CTL_X_MODE_0) +#define OSPI_4X_MODE (OSPI_CTL_X_MODE_1) +#define OSPI_8X_MODE (OSPI_CTL_X_MODE_0 | OSPI_CTL_X_MODE_1) +#define IS_OSPI_X_MODE(__XMODE__) (((__XMODE__) == OSPI_1X_MODE) || \ + ((__XMODE__) == OSPI_2X_MODE) || \ + ((__XMODE__) == OSPI_4X_MODE) || \ + ((__XMODE__) == OSPI_8X_MODE)) +/** + * @} + */ + + +/** @defgroup OSPI_MSB_LSB_FIRST + * @{ + */ +#define OSPI_FIRSTBIT_MSB (0U) +#define OSPI_FIRSTBIT_LSB (OSPI_CTL_LSB_FIRST) +#define IS_OSPI_FIRST_BIT(__FIRSTBIT__) (((__FIRSTBIT__) == OSPI_FIRSTBIT_MSB) || \ + ((__FIRSTBIT__) == OSPI_FIRSTBIT_LSB)) +/** + * @} + */ + + +/** @defgroup OSPI_BAUDRATE_PRESCALER + * @{ + */ +#define OSPI_BAUDRATE_PRESCALER_2 (2U) +#define OSPI_BAUDRATE_PRESCALER_4 (4U) +#define OSPI_BAUDRATE_PRESCALER_8 (8U) +#define OSPI_BAUDRATE_PRESCALER_16 (16U) +#define OSPI_BAUDRATE_PRESCALER_28 (28U) +#define OSPI_BAUDRATE_PRESCALER_32 (32U) +#define OSPI_BAUDRATE_PRESCALER_64 (64U) +#define OSPI_BAUDRATE_PRESCALER_128 (128U) +#define OSPI_BAUDRATE_PRESCALER_254 (254U) +#define IS_OSPI_BAUDRATE_PRESCALER(__BAUDRATE__) (((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_2) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_4) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_8) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_16) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_28) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_32) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_64) || \ + ((__BAUDRATE__) == OSPI_BAUDRATE_PRESCALER_128) || \ + ((__BAUDRATE__) <= OSPI_BAUDRATE_PRESCALER_254)) +/** + * @} + */ + + +/** @defgroup OSPI_MASTER_SAMPLE_SHIFT + * @{ + */ +#define OSPI_SAMPLE_SHIFT_NONE (0U) +#define OSPI_SAMPLE_SHIFT_1HCLK (1U) +#define OSPI_SAMPLE_SHIFT_1_5HCLK (2U) +#define OSPI_SAMPLE_SHIFT_2HCLK (3U) +#define OSPI_SAMPLE_SHIFT_2_5HCLK (4U) +#define OSPI_SAMPLE_SHIFT_3HCLK (5U) +#define OSPI_SAMPLE_SHIFT_3_5HCLK (6U) +#define OSPI_SAMPLE_SHIFT_4HCLK (7U) +#define OSPI_SAMPLE_SHIFT_4_5HCLK (8U) +#define OSPI_SAMPLE_SHIFT_5HCLK (9U) +#define OSPI_SAMPLE_SHIFT_5_5HCLK (10U) +#define OSPI_SAMPLE_SHIFT_6HCLK (11U) +#define OSPI_SAMPLE_SHIFT_6_5HCLK (12U) +#define OSPI_SAMPLE_SHIFT_7HCLK (13U) +#define IS_OSPI_SAMPLE_SHIFT(__SHIFT__) ((__SHIFT__) < 14) +/** + * @} + */ + +/** @defgroup OSPI_FIFO_Mode + * @{ + */ +#define OSPI_FIFO_BYTE (0U) +#define OSPI_FIFO_HALFWORD (1U) +#define OSPI_FIFO_WORD (2U) +#define IS_OSPI_FIFO_MODE(__FIFOMODE__) (((__FIFOMODE__) == OSPI_FIFO_BYTE) || \ + ((__FIFOMODE__) == OSPI_FIFO_HALFWORD) || \ + ((__FIFOMODE__) == OSPI_FIFO_WORD)) +/** + * @} + */ + +/** @defgroup OSPI_CS + * @{ + */ +#define OSPI_CS_0 (OSPI_CS_CS_0) +#define OSPI_CS_1 (OSPI_CS_CS_1) +#define OSPI_CS_2 (OSPI_CS_CS_2) +#define IS_OSPI_CS_SEL(__CSX__) (((__CSX__) == OSPI_CS_0) || \ + ((__CSX__) == OSPI_CS_1) || \ + ((__CSX__) == OSPI_CS_2)) +/** + * @} + */ + +/** @defgroup OSPI_DTR_STR + * @{ + */ +#define OSPI_DTRM_STR (0U) +#define OSPI_DTRM_DTR (OSPI_CTL_DTRM) +#define IS_OSPI_DTRM(__DTRM__) (((__DTRM__) == OSPI_DTRM_STR) || \ + ((__DTRM__) == OSPI_DTRM_DTR)) +/** + * @} + */ + +/** @defgroup OSPI_DQS_Output + * @{ + */ +#define OSPI_DQSOE_DISABLE (0U) +#define OSPI_DQSOE_ENABLE (OSPI_CTL_DQSOE) +#define IS_OSPI_DQSOE(__DQSOE__) (((__DQSOE__) == OSPI_DQSOE_DISABLE) || \ + ((__DQSOE__) == OSPI_DQSOE_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Data_Mask_Mode + * @{ + */ +#define OSPI_DM_DISABLE (0U) +#define OSPI_DM_ENABLE (OSPI_CTL_DM_EN) +#define IS_OSPI_DM(__DM_EN__) (((__DM_EN__) == OSPI_DM_DISABLE) || \ + ((__DM_EN__) == OSPI_DM_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_DataMask_Ctrl + * @{ + */ +#define OSPI_DMCTRL_ODD_ADDR (0U) +#define OSPI_DMCTRL_EVEN_ADDR (OSPI_CTL_DMCTRL) +#define IS_OSPI_DMCTRL_ADDR(__MASK__) (((__MASK__) == OSPI_DMCTRL_ODD_ADDR) || \ + ((__MASK__) == OSPI_DMCTRL_EVEN_ADDR)) +/** + * @} + */ + +/** @defgroup OSPI_Memory_Type + * @{ + */ +#define OSPI_MEM_XCCELA_OPI (0U) +#define OSPI_MEM_APM_OPI (OSPI_CTL_MEM_MODE_0) +#define OSPI_MEM_HYPERBUS (OSPI_CTL_MEM_MODE_1) +#define OSPI_MEM_XSPI (OSPI_CTL_MEM_MODE_0 | OSPI_CTL_MEM_MODE_1) +#define IS_OSPI_MEMORY_TYPE(__TYPE__) (((__TYPE__) == OSPI_MEM_XCCELA_OPI) || \ + ((__TYPE__) == OSPI_MEM_APM_OPI) || \ + ((__TYPE__) == OSPI_MEM_HYPERBUS) || \ + ((__TYPE__) == OSPI_MEM_XSPI)) +/** + * @} + */ + +/** @defgroup OSPI_APM_Dummy_Clock + * @{ + */ +#define OSPI_APM_DUMMY_NONE (0U) +#define OSPI_APM_DUMMY_1CLOCK (OSPI_CTL_APMD_CLK_0) +#define OSPI_APM_DUMMY_2CLOCK (OSPI_CTL_APMD_CLK_1) +#define OSPI_APM_DUMMY_3CLOCK (OSPI_CTL_APMD_CLK_0 | OSPI_CTL_APMD_CLK_1) +#define OSPI_APM_DUMMY_4CLOCK (OSPI_CTL_APMD_CLK_2) +#define OSPI_APM_DUMMY_5CLOCK (OSPI_CTL_APMD_CLK_0 | OSPI_CTL_APMD_CLK_2) +#define OSPI_APM_DUMMY_6CLOCK (OSPI_CTL_APMD_CLK_1 | OSPI_CTL_APMD_CLK_2) +#define OSPI_APM_DUMMY_7CLOCK (OSPI_CTL_APMD_CLK_0 | OSPI_CTL_APMD_CLK_1 | OSPI_CTL_APMD_CLK_2) +#define IS_OSPI_APM_DUMMY_CLOCK(__CLOCK__) (((__CLOCK__) == OSPI_APM_DUMMY_NONE || \ + ((__CLOCK__) == OSPI_APM_DUMMY_1CLOCK) || \ + ((__CLOCK__) == OSPI_APM_DUMMY_2CLOCK) || \ + ((__CLOCK__) == OSPI_APM_DUMMY_3CLOCK) || \ + ((__CLOCK__) == OSPI_APM_DUMMY_4CLOCK) || \ + ((__CLOCK__) == OSPI_APM_DUMMY_5CLOCK) || \ + ((__CLOCK__) == OSPI_APM_DUMMY_6CLOCK) || \ + ((__CLOCK__) <= OSPI_APM_DUMMY_7CLOCK))) +/** + * @} + */ + + +/** @defgroup OSPI_TX_OUT_Delay + * @{ + */ +#define OSPI_TX_OUT_DELAY_NONE (0U) +#define OSPI_TX_OUT_DELAY_HALF_HCLK (OSPI_TX_CTL_OUTDLY_0) +#define OSPI_TX_OUT_DELAY_1HCLK (OSPI_TX_CTL_OUTDLY_1) +#define OSPI_TX_OUT_DELAY_2HCLK (OSPI_TX_CTL_OUTDLY_0 | OSPI_TX_CTL_OUTDLY_1) +#define IS_OSPI_TX_OUT_DELAY(__DELAY__) (((__DELAY__) == OSPI_TX_OUT_DELAY_NONE) || \ + ((__DELAY__) == OSPI_TX_OUT_DELAY_HALF_HCLK) || \ + ((__DELAY__) == OSPI_TX_OUT_DELAY_1HCLK) || \ + ((__DELAY__) == OSPI_TX_OUT_DELAY_2HCLK)) +/** + * @} + */ + + /** @defgroup OSPI_DQS_Smaple + * @{ + */ +#define OSPI_DQS_SAMPLE_DISABLE (0U) +#define OSPI_DQS_SAMPLE_ENABLE (OSPI_RX_CTL_DQS_SAMP_EN) +#define IS_OSPI_DQS_SAMPLE(__DQS_SAMP__) (((__DQS_SAMP__) == OSPI_DQS_SAMPLE_DISABLE) || \ + ((__DQS_SAMP__) == OSPI_DQS_SAMPLE_ENABLE)) +/** + * @} + */ + + +/** @defgroup OSPI_Dummy_Data + * @{ + */ +#define IS_OSPI_DUMMY_DATA(__DUMMMY__) ((__DUMMMY__) <= 0xff) +/** + * @} + */ + + /** @defgroup OSPI_CSTimeout_Val + * @{ + */ +#define IS_OSPI_CS_TIMEOUT_VAL(__VAL__) ((__VAL__) <= 0xffff) +/** + * @} + */ + +/** @defgroup OSPI_Burst_Type + * @{ + */ +#define MEMOACC1_BURST_WRAPPED (0U) +#define MEMOACC1_BURST_LINEAR (OSPI_MEMO_ACC1_HYPER_BT) +#define IS_OSPI_BURST_TYPE(__BURST__) (((__BURST__) == MEMOACC1_BURST_WRAPPED) || \ + ((__BURST__) == MEMOACC1_BURST_LINEAR)) +/** + * @} + */ + +/** @defgroup OSPI_Data_Mode + * @{ + */ +#define MEMOACC1_DATA_MODE_x1 (0U) +#define MEMOACC1_DATA_MODE_x2 (OSPI_MEMO_ACC1_DATA_MODE_0) +#define MEMOACC1_DATA_MODE_x4 (OSPI_MEMO_ACC1_DATA_MODE_1) +#define IS_OSPI_DATA_MODE(__DATAMODE__) (((__DATAMODE__) == MEMOACC1_DATA_MODE_x1) || \ + ((__DATAMODE__) == MEMOACC1_DATA_MODE_x2) || \ + ((__DATAMODE__) == MEMOACC1_DATA_MODE_x4)) +/** + * @} + */ + +/** @defgroup OSPI_Alter_Byte_Mode + * @{ + */ +#define MEMOACC1_ALTER_BYTE_MODE_x1 (0U) +#define MEMOACC1_ALTER_BYTE_MODE_x2 (OSPI_MEMO_ACC1_ALTER_BYTE_MODE_0) +#define MEMOACC1_ALTER_BYTE_MODE_x4 (OSPI_MEMO_ACC1_ALTER_BYTE_MODE_1) +#define IS_OSPI_ALTER_BYTE_MODE(__ALTERMODE__) (((__ALTERMODE__) == MEMOACC1_ALTER_BYTE_MODE_x1) || \ + ((__ALTERMODE__) == MEMOACC1_ALTER_BYTE_MODE_x2) || \ + ((__ALTERMODE__) == MEMOACC1_ALTER_BYTE_MODE_x4)) +/** + * @} + */ + +/** @defgroup OSPI_Addr_Mode + * @{ + */ +#define MEMOACC1_ADDR_MODE_x1 (0U) +#define MEMOACC1_ADDR_MODE_x2 (OSPI_MEMO_ACC1_ADDR_MODE_0) +#define MEMOACC1_ADDR_MODE_x4 (OSPI_MEMO_ACC1_ADDR_MODE_1) +#define IS_OSPI_ADDR_MODE(__ADDRMODE__) (((__ADDRMODE__) == MEMOACC1_ADDR_MODE_x1) || \ + ((__ADDRMODE__) == MEMOACC1_ADDR_MODE_x2) || \ + ((__ADDRMODE__) == MEMOACC1_ADDR_MODE_x4)) +/** + * @} + */ + +/** @defgroup OSPI_Instr_Mode + * @{ + */ +#define MEMOACC1_INSTR_MODE_x1 (0U) +#define MEMOACC1_INSTR_MODE_x2 (OSPI_MEMO_ACC1_INSTR_MODE_0) +#define MEMOACC1_INSTR_MODE_x4 (OSPI_MEMO_ACC1_INSTR_MODE_1) +#define IS_OSPI_INSRT_MODE(__INSTRMODE__) (((__INSTRMODE__) == MEMOACC1_INSTR_MODE_x1) || \ + ((__INSTRMODE__) == MEMOACC1_INSTR_MODE_x2) || \ + ((__INSTRMODE__) == MEMOACC1_INSTR_MODE_x4)) +/** + * @} + */ + +/** @defgroup OSPI_Addr_Width + * @{ + */ +#define MEMOACC1_ADDR_WIDTH_8 (0U) +#define MEMOACC1_ADDR_WIDTH_16 (OSPI_MEMO_ACC1_ADDR_WIDTH_0) +#define MEMOACC1_ADDR_WIDTH_24 (OSPI_MEMO_ACC1_ADDR_WIDTH_1) +#define MEMOACC1_ADDR_WIDTH_32 (OSPI_MEMO_ACC1_ADDR_WIDTH_0 | OSPI_MEMO_ACC1_ADDR_WIDTH_1) +#define IS_OSPI_ADDR_WIDTH(__ADDRWIDTH__) (((__ADDRWIDTH__) == MEMOACC1_ADDR_WIDTH_8) || \ + ((__ADDRWIDTH__) == MEMOACC1_ADDR_WIDTH_16) || \ + ((__ADDRWIDTH__) == MEMOACC1_ADDR_WIDTH_24) || \ + ((__ADDRWIDTH__) == MEMOACC1_ADDR_WIDTH_32)) +/** + * @} + */ + +/** @defgroup OSPI_Dummy_Cycle + * @{ + */ +#define MEMOACC1_DUMMY_CYCLE_1 (0U) +#define MEMOACC1_DUMMY_CYCLE_2 (1U) +#define MEMOACC1_DUMMY_CYCLE_3 (2U) +#define MEMOACC1_DUMMY_CYCLE_4 (3U) +#define MEMOACC1_DUMMY_CYCLE_5 (4U) +#define MEMOACC1_DUMMY_CYCLE_6 (5U) +#define MEMOACC1_DUMMY_CYCLE_7 (6U) +#define MEMOACC1_DUMMY_CYCLE_8 (7U) +#define MEMOACC1_DUMMY_CYCLE_9 (8U) +#define MEMOACC1_DUMMY_CYCLE_10 (9U) +#define MEMOACC1_DUMMY_CYCLE_11 (10U) +#define MEMOACC1_DUMMY_CYCLE_12 (11U) +#define MEMOACC1_DUMMY_CYCLE_13 (12U) +#define MEMOACC1_DUMMY_CYCLE_14 (13U) +#define MEMOACC1_DUMMY_CYCLE_15 (14U) +#define MEMOACC1_DUMMY_CYCLE_16 (15U) +#define MEMOACC1_DUMMY_CYCLE_17 (16U) +#define MEMOACC1_DUMMY_CYCLE_18 (17U) +#define MEMOACC1_DUMMY_CYCLE_19 (18U) +#define MEMOACC1_DUMMY_CYCLE_20 (19U) +#define MEMOACC1_DUMMY_CYCLE_21 (20U) +#define MEMOACC1_DUMMY_CYCLE_22 (21U) +#define MEMOACC1_DUMMY_CYCLE_23 (22U) +#define MEMOACC1_DUMMY_CYCLE_24 (23U) +#define MEMOACC1_DUMMY_CYCLE_25 (24U) +#define MEMOACC1_DUMMY_CYCLE_26 (25U) +#define MEMOACC1_DUMMY_CYCLE_27 (26U) +#define MEMOACC1_DUMMY_CYCLE_28 (27U) +#define MEMOACC1_DUMMY_CYCLE_29 (28U) +#define MEMOACC1_DUMMY_CYCLE_30 (29U) +#define MEMOACC1_DUMMY_CYCLE_31 (30U) +#define MEMOACC1_DUMMY_CYCLE_32 (31U) +#define IS_OSPI_DUMMY_CYCLE(__CYCLE__) ((__CYCLE__) < 32) +/** + * @} + */ + +/** @defgroup OSPI_Read_Dummy_State + * @{ + */ +#define MEMOACC1_READ_DUMMY_DISABLE (0U) +#define MEMOACC1_READ_DUMMY_ENABLE (OSPI_MEMO_ACC1_RD_DB_EN) +#define IS_OSPI_READ_DUMMY_STATE(__STATE__) (((__STATE__) == MEMOACC1_READ_DUMMY_DISABLE) || \ + ((__STATE__) == MEMOACC1_READ_DUMMY_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Write_Dummy_State + * @{ + */ +#define MEMOACC1_WRITE_DUMMY_DISABLE (0U) +#define MEMOACC1_WRITE_DUMMY_ENABLE (OSPI_MEMO_ACC1_WR_DB_EN) +#define IS_OSPI_WRITE_DUMMY_STATE(__STATE__) (((__STATE__) == MEMOACC1_WRITE_DUMMY_DISABLE) || \ + ((__STATE__) == MEMOACC1_WRITE_DUMMY_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Alter_Byte_Size + * @{ + */ +#define MEMOACC1_ALTER_BYTE_SIZE_8 (0U) +#define MEMOACC1_ALTER_BYTE_SIZE_16 (OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_0) +#define MEMOACC1_ALTER_BYTE_SIZE_24 (OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_1) +#define MEMOACC1_ALTER_BYTE_SIZE_32 (OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_0 | OSPI_MEMO_ACC1_ALTER_BYTE_SIZE_1) +#define IS_OSPI_ALTER_BYTE_SIZE(__ALTERSIZE__) (((__ALTERSIZE__) == MEMOACC1_ALTER_BYTE_SIZE_8) || \ + ((__ALTERSIZE__) == MEMOACC1_ALTER_BYTE_SIZE_16) || \ + ((__ALTERSIZE__) == MEMOACC1_ALTER_BYTE_SIZE_24) || \ + ((__ALTERSIZE__) == MEMOACC1_ALTER_BYTE_SIZE_32)) +/** + * @} + */ + +/** @defgroup OSPI_Read_Alter_State + * @{ + */ +#define MEMOACC1_READ_ALTER_DISABLE (0U) +#define MEMOACC1_READ_ALTER_ENABLE (OSPI_MEMO_ACC1_RD_AB_EN) +#define IS_OSPI_READ_ALTER_STATE(__STATE__) (((__STATE__) == MEMOACC1_READ_ALTER_DISABLE) || \ + ((__STATE__) == MEMOACC1_READ_ALTER_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Write_Alte_State + * @{ + */ +#define MEMOACC1_WRITE_ALTER_DISABLE (0U) +#define MEMOACC1_WRITE_ALTER_ENABLE (OSPI_MEMO_ACC1_WR_AB_EN) +#define IS_OSPI_WRITE_ALTER_STATE(__STATE__) (((__STATE__) == MEMOACC1_WRITE_ALTER_DISABLE) || \ + ((__STATE__) == MEMOACC1_WRITE_ALTER_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_CMD_Send_State + * @{ + */ +#define MEMOACC1_CMD_SEND_ONCE_DISABLE (0U) +#define MEMOACC1_CMD_SEND_ONCE_ENABLE (OSPI_MEMO_ACC1_SEND_INSTR_ONCE_EN) +#define IS_OSPI_CMD_SEND_STATE(__STATE__) (((__STATE__) == MEMOACC1_CMD_SEND_ONCE_DISABLE) || \ + ((__STATE__) == MEMOACC1_CMD_SEND_ONCE_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Continuous_State + * @{ + */ +#define MEMOACC1_CON_DISABLE (0U) +#define MEMOACC1_CON_ENABLE (OSPI_MEMO_ACC1_CON_MODE_EN) +#define IS_OSPI_CONTINUOUS_STATE(__STATE__) (((__STATE__) == MEMOACC1_CON_DISABLE) || \ + ((__STATE__) == MEMOACC1_CON_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Cs_Timeout_State + * @{ + */ +#define MEMOACC1_CS_TIMEOUT_DISABLE (0U) +#define MEMOACC1_CS_TIMEOUT_ENABLE (OSPI_MEMO_ACC1_CS_TIMEOUT_EN) +#define IS_OSPI_CS_TIMEOUT_STATE(__STATE__) (((__STATE__) == MEMOACC1_CS_TIMEOUT_DISABLE) || \ + ((__STATE__) == MEMOACC1_CS_TIMEOUT_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Memory_State + * @{ + */ +#define MEMOACC1_MEMORY_DISABLE (0U) +#define MEMOACC1_MEMORY_ENABLE (OSPI_MEMO_ACC1_ACC_EN) +#define IS_OSPI_MEMORY_STATE(__STATE__) (((__STATE__) == MEMOACC1_MEMORY_DISABLE) || \ + ((__STATE__) == MEMOACC1_MEMORY_ENABLE)) +/** + * @} + */ + +/** @defgroup OSPI_Wrap_Size + * @{ + */ +#define MEMOACC2_WRAP_SIZE_0 (0U) +#define MEMOACC2_WRAP_SIZE_16 (OSPI_MEMO_ACC2_WRPS_1) +#define MEMOACC2_WRAP_SIZE_32 (OSPI_MEMO_ACC2_WRPS_0 | OSPI_MEMO_ACC2_WRPS_1) +#define MEMOACC2_WRAP_SIZE_64 (OSPI_MEMO_ACC2_WRPS_2) +#define IS_OSPI_WRAP_SIZE(__WRAPSIZE__) (((__WRAPSIZE__) == MEMOACC2_WRAP_SIZE_0) || \ + ((__WRAPSIZE__) == MEMOACC2_WRAP_SIZE_16) || \ + ((__WRAPSIZE__) == MEMOACC2_WRAP_SIZE_32) || \ + ((__WRAPSIZE__) == MEMOACC2_WRAP_SIZE_64)) +/** + * @} + */ + +/** @defgroup OSPI_Burst_Length + * @{ + */ +#define MEMOACC2_BURST_LEN_0 (0U) +#define MEMOACC2_BURST_LEN_16 (OSPI_MEMO_ACC2_BL_0) +#define MEMOACC2_BURST_LEN_32 (OSPI_MEMO_ACC2_BL_1) +#define MEMOACC2_BURST_LEN_64 (OSPI_MEMO_ACC2_BL_0 | OSPI_MEMO_ACC2_BL_1) +#define MEMOACC2_BURST_LEN_128 (OSPI_MEMO_ACC2_BL_2) +#define MEMOACC2_BURST_LEN_256 (OSPI_MEMO_ACC2_BL_0 | OSPI_MEMO_ACC2_BL_2) +#define MEMOACC2_BURST_LEN_512 (OSPI_MEMO_ACC2_BL_1 | OSPI_MEMO_ACC2_BL_2) +#define MEMOACC2_BURST_LEN_1024 (OSPI_MEMO_ACC2_BL_0 | OSPI_MEMO_ACC2_BL_1 | OSPI_MEMO_ACC2_BL_2) +#define IS_OSPI_BURST_LEN(__LEN__) (((__LEN__) == MEMOACC2_BURST_LEN_0) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_16) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_32) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_64) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_128) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_256) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_512) || \ + ((__LEN__) == MEMOACC2_BURST_LEN_1024)) +/** + * @} + */ + +/** @defgroup OSPI_Latency1_Cycles + * @{ + */ +#define MEMOACC2_LATENCY1_1 (0U) +#define MEMOACC2_LATENCY1_2 (1U) +#define MEMOACC2_LATENCY1_3 (2U) +#define MEMOACC2_LATENCY1_4 (3U) +#define MEMOACC2_LATENCY1_5 (4U) +#define MEMOACC2_LATENCY1_6 (5U) +#define MEMOACC2_LATENCY1_7 (6U) +#define MEMOACC2_LATENCY1_8 (7U) +#define MEMOACC2_LATENCY1_9 (8U) +#define MEMOACC2_LATENCY1_10 (9U) +#define MEMOACC2_LATENCY1_11 (10U) +#define MEMOACC2_LATENCY1_12 (11U) +#define MEMOACC2_LATENCY1_13 (12U) +#define MEMOACC2_LATENCY1_14 (13U) +#define MEMOACC2_LATENCY1_15 (14U) +#define MEMOACC2_LATENCY1_16 (15U) +#define IS_OSPI_LATENCY1_CYCLE(__CYCLE__) ((__CYCLE__) < 16) +/** + * @} + */ + +/** @defgroup OSPI_Latency0_Cycles + * @{ + */ +#define MEMOACC2_LATENCY0_1 (0U) +#define MEMOACC2_LATENCY0_2 (1U) +#define MEMOACC2_LATENCY0_3 (2U) +#define MEMOACC2_LATENCY0_4 (3U) +#define MEMOACC2_LATENCY0_5 (4U) +#define MEMOACC2_LATENCY0_6 (5U) +#define MEMOACC2_LATENCY0_7 (6U) +#define MEMOACC2_LATENCY0_8 (7U) +#define MEMOACC2_LATENCY0_9 (8U) +#define MEMOACC2_LATENCY0_10 (9U) +#define MEMOACC2_LATENCY0_11 (10U) +#define MEMOACC2_LATENCY0_12 (11U) +#define MEMOACC2_LATENCY0_13 (12U) +#define MEMOACC2_LATENCY0_14 (13U) +#define MEMOACC2_LATENCY0_15 (14U) +#define MEMOACC2_LATENCY0_16 (15U) +#define IS_OSPI_LATENCY0_CYCLE(__CYCLE__) ((__CYCLE__) < 16) + +/** + * @} + */ + +/** @defgroup OSPI_DLYB Exported Constants +* @{ +*/ +#define OSPI_DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */ +#define OSPI_DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ +#define OSPI_DLYB_FLAG_LENF (DLYB_CFGR_LENF) +#define OSPI_DLYB_LNG_10_0_MASK (0x07FF0000U) +#define OSPI_DLYB_LNG_11_10_MASK (0x0C000000U) +/** + * @} + */ + +/** @defgroup OSPI_DLYB_Instances + * @{ + */ +#define IS_OSPI_DLYB_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OSPI1_DLYB) || ((__INSTANCE__) == OSPI2_DLYB)) +/** + * @} + */ + +/** + * @brief OSPI Configuration Structure definition + */ +typedef struct +{ + uint32_t WorkMode; /* OSPI working mode selection. + This parameter can be a value of @ref OSPI_WORK_MODE */ + + uint32_t XMode; /* OSPI multi line mode selection. + This parameter can be a value of @ref OSPI_X_MODE */ + + uint32_t FirstBit; /* MSB/LSB selects the bits first. + This parameter can be a value of @ref SPI_MSB_LSB_FIRST */ + + uint32_t BaudRatePrescaler; /* OSPI BaudRate Prescaler. + This parameter can be a value of @ref OSPI_BAUDRATE_PRESCALER */ + + uint32_t SampleShifting; /* The master delay n hclk to sample data. + This parameter can be a value of @ref OSPI_MASTER_SAMPLE_SHIFT */ + + uint32_t FWMode; /* FIFO Byte/Half Word/Word Write Mode Selection. + This parameter can be a value of @ref OSPI_FIFO_Mode */ + + uint32_t FRMode; /* FIFO Byte/Half Word/Word Read Mode Selection. + This parameter can be a value of @ref OSPI_FIFO_Mode */ + +}OSPI_InitTypeDef; +/** + * @} + */ + +/** + * @brief OSPI handle Structure definition + */ +typedef struct +{ + OSPI_TypeDef *Instance; /* OSPI registers base address. + This parameter can be a value of @ref OSPI_Instances */ + + OSPI_InitTypeDef Init; /* OSPI communication parameters */ + + uint32_t CSx; /* OSPI chip selection signal. + This parameter can be a value of @ref OSPI_CS */ + + uint32_t RxState; /* OSPI state machine */ + uint32_t TxState; /* OSPI state machine */ + + uint8_t *Rx_Buffer; /* OSPI Rx Buffer */ + uint8_t *Tx_Buffer; /* OSPI Tx Buffer */ + + uint32_t Rx_Size; /* OSPI Rx Size */ + uint32_t Tx_Size; /* OSPI Tx Size */ + + uint32_t Rx_Count; /* OSPI RX Count */ + uint32_t Tx_Count; /* OSPI TX Count */ + +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *HDMA_Rx; /* OSPI Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* OSPI Tx DMA handle parameters */ +#endif + +}OSPI_HandleTypeDef; +/** + * @} + */ + +/** + * @brief OSPI Octal communication Configuration Structure definition + */ +typedef struct +{ + uint32_t DTRMode; /* Single/double transmission rate mode. + This parameter can be a value of @ref OSPI_DTR_STR*/ + + uint32_t DQSMode; /* It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_Data_Strobe*/ + + uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. + This parameter can be a value of @ref OSPI_Memory_Type */ + + uint32_t OutDelay; /* Output delay in DTR mode. + This parameter can be a value of @ref OSPI_TX_OUT_Delay */ + + uint32_t DQSSample; /* It enables or not DQS is used as a clock for sampling. + This parameter can be a value of @ref OSPI_DQS_Smaple*/ + + +}OSPI_OctalInitTypeDef; +/** + * @} + */ + +/** + * @brief OSPI Memory Configuration Structure definition + */ +typedef struct +{ + uint8_t ReadCmd; /* Memory read instruction. */ + uint8_t WriteCmd; /* Memory write instruction. */ + uint32_t AlterByte; /* Alter byte */ + uint32_t CsTimeoutVal; /* The time from CS lowering to forced raising */ + uint32_t HyperBurstType; /* Hyperbus burst type + This parameter can be a value of @ref OSPI_Burst_Type */ + uint32_t DataMode; /* Data mode + This parameter can be a value of @ref OSPI_Data_Mode */ + uint32_t AlterByteMode; /* Alter byte mode + This parameter can be a value of @ref OSPI_Alter_Byte_Mode */ + uint32_t AddrMode; /* Address mode + This parameter can be a value of @ref OSPI_Addr_Mode */ + uint32_t InstrMode; /* Instruction mode + This parameter can be a value of @ref OSPI_Instr_Mode */ + uint32_t AddrWidth; /* Address width + This parameter can be a value of @ref OSPI_Addr_Width */ + uint32_t DummyCycleSize; /* Dummy cycle size + This parameter can be a value of @ref OSPI_Dummy_Cycle */ + uint32_t ReadDummyByteEnable; /* Read dummy byte enable or disable + This parameter can be a value of @ref OSPI_Read_Dummy_State */ + uint32_t WriteummyByteEnable; /* Write dummy byte enable or disable + This parameter can be a value of @ref OSPI_Write_Dummy_State */ + uint32_t AlterByteSize; /* Alter byte size + This parameter can be a value of @ref OSPI_Alter_Byte_Size */ + uint32_t ReadAlterByteEnable; /* Read alter byte enable or disable + This parameter can be a value of @ref OSPI_Read_Alter_State */ + uint32_t WriteAlterByteEnable; /* Write alter byte enable or disable + This parameter can be a value of @ref OSPI_Write_Alte_State */ + uint32_t SendInstrOnce; /* Send command once or not + This parameter can be a value of @ref OSPI_CMD_Send_State */ + uint32_t ContinuousModeEnable; /* Continuous mode enable or disable + This parameter can be a value of @ref OSPI_Continuous_State */ + uint32_t CsTimeoutEnable; /* Cs timeout enable or disable + This parameter can be a value of @ref OSPI_Cs_Timeout_State */ + uint32_t WrapSize; /* Wrap size + This parameter can be a value of @ref OSPI_Wrap_Size */ + uint32_t BurstLen; /* Burst length + This parameter can be a value of @ref OSPI_Burst_Length */ + uint32_t HyperXspiLC1; /* The number of Latency cycles with RWDS being one + This parameter can be a value of @ref OSPI_Latency1_Cycles */ + uint32_t HyperXspiLc0; /* The number of Latency cycles with RWDS being zero + This parameter can be a value of @ref OSPI_Latency0_Cycles */ +}OSPI_MemoryInitTypeDef; + +/** + * @} + */ + +/** + * @brief DLYB Configuration Structure definition + */ + +typedef struct +{ + uint32_t Units; /*!< Specifies the Delay of a unit delay cell. + This parameter can be a value between 0 and DLYB_MAX_UNIT */ + + uint32_t PhaseSel; /*!< Specifies the Phase for the output clock. + This parameter can be a value between 0 and DLYB_MAX_SELECT */ +}OSPI_DLYB_CfgTypeDef; +/** + * @} + */ + +/* HAL_OSPI_Init */ +HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); + +/* HAL_OSPI_DeInit */ +HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi); + +/* HAL_OSPI_OctalInit */ +HAL_StatusTypeDef HAL_OSPI_OctalInit(OSPI_HandleTypeDef *hospi, OSPI_OctalInitTypeDef *Octal); + +/* HAL_OSPI_MemoryInit */ +HAL_StatusTypeDef HAL_OSPI_MemoryInit(OSPI_HandleTypeDef *hospi, OSPI_MemoryInitTypeDef *Memory); + +/* HAL_OSPI_CS_Select */ +void HAL_OSPI_CS_Select(OSPI_HandleTypeDef *hospi); + +/* HAL_OSPI_CS_Release */ +void HAL_OSPI_CS_Release(OSPI_HandleTypeDef *hospi); + +/* HAL_OSPI_Transmit */ +HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_TransmitKeepCS */ +HAL_StatusTypeDef HAL_OSPI_TransmitKeepCS(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_Receive */ +HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_ReceiveKeepCS */ +HAL_StatusTypeDef HAL_OSPI_ReceiveKeepCS(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_Transmit_IT */ +HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size); + +/* HAL_OSPI_Receive_IT */ +HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size); + +/* HAL_OSPI_Transmit_DMA */ +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size); + +/* HAL_OSPI_Receive_DMA */ +HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size); + +/* HAL_OSPI_SimultTransmitReceive */ +HAL_StatusTypeDef HAL_OSPI_SimultTransmitReceive(OSPI_HandleTypeDef *hospi, uint8_t *pTxData, \ + uint8_t *pRxData, uint32_t Size, uint32_t Timeout); + + +/* HAL_OSPI_TransmitByHalfWord */ +HAL_StatusTypeDef HAL_OSPI_TransmitByHalfWord(OSPI_HandleTypeDef *hospi, uint16_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_TransmitByWord */ +HAL_StatusTypeDef HAL_OSPI_TransmitByWord(OSPI_HandleTypeDef *hospi, uint32_t *pData, \ + uint32_t Size, uint32_t Timeout); + + +/* HAL_OSPI_ReceiveByHalfWord */ +HAL_StatusTypeDef HAL_OSPI_ReceiveByHalfWord(OSPI_HandleTypeDef *hospi, uint16_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_ReceiveByWord */ +HAL_StatusTypeDef HAL_OSPI_ReceiveByWord(OSPI_HandleTypeDef *hospi, uint32_t *pData, \ + uint32_t Size, uint32_t Timeout); + +/* HAL_OSPI_Transmit_Recieve_ByByte */ +HAL_StatusTypeDef HAL_OSPI_Transmit_Recieve_ByByte(OSPI_HandleTypeDef *hospi, uint8_t *pTxData, uint32_t TXSize, \ + uint8_t *pRxData, uint32_t RXSize, uint32_t Timeout); + +/* HAL_OSPI_Transmit_Recieve_ByHalfWord */ +HAL_StatusTypeDef HAL_OSPI_Transmit_Recieve_ByHalfWord(OSPI_HandleTypeDef *hospi, uint16_t *pTxData, uint32_t TXSize, \ + uint16_t *pRxData, uint32_t RXSize, uint32_t Timeout); + +/* HAL_OSPI_Transmit_Recieve_ByWord */ +HAL_StatusTypeDef HAL_OSPI_Transmit_Recieve_ByWord(OSPI_HandleTypeDef *hospi, uint32_t *pTxData, uint32_t TXSize, \ + uint32_t *pRxData, uint32_t RXSize, uint32_t Timeout); + +/* HAL_OSPI_GetTxState */ +uint8_t HAL_OSPI_GetTxState(OSPI_HandleTypeDef *hospi); +/* HAL_OSPI_GetRxState */ +uint8_t HAL_OSPI_GetRxState(OSPI_HandleTypeDef *hospi); + +/* HAL_OSPI_WireConfig */ +HAL_StatusTypeDef HAL_OSPI_WireConfig(OSPI_HandleTypeDef *hospi, uint32_t X_Mode); + +/* HAL_OSPI_TransmitRateMode */ +HAL_StatusTypeDef HAL_OSPI_TransmitRateMode(OSPI_HandleTypeDef *hospi, uint32_t mode); + +/* HAL_OSPI_FifoWriteMode */ +HAL_StatusTypeDef HAL_OSPI_FifoWriteMode(OSPI_HandleTypeDef *hospi, uint32_t mode); + +/* HAL_OSPI_FifoReadMode */ +HAL_StatusTypeDef HAL_OSPI_FifoReadMode(OSPI_HandleTypeDef *hospi, uint32_t mode); + +/* HAL_OSPI_APMDummyClock */ +HAL_StatusTypeDef HAL_OSPI_APMDummyClock(OSPI_HandleTypeDef *hospi, uint32_t APMClock); + +/* HAL_OSPI_TxOutDelay */ +HAL_StatusTypeDef HAL_OSPI_TxOutDelay(OSPI_HandleTypeDef *hospi, uint32_t Outdelay); + +/* HAL_OSPI_RxSampleDelay */ +HAL_StatusTypeDef HAL_OSPI_RxSampleDelay(OSPI_HandleTypeDef *hospi, uint32_t Sampledelay); + +/* HAL_OSPI_MemoryEnableDisable */ +HAL_StatusTypeDef HAL_OSPI_MemoryEnableDisable(OSPI_HandleTypeDef *hospi, uint32_t state); + +/* HAL_OSPI_DQSOutputEnableDisable */ +HAL_StatusTypeDef HAL_OSPI_DQSOutputEnableDisable(OSPI_HandleTypeDef *hospi, uint32_t state); + +/* HAL_OSPI_DQSSampleEnableDisable */ +HAL_StatusTypeDef HAL_OSPI_DQSSampleEnableDisable(OSPI_HandleTypeDef *hospi, uint32_t state); + +/* HAL_OSPI_DataMaskConfig */ +HAL_StatusTypeDef HAL_OSPI_DataMaskConfig(OSPI_HandleTypeDef *hospi, uint32_t DataMaskMode, uint32_t DataMaskCtrl); + + + +#endif + + + + + + + + + + + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_pmu.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_pmu.h new file mode 100644 index 0000000000000000000000000000000000000000..e733a3d428307f9de487c0575632f5ac13a3b562 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_pmu.h @@ -0,0 +1,325 @@ +/* + ****************************************************************************** + * @file HAL_PMU.h + * @version V1.0.0 + * @date 2022 + * @brief Header file of PMU HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_PMU_H__ +#define __HAL_PMU_H__ + +#include "hal.h" + + + + + + + +/** + * @brief IO wake-up source + */ +typedef enum +{ + PMU_WAKEUP1 = 0x00000001, //PA0 + PMU_WAKEUP2 = 0x00000002, //PA2 + PMU_WAKEUP3 = 0x00000004, //PI8 + PMU_WAKEUP4 = 0x00000008, //PC13 + PMU_WAKEUP5 = 0x00000010, //PI11 +}PMU_WakeUpIo_t; + +/** + * @brief RTC wake-up source + */ +typedef enum +{ + STANDBY_WAKEUP_WUTIE = RTC_IE_WUTIE, + STANDBY_WAKEUP_STAMP2 = (RTC_IE_STP2RIE | RTC_IE_STP2FIE), + STANDBY_WAKEUP_STAMP1 = (RTC_IE_STP1RIE | RTC_IE_STP1FIE), + STANDBY_WAKEUP_32S = RTC_IE_ADJ32_IE, + STANDBY_WAKEUP_ALARM = RTC_IE_ALM_IE, + STANDBY_WAKEUP_1KHZ = RTC_IE_1KHZ_IE, + STANDBY_WAKEUP_256HZ = RTC_IE_256HZ_IE, + STANDBY_WAKEUP_64HZ = RTC_IE_64HZ_IE , + STANDBY_WAKEUP_16HZ = RTC_IE_16HZ_IE , + STANDBY_WAKEUP_8HZ = RTC_IE_8HZ_IE , + STANDBY_WAKEUP_4HZ = RTC_IE_4HZ_IE , + STANDBY_WAKEUP_2HZ = RTC_IE_2HZ_IE , + STANDBY_WAKEUP_SEC = RTC_IE_SEC_IE , + STANDBY_WAKEUP_MIN = RTC_IE_MIN_IE , + STANDBY_WAKEUP_HOUR = RTC_IE_HOUR_IE , + STANDBY_WAKEUP_DATE = RTC_IE_DATE_IE , +}PMU_WakeUpRtc_t; + + +/** + * @brief Wakeup Polarity Configuration + */ +typedef enum +{ + PMU_WAKEUP_HIGH = 0x00000000, + PMU_WAKEUP_LOW = 0x00000001, +}PMU_WakeUpPolarity_t; + + +/** + * @brief Wakeup flag + */ +#define PMU_FLAG_WAKEUP1 ( PMU_SR_WUPFX_0 ) +#define PMU_FLAG_WAKEUP2 ( PMU_SR_WUPFX_1 ) +#define PMU_FLAG_WAKEUP3 ( PMU_SR_WUPFX_2 ) +#define PMU_FLAG_WAKEUP4 ( PMU_SR_WUPFX_3 ) +#define PMU_FLAG_WAKEUP5 ( PMU_SR_WUPFX_4 ) +//#define PMU_FLAG_WAKEUP6 ( PMU_SR_WUPFX_5 ) +#define PMU_FLAG_STANDBY ( PMU_SR_SBF ) +#define PMU_FLAG_RTC ( PMU_SR_RTCWUF ) +#define PMU_FLAG_RSET ( PMU_SR_RSTWUF ) +#define PMU_FLAG_IWDT ( PMU_SR_IWDTWUF ) +#define PMU_FLAG_BOR ( PMU_SR_BORWUF ) + + + +/** + * @brief Wait for an interrupt or event + */ + +#define WAIT_FOR_INT 0x00000000 +#define WAIT_FOR_EVENT 0x00000001 + +/** + * @brief Lowpower mode + */ +#define PMU_CTRL0_LPMS_STOP ( 0x0U << PMU_CTRL0_LPMS_Pos ) +#define PMU_CTRL0_LPMS_STANDBY ( 0x1U << PMU_CTRL0_LPMS_Pos ) + +/** + * @brief LVD Voltage + */ +#define PMU_LVD_1V71 ( 0x0U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V01 ( 0x1U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V23 ( 0x2U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V43 ( 0x3U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V51 ( 0x4U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V73 ( 0x5U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V80 ( 0x6U << PMU_CTRL1_LVDSEL_Pos) +#define PMU_LVD_2V90 ( 0x7U << PMU_CTRL1_LVDSEL_Pos) +#define IS_PMU_LVD_VOLTAGE(VOLTAGE) (((VOLTAGE) == PMU_LVD_1V71) || ((VOLTAGE) == PMU_LVD_2V01)|| \ + ((VOLTAGE) == PMU_LVD_2V23) || ((VOLTAGE) == PMU_LVD_2V43)|| \ + ((VOLTAGE) == PMU_LVD_2V51) || ((VOLTAGE) == PMU_LVD_2V73)|| \ + ((VOLTAGE) == PMU_LVD_2V80) || ((VOLTAGE) == PMU_LVD_2V90)) + +/** + * @brief LVD Filter + */ +#define PMU_LVD_FILTER_1 ( 0x0U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_2 ( 0x1U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_4 ( 0x2U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_16 ( 0x3U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_64 ( 0x4U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_256 ( 0x5U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_1024 ( 0x6U << PMU_CTRL1_FLTTIME_Pos) +#define PMU_LVD_FILTER_4095 ( 0x7U << PMU_CTRL1_FLTTIME_Pos) +#define IS_PMU_LVD_FILTER(FILTER) (((FILTER) == PMU_LVD_FILTER_1) || \ + ((FILTER) == PMU_LVD_FILTER_2) || \ + ((FILTER) == PMU_LVD_FILTER_4) || \ + ((FILTER) == PMU_LVD_FILTER_16) || \ + ((FILTER) == PMU_LVD_FILTER_64) || \ + ((FILTER) == PMU_LVD_FILTER_256) || \ + ((FILTER) == PMU_LVD_FILTER_1024) || \ + ((FILTER) == PMU_LVD_FILTER_4095)) + +/** + * @brief BOR Voltage + */ +#define PMU_BOR_2V0_2V1 ( 0x0U << PMU_CTRL2_BORCFG_Pos) +#define PMU_BOR_2V2_2V3 ( 0x1U << PMU_CTRL2_BORCFG_Pos) +#define PMU_BOR_2V49_2V61 ( 0x2U << PMU_CTRL2_BORCFG_Pos) +#define PMU_BOR_2V77_2V90 ( 0x3U << PMU_CTRL2_BORCFG_Pos) +#define IS_PMU_BOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PMU_BOR_2V0_2V1) || \ + ((VOLTAGE) == PMU_BOR_2V2_2V3) || \ + ((VOLTAGE) == PMU_BOR_2V49_2V61) || \ + ((VOLTAGE) == PMU_BOR_2V77_2V90)) + +/** @defgroup STANDBY mode wake-up waiting time + * @{ + */ +#define IS_PMU_STANDBY_WAKE_WAIT(WAIT) ((WAIT) <= 0xFU) + + +/** @defgroup PMU STOP wakeup wait time + * @{ + */ +#define IS_PMU_STOP_WAKE_WAIT(WAIT) ((WAIT) <= 0xFFFU) + + +/** @defgroup STANDBY domain IO + * @{ + */ +#define PMU_PIN_PC13 (0x00U) +#define PMU_PIN_PC14 (0x01U) +#define PMU_PIN_PC15 (0x02U) +#define PMU_PIN_PI8 (0x03U) +#define IS_PMU_PIN(PIN) (((PIN) == PMU_PIN_PC13) || ((PIN) == PMU_PIN_PC14) || \ + ((PIN) == PMU_PIN_PC15) || ((PIN) == PMU_PIN_PI8)) + +/** @defgroup STANDBY domain IO function selection + * @{ + */ +#define PMU_PIN_FUNCTION_GPIO (0U) +#define PMU_PIN_FUNCTION_PC14_VALUE (1U) +#define PMU_PIN_FUNCTION_PC15_VALUE (1U) +#define PMU_PIN_FUNCTION_PI8_VALUE (1U) +#define PMU_PIN_FUNCTION_PC13_RTC_SIGNAL (1U) +#define PMU_PIN_FUNCTION_TAMPER (2U) +#define PMU_PIN_FUNCTION_PC13_VALUE (3U) +#define IS_PMU_PIN_FUNCTION(__FUNC__) (((__FUNC__) == PMU_PIN_FUNCTION_GPIO) || \ + ((__FUNC__) == PMU_PIN_FUNCTION_PC14_VALUE) || \ + ((__FUNC__) == PMU_PIN_FUNCTION_PC15_VALUE) || \ + ((__FUNC__) == PMU_PIN_FUNCTION_PI8_VALUE) || \ + ((__FUNC__) == PMU_PIN_FUNCTION_PC13_RTC_SIGNAL) || \ + ((__FUNC__) == PMU_PIN_FUNCTION_TAMPER) || \ + ((__FUNC__) == PMU_PIN_FUNCTION_PC13_VALUE)) +/** + * @} + */ + +/** @defgroup STANDBY domain IO Pin Value + * @{ + */ +#define PMU_PIN_VALUE_0 (0x00U) +#define PMU_PIN_VALUE_1 (0x01U) +#define IS_PMU_PIN_VALUE(VALUE) (((VALUE) == PMU_PIN_VALUE_0) || ((VALUE) == PMU_PIN_VALUE_1)) + + +/** @defgroup PMU domain IO Pin (PC13) output mode + * @{ + */ +#define PMU_PIN_PC13_OD (0U) +#define PMU_PIN_PC13_PP (1U) +#define IS_PMU_PIN_PC13_OUTPUT(__MODE__) (((__MODE__) == PMU_PIN_PC13_OD) || \ + ((__MODE__) == PMU_PIN_PC13_PP)) +/** + * @} + */ + + +/** + * @brief Clear all wake-up status + */ +#define ALL_WANKEUP_STATUS (0xFFFFFFFF) + + +/** + * @brief RTC module write enable or diasble + */ +#define __HAL_PMU_RTC_WRITE_ENABLE (PMU->CTRL0 |= PMU_CTRL0_RTC_WE) +#define __HAL_PMU_RTC_WRITE_DISABLE (PMU->CTRL0 &= ~PMU_CTRL0_RTC_WE) + +/** + * @brief Tamper Pin + */ +#define PMU_IOSEL_PC13_SEL_RTC_TAMPER (0x2U) +#define PMU_IOSEL_PI8_SEL_RTC_TAMPER (0x2U) + +/** @brief PC13 function select + * @param __FUNC__: PC13 function select. + * This parameter can be 0: GPIO1RTC Fout2RTC tamper 3PC13 Value + */ +#define __HAL_PMU_PC13_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PC13SEL_Msk)) | (__FUNC__ << PMU_IOSEL_PC13SEL_Pos)) + +/** @brief PC14 function select + * @param __FUNC__: PC14 function select. + * This parameter can be 0: GPIO1PC14 Value + */ +#define __HAL_PMU_PC14_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PC14SEL_Msk)) | (__FUNC__ << PMU_IOSEL_PC14SEL_Pos)) + +/** @brief PC15 function select + * @param __FUNC__: PC15 function select. + * This parameter can be 0: GPIO1PC15 Value + */ +#define __HAL_PMU_PC15_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PC15SEL_Msk)) | (__FUNC__ << PMU_IOSEL_PC15SEL_Pos)) + +/** @brief PI8 function select + * @param __FUNC__: PI8 function select. + * This parameter can be 0: GPIO1PI8 Value2RTC tamper + */ +#define __HAL_PMU_PI8_SEL(__FUNC__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PI8SEL_Msk)) | (__FUNC__ << PMU_IOSEL_PI8SEL_Pos)) + + +/** @brief PC13 Value set + * @param __FUNC__: PC13 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_PMU_PC13_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PC13VALUE_Msk)) | (__VALUE__ << PMU_IOSEL_PC13VALUE_Pos)) + +/** @brief PC14 Value set + * @param __FUNC__: PC14 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_PMU_PC14_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PC14VALUE_Msk)) | (__VALUE__ << PMU_IOSEL_PC14VALUE_Pos)) + +/** @brief PC15 Value set + * @param __FUNC__: PC15 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_PMU_PC15_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PC15VALUE_Msk)) | (__VALUE__ << PMU_IOSEL_PC15VALUE_Pos)) + +/** @brief PI8 Value set + * @param __FUNC__: PI8 Value set. + * This parameter can be 0: set1claer + */ +#define __HAL_PMU_PI8_VALUE(__VALUE__) (PMU->IOSEL |= (PMU->IOSEL & ~(PMU_IOSEL_PI8VALUE_Msk)) | (__VALUE__ << PMU_IOSEL_PI8VALUE_Pos)) + +void HAL_PMU_Init(void); + +void HAL_PMU_EnterSleep(uint32_t mode); + +void HAL_PMU_EnterStop(uint32_t mode); + +void HAL_PMU_EnterStandbyMode(uint32_t mode); + +void HAL_PMU_WakeupIOInit(PMU_WakeUpIo_t wakeup_io, PMU_WakeUpPolarity_t polarity); + +void HAL_PMU_WakeupIODeInit(PMU_WakeUpIo_t wakeup_io); + +void HAL_PMU_StandbyWakeupRTCConfig(PMU_WakeUpRtc_t wakeup_rtc); + +void HAL_PMU_StandbyWakeupRTCRelease(PMU_WakeUpRtc_t wakeup_rtc); + +bool HAL_PMU_CheckStandbyStatus(void); + +bool HAL_PMU_CheckDeepSleepStatus(void); + +uint32_t HAL_PMU_GetWakeupSource(void); + +void HAL_PMU_ClearWakeupStatus(uint32_t status); + +void HAL_PMU_LvdEnable(uint32_t voltage, uint32_t filter, uint32_t filter_en); + +void HAL_PMU_LvdDisable(void); + +void HAL_PMU_BorResetEnable(uint32_t voltage); + +void HAL_PMU_BorResetDisable(void); + +void HAL_PMU_BorIrqEnable(uint32_t voltage); + +void HAL_PMU_BorIrqtDisable(void); + +void HAL_PMU_StopWaitTime(uint32_t stopWaitTime); + +void HAL_PMU_StandbypWaitTime(uint32_t standbyWaitTime); + +void HAL_PMU_StandbyDomainPinConfig(uint32_t PMU_Pin, uint32_t PMU_Func); + +void HAL_PMU_SetStandbyDomainPinValue(uint32_t PMU_Pin, uint32_t PMU_PinValue); + +uint32_t HAL_PMU_GetStandbyDomainPinValue(uint32_t PMU_Pin); + + +#endif + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_rcc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_rcc.h new file mode 100644 index 0000000000000000000000000000000000000000..60c77a5ac042242b80ba3a20190708d49c9d34de --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_rcc.h @@ -0,0 +1,1986 @@ +/****************************************************************************** +*@file : hal_rcc.h +*@brief : Header file of RCC HAL module. +******************************************************************************/ + +#ifndef __HAL_RCC_H__ +#define __HAL_RCC_H__ + +#include "acm32h5xx_hal_conf.h" + + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLL; /*!< The new state of the PLL. + This parameter can be a value of @ref FunctionalState */ + + uint32_t Source; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Source */ + + uint32_t PLLQCLK; + + uint32_t PLLPCLK; + + uint32_t PLLQ; /*!< PLLM: Output frequency division control field. + This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + + uint32_t PLLP; /*!< PLLN: the frequency division factor of the reference frequency. + This parameter must be a number between Min_Data = 0 and Max_Data = 3 */ + + uint32_t PLLN; /*!< PLLP: the frequency multiplication factor of the reference frequency.. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + + uint32_t PLLF; /*!< PLLP: the frequency multiplication factor of the reference frequency.. + This parameter must be a number between Min_Data = 0 and Max_Data = 511 */ + + uint32_t SSC; + + uint32_t SSCMode; + + uint32_t SSCSpectrum; + + uint32_t SSCStep; + + +}RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (RCH, RCL, XTH, and XTL) or PLL + * configuration structure definition + */ + +typedef struct +{ + uint32_t OscType; /*!< The oscillators or PLL to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t RCH; /*!< The new state of the RCH. + This parameter can be a value of @ref FunctionalState */ + + uint32_t RCHDiv16; /*!< If the system clock is RCH, the system clock will change + to 1/16 of the original after this position is ENABLE. + This parameter can be a value of @ref FunctionalState */ + + uint32_t RCL; /*!< The new state of the RCL. + This parameter can be a value of @ref FunctionalState */ + + uint32_t XTH; /*!< The new state of the XTH. + This parameter can be a value of @ref FunctionalState */ + + uint32_t XTHBypass; /*!< XTH oscillator bypass + This parameter can be a value of @ref FunctionalState */ + + uint32_t XTL; /*!< The new state of the XTL. + This parameter can be a value of @ref FunctionalState */ + + uint32_t XTLBypass; /*!< XTL oscillator bypass + This parameter can be a value of @ref FunctionalState */ + + RCC_PLLInitTypeDef PLL1; /*!< PLL1 structure parameters */ + + RCC_PLLInitTypeDef PLL2; /*!< PLL2 structure parameters */ + + RCC_PLLInitTypeDef PLL3; /*!< PLL3 structure parameters */ + +}RCC_OscInitTypeDef; + + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The system clock source. + This parameter can be a value of @ref RCC_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The system clock source. + This parameter can be a value of @ref RCC_Sysclk_Source */ + + uint32_t SYSCLKDiv0; /*!< First level frequency division of system clock. + This parameter can be a value of @ref RCC_Sysclk_DIV0 */ + + uint32_t SYSCLKDiv1; /*!< Second level frequency division of system clock. + This parameter can be a value of @ref RCC_Sysclk_DIV1 */ + + uint32_t PCLK1Div; /*!< PCLK1 (the APB1 clock) divider. + This parameter can be a value of @ref RCC_PCLK1_DIV */ + + uint32_t PCLK2Div; /*!< PCLK2 (the APB2 clock) divider. + This parameter can be a value of @ref RCC_PCLK2_DIV */ + + uint32_t PCLK3Div; /*!< PCLK2 (the APB2 clock) divider. + This parameter can be a value of @ref RCC_PCLK2_DIV */ + + uint32_t PCLK4Div; /*!< PCLK2 (the APB2 clock) divider. + This parameter can be a value of @ref RCC_PCLK2_DIV */ + +}RCC_ClkInitTypeDef; + +/** + * @brief RCC MCO configuration structure definition + */ + +typedef struct +{ + uint32_t MCO; /*!< MCO output select. + This parameter can be a value of @ref RCC_MCO_Output */ + + uint32_t MCO1; /*!< The new state of the MCO1. + This parameter can be a value of @ref FunctionalState */ + + uint32_t MCO1Div; /*!< MCO11 clock divider. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + + uint32_t MCO1RevPol; /*!< The new state of the MCO1 clock reverse polarity. + This parameter can be a value of @ref FunctionalState */ + + uint32_t MCO2; /*!< The new state of the MCO1. + This parameter can be a value of @ref FunctionalState */ + + uint32_t MCO2Div; /*!< MCO11 clock divider. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + + uint32_t MCO2RevPol; /*!< The new state of the MCO1 clock reverse polarity. + This parameter can be a value of @ref FunctionalState */ + +}RCC_MCOInitTypeDef; + + +/** @defgroup RCC_Oscillator_Type + * @{ + */ + +#define RCC_OSC_TYPE_RCH ( 0x01U ) +#define RCC_OSC_TYPE_RCL ( 0x02U ) +#define RCC_OSC_TYPE_XTH ( 0x04U ) +#define RCC_OSC_TYPE_XTL ( 0x08U ) +#define RCC_OSC_TYPE_PLL1 ( 0x10U ) +#define RCC_OSC_TYPE_PLL2 ( 0x20U ) +#define RCC_OSC_TYPE_PLL3 ( 0x40U ) + +/** + * @} + */ + +/** @brief Oscillator type mask for assert test + * @{ + */ + +#define RCC_OSC_TYPE_MASK ( RCC_OSC_TYPE_RCH | RCC_OSC_TYPE_RCL | RCC_OSC_TYPE_XTH | RCC_OSC_TYPE_XTL | \ + RCC_OSC_TYPE_PLL1 | RCC_OSC_TYPE_PLL2 | RCC_OSC_TYPE_PLL3 ) + +/** + * @} + */ + +/** @defgroup + * @{ + */ + +#define RCC_IT_RCL_READY ( BIT0 ) +#define RCC_IT_XTL_READY ( BIT1 ) +#define RCC_IT_RCH_READY ( BIT2 ) +#define RCC_IT_XTH_READY ( BIT3 ) +#define RCC_IT_PLL1_READY ( BIT4 ) +#define RCC_IT_PLL2_READY ( BIT5 ) +#define RCC_IT_PLL3_READY ( BIT6 ) +#define RCC_IT_XTH_STOP ( BIT27 ) +#define RCC_IT_XTL_STOP ( BIT31 ) +/** + * @} + */ + +#define RCC_IT_MASK ( RCC_IT_RCL_READY | RCC_IT_XTL_READY | RCC_IT_RCH_READY | \ + RCC_IT_XTH_READY | RCC_IT_PLL1_READY | RCC_IT_PLL2_READY | \ + RCC_IT_PLL3_READY | RCC_IT_XTH_STOP | RCC_IT_XTL_STOP ) +#define RCC_IT_READY_MASK ( RCC_IT_RCL_READY | RCC_IT_XTL_READY | RCC_IT_RCH_READY | RCC_IT_XTH_READY | \ + RCC_IT_PLL1_READY | RCC_IT_PLL2_READY | RCC_IT_PLL3_READY ) +#define RCC_IT_STOP_MASK ( RCC_IT_XTH_STOP | RCC_IT_XTL_STOP ) + +#define RCC_IT_CLEAR_FLAG_MASK ( (RCC_IT_READY_MASK << 16) | (RCC_IT_STOP_MASK >> 2) ) + +/** @defgroup + * @{ + */ + +#define RCC_FLAG_RCL_RDY ( BIT0 ) +#define RCC_FLAG_XTL_RDY ( BIT1 ) +#define RCC_FLAG_RCH_RDY ( BIT2 ) +#define RCC_FLAG_XTH_RDY ( BIT3 ) +#define RCC_FLAG_PLL1_RDY ( BIT4 ) +#define RCC_FLAG_PLL2_RDY ( BIT5 ) +#define RCC_FLAG_PLL3_RDY ( BIT6 ) +#define RCC_FLAG_XTH_STOP ( BIT27 ) +#define RCC_FLAG_XTL_STOP ( BIT31 ) +/** + * @} + */ + +#define RCC_FLAG_MASK ( RCC_FLAG_RCL_RDY | RCC_FLAG_XTL_RDY | RCC_FLAG_RCH_RDY | \ + RCC_FLAG_XTH_RDY | RCC_FLAG_PLL1_RDY | RCC_FLAG_PLL2_RDY | \ + RCC_FLAG_PLL3_RDY | RCC_FLAG_XTH_STOP | RCC_FLAG_XTL_STOP ) + +/** @defgroup RCC_XTL_Drive_Capacity + * @{ + */ + +#define RCC_XTL_DRIVE_NORMAL_LEVEL0 ( 0U ) +#define RCC_XTL_DRIVE_NORMAL_LEVEL1 ( 1U ) +#define RCC_XTL_DRIVE_NORMAL_LEVEL2 ( 2U ) +#define RCC_XTL_DRIVE_NORMAL_LEVEL3 ( 3U ) +#define RCC_XTL_DRIVE_LOWPOWER_LEVEL0 ( 4U ) +#define RCC_XTL_DRIVE_LOWPOWER_LEVEL1 ( 5U ) +#define RCC_XTL_DRIVE_LOWPOWER_LEVEL2 ( 6U ) +#define RCC_XTL_DRIVE_LOWPOWER_LEVEL3 ( 7U ) +#define RCC_XTL_DRIVE_MAX ( 8U ) + +/** + * @} + */ + +/** @defgroup RCC_PLL_Source + * @{ + */ + +#define RCC_PLL_SOURCE_RCH_DIV16 ( 0U ) +#define RCC_PLL_SOURCE_XTH ( 1U ) +#define RCC_PLL_SOURCE_MAX ( 2U ) + +#define RCC_PLL_SSC_MODE_CENTER ( 0 ) +#define RCC_PLL_SSC_MODE_DOWN ( RCC_PLL1SCR_PLL1SSCMD ) + +/** @defgroup RCC_Clock_Type + * @{ + */ + +#define RCC_CLOCK_TYPE_SYSCLK ( 0x01U ) +#define RCC_CLOCK_TYPE_SYSDIV0 ( 0x02U ) +#define RCC_CLOCK_TYPE_SYSDIV1 ( 0x04U ) +#define RCC_CLOCK_TYPE_PCLK1 ( 0x08U ) +#define RCC_CLOCK_TYPE_PCLK2 ( 0x10U ) +#define RCC_CLOCK_TYPE_PCLK3 ( 0x20U ) +#define RCC_CLOCK_TYPE_PCLK4 ( 0x40U ) + +/** + * @} + */ +/** @brief System Clock type mask for assert test + * @{ + */ + +#define RCC_CLOCK_TYPE_MASK ( RCC_CLOCK_TYPE_SYSCLK | RCC_CLOCK_TYPE_SYSDIV0 | RCC_CLOCK_TYPE_SYSDIV1 | \ + RCC_CLOCK_TYPE_PCLK1 | RCC_CLOCK_TYPE_PCLK2 | RCC_CLOCK_TYPE_PCLK3 | RCC_CLOCK_TYPE_PCLK4) + +/** + * @} + */ + +/** @defgroup RCC_Sysclk_Source + * @{ + */ + +#define RCC_SYSCLK_SOURCE_RCH ( 0U ) +#define RCC_SYSCLK_SOURCE_XTH ( 1U ) +#define RCC_SYSCLK_SOURCE_PLL1PCLK ( 2U ) +#define RCC_SYSCLK_SOURCE_MAX ( 3U ) + +/** + * @} + */ + + +/** @defgroup RCC_FLT_CLK_Source + * @{ + */ + +#define RCC_FLT_CLK_SOURCE_PCLK1_DIV32 ( 0U ) +#define RCC_FLT_CLK_SOURCE_RCL ( 1U ) +#define RCC_FLT_CLK_SOURCE_MAX ( 2U ) + +/** + * @} + */ + +/** @defgroup RCC_LPUART1_CLK_Source + * @{ + */ + +#define RCC_LPUART1_CLK_SOURCE_RCL ( 0U ) +#define RCC_LPUART1_CLK_SOURCE_XTL ( 1U ) +#define RCC_LPUART1_CLK_SOURCE_PCLK1_DIV4 ( 2U ) +#define RCC_LPUART1_CLK_SOURCE_PCLK1_DIV8 ( 3U ) +#define RCC_LPUART1_CLK_SOURCE_PCLK1_DIV16 ( 4U ) +#define RCC_LPUART1_CLK_SOURCE_PCLK1_DIV32 ( 5U ) +#define RCC_LPUART1_CLK_SOURCE_MAX ( 6U ) + +/** + * @} + */ + +/** @defgroup RCC_LPTIM1_CLK_Source + * @{ + */ + +#define RCC_LPTIM1_CLK_SOURCE_PCLK1 ( 0U ) +#define RCC_LPTIM1_CLK_SOURCE_RCL ( 1U ) +#define RCC_LPTIM1_CLK_SOURCE_RCH ( 2U ) +#define RCC_LPTIM1_CLK_SOURCE_XTL ( 3U ) +#define RCC_LPTIM1_CLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_LPTIM2_CLK_Source + * @{ + */ + +#define RCC_LPTIM2_CLK_SOURCE_PCLK1 ( 0U ) +#define RCC_LPTIM2_CLK_SOURCE_RCL ( 1U ) +#define RCC_LPTIM2_CLK_SOURCE_RCH ( 2U ) +#define RCC_LPTIM2_CLK_SOURCE_XTL ( 3U ) +#define RCC_LPTIM2_CLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_LPTIM3_CLK_Source + * @{ + */ + +#define RCC_LPTIM3_CLK_SOURCE_PCLK3 ( 0U ) +#define RCC_LPTIM3_CLK_SOURCE_RCL ( 1U ) +#define RCC_LPTIM3_CLK_SOURCE_RCH ( 2U ) +#define RCC_LPTIM3_CLK_SOURCE_XTL ( 3U ) +#define RCC_LPTIM3_CLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_LPTIM345_CLK_Source + * @{ + */ + +#define RCC_LPTIM4_CLK_SOURCE_PCLK3 ( 0U ) +#define RCC_LPTIM4_CLK_SOURCE_RCL ( 1U ) +#define RCC_LPTIM4_CLK_SOURCE_RCH ( 2U ) +#define RCC_LPTIM4_CLK_SOURCE_XTL ( 3U ) +#define RCC_LPTIM4_CLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_LPTIM345_CLK_Source + * @{ + */ + +#define RCC_LPTIM5_CLK_SOURCE_PCLK3 ( 0U ) +#define RCC_LPTIM5_CLK_SOURCE_RCL ( 1U ) +#define RCC_LPTIM5_CLK_SOURCE_RCH ( 2U ) +#define RCC_LPTIM5_CLK_SOURCE_XTL ( 3U ) +#define RCC_LPTIM5_CLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_LPTIM6_CLK_Source + * @{ + */ + +#define RCC_LPTIM6_CLK_SOURCE_PCLK3 ( 0U ) +#define RCC_LPTIM6_CLK_SOURCE_RCL ( 1U ) +#define RCC_LPTIM6_CLK_SOURCE_RCH ( 2U ) +#define RCC_LPTIM6_CLK_SOURCE_XTL ( 3U ) +#define RCC_LPTIM6_CLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_SDMMC_CLK_Source + * @{ + */ + +#define RCC_SDMMC_CLK_SOURCE_SYSCLK ( 0U ) +#define RCC_SDMMC_CLK_SOURCE_PLL2PCLK ( 1U ) +#define RCC_SDMMC_CLK_SOURCE_MAX ( 2U ) + +/** + * @} + */ + +/** @defgroup RCC_SDMMC_SCLK_Source + * @{ + */ + +#define RCC_SDMMC_SCLK_SOURCE_SDMMC_CLK_DELAY ( 0U ) +#define RCC_SDMMC_SCLK_SOURCE_SDMMC1_CKIN ( 1U ) +#define RCC_SDMMC_SCLK_SOURCE_SDMMC2_CKIN ( 2U ) +#define RCC_SDMMC_SCLK_SOURCE_SDMMC_CLK_NO_DELAY ( 3U ) +#define RCC_SDMMC_SCLK_SOURCE_MAX ( 4U ) + +/** + * @} + */ + +/** @defgroup RCC_RTC_CLK_Source + * @{ + */ + +#define RCC_RTC_CLK_SOURCE_RCL ( 0U ) +#define RCC_RTC_CLK_SOURCE_XTL ( 1U ) +#define RCC_RTC_CLK_SOURCE_MAX ( 2U ) + +/** + * @} + */ + +/** @defgroup RCC_MCO_Output + * @{ + */ + +#define RCC_MCO_HCLK ( 0U ) +#define RCC_MCO_RCH ( 1U ) +#define RCC_MCO_RCL ( 2U ) +#define RCC_MCO_XTH ( 3U ) +#define RCC_MCO_XTL ( 4U ) +#define RCC_MCO_PLL1PCLK ( 5U ) +#define RCC_MCO_PLL2PCLK ( 6U ) +#define RCC_MCO_PLL2QCLK ( 7U ) +#define RCC_MCO_PLL3PCLK ( 8U ) +#define RCC_MCO_PLL3QCLK ( 9U ) +#define RCC_MCO_SYSCLK ( 10U ) +#define RCC_MCO_LPUART1_CLK ( 11U ) +#define RCC_MCO_FCLK_DIV8 ( 12U ) +#define RCC_MCO_USB1_48M ( 13U ) +#define RCC_MCO_USB2_48M ( 14U ) +#define RCC_MCO_RTC_PCLK ( 15U ) +#define RCC_MCO_SDMMC_SAMPLE_CLK ( 16U ) +#define RCC_MCO_SDMMC_DRIVE_CLK ( 17U ) +#define RCC_MCO_MAX ( 18U ) + +/** + * @} + */ + +/** @defgroup RCC_Reset_Source RCC Reset Source + * @{ + */ + +#define RCC_RESET_SOURCE_PWR ( RCC_RSR_PWRRSTF ) +#define RCC_RESET_SOURCE_POR12 ( RCC_RSR_POR12RSTF ) +#define RCC_RESET_SOURCE_SRST ( RCC_RSR_SRSTF ) +#define RCC_RESET_SOURCE_RSTN ( RCC_RSR_RSTNF ) +#define RCC_RESET_SOURCE_SYSREQ ( RCC_RSR_SYSREQRSTF ) +#define RCC_RESET_SOURCE_LOCKUP ( RCC_RSR_LOCKUPRSTF ) +#define RCC_RESET_SOURCE_IWDT ( RCC_RSR_IWDTRSTF ) +#define RCC_RESET_SOURCE_WDT ( RCC_RSR_WDTRSTF ) +#define RCC_RESET_SOURCE_LVD ( RCC_RSR_LVDRSTF ) + +/** + * @} + */ + +/** @defgroup RCC_Reset_Source RCC Reset Source + * @{ + */ + +#define RCC_RESET_SOURCE_MASK ( RCC_RESET_SOURCE_PWR | RCC_RESET_SOURCE_POR12 | RCC_RESET_SOURCE_SRST | \ + RCC_RESET_SOURCE_RSTN | RCC_RESET_SOURCE_SYSREQ | RCC_RESET_SOURCE_LOCKUP | \ + RCC_RESET_SOURCE_IWDT | RCC_RESET_SOURCE_WDT | RCC_RESET_SOURCE_LVD) + +/** + * @} + */ +#define __HAL_RCC_RTC_ENABLE() ( RCC->STDBYCTRL |= RCC_STDBYCTRL_RTCEN ) +#define __HAL_RCC_RTC_DISABLE() ( RCC->STDBYCTRL &= ~RCC_STDBYCTRL_RTCEN ) + +#define __HAL_RCC_XTH_STOP_ENABLE() ( RCC->XTHCR |= RCC_XTHCR_XTHSDEN ) +#define __HAL_RCC_XTH_STOP_DISABLE() ( RCC->XTHCR &= ~RCC_XTHCR_XTHSDEN ) + +#define __HAL_RCC_XTL_STOP_ENABLE() ( RCC->STDBYCTRL |= RCC_STDBYCTRL_XTLSDEN ) +#define __HAL_RCC_XTL_STOP_DISABLE() ( RCC->STDBYCTRL &= ~RCC_STDBYCTRL_XTLSDEN ) + +#define RCC_RCH_READY_TIMEOUT ( 0xFFFFU ) +#define RCC_RCH_UNREADY_TIMEOUT ( 0xFFFFU ) +#define RCC_RCHP_READY_TIMEOUT ( 0xFFFFU ) +#define RCC_RCHP_UNREADY_TIMEOUT ( 0xFFFFU ) +#define RCC_RCL_READY_TIMEOUT ( 0xFFFFU ) +#define RCC_RCL_UNREADY_TIMEOUT ( 0xFFFFU ) +#define RCC_XTH_READY_TIMEOUT ( 0xFFFFFU ) +#define RCC_XTH_UNREADY_TIMEOUT ( 0xFFFFFU ) +#define RCC_XTL_READY_TIMEOUT ( 0xFFFFFU ) +#define RCC_XTL_UNREADY_TIMEOUT ( 0xFFFFU ) +#define RCC_PLL1_READY_TIMEOUT ( 0xFFFFU ) +#define RCC_PLL2_READY_TIMEOUT ( 0xFFFFU ) +#define RCC_PLL3_READY_TIMEOUT ( 0xFFFFU ) + + + +#define __HAL_RCC_FDCAN2_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_FDCAN2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_FDCAN2RST; \ + }while (0) + +#define __HAL_RCC_FDCAN1_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_FDCAN1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_FDCAN1RST; \ + }while (0) + +#define __HAL_RCC_USB2_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_USB2CRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_USB2CRST; \ + }while (0) + +#define __HAL_RCC_USB1_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_USB1CRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_USB1CRST; \ + }while (0) + +#define __HAL_RCC_SPI6_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_SPI6RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_SPI6RST; \ + }while (0) + +#define __HAL_RCC_SPI5_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_SPI5RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_SPI5RST; \ + }while (0) + +#define __HAL_RCC_SPI4_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_SPI4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_SPI4RST; \ + }while (0) + +#define __HAL_RCC_SPI3_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_SPI3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_SPI3RST; \ + }while (0) + +#define __HAL_RCC_SPI2_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_SPI2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_SPI2RST; \ + }while (0) + +#define __HAL_RCC_SPI1_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_SPI1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_SPI1RST; \ + }while (0) + + +#define __HAL_RCC_DMA2D_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_DMA2DRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_DMA2DRST; \ + }while (0) + +#define __HAL_RCC_ETH_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_ETHRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_ETHRST; \ + }while (0) + +#define __HAL_RCC_CRC_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_CRCRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_CRCRST; \ + }while (0) + +#define __HAL_RCC_DMA2_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_DMA2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_DMA2RST; \ + }while (0) + +#define __HAL_RCC_DMA1_RESET() do \ + { \ + RCC->AHB1RSTR &= ~RCC_AHB1RSTR_DMA1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB1RSTR |= RCC_AHB1RSTR_DMA1RST; \ + }while (0) + +/** @brief the AHB2 peripheral reset. + */ + +#define __HAL_RCC_THM_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_THMRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_THMRST; \ + }while (0) + +#define __HAL_RCC_FDCAN3_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_FDCAN3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_FDCAN3RST; \ + }while (0) + +#define __HAL_RCC_UAC_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_UACRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_UACRST; \ + }while (0) + +#define __HAL_RCC_DCMI_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_DCMIRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_DCMIRST; \ + }while (0) + +#define __HAL_RCC_DAC2_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_DAC2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_DAC2RST; \ + }while (0) + +#define __HAL_RCC_DAC1_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_DAC1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_DAC1RST; \ + }while (0) + +#define __HAL_RCC_ADC3_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_ADC3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_ADC3RST; \ + }while (0) + +#define __HAL_RCC_ADC12_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_ADC12RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_ADC12RST; \ + }while (0) + +#define __HAL_RCC_GPIOQ_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOQRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOQRST; \ + }while (0) + +#define __HAL_RCC_GPIOP_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOPRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOPRST; \ + }while (0) + +#define __HAL_RCC_GPIOO_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOORST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOORST; \ + }while (0) + +#define __HAL_RCC_GPION_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIONRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIONRST; \ + }while (0) + +#define __HAL_RCC_GPIOM_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOMRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOMRST; \ + }while (0) + +#define __HAL_RCC_GPIOL_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOLRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOLRST; \ + }while (0) + +#define __HAL_RCC_GPIOK_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOKRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOKRST; \ + }while (0) + +#define __HAL_RCC_GPIOJ_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOJRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOJRST; \ + }while (0) + +#define __HAL_RCC_GPIOI_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOIRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOIRST; \ + }while (0) + +#define __HAL_RCC_GPIOH_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOHRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOHRST; \ + }while (0) + +#define __HAL_RCC_GPIOG_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOGRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOGRST; \ + }while (0) + +#define __HAL_RCC_GPIOF_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOFRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOFRST; \ + }while (0) + +#define __HAL_RCC_GPIOE_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOERST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOERST; \ + }while (0) + +#define __HAL_RCC_GPIOD_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIODRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIODRST; \ + }while (0) + +#define __HAL_RCC_GPIOC_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOCRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOCRST; \ + }while (0) + +#define __HAL_RCC_GPIOB_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOBRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOBRST; \ + }while (0) + +#define __HAL_RCC_GPIOA_RESET() do \ + { \ + RCC->AHB2RSTR &= ~RCC_AHB2RSTR_GPIOARST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB2RSTR |= RCC_AHB2RSTR_GPIOARST; \ + }while (0) + +/** @brief the AHB3 peripheral reset. + */ + +#define __HAL_RCC_FMC_RESET() do \ + { \ + RCC->AHB3RSTR &= ~RCC_AHB3RSTR_FMCRST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB3RSTR |= RCC_AHB3RSTR_FMCRST; \ + }while (0) + +#define __HAL_RCC_OSPI2_RESET() do \ + { \ + RCC->AHB3RSTR &= ~RCC_AHB3RSTR_OSPI2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB3RSTR |= RCC_AHB3RSTR_OSPI2RST; \ + }while (0) + +#define __HAL_RCC_OSPI1_RESET() do \ + { \ + RCC->AHB3RSTR &= ~RCC_AHB3RSTR_OSPI1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB3RSTR |= RCC_AHB3RSTR_OSPI1RST; \ + }while (0) + +#define __HAL_RCC_SDIO_RESET() do \ + { \ + RCC->AHB3RSTR &= ~RCC_AHB3RSTR_SDIORST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB3RSTR |= RCC_AHB3RSTR_SDIORST; \ + }while (0) + +#define __HAL_RCC_SPI8_RESET() do \ + { \ + RCC->AHB3RSTR &= ~RCC_AHB3RSTR_SPI8RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB3RSTR |= RCC_AHB3RSTR_SPI8RST; \ + }while (0) + +#define __HAL_RCC_SPI7_RESET() do \ + { \ + RCC->AHB3RSTR &= ~RCC_AHB3RSTR_SPI7RST; \ + __NOP();__NOP();__NOP(); \ + RCC->AHB3RSTR |= RCC_AHB3RSTR_SPI7RST; \ + }while (0) + +/** @brief the APB1 peripheral reset. + */ + +#define __HAL_RCC_LPUART1_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_LPUART1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_LPUART1RST; \ + }while (0) + +#define __HAL_RCC_LPTIM1_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_LPTIM1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_LPTIM1RST; \ + }while (0) + +#define __HAL_RCC_PMU_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_PMURST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_PMURST; \ + }while (0) + +#define __HAL_RCC_I2C4_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2C4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2C4RST; \ + }while (0) + +#define __HAL_RCC_I2C3_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2C3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2C3RST; \ + }while (0) + +#define __HAL_RCC_I2C2_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2C2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2C2RST; \ + }while (0) + +#define __HAL_RCC_I2C1_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2C1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2C1RST; \ + }while (0) + +#define __HAL_RCC_USART5_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_USART5RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_USART5RST; \ + }while (0) + +#define __HAL_RCC_USART4_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_USART4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_USART4RST; \ + }while (0) + +#define __HAL_RCC_USART3_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_USART3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_USART3RST; \ + }while (0) + +#define __HAL_RCC_USART2_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_USART2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_USART2RST; \ + }while (0) + +#define __HAL_RCC_I2S3_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2S3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2S3RST; \ + }while (0) + +#define __HAL_RCC_I2S2_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2S2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2S2RST; \ + }while (0) + +#define __HAL_RCC_I2S1_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_I2S1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_I2S1RST; \ + }while (0) + +#define __HAL_RCC_WDT_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_WDTRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_WDTRST; \ + }while (0) + +#define __HAL_RCC_TIM14_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM14RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM14RST; \ + }while (0) + +#define __HAL_RCC_TIM13_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM13RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM13RST; \ + }while (0) + +#define __HAL_RCC_TIM12_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM12RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM12RST; \ + }while (0) + +#define __HAL_RCC_TIM7_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM7RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM7RST; \ + }while (0) + +#define __HAL_RCC_TIM6_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM6RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM6RST; \ + }while (0) + +#define __HAL_RCC_TIM5_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM5RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM5RST; \ + }while (0) + +#define __HAL_RCC_TIM4_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM4RST; \ + }while (0) + +#define __HAL_RCC_TIM3_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM3RST; \ + }while (0) + +#define __HAL_RCC_TIM2_RESET() do \ + { \ + RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_TIM2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR1 |= RCC_APB1RSTR1_TIM2RST; \ + }while (0) + +#define __HAL_RCC_EFUSE2_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_EFUSE2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_EFUSE2RST; \ + }while (0) + +#define __HAL_RCC_EFUSE1_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_EFUSE1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_EFUSE1RST; \ + }while (0) + +#define __HAL_RCC_TIM26_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_TIM26RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_TIM26RST; \ + }while (0) + +#define __HAL_RCC_TIM25_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_TIM25RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_TIM25RST; \ + }while (0) + +#define __HAL_RCC_USART8_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_USART8RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_USART8RST; \ + }while (0) + +#define __HAL_RCC_USART7_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_USART7RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_USART7RST; \ + }while (0) + +#define __HAL_RCC_LPTIM2_RESET() do \ + { \ + RCC->APB1RSTR2 &= ~RCC_APB1RSTR2_LPTIM2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB1RSTR2 |= RCC_APB1RSTR2_LPTIM2RST; \ + }while (0) + +/** @brief the APB2 peripheral reset. + */ + +#define __HAL_RCC_USART10_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_USART10RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_USART10RST; \ + }while (0) + +#define __HAL_RCC_USART9_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_USART9RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_USART9RST; \ + }while (0) + +#define __HAL_RCC_TIM24_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM24RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM24RST; \ + }while (0) + +#define __HAL_RCC_TIM23_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM23RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM23RST; \ + }while (0) + +#define __HAL_RCC_TIM22_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM22RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM22RST; \ + }while (0) + +#define __HAL_RCC_TIM21_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM21RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM21RST; \ + }while (0) + +#define __HAL_RCC_TIM19_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM19RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM19RST; \ + }while (0) + +#define __HAL_RCC_TIM18_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM18RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM18RST; \ + }while (0) + +#define __HAL_RCC_TIM11_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM11RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM11RST; \ + }while (0) + +#define __HAL_RCC_TIM10_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM10RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM10RST; \ + }while (0) + +#define __HAL_RCC_TIM9_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM9RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM9RST; \ + }while (0) + +#define __HAL_RCC_LTDC_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_LTDCRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_LTDCRST; \ + }while (0) + +#define __HAL_RCC_TKEY_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TKEYRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TKEYRST; \ + }while (0) + +#define __HAL_RCC_TIM20_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM20RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM20RST; \ + }while (0) + +#define __HAL_RCC_TIM17_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM17RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM17RST; \ + }while (0) + +#define __HAL_RCC_TIM16_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM16RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM16RST; \ + }while (0) + +#define __HAL_RCC_TIM15_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM15RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM15RST; \ + }while (0) + +#define __HAL_RCC_USART6_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_USART6RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_USART6RST; \ + }while (0) + +#define __HAL_RCC_USART1_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_USART1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_USART1RST; \ + }while (0) + +#define __HAL_RCC_TIM8_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM8RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM8RST; \ + }while (0) + +#define __HAL_RCC_TIM1_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_TIM1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_TIM1RST; \ + }while (0) + +#define __HAL_RCC_EXTI_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_EXTIRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_EXTIRST; \ + }while (0) + +#define __HAL_RCC_CMP1_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_CMP1RST_A; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_CMP1RST_A; \ + }while (0) + +#define __HAL_RCC_SYSCFG_RESET() do \ + { \ + RCC->APB2RSTR &= ~RCC_APB2RSTR_SYSCFGRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB2RSTR |= RCC_APB2RSTR_SYSCFGRST; \ + }while (0) + +/** @brief the APB3 peripheral reset. + */ + +#define __HAL_RCC_LPTIM6_RESET() do \ + { \ + RCC->APB3RSTR &= ~RCC_APB3RSTR_LPTIM6RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB3RSTR |= RCC_APB3RSTR_LPTIM6RST; \ + }while (0) + +#define __HAL_RCC_LPTIM5_RESET() do \ + { \ + RCC->APB3RSTR &= ~RCC_APB3RSTR_LPTIM5RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB3RSTR |= RCC_APB3RSTR_LPTIM5RST; \ + }while (0) + +#define __HAL_RCC_LPTIM4_RESET() do \ + { \ + RCC->APB3RSTR &= ~RCC_APB3RSTR_LPTIM4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB3RSTR |= RCC_APB3RSTR_LPTIM4RST; \ + }while (0) + +#define __HAL_RCC_LPTIM3_RESET() do \ + { \ + RCC->APB3RSTR &= ~RCC_APB3RSTR_LPTIM3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB3RSTR |= RCC_APB3RSTR_LPTIM3RST; \ + }while (0) + +/** @brief the APB4 peripheral reset. + */ + +#define __HAL_RCC_DPWM6_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_DPWM6RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_DPWM6RST; \ + }while (0) + +#define __HAL_RCC_DPWM5_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_DPWM5RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_DPWM5RST; \ + }while (0) + +#define __HAL_RCC_SPWM6_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_SPWM6RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_SPWM6RST; \ + }while (0) + +#define __HAL_RCC_SPWM5_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_SPWM5RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_SPWM5RST; \ + }while (0) + +#define __HAL_RCC_SPWM4_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_SPWM4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_SPWM4RST; \ + }while (0) + +#define __HAL_RCC_SPWM3_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_SPWM3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_SPWM3RST; \ + }while (0) + +#define __HAL_RCC_MDAC_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_MDACRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_MDACRST; \ + }while (0) + +#define __HAL_RCC_LPT_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_LPTRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_LPTRST; \ + }while (0) + +#define __HAL_RCC_PNDL_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_PNDLRST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_PNDLRST; \ + }while (0) + +#define __HAL_RCC_DPWM4_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_DPWM4RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_DPWM4RST; \ + }while (0) + +#define __HAL_RCC_DPWM3_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_DPWM3RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_DPWM3RST; \ + }while (0) + +#define __HAL_RCC_DPWM2_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_DPWM2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_DPWM2RST; \ + }while (0) + +#define __HAL_RCC_DPWM1_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_DPWM1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_DPWM1RST; \ + }while (0) + +#define __HAL_RCC_SPWM2_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_SPWM2RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_SPWM2RST; \ + }while (0) + +#define __HAL_RCC_SPWM1_RESET() do \ + { \ + RCC->APB4RSTR &= ~RCC_APB4RSTR_SPWM1RST; \ + __NOP();__NOP();__NOP(); \ + RCC->APB4RSTR |= RCC_APB4RSTR_SPWM1RST; \ + }while (0) + +/** @brief Enable or Disable the AHB1 peripheral clock. + */ + +#define __HAL_RCC_SRAM2_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SRAM2CKEN ) +#define __HAL_RCC_SRAM2_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SRAM2CKEN ) +#define __HAL_RCC_SRAM1_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SRAM1CKEN ) +#define __HAL_RCC_SRAM1_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SRAM1CKEN ) +#define __HAL_RCC_ROM_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_ROMCKEN ) +#define __HAL_RCC_ROM_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_ROMCKEN ) +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_BKPSRAMCKEN ) +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_BKPSRAMCKEN ) +#define __HAL_RCC_FDCAN2_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_FDCAN2CKEN ) +#define __HAL_RCC_FDCAN2_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_FDCAN2CKEN ) +#define __HAL_RCC_FDCAN1_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_FDCAN1CKEN ) +#define __HAL_RCC_FDCAN1_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_FDCAN1CKEN ) +#define __HAL_RCC_USB2_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_USB2CCKEN ) +#define __HAL_RCC_USB2_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_USB2CCKEN ) +#define __HAL_RCC_USB1_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_USB1CCKEN ) +#define __HAL_RCC_USB1_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_USB1CCKEN ) +#define __HAL_RCC_SPI6_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SPI6CKEN ) +#define __HAL_RCC_SPI6_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SPI6CKEN ) +#define __HAL_RCC_SPI5_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SPI5CKEN ) +#define __HAL_RCC_SPI5_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SPI5CKEN ) +#define __HAL_RCC_SPI4_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SPI4CKEN ) +#define __HAL_RCC_SPI4_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SPI4CKEN ) +#define __HAL_RCC_SPI3_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SPI3CKEN ) +#define __HAL_RCC_SPI3_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SPI3CKEN ) +#define __HAL_RCC_SPI2_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SPI2CKEN ) +#define __HAL_RCC_SPI2_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SPI2CKEN ) +#define __HAL_RCC_SPI1_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_SPI1CKEN ) +#define __HAL_RCC_SPI1_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_SPI1CKEN ) +#define __HAL_RCC_DMA2D_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_DMA2DCKEN ) +#define __HAL_RCC_DMA2D_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_DMA2DCKEN ) +#define __HAL_RCC_ETHRX_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_ETHRXCKEN ) +#define __HAL_RCC_ETHRX_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_ETHRXCKEN ) +#define __HAL_RCC_ETHTX_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_ETHTXCKEN ) +#define __HAL_RCC_ETHTX_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_ETHTXCKEN ) +#define __HAL_RCC_ETHMAC_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_ETHMACCKEN ) +#define __HAL_RCC_ETHMAC_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_ETHMACCKEN ) +#define __HAL_RCC_CRC_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_CRCCKEN ) +#define __HAL_RCC_CRC_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_CRCCKEN ) +#define __HAL_RCC_DMA2_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_DMA2CKEN ) +#define __HAL_RCC_DMA2_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_DMA2CKEN ) +#define __HAL_RCC_DMA1_CLK_ENABLE() ( RCC->AHB1CKENR |= RCC_AHB1CKENR_DMA1CKEN ) +#define __HAL_RCC_DMA1_CLK_DISABLE() ( RCC->AHB1CKENR &= ~RCC_AHB1CKENR_DMA1CKEN ) + +/** @brief Enable or Disable the AHB2 peripheral clock. + */ + +#define __HAL_RCC_THM_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_THMCKEN ) +#define __HAL_RCC_THM_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_THMCKEN ) +#define __HAL_RCC_FDCAN3_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_FDCAN3CKEN ) +#define __HAL_RCC_FDCAN3_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_FDCAN3CKEN ) +#define __HAL_RCC_CORDIC_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_CORDICCKEN ) +#define __HAL_RCC_CORDIC_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_CORDICCKEN ) +#define __HAL_RCC_HRNG_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_HRNGCKEN ) +#define __HAL_RCC_HRNG_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_HRNGCKEN ) +#define __HAL_RCC_AES_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_AESCKEN ) +#define __HAL_RCC_AES_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_AESCKEN ) +#define __HAL_RCC_AES_SPI1_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_AESSPI1CKEN ) +#define __HAL_RCC_AES_SPI1_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_AESSPI1CKEN ) +#define __HAL_RCC_DCMI_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_DCMICKEN ) +#define __HAL_RCC_DCMI_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_DCMICKEN ) +#define __HAL_RCC_DAC2_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_DAC2CKEN ) +#define __HAL_RCC_DAC2_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_DAC2CKEN ) +#define __HAL_RCC_DAC1_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_DAC1CKEN ) +#define __HAL_RCC_DAC1_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_DAC1CKEN ) +#define __HAL_RCC_ADC3_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_ADC3CKEN ) +#define __HAL_RCC_ADC3_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_ADC3CKEN ) +#define __HAL_RCC_ADC12_CLK_ENABLE() ( RCC->AHB2CKENR |= RCC_AHB2CKENR_ADC12CKEN ) +#define __HAL_RCC_ADC12_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_ADC12CKEN ) +#define __HAL_RCC_GPIOQ_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOQCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOQ_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOQCKEN ) +#define __HAL_RCC_GPIOP_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOPCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOP_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOPCKEN ) +#define __HAL_RCC_GPIOO_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOOCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOO_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOOCKEN ) +#define __HAL_RCC_GPION_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIONCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPION_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIONCKEN ) +#define __HAL_RCC_GPIOM_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOMCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOM_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOMCKEN ) +#define __HAL_RCC_GPIOL_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOLCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOL_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOLCKEN ) +#define __HAL_RCC_GPIOK_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOKCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOK_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOKCKEN ) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOJCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOJCKEN ) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOICKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOI_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOICKEN ) +#define __HAL_RCC_GPIOH_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOHCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOH_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOHCKEN ) +#define __HAL_RCC_GPIOG_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOGCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOG_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOGCKEN ) +#define __HAL_RCC_GPIOF_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOFCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOF_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOFCKEN ) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOECKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOE_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOECKEN ) +#define __HAL_RCC_GPIOD_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIODCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOD_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIODCKEN ) +#define __HAL_RCC_GPIOC_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOCCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOC_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOCCKEN ) +#define __HAL_RCC_GPIOB_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOBCKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOB_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOBCKEN ) +#define __HAL_RCC_GPIOA_CLK_ENABLE() do \ + { \ + RCC->AHB2CKENR |= RCC_AHB2CKENR_GPIOACKEN; \ + RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN; \ + } while (0) +#define __HAL_RCC_GPIOA_CLK_DISABLE() ( RCC->AHB2CKENR &= ~RCC_AHB2CKENR_GPIOACKEN ) + +/** @brief Enable or Disable the AHB3 peripheral clock. + */ + +#define __HAL_RCC_FMC_CLK_ENABLE() ( RCC->AHB3CKENR |= RCC_AHB3CKENR_FMCCKEN ) +#define __HAL_RCC_FMC_CLK_DISABLE() ( RCC->AHB3CKENR &= ~RCC_AHB3CKENR_FMCCKEN ) +#define __HAL_RCC_OSPI2_CLK_ENABLE() ( RCC->AHB3CKENR |= RCC_AHB3CKENR_OSPI2CKEN ) +#define __HAL_RCC_OSPI2_CLK_DISABLE() ( RCC->AHB3CKENR &= ~RCC_AHB3CKENR_OSPI2CKEN ) +#define __HAL_RCC_OSPI1_CLK_ENABLE() ( RCC->AHB3CKENR |= RCC_AHB3CKENR_OSPI1CKEN ) +#define __HAL_RCC_OSPI1_CLK_DISABLE() ( RCC->AHB3CKENR &= ~RCC_AHB3CKENR_OSPI1CKEN ) +#define __HAL_RCC_SDMMC_CLK_ENABLE() ( RCC->AHB3CKENR |= RCC_AHB3CKENR_SDMMCCKEN ) +#define __HAL_RCC_SDMMC_CLK_DISABLE() ( RCC->AHB3CKENR &= ~RCC_AHB3CKENR_SDMMCCKEN ) +#define __HAL_RCC_SPI7_CLK_ENABLE() ( RCC->AHB3CKENR |= RCC_AHB3CKENR_SPI7CKEN) +#define __HAL_RCC_SPI7_CLK_DISABLE() ( RCC->AHB3CKENR &= ~RCC_AHB3CKENR_SPI7CKEN) +#define __HAL_RCC_SPI8_CLK_ENABLE() ( RCC->AHB3CKENR |= RCC_AHB3CKENR_SPI8CKEN) +#define __HAL_RCC_SPI8_CLK_DISABLE() ( RCC->AHB3CKENR &= ~RCC_AHB3CKENR_SPI8CKEN) + +/** @brief Enable or Disable the APB1 peripheral clock. + */ + +#define __HAL_RCC_LPUART1_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_LPUART1CKEN ) +#define __HAL_RCC_LPUART1_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_LPUART1CKEN ) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_LPTIM1CKEN ) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_LPTIM1CKEN ) +#define __HAL_RCC_PMU_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_PMUCKEN ) +#define __HAL_RCC_PMU_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_PMUCKEN ) +#define __HAL_RCC_I2C4_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2C4CKEN ) +#define __HAL_RCC_I2C4_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2C4CKEN ) +#define __HAL_RCC_I2C3_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2C3CKEN ) +#define __HAL_RCC_I2C3_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2C3CKEN ) +#define __HAL_RCC_I2C2_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2C2CKEN ) +#define __HAL_RCC_I2C2_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2C2CKEN ) +#define __HAL_RCC_I2C1_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2C1CKEN ) +#define __HAL_RCC_I2C1_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2C1CKEN ) +#define __HAL_RCC_USART5_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_USART5CKEN ) +#define __HAL_RCC_USART5_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_USART5CKEN ) +#define __HAL_RCC_USART4_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_USART4CKEN ) +#define __HAL_RCC_USART4_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_USART4CKEN ) +#define __HAL_RCC_USART3_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_USART3CKEN ) +#define __HAL_RCC_USART3_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_USART3CKEN ) +#define __HAL_RCC_USART2_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_USART2CKEN ) +#define __HAL_RCC_USART2_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_USART2CKEN ) +#define __HAL_RCC_I2S3_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2S3CKEN ) +#define __HAL_RCC_I2S3_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2S3CKEN ) +#define __HAL_RCC_I2S2_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2S2CKEN ) +#define __HAL_RCC_I2S2_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2S2CKEN ) +#define __HAL_RCC_I2S1_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_I2S1CKEN ) +#define __HAL_RCC_I2S1_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_I2S1CKEN ) +#define __HAL_RCC_WDT_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_WDTCKEN ) +#define __HAL_RCC_WDT_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_WDTCKEN ) +#define __HAL_RCC_RTC_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_RTCCKEN ) +#define __HAL_RCC_RTC_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_RTCCKEN ) +#define __HAL_RCC_TIM14_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM14CKEN ) +#define __HAL_RCC_TIM14_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM14CKEN ) +#define __HAL_RCC_TIM13_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM13CKEN ) +#define __HAL_RCC_TIM13_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM13CKEN ) +#define __HAL_RCC_TIM12_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM12CKEN ) +#define __HAL_RCC_TIM12_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM12CKEN ) +#define __HAL_RCC_TIM7_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM7CKEN ) +#define __HAL_RCC_TIM7_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM7CKEN ) +#define __HAL_RCC_TIM6_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM6CKEN ) +#define __HAL_RCC_TIM6_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM6CKEN ) +#define __HAL_RCC_TIM5_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM5CKEN ) +#define __HAL_RCC_TIM5_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM5CKEN ) +#define __HAL_RCC_TIM4_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM4CKEN ) +#define __HAL_RCC_TIM4_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM4CKEN ) +#define __HAL_RCC_TIM3_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM3CKEN ) +#define __HAL_RCC_TIM3_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM3CKEN ) +#define __HAL_RCC_TIM2_CLK_ENABLE() ( RCC->APB1CKENR1 |= RCC_APB1CKENR1_TIM2CKEN ) +#define __HAL_RCC_TIM2_CLK_DISABLE() ( RCC->APB1CKENR1 &= ~RCC_APB1CKENR1_TIM2CKEN ) +#define __HAL_RCC_EFUSE2_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_EFUSE2CKEN ) +#define __HAL_RCC_EFUSE2_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_EFUSE2CKEN ) +#define __HAL_RCC_EFUSE1_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_EFUSE1CKEN ) +#define __HAL_RCC_EFUSE1_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_EFUSE1CKEN ) +#define __HAL_RCC_TIM26_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_TIM26CKEN ) +#define __HAL_RCC_TIM26_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_TIM26CKEN ) +#define __HAL_RCC_TIM25_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_TIM25CKEN ) +#define __HAL_RCC_TIM25_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_TIM25CKEN ) +#define __HAL_RCC_USART8_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_USART8CKEN ) +#define __HAL_RCC_USART8_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_USART8CKEN ) +#define __HAL_RCC_USART7_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_USART7CKEN ) +#define __HAL_RCC_USART7_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_USART7CKEN ) +#define __HAL_RCC_LPTIM2_CLK_ENABLE() ( RCC->APB1CKENR2 |= RCC_APB1CKENR2_LPTIM2CKEN ) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() ( RCC->APB1CKENR2 &= ~RCC_APB1CKENR2_LPTIM2CKEN ) + +/** @brief Enable or Disable the APB2 peripheral clock. + */ + +#define __HAL_RCC_USART10_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_USART10CKEN ) +#define __HAL_RCC_USART10_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_USART10CKEN ) +#define __HAL_RCC_USART9_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_USART9CKEN ) +#define __HAL_RCC_USART9_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_USART9CKEN ) +#define __HAL_RCC_TIM24_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM24CKEN ) +#define __HAL_RCC_TIM24_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM24CKEN ) +#define __HAL_RCC_TIM23_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM23CKEN ) +#define __HAL_RCC_TIM23_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM23CKEN ) +#define __HAL_RCC_TIM22_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM22CKEN ) +#define __HAL_RCC_TIM22_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM22CKEN ) +#define __HAL_RCC_TIM21_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM21CKEN ) +#define __HAL_RCC_TIM21_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM21CKEN ) +#define __HAL_RCC_TIM19_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM19CKEN ) +#define __HAL_RCC_TIM19_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM19CKEN ) +#define __HAL_RCC_TIM18_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM18CKEN ) +#define __HAL_RCC_TIM18_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM18CKEN ) +#define __HAL_RCC_TIM11_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM11CKEN ) +#define __HAL_RCC_TIM11_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM11CKEN ) +#define __HAL_RCC_TIM10_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM10CKEN ) +#define __HAL_RCC_TIM10_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM10CKEN ) +#define __HAL_RCC_TIM9_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM9CKEN ) +#define __HAL_RCC_TIM9_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM9CKEN ) +#define __HAL_RCC_LTDC_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_LTDCCKEN ) +#define __HAL_RCC_LTDC_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_LTDCCKEN ) +#define __HAL_RCC_TKEY_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TKEYCKEN ) +#define __HAL_RCC_TKEY_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TKEYCKEN ) +#define __HAL_RCC_TIM20_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM20CKEN ) +#define __HAL_RCC_TIM20_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM20CKEN ) +#define __HAL_RCC_TIM17_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM17CKEN ) +#define __HAL_RCC_TIM17_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM17CKEN ) +#define __HAL_RCC_TIM16_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM16CKEN ) +#define __HAL_RCC_TIM16_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM16CKEN ) +#define __HAL_RCC_TIM15_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM15CKEN ) +#define __HAL_RCC_TIM15_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM15CKEN ) +#define __HAL_RCC_USART6_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_USART6CKEN ) +#define __HAL_RCC_USART6_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_USART6CKEN ) +#define __HAL_RCC_USART1_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_USART1CKEN ) +#define __HAL_RCC_USART1_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_USART1CKEN ) +#define __HAL_RCC_TIM8_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM8CKEN ) +#define __HAL_RCC_TIM8_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM8CKEN ) +#define __HAL_RCC_TIM1_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_TIM1CKEN ) +#define __HAL_RCC_TIM1_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_TIM1CKEN ) +#define __HAL_RCC_EXTI_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_EXTICKEN ) +#define __HAL_RCC_EXTI_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_EXTICKEN ) +#define __HAL_RCC_CMP1_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_CMP1CKEN_A ) +#define __HAL_RCC_CMP1_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_CMP1CKEN_A ) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() ( RCC->APB2CKENR |= RCC_APB2CKENR_SYSCFGCKEN ) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() ( RCC->APB2CKENR &= ~RCC_APB2CKENR_SYSCFGCKEN ) + +/** @brief Enable or Disable the APB3 peripheral clock. + */ + +#define __HAL_RCC_LPTIM6_CLK_ENABLE() ( RCC->APB3CKENR |= RCC_APB3CKENR_LPTIM6CKEN ) +#define __HAL_RCC_LPTIM6_CLK_DISABLE() ( RCC->APB3CKENR &= ~RCC_APB3CKENR_LPTIM6CKEN ) +#define __HAL_RCC_LPTIM5_CLK_ENABLE() ( RCC->APB3CKENR |= RCC_APB3CKENR_LPTIM5CKEN ) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() ( RCC->APB3CKENR &= ~RCC_APB3CKENR_LPTIM5CKEN ) +#define __HAL_RCC_LPTIM4_CLK_ENABLE() ( RCC->APB3CKENR |= RCC_APB3CKENR_LPTIM4CKEN ) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() ( RCC->APB3CKENR &= ~RCC_APB3CKENR_LPTIM4CKEN ) +#define __HAL_RCC_LPTIM3_CLK_ENABLE() ( RCC->APB3CKENR |= RCC_APB3CKENR_LPTIM3CKEN ) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() ( RCC->APB3CKENR &= ~RCC_APB3CKENR_LPTIM3CKEN ) + +/** @brief Enable or Disable the APB4 peripheral clock. + */ + +#define __HAL_RCC_DPWM6_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_DPWM6CKEN ) +#define __HAL_RCC_DPWM6_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_DPWM6CKEN ) +#define __HAL_RCC_DPWM5_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_DPWM5CKEN ) +#define __HAL_RCC_DPWM5_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_DPWM5CKEN ) +#define __HAL_RCC_SPWM6_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_SPWM6CKEN ) +#define __HAL_RCC_SPWM6_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_SPWM6CKEN ) +#define __HAL_RCC_SPWM5_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_SPWM5CKEN ) +#define __HAL_RCC_SPWM5_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_SPWM5CKEN ) +#define __HAL_RCC_SPWM4_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_SPWM4CKEN ) +#define __HAL_RCC_SPWM4_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_SPWM4CKEN ) +#define __HAL_RCC_SPWM3_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_SPWM3CKEN ) +#define __HAL_RCC_SPWM3_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_SPWM3CKEN ) +#define __HAL_RCC_MDAC_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_MDACCKEN ) +#define __HAL_RCC_MDAC_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_MDACCKEN ) +#define __HAL_RCC_PNDL_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_PNDLCKEN ) +#define __HAL_RCC_PNDL_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_PNDLCKEN ) +#define __HAL_RCC_DPWM4_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_DPWM4CKEN ) +#define __HAL_RCC_DPWM4_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_DPWM4CKEN ) +#define __HAL_RCC_DPWM3_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_DPWM3CKEN ) +#define __HAL_RCC_DPWM3_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_DPWM3CKEN ) +#define __HAL_RCC_DPWM2_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_DPWM2CKEN ) +#define __HAL_RCC_DPWM2_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_DPWM2CKEN ) +#define __HAL_RCC_DPWM1_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_DPWM1CKEN ) +#define __HAL_RCC_DPWM1_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_DPWM1CKEN ) +#define __HAL_RCC_SPWM2_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_SPWM2CKEN ) +#define __HAL_RCC_SPWM2_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_SPWM2CKEN ) +#define __HAL_RCC_SPWM1_CLK_ENABLE() ( RCC->APB4CKENR |= RCC_APB4CKENR_SPWM1CKEN ) +#define __HAL_RCC_SPWM1_CLK_DISABLE() ( RCC->APB4CKENR &= ~RCC_APB4CKENR_SPWM1CKEN ) + +/******************************************************************************/ + +/** @defgroup RCC Private Macros + * @{ + */ + +#define IS_RCC_RESET_SOURCE(SOURCE) ((((SOURCE) & RCC_RESET_SOURCE_MASK) != 0U) && \ + (((SOURCE) & ~RCC_RESET_SOURCE_MASK) == 0U)) + +#define IS_RCC_OSC_TYPE(TYPE) ((((TYPE) & RCC_OSC_TYPE_MASK) != 0U) && \ + (((TYPE) & ~RCC_OSC_TYPE_MASK) == 0U)) + +#define IS_RCC_OSC_XTL_DRIVE(DRIVE) ((DRIVE) < RCC_XTL_DRIVE_MAX) + +#define IS_RCC_IT(IT) ((((IT) & RCC_IT_MASK) != 0U) && \ + (((IT) & ~RCC_IT_MASK) == 0U)) + +#define IS_RCC_IT_FLAG(FLAG) ((((FLAG) & RCC_FLAG_MASK) != 0U) && \ + (((FLAG) & ~RCC_FLAG_MASK) == 0U)) + +#define IS_RCC_PLL_CLOCK_SOURCE(SOURCE) ((SOURCE) < RCC_PLL_SOURCE_MAX) + +#define IS_RCC_PLL1_PLLQ(PLLQ) (((PLLQ) != 0) && ((PLLQ) <= 15)) + +#define IS_RCC_PLL1_PLLP(PLLP) (((PLLP) == 2U) || \ + ((PLLP) == 4U) || \ + ((PLLP) == 6U) || \ + ((PLLP) == 8U)) + +#define IS_RCC_PLL1_PLLN(PLLN) (((PLLN) != 0) && ((PLLN) <= 63U)) + +#define IS_RCC_PLL1_PLLF(PLLF) (((PLLF) >= 50U) && ((PLLF) <= 511U)) + +#define IS_RCC_PLL2_PLLQ(PLLQ) (((PLLQ) != 0) && ((PLLQ) <= 15)) + +#define IS_RCC_PLL2_PLLP(PLLP) (((PLLP) == 2U) || \ + ((PLLP) == 4U) || \ + ((PLLP) == 6U) || \ + ((PLLP) == 8U)) + +#define IS_RCC_PLL2_PLLN(PLLN) (((PLLN) != 0) && ((PLLN) <= 63U)) + +#define IS_RCC_PLL2_PLLF(PLLF) (((PLLF) >= 50U) && ((PLLF) <= 511U)) + +#define IS_RCC_PLL3_PLLQ(PLLQ) (((PLLQ) == 1U) || \ + ((PLLQ) == 2U) || \ + ((PLLQ) == 4U) || \ + ((PLLQ) == 8U)) + +#define IS_RCC_PLL3_PLLP(PLLP) (((PLLP) == 1U) || \ + ((PLLP) == 2U) || \ + ((PLLP) == 4U) || \ + ((PLLP) == 8U)) + +#define IS_RCC_PLL3_PLLN(PLLN) (((PLLN) != 0) && ((PLLN) <= 64U)) + +#define IS_RCC_PLL3_PLLF(PLLF) (((PLLF) != 0) && ((PLLF) <= 128U)) + +#define IS_RCC_CLOCK_TYPE(TYPE) ((((TYPE) & RCC_CLOCK_TYPE_MASK) != 0U) && \ + (((TYPE) & ~RCC_CLOCK_TYPE_MASK) == 0U)) + +#define IS_RCC_SYSCLK_SOURCE(SOURCE) ((SOURCE) < RCC_SYSCLK_SOURCE_MAX) + +#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) != 0) && ((DIV) <= 16U)) + +#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) != 0) && ((DIV) <= 16U)) + +#define IS_RCC_PCLK_DIV(DIV) (((DIV) == 1) || \ + ((DIV) == 2) || \ + ((DIV) == 4) || \ + ((DIV) == 8) || \ + ((DIV) == 16)) + +#define IS_RCC_HRNGS_CLK_DIV(DIV) (((DIV) != 0) && ((DIV) <= 128U)) + +#define IS_RCC_FLT_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_FLT_CLK_SOURCE_MAX) + +#define IS_RCC_LPUART1_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPUART1_CLK_SOURCE_MAX) + +#define IS_RCC_LPTIM1_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPTIM1_CLK_SOURCE_MAX) + +#define IS_RCC_LPTIM2_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPTIM2_CLK_SOURCE_MAX) + +#define IS_RCC_LPTIM3_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPTIM3_CLK_SOURCE_MAX) + +#define IS_RCC_LPTIM4_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPTIM4_CLK_SOURCE_MAX) + +#define IS_RCC_LPTIM5_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPTIM5_CLK_SOURCE_MAX) + +#define IS_RCC_LPTIM6_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_LPTIM6_CLK_SOURCE_MAX) + +#define IS_RCC_SDMMC_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_SDMMC_CLK_SOURCE_MAX) + +#define IS_RCC_SDMMC_SCLK_SOURCE(SOURCE) ((SOURCE) < RCC_SDMMC_SCLK_SOURCE_MAX) + +#define IS_RCC_LCD_CLK_DIV(DIV) (((DIV) == 2) || \ + ((DIV) == 4) || \ + ((DIV) == 8) || \ + ((DIV) == 16)) + +#define IS_RCC_RTC_CLK_SOURCE(SOURCE) ((SOURCE) < RCC_RTC_CLK_SOURCE_MAX) + +#define IS_RCC_MCO(MCO) ((MCO) < RCC_MCO_MAX) + +#define IS_RCC_MCO1_DIV(DIV) (((DIV) != 0) && ((DIV) <= 65536U)) + +#define IS_RCC_MCO2_DIV(DIV) (((DIV) != 0) && ((DIV) <= 64U)) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_RCC_ReadyIRQHandler(void); +void HAL_RCC_XTHStopIRQHandler(void); +void HAL_RCC_XTLStopIRQHandler(void); +void HAL_RCC_RCHReadyCallback(void); +void HAL_RCC_RCLReadyCallback(void); +void HAL_RCC_XTHReadyCallback(void); +void HAL_RCC_XTLReadyCallback(void); +void HAL_RCC_PLL1ReadyCallback(void);; +void HAL_RCC_PLL2ReadyCallback(void); +void HAL_RCC_PLL3ReadyCallback(void); +void HAL_RCC_XTHStopCallback(void); +void HAL_RCC_XTLStopCallback(void); + +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInit); + +HAL_StatusTypeDef HAL_RCC_RCHConfig(FunctionalState RCH, FunctionalState Div16); +HAL_StatusTypeDef HAL_RCC_RCLConfig(FunctionalState RCL); +HAL_StatusTypeDef HAL_RCC_XTHConfig(FunctionalState XTH, FunctionalState Bypass); +HAL_StatusTypeDef HAL_RCC_XTLConfig(FunctionalState XTL, FunctionalState Bypass); +HAL_StatusTypeDef HAL_RCC_PLL1Config(FunctionalState PLL1, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ); +HAL_StatusTypeDef HAL_RCC_PLL1SSCConfig(FunctionalState PLL1, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ, \ + FunctionalState SSC, uint32_t Mode, uint32_t Spectrum, uint32_t Step); +HAL_StatusTypeDef HAL_RCC_PLL1PCLKConfig(FunctionalState PLL1PCLK); +HAL_StatusTypeDef HAL_RCC_PLL1QCLKConfig(FunctionalState PLL1QCLK); +HAL_StatusTypeDef HAL_RCC_PLL2Config(FunctionalState PLL2, uint32_t PLLSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ); +HAL_StatusTypeDef HAL_RCC_PLL2SSCConfig(FunctionalState PLL2, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ, \ + FunctionalState SSC, uint32_t Mode, uint32_t Spectrum, uint32_t Step); +HAL_StatusTypeDef HAL_RCC_PLL2PCLKConfig(FunctionalState PLL1PCLK); +HAL_StatusTypeDef HAL_RCC_PLL2QCLKConfig(FunctionalState PLL1QCLK); +HAL_StatusTypeDef HAL_RCC_PLL3Config(FunctionalState PLL3, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ); +HAL_StatusTypeDef HAL_RCC_PLL3PCLKConfig(FunctionalState PLL1PCLK); +HAL_StatusTypeDef HAL_RCC_PLL3QCLKConfig(FunctionalState PLL1QCLK); + +HAL_StatusTypeDef HAL_RCC_ITConfig(uint32_t IT, FunctionalState NewStatus); +uint32_t HAL_RCC_GetITFlag(uint32_t IT); +HAL_StatusTypeDef HAL_RCC_ClearITFlag(uint32_t IT); + +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInit); +HAL_StatusTypeDef HAL_RCC_SYSCLKSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_SYSCLKDiv0Config(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_SYSCLKDiv1Config(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_PCLK1DivConfig(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_PCLK2DivConfig(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_PCLK3DivConfig(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_PCLK4DivConfig(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_HRNGSClockDivConfig(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_FLTClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPUART1ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPTIM1ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPTIM2ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPTIM3ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPTIM4ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPTIM5ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_LPTIM6ClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_SDMMCClockSourceConfig(uint32_t ClockSource); +HAL_StatusTypeDef HAL_RCC_SDMMCSampleClockSourceConfig(uint32_t SampleClockSource); +HAL_StatusTypeDef HAL_RCC_LCDPiexlClockDivConfig(uint32_t Div); +HAL_StatusTypeDef HAL_RCC_RTCClockSourceConfig(uint32_t ClockSource); + +HAL_StatusTypeDef HAL_RCC_GetClock(RCC_ClkInitTypeDef *RCC_ClkInit); +HAL_StatusTypeDef HAL_RCC_GetSYSCLKSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetHRNGSlowClockDiv(uint32_t *pClockDiv); +HAL_StatusTypeDef HAL_RCC_GetFLTClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPUART1ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPTIM1ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPTIM2ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPTIM3ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPTIM4ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPTIM5ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetLPTIM6ClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetSDMMCSampleClockSource(uint32_t *pClockSource); +HAL_StatusTypeDef HAL_RCC_GetRTCClockSource(uint32_t *pClockSource); + +uint32_t HAL_RCC_GetRCHTrimFreq(void); +uint32_t HAL_RCC_GetRCLTrimFreq(void); +uint32_t HAL_RCC_GetRCHFreq(void); +uint32_t HAL_RCC_GetRCLFreq(void); +uint32_t HAL_RCC_GetXTHFreq(void); +uint32_t HAL_RCC_GetXTLFreq(void); +uint32_t HAL_RCC_GetPLL1Freq(void); +uint32_t HAL_RCC_GetPLL1PFreq(void); +uint32_t HAL_RCC_GetPLL2Freq(void); +uint32_t HAL_RCC_GetPLL2QFreq(void); +uint32_t HAL_RCC_GetPLL2PFreq(void); +uint32_t HAL_RCC_GetPLL3Freq(void); +uint32_t HAL_RCC_GetPLL3QFreq(void); +uint32_t HAL_RCC_GetPLL3PFreq(void); +uint32_t HAL_RCC_GetSYSCLKFreq(void); +uint32_t HAL_RCC_GetSysCoreClockFreq(void); +uint32_t HAL_RCC_GetFCLKFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK3Freq(void); +uint32_t HAL_RCC_GetPCLK4Freq(void); +uint32_t HAL_RCC_GetHRNGSClockFreq(void); +uint32_t HAL_RCC_GetFLTClockFreq(void); +uint32_t HAL_RCC_GetLPUART1ClockFreq(void); +uint32_t HAL_RCC_GetLPTIM1ClockFreq(void); +uint32_t HAL_RCC_GetLPTIM2ClockFreq(void); +uint32_t HAL_RCC_GetLPTIM3ClockFreq(void); +uint32_t HAL_RCC_GetLPTIM4ClockFreq(void); +uint32_t HAL_RCC_GetLPTIM5ClockFreq(void); +uint32_t HAL_RCC_GetLPTIM6ClockFreq(void); +uint32_t HAL_RCC_GetSDMMCClockFreq(void); +uint32_t HAL_RCC_GetLCDPiexlClockFreq(void); +uint32_t HAL_RCC_GetRTCClockFreq(void); + +uint32_t HAL_RCC_MCOConfig(RCC_MCOInitTypeDef *MCO_InitStruct); +uint32_t HAL_RCC_MCO1Config(uint32_t MCO, uint32_t NewStatus, uint32_t Div); +uint32_t HAL_RCC_MCO2Config(uint32_t MCO, uint32_t NewStatus, uint32_t Div); + +void HAL_RCC_SoftwareReset(void); +void HAL_RCC_StandbyReset(void); + +void HAL_RCC_LockupResetConfig(FunctionalState NewState); +void HAL_RCC_IWDTResetConfig(FunctionalState NewState); +void HAL_RCC_WDTResetConfig(FunctionalState NewState); +void HAL_RCC_LVDResetConfig(FunctionalState NewState); + +uint32_t HAL_RCC_GetResetSource(void); +void HAL_RCC_ClearAllResetSource(void); + + +#endif + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_rtc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..817a308af39b8d95bd0e3365bc6fcecabb713357 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_rtc.h @@ -0,0 +1,484 @@ +/* + ****************************************************************************** + * @file HAL_RTC.h + * @version V1.0.0 + * @date 2022 + * @brief Header file of RTC HAL module. + ****************************************************************************** +*/ + +#ifndef __HAL_RTC_H__ +#define __HAL_RTC_H__ + +#include "hal.h" + + + + + + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< The RTC Clock Source to be configured.*/ + + uint32_t Compensation; /*!< The RTC Clock Compensation to be configured.*/ + + uint32_t CompensationValue; /*!< The RTC Clock Compensation Value to be configured.*/ +}RTC_ConfigTypeDef; + + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x99 */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).*/ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31 */ + + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.*/ +}RTC_DateTypeDef; +/* Attention: YearMonthDateWeek use BCD code */ + + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hour; /*!< Specifies the RTC Time Hour. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23 */ + + uint8_t Minute; /*!< Specifies the RTC Time Minute. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ + + uint8_t Second; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ +}RTC_TimeTypeDef; +/* Attention: HourMinuteSecond use BCD code */ + + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t u32_AlarmMode; /*!< Specifies the RTC alarm Mode.*/ + + uint32_t u32_AlarmInterrupt; /*!< Specifies the RTC alarm interrupt Enable or Disable.*/ + + uint32_t u32_DayMask; /*!< Specifies the RTC alarm Day/Week Mask.*/ + + uint32_t u32_HourMask; /*!< Specifies the RTC alarm Hour Mask.*/ + + uint32_t u32_MinMask; /*!< Specifies the RTC alarm Min Mask.*/ + + uint32_t u32_AlarmWeek; /*!< Specifies the RTC alarm week select(Select WeekMode this parameter is valid).*/ + + uint32_t u32_AlarmDay; /*!< Specifies the RTC alarm day select(Select DayMode this parameter is valid). + This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31 */ + + uint32_t u32_Hours; /*!< Specifies the RTC alarm Hour. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23 */ + + uint32_t u32_Minutes; /*!< Specifies the RTC alarm Minute. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ + + uint32_t u32_Seconds; /*!< Specifies the RTC alarm Seconds. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */ +}RTC_AlarmTypeDef; + + +/** + * @brief RTC Temper structure definition + */ +typedef struct +{ + uint32_t u32_TemperEdge; /*!< Specifies the RTC Temper edge select. */ + + uint32_t u32_InterruptEN; /*!< Specifies the RTC Temper interrupt enable.*/ + + uint32_t u32_ClearBackup; /*!< Specifies the RTC Temper clear backup register. */ + + uint32_t u32_FilterClk; /*!< Specifies the RTC Temper Filter Clock select. */ + + uint32_t u32_Filter; /*!< Specifies the RTC Temper Filter select.*/ + + uint32_t u32_FilterEn; /*!< Specifies the RTC Temper Filter enable.*/ +}RTC_TemperTypeDef; + + +/** + * @brief RTC Wakeup Timer structure definition + */ +typedef struct +{ + uint32_t u32_WuckSel; /*!< The RTC WUCKSEL Value to be configured. + This parameter can be a value of @ref WUCKSEL_1Hz */ + + uint32_t u32_InterruptEN; /*!< Specifies the RTC Temper interrupt enable. + This parameter can be a value of @ref RTC_WUTIMER Interrupt */ + uint32_t WakeUpCounter; + +}RTC_WUTimerTypeDef; + +/** + * @brief RTC Temper index definition + */ +typedef enum +{ + RTC_TEMPER_1, + RTC_TEMPER_2, +}RTC_Temper_t; + +/** @defgroup RTC write enable command + * @{ + */ +#define RTC_WRITE_PROTECT_DISABLE (0xCA53CA53) +#define RTC_WRITE_PROTECT_ENABLE (0x00000000) + +/** @defgroup ClockSource + * @{ + */ +#define RTC_CLOCK_RC32K (0x00000000) +#define RTC_CLOCK_XTL (0x00000004) +#define IS_RTC_CLOCKSRC(__CLOCKSRC__) (((__CLOCKSRC__) == RTC_CLOCK_RC32K) || \ + ((__CLOCKSRC__) == RTC_CLOCK_XTL)) + +/** @defgroup Clock Compensation + * @{ + */ +#define COMPENSATION_INCREASE (0x00000000) +#define COMPENSATION_DECREASE (0x00000200) +#define IS_RTC_COMPENSATION(__COMPENSATION__) (((__COMPENSATION__) == COMPENSATION_INCREASE) || \ + ((__COMPENSATION__) == COMPENSATION_DECREASE)) + +/** @defgroup Clock Compensation Value + * @{ + */ +#define IS_RTC_COMPENSATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1ff) + +/** @defgroup RTC Date Definitions + * @{ + */ +#define RTC_MONTH_JANUARY (0x01) +#define RTC_MONTH_FEBRUARY (0x02) +#define RTC_MONTH_MARCH (0x03) +#define RTC_MONTH_APRIL (0x04) +#define RTC_MONTH_MAY (0x05) +#define RTC_MONTH_JUNE (0x06) +#define RTC_MONTH_JULY (0x07) +#define RTC_MONTH_AUGUST (0x08) +#define RTC_MONTH_SEPTEMBER (0x09) +#define RTC_MONTH_OCTOBER (0x10) +#define RTC_MONTH_NOVEMBER (0x11) +#define RTC_MONTH_DECEMBER (0x12) + +#define RTC_WEEKDAY_MONDAY (0x01) +#define RTC_WEEKDAY_TUESDAY (0x02) +#define RTC_WEEKDAY_WEDNESDAY (0x03) +#define RTC_WEEKDAY_THURSDAY (0x04) +#define RTC_WEEKDAY_FRIDAY (0x05) +#define RTC_WEEKDAY_SATURDAY (0x06) +#define RTC_WEEKDAY_SUNDAY (0x07) + +#define IS_RTC_YEAR(YEAR) (((YEAR) >= 0x00) && ((YEAR) <= 0x99)) +#define IS_RTC_MONTH(MONTH) (((MONTH) > 0x00) && ((MONTH) <= 0x12)) +#define IS_RTC_DAY(DAY) (((DAY) > 0x00) && ((DAY) <= 0x31)) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) > 0x00) && ((WEEKDAY) <= 0x07)) + + +/** @defgroup RTC_AlarmInterrupt Definitions + * @{ + */ +#define RTC_ALARM_INT_ENABLE (0x00000000) +#define RTC_ALARM_INT_DISABLE (0x00000001) +#define IS_RTC_ALARM_INT(__INT__) (((__INT__) == RTC_ALARM_INT_ENABLE) || \ + ((__INT__) == RTC_ALARM_INT_DISABLE)) + + +/** @defgroup RTC_DayMask Definitions + * @{ + */ +#define RTC_ALARM_DAY_MASK_ENABLE RTC_CR_ALM_MSKD +#define RTC_ALARM_DAY_MASK_DISABLE (0x00000000) +#define IS_RTC_ALARM_DAY_MASK(__MASKD__) (((__MASKD__) == RTC_ALARM_DAY_MASK_ENABLE) || \ + ((__MASKD__) == RTC_ALARM_DAY_MASK_DISABLE)) + + +/** @defgroup RTC_HourMask Definitions + * @{ + */ +#define RTC_ALARM_HOUR_MASK_ENABLE RTC_CR_ALM_MSKH +#define RTC_ALARM_HOUR_MASK_DISABLE (0x00000000) +#define IS_RTC_ALARM_HOUR_MASK(__MASKH__) (((__MASKH__) == RTC_ALARM_HOUR_MASK_ENABLE) || \ + ((__MASKH__) == RTC_ALARM_HOUR_MASK_DISABLE)) + +/** @defgroup RTC_MinMask Definitions + * @{ + */ +#define RTC_ALARM_MIN_MASK_ENABLE RTC_CR_ALM_MSKM +#define RTC_ALARM_MIN_MASK_DISABLE (0x00000000) +#define IS_RTC_ALARM_MIN_MASK(__MASKM__) (((__MASKM__) == RTC_ALARM_MIN_MASK_ENABLE) || \ + ((__MASKM__) == RTC_ALARM_MIN_MASK_DISABLE)) + + +/** @defgroup RTC_Alarm_WeekSelect Definitions + * @{ + */ +#define RTC_ALARM_WEEK_SUNDAY (0x01000000) +#define RTC_ALARM_WEEK_MONDAY (0x02000000) +#define RTC_ALARM_WEEK_TUESDAY (0x04000000) +#define RTC_ALARM_WEEK_WEDNESDAY (0x08000000) +#define RTC_ALARM_WEEK_THURSDAY (0x10000000) +#define RTC_ALARM_WEEK_FRIDAY (0x20000000) +#define RTC_ALARM_WEEK_SATURDAY (0x40000000) +#define IS_RTC_ALARM_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_ALARM_WEEK_SUNDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_MONDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_TUESDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_THURSDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_FRIDAY) || \ + ((__WEEKDAY__) == RTC_ALARM_WEEK_SATURDAY) || \ + ((__WEEKDAY__) >= 0x01000000 && (__WEEKDAY__) <= 0x7F000000)) + +/** @defgroup RTC_Temper_edge Definitions + * @{ + */ +#define RTC_TEMP_EDGE_RISING (0x00000000) +#define RTC_TEMP_EDGE_FALLING (0x00000001) +#define IS_RTC_TEMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TEMP_EDGE_RISING) || \ + ((__EDGE__) == RTC_TEMP_EDGE_FALLING)) + + + +/** @defgroup RTC_TemperInterrupt Definitions + * @{ + */ +#define RTC_TEMP_INT_DISABLE (0x00000000) +#define RTC_TEMP_INT_ENABLE (0x00000001) +#define IS_RTC_TEMP_INT(__INT__) (((__INT__) == RTC_TEMP_INT_ENABLE) || \ + ((__INT__) == RTC_TEMP_INT_DISABLE)) + + + +/** @defgroup RTC_ClearBackup Definitions + * @{ + */ +#define RTC_TEMP_CLEAR_DISABLE (0x00000000) +#define RTC_TEMP_CLEAR_ENABLE (0x00000001) +#define IS_RTC_TEMP_CLEAR_BACKUP(__CLEAR__) (((__CLEAR__) == RTC_TEMP_CLEAR_DISABLE) || \ + ((__CLEAR__) == RTC_TEMP_CLEAR_ENABLE)) + + + +/** @defgroup RTC_TemperFilter Clock Definitions + * @{ + */ +#define RTC_TEMP_FILTER_RTCCLK (0x00000000) +#define RTC_TEMP_FILTER_512_RTCCLK (RTC_CR_TAMPFLTCLK) +#define IS_RTC_TEMP_FILTER_CLK(__CLK__) (((__CLK__) == RTC_TEMP_FILTER_RTCCLK) || \ + ((__CLK__) == RTC_TEMP_FILTER_512_RTCCLK)) +/** @defgroup RTC_TemperFilter Definitions + * @{ + */ +#define RTC_TEMP_FILTER_1_RTCCLK (0x00000000) +#define RTC_TEMP_FILTER_2_RTCCLK (0x00000001) +#define RTC_TEMP_FILTER_4_RTCCLK (0x00000002) +#define RTC_TEMP_FILTER_8_RTCCLK (0x00000003) +#define IS_RTC_TEMP_FILTER(__FILTER__) (((__FILTER__) == RTC_TEMP_FILTER_1_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_2_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_4_RTCCLK) || \ + ((__FILTER__) == RTC_TEMP_FILTER_8_RTCCLK)) +/** @defgroup Alarm clock week/day selection + + * @{ + */ +#define RTC_ALM_ALM_WDS_DAY (0x80000000) +#define RTC_ALM_ALM_WDS_WEEK (0x00000000) +#define IS_RTC_ALARM_MODE(__MODE__) (((__MODE__) == RTC_ALM_ALM_WDS_WEEK) ||\ + ((__MODE__) == RTC_ALM_ALM_WDS_DAY)) + +/** @defgroup RTC Time Definitions + * @{ + */ +#define IS_RTC_HOUR(HOUR) (((HOUR) >= 0) && ((HOUR) <= 0x23)) +#define IS_RTC_MINUTES(MINUTES) (((MINUTES) >= 0) && ((MINUTES) <= 0x59)) +#define IS_RTC_SECONDS(SECONDS) (((SECONDS) >= 0) && ((SECONDS) <= 0x59)) + + +/** @defgroup RTC_Backup_Registers_Definitions +* @{ +*/ +#define RTC_BKP_DR0 (0) +#define RTC_BKP_DR1 (1) +#define RTC_BKP_DR2 (2) +#define RTC_BKP_DR3 (3) +#define RTC_BKP_DR4 (4) +#define RTC_BKP_DR5 (5) +#define RTC_BKP_DR6 (6) +#define RTC_BKP_DR7 (7) +#define RTC_BKP_DR8 (8) +#define RTC_BKP_DR9 (9) +#define RTC_BKP_DR10 (10) +#define RTC_BKP_DR11 (11) +#define RTC_BKP_DR12 (12) +#define RTC_BKP_DR13 (13) +#define RTC_BKP_DR14 (14) +#define RTC_BKP_DR15 (15) +#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ + ((BKP) == RTC_BKP_DR1) || \ + ((BKP) == RTC_BKP_DR2) || \ + ((BKP) == RTC_BKP_DR3) || \ + ((BKP) == RTC_BKP_DR4) || \ + ((BKP) == RTC_BKP_DR5) || \ + ((BKP) == RTC_BKP_DR6) || \ + ((BKP) == RTC_BKP_DR7) || \ + ((BKP) == RTC_BKP_DR8) || \ + ((BKP) == RTC_BKP_DR9) || \ + ((BKP) == RTC_BKP_DR10) || \ + ((BKP) == RTC_BKP_DR11) || \ + ((BKP) == RTC_BKP_DR12) || \ + ((BKP) == RTC_BKP_DR13) || \ + ((BKP) == RTC_BKP_DR14) || \ + ((BKP) == RTC_BKP_DR15)) + + /** @defgroup RTC Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 (0x01000000U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 (0x02000000U) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (0x03000000U) +#define RTC_WAKEUPCLOCK_1HZ (0x04000000U) +#define RTC_WAKEUPCLOCK_0_5HZ (0x05000000U) +#define RTC_WAKEUPCLOCK_2HZ (0x06000000U) +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_1HZ) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_0_5HZ) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_2HZ)) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) + + +/** @defgroup RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_FLAG_DATE (0x00000001UL) +#define RTC_IT_FLAG_HOUR (0x00000002UL) +#define RTC_IT_FLAG_MIN (0x00000004UL) +#define RTC_IT_FLAG_SEC (0x00000008UL) +#define RTC_IT_FLAG_2HZ (0x00000010UL) +#define RTC_IT_FLAG_4HZ (0x00000020UL) +#define RTC_IT_FLAG_8HZ (0x00000040UL) +#define RTC_IT_FLAG_16HZ (0x00000080UL) +#define RTC_IT_FLAG_64HZ (0x00000100UL) +#define RTC_IT_FLAG_256HZ (0x00000200UL) +#define RTC_IT_FLAG_1KHZ (0x00000400UL) +#define RTC_IT_FLAG_ALM (0x00000800UL) +#define RTC_IT_FLAG_32S (0x00001000UL) +#define RTC_IT_FLAG_STP1F (0x00002000UL) +#define RTC_IT_FLAG_STP1R (0x00004000UL) +#define RTC_IT_FLAG_STP2F (0x00008000UL) +#define RTC_IT_FLAG_STP2R (0x00010000UL) +#define RTC_IT_FLAG_WUT (0x00020000UL) +#define IS_RTC_IT_FLAG(FLAG) (((FLAG) == RTC_IT_FLAG_DATE) || ((FLAG) == RTC_IT_FLAG_HOUR) || \ + ((FLAG) == RTC_IT_FLAG_MIN)|| ((FLAG) == RTC_IT_FLAG_SEC) || \ + ((FLAG) == RTC_IT_FLAG_2HZ)|| ((FLAG) == RTC_IT_FLAG_4HZ) || \ + ((FLAG) == RTC_IT_FLAG_8HZ)|| ((FLAG) == RTC_IT_FLAG_16HZ) || \ + ((FLAG) == RTC_IT_FLAG_64HZ)|| ((FLAG) == RTC_IT_FLAG_256HZ) || \ + ((FLAG) == RTC_IT_FLAG_1KHZ)|| ((FLAG) == RTC_IT_FLAG_ALM) || \ + ((FLAG) == RTC_IT_FLAG_32S)|| ((FLAG) == RTC_IT_FLAG_STP1F) || \ + ((FLAG) == RTC_IT_FLAG_STP1R)|| ((FLAG) == RTC_IT_FLAG_STP2F) || \ + ((FLAG) == RTC_IT_FLAG_STP2R)|| ((FLAG) == RTC_IT_FLAG_WUT)) +/** + * @} + */ + + + +/* RTC stamp1 interrupt enabledisable */ +#define __HAL_RTC_ENABLE_STAMP1_IT (RTC->IE |= (RTC_IE_STP1RIE | RTC_IE_STP1FIE)) +#define __HAL_RTC_DISABLE_STAMP1_IT (RTC->IE &= ~(RTC_IE_STP1RIE | RTC_IE_STP1FIE)) + +/* RTC stamp2 interrupt enabledisable */ +#define __HAL_RTC_ENABLE_STAMP2_IT (RTC->IE |= (RTC_IE_STP2RIE | RTC_IE_STP2FIE)) +#define __HAL_RTC_DISABLE_STAMP2_IT (RTC->IE &= ~(RTC_IE_STP2RIE | RTC_IE_STP2FIE)) + +/* RTC 32S interrupt enabledisable */ +#define __HAL_RTC_ENABLE_32S_IT (RTC->IE |= RTC_IE_ADJ32_IE) +#define __HAL_RTC_DISABLE_32S_IT (RTC->IE &= ~RTC_IE_ADJ32_IE) + +/* RTC alarm interrupt enabledisable */ +#define __HAL_RTC_ENABLE_ALM_IT (RTC->IE |= RTC_IE_ALM_IE) +#define __HAL_RTC_DISABLE_ALM_IT (RTC->IE &= RTC_IE_ALM_IE) + +/* RTC sec interrupt enabledisable */ +#define __HAL_RTC_ENABLE_SEC_IT (RTC->IE |= RTC_IE_SEC_IE) +#define __HAL_RTC_DISABLE_SEC_IT (RTC->IE &= ~RTC_IE_SEC_IE) + +/* RTC Minute interrupt enabledisable */ +#define __HAL_RTC_ENABLE_MIN_IT (RTC->IE |= RTC_IE_MIN_IE) +#define __HAL_RTC_DISABLE_MIN_IT (RTC->IE &= ~RTC_IE_MIN_IE) + +/* RTC Hour interrupt enabledisable */ +#define __HAL_RTC_ENABLE_HOUR_IT (RTC->IE |= RTC_IE_HOUR_IE) +#define __HAL_RTC_DISABLE_HOUR_IT (RTC->IE &= ~RTC_IE_HOUR_IE) + +/* RTC Date interrupt enabledisable */ +#define __HAL_RTC_ENABLE_DATE_IT (RTC->IE |= RTC_IE_DATE_IE) +#define __HAL_RTC_DISABLE_DATE_IT (RTC->IE &= ~RTC_IE_DATE_IE) + +/* RTC Timer Wakeup interrupt enabledisable */ +#define __HAL_RTC_ENABLE_WUTIE_IT (RTC->IE |= RTC_IE_WUTIE) +#define __HAL_RTC_DISABLE_WUTIE_IT (RTC->IE &= ~RTC_IE_WUTIE) + + +HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc); + +void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time); + +void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time); + +void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date); + +void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date); + +void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm); + +void HAL_RTC_AlarmEnable(void); + +void HAL_RTC_AlarmDisable(void); + +void HAL_RTC_Tamper(RTC_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper); + +void HAL_RTC_TamperEnable(RTC_Temper_t fe_Temper); + +void HAL_RTC_TamperDisable(RTC_Temper_t fe_Temper); + +void HAL_RTC_SetWakeUpTimer(RTC_WUTimerTypeDef *hrtc); + +void HAL_RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); + +uint32_t HAL_RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); + +void HAL_RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); + +FlagStatus HAL_RTC_GetFlagStatus(uint32_t RTC_FLAG); + +void HAL_RTC_ClearFlag(uint32_t RTC_FLAG); + +ITStatus HAL_RTC_GetITStatus(uint32_t RTC_IT); + +void HAL_RTC_ClearITPendingBit(uint32_t RTC_IT); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_sdmmc.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..3d3ce857a2068271a62e8ff0ef086c964c82f50b --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_sdmmc.h @@ -0,0 +1,400 @@ +/* + ****************************************************************************** + * @file HAL_SDMMC.h + * @version V1.0.0 + * @date 2020 + * @brief Header file of SDMMC HAL module. + ****************************************************************************** +*/ +#ifndef __HAL_SDMMC_H__ +#define __HAL_SDMMC_H__ + +#include "hal.h" + + +//#define SDMMC_INT_MODE + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +#define FCLK 220 + + +#define SDMMC_CH0 0 +#define SDMMC_CH1 1 + +#define EMMC_CARD 0 +#define SD_CARD 1 + +#define SDMMC_IDMA_DESC_NUM 16 + +//refer register RCC_PERCFGR +#define SDMMC_CLK_SRC_SYS_CLK (0<<11) //select SYS_CLK as SDIO source clock +#define SDMMC_CLK_SRC_PLL2_P_CLK (1<<11) //select PLL2_P_CLK as SDIO source clock +#define SDMMC_CLK_SRC_MSK (1<<11) +#define SDMMC_CLK_SRC SDMMC_CLK_SRC_SYS_CLK + +//refer register RCC_PERCFGR +#define SDMMC_SAMPLE_CLK_DELAY_BLK 0 //DLYB enable +#define SDMMC_SAMPLE_CLK_C1_FEEDBACK 1 //card1 feedback clock +#define SDMMC_SAMPLE_CLK_C2_FEEDBACK 2 //card2 feedback clock +#define SDMMC_SAMPLE_CLK_SDIO 3 //bypass DLYB + + +#define SDMMC_BUS_CLK_FREQ ((FCLK/8)*1000000) + + +#define SDMMC_CLK_SRC_DIV0 0 //clk src from DIV0 +#define SDMMC_CLK_SRC_DIV1 1 //clk src from DIV1 +#define SDMMC_CLK_SRC_DIV2 2 //clk src from DIV2 +#define SDMMC_CLK_SRC_DIV3 3 //clk src from DIV3 + +#define SDMMC_POWER_ON(x) (1<STATUS = (FLAG) + +#define __SPI_RXFIFO_RESET(SPIx) do{ \ + SET_BIT((SPIx)->RX_CTL, SPI_RX_CTL_FIFO_RESET); \ + CLEAR_BIT((SPIx)->RX_CTL, SPI_RX_CTL_FIFO_RESET); \ +}while(0); + +#define __SPI_TXFIFO_RESET(SPIx) do{ \ + SET_BIT((SPIx)->TX_CTL, SPI_TX_CTL_FIFO_RESET); \ + CLEAR_BIT((SPIx)->TX_CTL, SPI_TX_CTL_FIFO_RESET); \ +}while(0); + + +#define __HAL_SPI_TRANSSTART_CS_LOW(hspi) (hspi)->Instance->CS |= (hspi)->CSx +#define __HAL_SPI_CS_RELEASE(hspi) (hspi)->Instance->CS &= ~((hspi)->CSx) + +#define __SPI_MEMACC_ENABLE(SPIx) (SPIx)->MEMO_ACC.acc_en = 1 +#define __SPI_MEMACC_DISABLE(SPIx) (SPIx)->MEMO_ACC.acc_en = 0 + +#define __SPI_MEMACC_INSTRONCE_CLEAR(SPIx) (SPIx)->MEMO_ACC.instr_once_clr = 1 + +/** + * @brief SPI handle Structure definition + */ +typedef struct +{ + SPI_TypeDef *Instance; /* SPI registers base address */ + + SPI_InitTypeDef Init; /* SPI communication parameters */ + + uint8_t CSx; + + volatile uint32_t RxState; /* SPI state machine */ + volatile uint32_t TxState; /* SPI state machine */ + + uint8_t *Rx_Buffer; /* SPI Rx Buffer */ + uint8_t *Tx_Buffer; /* SPI Tx Buffer */ + + uint32_t Rx_Size; /* SPI Rx Size */ + uint32_t Tx_Size; /* SPI Tx Size */ + + uint32_t Rx_Count; /* SPI RX Count */ + uint32_t Tx_Count; /* SPI TX Count */ + + bool KeepCS; /* whether CS need kept at the end of transfer in IT mode. true for keeping */ +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *HDMA_Rx; /* SPI Rx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Tx; /* SPI Tx DMA handle parameters */ +#endif +}SPI_HandleTypeDef; + + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); + +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); + +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +HAL_StatusTypeDef HAL_SPI_TransmitKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_ReceiveKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +HAL_StatusTypeDef HAL_SPI_Transmit_IT_KeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT_KeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); + +#ifdef HAL_DMA_MODULE_ENABLED +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size); +#endif + +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout); + +HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode); + +uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi); +uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi); + +HAL_StatusTypeDef HAL_SPI_WaitTxTimeout(SPI_HandleTypeDef *hspi, uint32_t timeout); +HAL_StatusTypeDef HAL_SPI_WaitRxTimeout(SPI_HandleTypeDef *hspi, uint32_t timeout); +HAL_StatusTypeDef HAL_SPI_Switch_CS(SPI_HandleTypeDef *hspi, uint8_t CSx); + +HAL_StatusTypeDef HAL_SPI_MEMACCInit(SPI_HandleTypeDef* hspi, SPI_MemACCInitTypeDef* MemACCParam); + +HAL_StatusTypeDef HAL_SPI_TransmitNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitNoneBatchKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); + +HAL_StatusTypeDef HAL_SPI_ReceiveNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_ReceiveNoneBatchKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout); +#endif + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_timer.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..1325f5f725c6309e7b0295569562586b4484e623 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_timer.h @@ -0,0 +1,694 @@ +/*********************************************************************** + * Filename : hal_timer.h + * Description : timer driver header file + * Author(s) : Eric + * version : V1.0 + * Modify date : 2016-03-24 + ***********************************************************************/ +#ifndef __HAL_TIMER_H__ +#define __HAL_TIMER_H__ + +#include "hal.h" + + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) ( ((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM18) || \ + ((INSTANCE) == TIM19) || \ + ((INSTANCE) == TIM20) || \ + ((INSTANCE) == TIM25) \ + ) + +#define IS_TIM_BREAKSOURCE_INSTANCE ( ((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM18) || \ + ((INSTANCE) == TIM19) || \ + ((INSTANCE) == TIM20) || \ + ((INSTANCE) == TIM25) \ + ) + +/************** TIM Instances : supporting Break source selection *************/ + + + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) ( ((INSTANCE) != TIM6) && \ + ((INSTANCE) != TIM7) && \ + ((INSTANCE) != TIM21) && \ + ((INSTANCE) != TIM22) ) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM12) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20) || \ + ((INSTANCE) == TIM23) || \ + ((INSTANCE) == TIM24) || \ + ((INSTANCE) == TIM25) ) + + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20) || \ + ((INSTANCE) == TIM23) || \ + ((INSTANCE) == TIM24) ) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20) || \ + ((INSTANCE) == TIM23) || \ + ((INSTANCE) == TIM24) ) + + + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) ( ((INSTANCE) != TIM6) && \ + ((INSTANCE) != TIM7) && \ + ((INSTANCE) != TIM21) && \ + ((INSTANCE) != TIM22) ) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((( (INSTANCE) == TIM1) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM8) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM20) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)) ) \ + || \ + (((INSTANCE) == TIM15) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM16) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM18) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM19) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM25) && \ + ((CHANNEL) == TIM_CHANNEL_1) ) ) + + + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) ) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) ) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM3) || \ + ((INSTANCE) == TIM4) ) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM9) || \ + ((INSTANCE) == TIM10) || \ + ((INSTANCE) == TIM11) || \ + ((INSTANCE) == TIM12) || \ + ((INSTANCE) == TIM13) || \ + ((INSTANCE) == TIM14) || \ + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM16) || \ + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM18) || \ + ((INSTANCE) == TIM19) || \ + ((INSTANCE) == TIM20) || \ + ((INSTANCE) == TIM25) ) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_32_BITS_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ + ((INSTANCE) == TIM5) || \ + ((INSTANCE) == TIM23) || \ + ((INSTANCE) == TIM24) ) + + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ + ((INSTANCE) == TIM8)) + + +#define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) +#define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +#define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER |= (__INTERRUPT__)) +#define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->DIER &= ~(__INTERRUPT__)) + +#define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__)) +#define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__) ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__)) + +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +#define TIM_CR2_CCPC_Pos (0U) +#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) +#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk +#define TIM_CR2_CCUS_Pos (2U) +#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) +#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk +#define TIM_CR2_CCDS_Pos (3U) +#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) +#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk + +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS +#define TIM_COMMUTATION_SOFTWARE 0x00000000U + +#define TIM_IT_UPDATE BIT0 +#define TIM_IT_CC1 BIT1 +#define TIM_IT_CC2 BIT2 +#define TIM_IT_CC3 BIT3 +#define TIM_IT_CC4 BIT4 +#define TIM_IT_COM BIT5 +#define TIM_IT_TRIGGER BIT6 +#define TIM_IT_BREAK BIT7 + +#define TIM_DMA_UPDATE BIT8 +#define TIM_DMA_CC1 BIT9 +#define TIM_DMA_CC2 BIT10 +#define TIM_DMA_CC3 BIT11 +#define TIM_DMA_CC4 BIT12 +#define TIM_DMA_COM BIT13 +#define TIM_DMA_TRIGGER BIT14 +#define TIM_DMA_BREAK BIT15 + + + +#define TIM_EVENTSOURCE_UPDATE BIT0 /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 BIT1 /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 BIT2 /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 BIT3 /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 BIT4 /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM BIT5 /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER BIT6 /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK BIT7 /*!< A break event is generated */ + +#define TIM_ARR_PRELOAD_DISABLE 0 +#define TIM_ARR_PRELOAD_ENABLE 1 + +#define TIM_COUNTERMODE_DIR_INDEX 4 +#define TIM_COUNTERMODE_UP (0 << TIM_COUNTERMODE_DIR_INDEX) +#define TIM_COUNTERMODE_DOWN (1 << TIM_COUNTERMODE_DIR_INDEX) + +#define TIM_COUNTERMODE_CMS_INDEX 5 +#define TIM_COUNTERMODE_CENTERALIGNED1 (1 << TIM_COUNTERMODE_CMS_INDEX) +#define TIM_COUNTERMODE_CENTERALIGNED2 (2 << TIM_COUNTERMODE_CMS_INDEX) +#define TIM_COUNTERMODE_CENTERALIGNED3 (3 << TIM_COUNTERMODE_CMS_INDEX) + +#define TIM_CLKCK_DIV_INDEX 8 +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 (1U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 (2U << TIM_CLKCK_DIV_INDEX) /*!< Clock division: tDTS=4*tCK_INT */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET (0U << 4) +#define TIM_TRGO_ENABLE (1U << 4) +#define TIM_TRGO_UPDATE (2U << 4) +#define TIM_TRGO_CMP_PULSE (3U << 4) +#define TIM_TRGO_OC1REF (4U << 4) +#define TIM_TRGO_OC2REF (5U << 4) +#define TIM_TRGO_OC3REF (6U << 4) +#define TIM_TRGO_OC4REF (7U << 4) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET (0U << 20) +#define TIM_TRGO2_ENABLE (1U << 20) +#define TIM_TRGO2_UPDATE (2U << 20) +#define TIM_TRGO2_CMP_PULSE (3U << 20) +#define TIM_TRGO2_OC1REF (4U << 20) +#define TIM_TRGO2_OC2REF (5U << 20) +#define TIM_TRGO2_OC3REF (6U << 20) +#define TIM_TRGO2_OC4REF (7U << 20) +#define TIM_TRGO2_OC5REF (8U << 20) +#define TIM_TRGO2_OC6REF (9U << 20) +#define TIM_TRGO2_OC4REF_RISINGFALLING (10U << 20) +#define TIM_TRGO2_OC6REF_RISINGFALLING (11U << 20) +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (12U << 20) +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (13U << 20) +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (14U << 20) +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (15U << 20) +/** + * @} + */ + +#define TIM_MASTERSLAVEMODE_DISABLE 0 +#define TIM_MASTERSLAVEMODE_ENABLE BIT7 + + +#define TIM_SLAVE_MODE_INDEX 0 +#define TIM_SLAVE_MODE_DIS (0U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC1 (1U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC2 (2U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_ENC3 (3U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_RST (4U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_GATE (5U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_TRIG (6U << TIM_SLAVE_MODE_INDEX) +#define TIM_SLAVE_MODE_EXT1 (7U << TIM_SLAVE_MODE_INDEX) + +#define TIM_SMCR_OCCS_Pos (3U) +#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ +#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ + +#define TIM_SMCR_TS_Pos (4U) +#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */ +#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!Instance->CR1 |= UART_CR1_UARTEN) +/** + * @} + */ + +/** @brief Disable UART + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~UART_CR1_UARTEN) +/** + * @} + */ + + +#define CLEAR_STATUS(reg, flag) WRITE_REG(reg, flag) + + +#define __HAL_UART_TXI_FIFO_LEVEL_SET(uartx, fifo_level) MODIFY_REG(uartx->CR3, UART_CR3_TXIFLSEL_Msk, fifo_level); + +#define __HAL_UART_RXI_FIFO_LEVEL_SET(uartx, fifo_level) MODIFY_REG(uartx->CR3, UART_CR3_RXIFLSEL_Msk, fifo_level); + + +/** @brief Resume receiving data in IT mode. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + * @note This macro is currently only used in idle call back function @HAL_UART_IdleCallback. +*/ +#define __HAL_UART_Resume_Receive_IT(__HANDLE__) do {\ + (__HANDLE__)->RxBusy = true; \ + (__HANDLE__)->Instance->IE |= UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI | UART_IE_RXI | UART_IE_IDLEI;\ +}while(0); +/** + * @} + */ + + +/** @brief Clear data in UART FIFO. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + * @note __HAL_UART_FIFO_FLUSH will keep the UART FIFO in enabled state. +*/ +#define __HAL_UART_FIFO_FLUSH(__HANDLE__) do{\ + CLEAR_BIT((__HANDLE__)->Instance->CR3, UART_CR3_FEN); \ + SET_BIT((__HANDLE__)->Instance->CR3, UART_CR3_FEN); \ +}while(0); +/** + * @} + */ + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); + +void HAL_UART_MspInit(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_UART_RS485_Init(UART_HandleTypeDef *huart, UART_RS485_DE_POL_Enum de_polarity, uint8_t deat_time, uint8_t dedt_time); + +HAL_StatusTypeDef HAL_UART_IRDA_Init(UART_HandleTypeDef *huart, bool is_lowpwr); + +HAL_StatusTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); + +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_UART_Receive_To_IDLEorBCNT(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, + UART_Receive_Mode_Enum rece_mode, uint32_t timeout); + +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); + +#ifdef HAL_DMA_MODULE_ENABLED +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif + +HAL_StatusTypeDef HAL_UART_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t addr, UART_WakeupMode_Enum wakeupMode); +HAL_StatusTypeDef HAL_UART_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); + +void HAL_UART_SetDebugUart(UART_TypeDef *UARTx); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_uart_7816m.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_uart_7816m.h new file mode 100644 index 0000000000000000000000000000000000000000..c590646ef965fae0b74dc0ee9f7b25b470cd7b18 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_uart_7816m.h @@ -0,0 +1,17 @@ +/****************************************************************************** +* @file : hal_uart_7816m.h +* @brief : header file +* @ver : V1.0.0 +* @date : 2020 +******************************************************************************/ +#ifndef __HAL_UART_7816M_H__ +#define __HAL_UART_7816M_H__ + +#include "acm32h5xx_hal_conf.h" + + +HAL_StatusTypeDef HAL_UART_7816M_Init(UART_HandleTypeDef *huart, uint32_t clk_psc, uint32_t guard_time); +HAL_StatusTypeDef HAL_UART_7816M_Receive(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout); +HAL_StatusTypeDef HAL_UART_7816M_Transmit(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_uart_ex.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_uart_ex.h new file mode 100644 index 0000000000000000000000000000000000000000..8c06dcfccd23c666c4fa260bd13a50f444643eae --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_uart_ex.h @@ -0,0 +1,22 @@ +/****************************************************************************** +*@file : hal_uart_ex.h +*@brief : Header file of UART EX HAL module. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ +#ifndef __HAL_UART_EX_H__ +#define __HAL_UART_EX_H__ + +#include "acm32h5xx_hal_conf.h" + +/**************** Definition of LIN BUS VERSION ***********************/ +#define UART_LIN_V1D3 0 //Lin bus version 1.3 +#define UART_LIN_V2DX 1 //Lin bus version 2.0/2.1/2.2 + +#define HAL_UART_LIN_Init HAL_UART_Init +void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size); +void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size); +uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout); +uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_usart.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..2a6dd53500a91c909584600521b5349e98fe214f --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_usart.h @@ -0,0 +1,331 @@ +/****************************************************************************** +* @file hal_usart.h + +* @brief Header file of USART HAL module. +* @version V1.0.0 +* @date 2020 +******************************************************************************/ +#ifndef __HAL_USART_H__ +#define __HAL_USART_H__ + +#include "acm32h5xx_hal_conf.h" + + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#define USART_WORDLENGTH_5B (0x00000000U) /*!< 5-bit Word Length */ +#define USART_WORDLENGTH_6B (USART_CR3_WLEN_0) /*!< 6-bit Word Length */ +#define USART_WORDLENGTH_7B (USART_CR3_WLEN_1) /*!< 7-bit Word Length */ +#define USART_WORDLENGTH_8B (USART_CR3_WLEN_0 | USART_CR3_WLEN_1) /*!< 8-bit Word Length */ +#define USART_WORDLENGTH_9B (USART_CR3_WLEN_2) /*!< 9-bit Word Length */ +/** + * @} + */ + + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE (0x00000000U) /*!< No parity */ +#define USART_PARITY_EVEN (USART_CR3_PEN | USART_CR3_EPS) /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR3_PEN) /*!< Odd parity */ +#define USART_PARITY_0 (USART_CR3_SPS | USART_CR3_PEN | USART_CR3_EPS) /*!< 0 parity */ +#define USART_PARITY_1 (USART_CR3_SPS | USART_CR3_PEN) /*!< 1 parity */ +/** + * @} + */ + + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_2 (USART_CR3_STP2) /*!< USART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_Mode USART Transfer Mode + * @{ + */ +#define USART_MODE_RX (USART_CR1_RXE) /*!< RX mode */ +#define USART_MODE_TX (USART_CR1_TXE) /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TXE | USART_CR1_RXE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE (0x00000000U) +#define USART_CLOCK_ENABLE (USART_CR2_CLKEN) /*! 0x00000080 */ +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW (0x00000000U) +#define USART_POLARITY_HIGH (USART_CR2_CPOL) /*! 0x00000400 */ +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE (0x00000000U) +#define USART_PHASE_2EDGE (USART_CR2_CPHA) /*! 0x00000200 */ +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE (0x00000000U) +#define USART_LASTBIT_ENABLE (USART_CR2_LBCL) /*! 0x00000100 */ +/** + * @} + */ + +/** @defgroup USART_NACK_State USART NACK State + * @{ + */ +#define USART_NACK_ENABLE (USART_CR2_NACK) /*! 0x00000040 */ +#define USART_NACK_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup FIFO interrupt Config + * @{ + */ +#define USART_TX_FIFO_1_16 (USART_CR3_TXIFLSEL_2 | USART_CR3_TXIFLSEL_0) /*!< Transfer 1 Data */ +#define USART_TX_FIFO_1_8 (0x00000000) /*!< Transfer 2 Data */ +#define USART_TX_FIFO_1_4 (USART_CR3_TXIFLSEL_0) /*!< Transfer 4 Data */ +#define USART_TX_FIFO_1_2 (USART_CR3_TXIFLSEL_1) /*!< Transfer 8 Data */ +#define USART_TX_FIFO_3_4 (USART_CR3_TXIFLSEL_1 | USART_CR3_TXIFLSEL_0) /*!< Transfer 12 Data */ +#define USART_TX_FIFO_7_8 (USART_CR3_TXIFLSEL_2) /*!< Transfer 14 Data */ + +#define USART_RX_FIFO_1_16 (USART_CR3_RXIFLSEL_2 | USART_CR3_RXIFLSEL_0) /*!< Receive 1 Data */ +#define USART_RX_FIFO_1_8 (0x00000000) /*!< Receive 2 Data */ +#define USART_RX_FIFO_1_4 (USART_CR3_RXIFLSEL_0) /*!< Receive 4 Data */ +#define USART_RX_FIFO_1_2 (USART_CR3_RXIFLSEL_1) /*!< Receive 8 Data */ +#define USART_RX_FIFO_3_4 (USART_CR3_RXIFLSEL_1 | USART_CR3_RXIFLSEL_0) /*!< Receive 12 Data */ +#define USART_RX_FIFO_7_8 (USART_CR3_RXIFLSEL_2) /*!< Receive 14 Data */ +/** + * @} + */ + +/** @defgroup USART_Error_Code USART Error Code + * @{ + */ +#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +/** + * @} + */ + + +/* + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the USART communication baud rate. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity. */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode. */ + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity. */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase. */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit. */ +}USART_InitTypeDef; + +/* + * @brief USART handle Structure definition + */ +typedef struct +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + uint32_t TxSize; /*!< USART Transmit parameters in interrupt */ + __IO uint32_t TxCount; + uint8_t *TxData; + + uint32_t RxSize; /*!< USART Receive parameters in interrupt */ + __IO uint32_t RxCount; + uint8_t *RxData; + + + __IO uint8_t TxBusy; + __IO uint8_t RxBusy; +#ifdef HAL_DMA_MODULE_ENABLED + DMA_HandleTypeDef *HDMA_Tx; /*!< USART Tx DMA handle parameters */ + DMA_HandleTypeDef *HDMA_Rx; /*!< USART Rx DMA handle parameters */ +#endif + __IO uint32_t ErrorCode; /*!Instance->CR1 |= USART_CR1_USARTEN) + +/** @brief Disable USART + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_USARTEN) + + +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + + + +#define CLEAR_STATUS(reg, flag) WRITE_REG(reg, flag) + + +#define __USART_TXI_FIFO_LEVEL_SET(fifo_level) MODIFY_REG(husart->Instance->CR3, USART_CR3_TXIFLSEL_Msk, fifo_level); + +#define __USART_RXI_FIFO_LEVEL_SET(fifo_level) MODIFY_REG(husart->Instance->CR3, USART_CR3_RXIFLSEL_Msk, fifo_level); +/** + * @} + */ + +/* HAL_USART_IRQHandler */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *huart); + +/* HAL_USART_MspInit */ +void HAL_USART_MspInit(USART_HandleTypeDef *huart); + +/* HAL_USART_Init */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *huart); + +/* HAL_USART_DeInit */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *huart); + +/* HAL_USART_GetState */ +HAL_StatusTypeDef HAL_USART_GetState(USART_HandleTypeDef *huart); + +/* HAL_USART_GetError*/ +uint32_t HAL_USART_GetError(USART_HandleTypeDef *huart); + +/* HAL_USART_Abort*/ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *huart); + +/* HAL_USART_DMAPause */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *huart); + +/* HAL_USART_DMAResume */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *huart); + + +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *huart); + +/* HAL_USART_Transmit */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout); + +/* HAL_USART_Receive */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout); + +/* HAL_USART_Transmit_IT */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); + +/* HAL_USART_Receive_IT */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); + +/* HAL_USART_Transmit_DMA */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); + +/* HAL_USART_Receive_DMA */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *huart, uint8_t *buf, uint32_t size); + +void HAL_USART_SetDebugUart(USART_TypeDef *USARTx); + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_wdt.h b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..c78c366772c1454c3b2e7c4b028c14431e4939ce --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Inc/hal_wdt.h @@ -0,0 +1,140 @@ + +/****************************************************************************** +*@file : hal_wdt.h +*@brief : Header file of WDT HAL module. +******************************************************************************/ + +#ifndef __HAL_WDT_H__ +#define __HAL_WDT_H__ + +#include "hal.h" + + +/** + * @brief WDT Init structure definition + */ + +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the WDT. + This parameter can be any value of @ref WDT_Clock_Prescaler */ + + uint32_t Mode; /*!< Specifies whether WDT mode is reset or interrupted. + This parameter can be any value of @ref WDT_Mode */ + + uint32_t Load; /*!< Specifies the WDT reload values. + This parameter must be a number between Min_Data = 0x00000000 + and Max_Data = 0xFFFFFFFF */ + + uint32_t IntClrTime; /*!< Specifies the wakeup value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0x0000 + and Max_Data = 0xFFFF */ + +} WDT_InitTypeDef; + +/** + * @brief WDT Handle Structure definition + */ + +typedef struct +{ + WDT_TypeDef *Instance; /*!< Register base address */ + + WDT_InitTypeDef Init; /*!< WDT required parameters */ + +} WDT_HandleTypeDef; + + +/** @defgroup WDT_Cmd + * @{ + */ + +#define WDT_CMD_FEED_WATCHDOG ( 0xAA55A55AU ) + +/** + * @} + */ +/** @defgroup WDT_Clock_Prescaler + * @{ + */ + +#define WDT_CLOCK_PRESCALER_1 ( 0U ) +#define WDT_CLOCK_PRESCALER_2 ( WDT_CTRL_DIVISOR_0 ) +#define WDT_CLOCK_PRESCALER_4 ( WDT_CTRL_DIVISOR_1 ) +#define WDT_CLOCK_PRESCALER_8 ( WDT_CTRL_DIVISOR_1 | WDT_CTRL_DIVISOR_0 ) +#define WDT_CLOCK_PRESCALER_16 ( WDT_CTRL_DIVISOR_2 ) +#define WDT_CLOCK_PRESCALER_32 ( WDT_CTRL_DIVISOR_2 | WDT_CTRL_DIVISOR_0 ) +#define WDT_CLOCK_PRESCALER_64 ( WDT_CTRL_DIVISOR_2 | WDT_CTRL_DIVISOR_1 ) +#define WDT_CLOCK_PRESCALER_128 ( WDT_CTRL_DIVISOR_2 | WDT_CTRL_DIVISOR_1 | WDT_CTRL_DIVISOR_0 ) + +/** + * @} + */ + +/** @defgroup WDT_Mode + * @{ + */ + +#define WDT_MODE_RESET ( 0U ) +#define WDT_MODE_INTERRUPT ( WDT_CTRL_MODE ) + +/** + * @} + */ + + +/** + * @brief + */ + +#define WDT_GET_IT_ENABLE(__HWDT__) ( (__HWDT__)->Instance->CTRL |= WDT_CTRL_INTEN ) + +#define WDT_GET_IT_DISABLE(__HWDT__) ( (__HWDT__)->Instance->CTRL &= ~WDT_CTRL_INTEN ) + +#define WDT_GET_RIS(__HWDT__) ( ((__HWDT__)->Instance->RIS & WDT_RIS_WDTRIS) ? SET : RESET ) + + + +/** @defgroup EXTI Private Macros + * @{ + */ + +#define IS_WDT_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WDT) + +#define IS_WDT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WDT_CLOCK_PRESCALER_1) || \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_2) || \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_4) || \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_8) || \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_16) || \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_32)|| \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_64)|| \ + ((__PRESCALER__) == WDT_CLOCK_PRESCALER_128)) + +#define IS_WDT_MODE(__MODE__) (((__MODE__) == WDT_MODE_RESET) || \ + ((__MODE__) == WDT_MODE_INTERRUPT)) + +#define IS_WDT_INTCLRTIME(__TIME__) ((__TIME__) <= 0xFFFFU) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +void HAL_WDT_IRQHandler(WDT_HandleTypeDef *hiwdt); + +void HAL_WDT_Callback(WDT_HandleTypeDef *hiwdt); + +HAL_StatusTypeDef HAL_WDT_Init(WDT_HandleTypeDef * hidt); + +void HAL_WDT_MspInit(WDT_HandleTypeDef * hiwdt); + +HAL_StatusTypeDef HAL_WDT_Refresh(WDT_HandleTypeDef *hiwdt); + +FlagStatus HAL_WDT_GetPending(void); + +void HAL_WDT_ClearPending(void); + + + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_HCD.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_HCD.c new file mode 100644 index 0000000000000000000000000000000000000000..e91cc54966142e92ce2098ed0503b98c7ab6fbf2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_HCD.c @@ -0,0 +1,1710 @@ +/** + ****************************************************************************** + * @file hal_hcd.c + * @author MCD Application Team + * @brief HCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a HCD_HandleTypeDef handle structure, for example: + HCD_HandleTypeDef hhcd; + + (#)Fill parameters of Init structure in HCD handle + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure HCD pin-out + (##) Configure HCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the HAL HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HAL_HCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hal.h" + + + +#ifdef HAL_HCD_MODULE_ENABLED + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx; + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + + USBx = hhcd->Instance; + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_SPEED_HIGH: High speed mode, + * HCD_SPEED_FULL: Full speed mode, + * HCD_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + HAL_StatusTypeDef status; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].max_packet = mps; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + hhcd->hc[ch_num].speed = speed; + + status = USB_HC_Init(hhcd->Instance, + ch_num, + epnum, + dev_address, + speed, + ep_type, + mps); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /*send data */ + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].last_xfer_count = 0; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SRQINT)) + { +// hhcd->ConnectCallback(hhcd); +// USBH_PWR_ON(); + + __HAL_PCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SRQINT); + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + { + HCD_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if(interrupt&0x01) + { + if((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + + interrupt >>= 1; + + if(0==interrupt) + { + break; + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + } +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callabck is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + __HAL_HCD_ENABLE(hhcd); + (void)USB_DriveVbus(hhcd->Instance, 1U); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_ResetPort(hhcd->Instance)); +} + +/** + * @brief Set port into suspend mode. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef USB_SuspPort(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef HAL_HCD_SuspPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_SuspPort(hhcd->Instance)); +} + +/** + * @brief host enable HNP. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef USB_HstEnHnp(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef HAL_HCD_EnHnp(HCD_HandleTypeDef *hhcd) +{ + return (USB_HstEnHnp(hhcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); + hhcd->hc[ch_num].state = HC_BBLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_STALL; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + } + else + { + /* ... */ + } + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[ch_num].state = HC_XFRC; + hhcd->hc[ch_num].ErrCnt = 0U; +// __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + __HAL_HCD_CLEAR_HC_INT(ch_num, (USB_OTG_HCINT_XFRC | USB_OTG_HCINT_ACK)); + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + { + USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[ch_num].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[ch_num].toggle_in ^= 1U; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } + hhcd->hc[ch_num].toggle_in ^= 1U; + + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + { + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + } + else if (hhcd->hc[ch_num].state == HC_STALL) + { + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } + else + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else if (hhcd->hc[ch_num].state == HC_NAK) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else if (hhcd->hc[ch_num].state == HC_BBLERR) + { + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + { + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[ch_num].ErrCnt = 0U; + + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[ch_num].state = HC_NAK; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)chnum; + uint32_t tmpreg; + + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + + if (hhcd->hc[ch_num].do_ping == 1U) + { + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + { + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + { + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[ch_num].state = HC_XFRC; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_STALL; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].state = HC_NAK; + + if (hhcd->hc[ch_num].do_ping == 0U) + { + if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) + { + hhcd->hc[ch_num].do_ping = 1U; + } + } + + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + { + __HAL_HCD_MASK_HALT_HC_INT(ch_num); + + if (hhcd->hc[ch_num].state == HC_XFRC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } + } + else if (hhcd->hc[ch_num].state == HC_NAK) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_NYET) + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[ch_num].state == HC_STALL) + { + hhcd->hc[ch_num].urb_state = URB_STALL; + } + else if ((hhcd->hc[ch_num].state == HC_XACTERR) || + (hhcd->hc[ch_num].state == HC_DATATGLERR)) + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 3U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } + else + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + else + { + /* ... */ + } + + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none + */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t temp; + uint32_t tmpreg; + uint32_t ch_num; + + temp = hhcd->Instance->GRXSTSP; + ch_num = temp & USB_OTG_GRXSTSP_EPNUM; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + +// uart_printf("PacketIn==%x %x %x %08x\r\n", ch_num, pktsts, pktcnt, temp); + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + { + (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + + /*manage multiple Xfer */ + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; + hhcd->hc[ch_num].last_xfer_count = pktcnt; + + if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0, hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + hprt0_dup = USBx_HPRT0; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + { + USBx_HOST->HFIR = 30000U|BIT16; // Use 30MHz + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; + +} + + +HAL_StatusTypeDef HAL_HCD_UnmaskSofInt(HCD_HandleTypeDef *hhcd) +{ + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTMSK_SOFM); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_HCD_MaskSofInt(HCD_HandleTypeDef *hhcd) +{ + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTMSK_SOFM); + + return HAL_OK; +} + + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ +#endif /* HAL_HCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_PCD.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_PCD.c new file mode 100644 index 0000000000000000000000000000000000000000..c3e93b3496579939342b66fd3aeecc7dde8b57ee --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_PCD.c @@ -0,0 +1,1870 @@ +/** + ****************************************************************************** + * @file ACM32H5xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 Aisinochip. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hal.h" + +/** @addtogroup ACM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#include "usbd_def.h" + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) + HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); + HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); + HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); + extern HAL_StatusTypeDef USB_PHY_8BIT_16BIT_Select(USB_OTG_GlobalTypeDef *USBx, uint32_t Phy_cfg); +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx; + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + USBx = hpcd->Instance; + + if (hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Disable DMA mode for FS instance */ +// if ((USBx->CID & (0x1U << 8)) == 0U) +// { +// hpcd->Init.dma_enable = 0U; +// } + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + if ( (USB_OTG_ULPI_PHY == hpcd->Init.phy_itface) && (HCFG_30_MHZ == hpcd->Init.phy_cfg) ) + { + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6, GPIO_PIN_SET); + HAL_SimpleDelay(1000); + HAL_GPIO_WritePin(GPIOC, GPIO_PIN_6, GPIO_PIN_RESET); + HAL_SimpleDelay(50000); + } // reset ULPI PHY USB3300 + + + /* Force Device Mode*/ + (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE); + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + + + (void)USB_DevDisconnect(hpcd->Instance); + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + (void)HAL_PCD_Stop(hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_PCD_MspDeInit(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callabck is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief UnRegister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_PCD_ENABLE(hpcd); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + __HAL_PCD_DISABLE(hpcd); + + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + __HAL_UNLOCK(hpcd); + return HAL_ERROR; + } + + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ + + +void USBD_Setup_Process(PCD_HandleTypeDef *p_pcd ); + +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i, ep_intr, epint, epnum; + uint32_t fifoemptymsk, temp; + USB_OTG_EPTypeDef *ep; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + if (hpcd->Instance->GRXSTSR) + { + temp = hpcd->Instance->GRXSTSP; + ep = &(hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]); + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(hpcd->Instance, ep->xfer_buff, + (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(hpcd->Instance, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + + else + { + /* ... */ + } + + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); // for EP0, it is normally received zero length byte + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) // setup completely + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + CLEAR_OUT_EP_INTR(0, USB_OTG_DOEPINT_STPKTRX); + USBD_Setup_Process(hpcd); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT) ) + { + uint32_t epint, ep_intr, epnum; + + epnum = 0U; + + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + if (0 != epnum) + { + ( (USBD_HandleTypeDef*)(hpcd->pData))->pClass->DataIn(hpcd->pData, epnum); + } + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + } + + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + + } + epnum++; + ep_intr >>= 1U; + } + + } // process all IN EP events + + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); // fifo num = 16 means all fifo + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0x0009U; // completely and timeout interrupt enabled, TX empty interrupt enable will set in transfer function + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + + USBx_OUTEP(i)->DOEPINT = 0x000EU; // transfer completely and setup phase done 0xFB7FU + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + + USBx_DEVICE->DAINTMSK |= 0x10001U; // IN EP0 and Out EP0, for device EP inerrupt mask + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + USBx_DEVICE->DOEPMSK = USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_OTEPSPRM ; //transfer completely, EP disabled, setup phase end, status phase received, NAK + + USBx_DEVICE->DIEPMSK = USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_TOM; //transfer completely, EP disabled, timeout ? + + if (hpcd->Init.dma_enable == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)hpcd->Setup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + + HAL_PCD_ResetCallback(hpcd); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + } +} +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + } + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + } + else + { + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + } + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_ActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +{ + return hpcd->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ + HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ + HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + + if (hpcd->Init.dma_enable == 1U) + { + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + if (0 == epnum) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)hpcd->Setup; + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + else + { + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); + } + } + else + { + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ + HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ + HAL_PCD_SetupStageCallback(hpcd); + + return HAL_OK; +} +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_PCD_EX.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_PCD_EX.c new file mode 100644 index 0000000000000000000000000000000000000000..28bcc53236355e1da5afe4bf16fce5ca310d524e --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/HAL_PCD_EX.c @@ -0,0 +1,203 @@ +/** + ****************************************************************************** + * @file ACM32H5xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 Aisinochip. + * All rights reserved.

+ * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hal.h" + +/** @addtogroup ACM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ + +/** + * @brief Send LPM message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/LL_USB.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/LL_USB.c new file mode 100644 index 0000000000000000000000000000000000000000..a64e5eca9e66f125ad2f95ceabf9ca2ba519645a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/LL_USB.c @@ -0,0 +1,2769 @@ +/** + ****************************************************************************** + * @file LL_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2024 Aisinochip. + * All rights reserved. + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hal.h" + +/** @addtogroup ACM32H5xx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_HS1) || defined (USB_OTG_HS2) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +#ifdef USB_HS_PHYC +static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); +#endif + + +uint32_t Send_Array_32Align[256]; // 1024 bytes + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + + USBx_DEVICE->DCFG |= BIT14; //XCVRDLY + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + ret = HAL_OK; + } + + else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); //BIT6, 0 = USB 2.0 PHY, 1 = USB 1.1 PHY + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + /* Select UTMI Interace */ + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; // BIT4, 0 = select UTMI, 1 = ULPI + + if(HCFG_60_MHZ == cfg.phy_cfg) // 8BIT-60M + { + USBx->GUSBCFG &= (~USB_OTG_GUSBCFG_PHYIF); // select 8BIT 60M PHY interface + } + else + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYIF; // select 16BIT 30M PHY interface + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + HAL_Delay(2U); // delay at least 1ms + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + ret = HAL_OK; + } + else if (cfg.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); //BIT6, 0 = USB 2.0 PHY, 1 = USB 1.1 PHY + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + /* Select UTMI Interace */ + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; // BIT4, 0 = select UTMI, 1 = ULPI + + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; // USB 1.1 PHY + + if(HCFG_60_MHZ == cfg.phy_cfg) // 8BIT-60M + { + USBx->GUSBCFG &= (~USB_OTG_GUSBCFG_PHYIF); // select 8BIT 60M PHY interface + } + else + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYIF; // select 16BIT 30M PHY interface + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + HAL_Delay(2U); // delay at least 1ms + ret = HAL_OK; + + } + else + { + ret = HAL_ERROR; + } + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + + return ret; +} + + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + UsbTrd = 0x08; // about 500ns, should < 625ns + } + else if (speed == USBD_HS_SPEED) + { + if (USBx->GUSBCFG & BIT3) + { + UsbTrd = USBD_HS_TRDT_VALUE_16BIT; // about 351ns, should < 400ns for device + } + else + { + UsbTrd = USBD_HS_TRDT_VALUE_8BIT; + } + + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status +*/ +UINT32 USB_ReadRegGotgint(USB_OTG_GlobalTypeDef *USBx) +{ + return USBx->GOTGINT; +} + + +/** + * @brief USB_SetCurrentMode : Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_HOST_MODE: Host mode + * @arg USB_DRD_MODE: Dual Role Device mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + if(USBx->GOTGCTL & USB_OTG_GOTGCTL_CURR_MODE) // Host Mode already + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } + else + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + HAL_Delay(35U); // At least 25ms, set 35ms here + } + + } + else if (mode == USB_DEVICE_MODE) + { + if(USBx->GOTGCTL & USB_OTG_GOTGCTL_CURR_MODE) // Host Mode + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + HAL_Delay(35U); // At least 25ms, set 35ms here + } + else + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } + + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit : Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ +// USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ +// USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; +// USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + else + { + /* Enable HW VBUS sensing */ +// USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + + /* Device mode configuration */ + USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (1U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= (1 << 29); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; // enable RX FIFO not empty interrupt + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT; //enable reset/enum done/out ep/in ep/rx fifo not empty + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + uint32_t count = 0U; + + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0; + + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg PCD_SPEED_HIGH: High speed mode + * @arg PCD_SPEED_FULL: Full speed mode + */ +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + + +HAL_StatusTypeDef USB_EPIntEnable(USB_OTG_GlobalTypeDef *USBx, uint8_t ep_addr) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t ep_num=(ep_addr&EP_ADDR_MSK); + + if (ep_addr&(1<<7)) //ep in + { + USBx_DEVICE->DAINTMSK |= (1<DAINTMSK |= (1<<(16+ep_num)); + } + + return HAL_OK; +} + + +HAL_StatusTypeDef USB_EPIntDisable(USB_OTG_GlobalTypeDef *USBx, uint8_t ep_addr) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t ep_num=(ep_addr&EP_ADDR_MSK); + + if (ep_addr&(1<<7)) //ep in + { + USBx_DEVICE->DAINTMSK &= ~(1<DAINTMSK &= ~(1<<(16+ep_num)); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + +/** + * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + + + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + + +/** + * @brief USB_SetTestMode : Set Test mode, used in eye pattern test in HS Mode + * @param USBx Selected device + * @param register value + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetTestMode(USB_OTG_GlobalTypeDef *USBx, uint32_t value) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL = value; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; +// HAL_Delay(3U); + + HAL_SimpleDelay(100); + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; +// HAL_Delay(3U); + HAL_SimpleDelay(1000); + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadIntSts(USB_OTG_GlobalTypeDef *USBx) +{ + return USBx->GINTSTS; +} + + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevDctl(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return USBx_DEVICE->DCTL; +} + + + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval HAL status + */ +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; +// tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg, msk, emp; + +// msk = USBx_DEVICE->DIEPMSK; +// emp = USBx_DEVICE->DIEPEMPMSK; +// msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; +// tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT; + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS |= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +#ifdef USB_HS_PHYC +/** + * @brief Enables control of a High Speed USB PHY’s + * Init the low level hardware : GPIO, CLOCK, NVIC... + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) +{ + UNUSED(USBx); + uint32_t count = 0U; + + /* Enable LDO */ + USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + /* wait for LDO Ready */ + while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) + { + if (++count > 200000U) + { + return HAL_TIMEOUT; + } + } + + /* Controls PHY frequency operation selection */ + if (HSE_VALUE == 12000000U) /* HSE = 12MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); + } + else if (HSE_VALUE == 12500000U) /* HSE = 12.5MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); + } + else if (HSE_VALUE == 16000000U) /* HSE = 16MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); + } + else if (HSE_VALUE == 24000000U) /* HSE = 24MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); + } + else if (HSE_VALUE == 25000000U) /* HSE = 25MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); + } + else if (HSE_VALUE == 32000000U) /* HSE = 32MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); + } + else + { + /* ... */ + } + + /* Control the tuning interface of the High Speed PHY */ + USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE; + + /* Enable PLL internal PHY */ + USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + /* 2ms Delay required to get internal phy clock stable */ + HAL_Delay(2U); + + return HAL_OK; +} + +#endif /* USB_HS_PHYC */ +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + +// uart_printf("HCFG:0x%x\n", USBx_HOST->HCFG ); + + /* Make sure the FIFOs are flushed. */ + (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ + (void)USB_FlushRxFifo(USBx); + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINTMSK = 0U; + } + + + /* Enable VBUS driving */ + (void)USB_DriveVbus(USBx, 1U); + + HAL_Delay(200U); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xFFFFFFFFU; + + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return HAL_OK; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = 48000U | (1<<16); + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = 6000U; + } + else + { + /* ... */ + } + + return HAL_OK; +} + +/** +* @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** +* @brief USB_SuspPort : Suspend Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1) Set the host port enter suspend mode, host will stop send + * sof/keep-alive + */ +HAL_StatusTypeDef USB_SuspPort(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PSUSP | hprt0); + + return HAL_OK; +} + +/** +* @brief device request HNP + * @param USBx Selected device + * @retval HAL status + * @note (1) + * + */ +HAL_StatusTypeDef USB_DevReqHnp(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GOTGCTL |= USB_OTG_GOTGCTL_HNPRQ; + + return HAL_OK; +} + +/** +* @brief device request SRP + * @param USBx Selected device + * @retval HAL status + * @note (1) + * + */ +HAL_StatusTypeDef USB_DevReqSrp(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_SRPCAP; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_SRQ; + + return HAL_OK; +} + +/** +* @brief Host enable HNP + * @param USBx Selected device + * @retval HAL status + * @note (1) + * + */ +HAL_StatusTypeDef USB_HstEnHnp(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_HNPCAP; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_HSHNPEN; + + return HAL_OK; +} + +/** +* @brief Host enable HNP + * @param USBx Selected device + * @retval HAL status + * @note (1) + * + */ +HAL_StatusTypeDef USB_DevEnHnp(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_HNPCAP; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_DHNPEN; + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : VBUS Active + * 1 : VBUS Inactive + * @retval HAL status +*/ +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number +*/ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir, HCcharLowSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { +// if ((USBx->CID & (0x1U << 8)) != 0U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + } + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + if (speed == HPRT0_PRTSPD_LOW_SPEED) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + + if (ep_type == EP_TYPE_INTR) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + static __IO uint32_t tmpreg = 0U; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = 256U; + + + if (hc->speed == USBH_HS_SPEED) +// if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) + { + if ((dma == 0U) && (hc->do_ping == 1U)) + { + + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + else if (dma == 1U) + { + USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + hc->do_ping = 0U; + } + else + { + /* ... */ + } + } + + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + if (hc->ep_is_in != 0U) + { + hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma == 0U) /* Slave mode */ + { + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do + { + if (++count > 1000U) + { + break; + } + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do + { + if (++count > 1000U) + { + break; + } + } + while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + +// uart_printf("do ping\n"); + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush FIFO */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + if (++count > 1000U) + { + break; + } + } + while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = 0xFFFFFFFFU; + USBx->GINTSTS = 0xFFFFFFFFU; + + (void)USB_EnableGlobalInt(USBx); + + return HAL_OK; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +HAL_StatusTypeDef USBD_EP0_Write_FIFO_And_Send(USB_OTG_GlobalTypeDef *USBx, uint32_t * pdata, uint16_t length) +{ + uint32_t USBx_BASE, i, length_words; + + length_words = length/4; + USBx_BASE = (uint32_t)USBx; + + USBx_INEP(0)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(0)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + USBx_INEP(0)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(0)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & (length) ); + + USBx_INEP(0)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + for ( i = 0; i < length_words; i++) + { + USBx_DFIFO(0) = pdata[i]; + } + + if(length%4) + { + USBx_DFIFO(0) = pdata[i]; + } + + return HAL_OK; +} + + +HAL_StatusTypeDef USBD_EP0_Write_FIFO_And_Send_DMA(USB_OTG_GlobalTypeDef *USBx, uint32_t * pdata, uint16_t length) +{ + uint32_t USBx_BASE, i, length_words; + + length_words = length/4; + USBx_BASE = (uint32_t)USBx; + + + if(0 != length) + { + USBx_INEP(0)->DIEPDMA = (uint32_t)(pdata); + } + + USBx_INEP(0)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(0)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + USBx_INEP(0)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(0)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & (length) ); + + USBx_INEP(0)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + + return HAL_OK; +} + +// length : calculate in bytes; when length = 0, send zero length packct + +HAL_StatusTypeDef USBD_EP0_Send_Data(void *hpcd, uint8_t * data, uint16_t length) +{ + uint32_t USBx_BASE, length_sent, epint; + uint32_t *p_Src; + USB_OTG_EPTypeDef *ep; + PCD_HandleTypeDef *p_hpcd; + + p_hpcd = (PCD_HandleTypeDef *) hpcd; + USBx_BASE = (uint32_t)((PCD_HandleTypeDef *)p_hpcd->Instance); + + if(length > 0) + { + if (0 != ( (uint32_t)data % 4) ) + { + memcpy(Send_Array_32Align, data, length); + p_Src = Send_Array_32Align; + } + else + { + p_Src = (uint32_t *)data; + } + } + + ep = &p_hpcd->IN_ep[0]; + ep->xfer_count = 0; + ep->xfer_len = length; + + // for zero length packet, USBD_EP0_Write_FIFO_And_Send will not write data to FIFO. + do + { + if (length > ep->maxpacket) + { + length_sent = ep->maxpacket; + } + else + { + length_sent = length; + } + if (p_hpcd->Init.dma_enable) + { + USBD_EP0_Write_FIFO_And_Send_DMA( (USB_OTG_GlobalTypeDef *)USBx_BASE, p_Src, length_sent); + } + else + { + USBD_EP0_Write_FIFO_And_Send( (USB_OTG_GlobalTypeDef *)USBx_BASE, p_Src, length_sent); + } + + while(1) + { + epint = USB_ReadDevInEPInterrupt( (USB_OTG_GlobalTypeDef *)USBx_BASE, 0); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + CLEAR_IN_EP_INTR(0, USB_OTG_DIEPINT_XFRC); + break; + } + } + ep->xfer_count += length_sent; + length = length - length_sent; + p_Src = p_Src + (length_sent + 3)/4; + + } + while(ep->xfer_count < ep->xfer_len); + + if (ep->xfer_len) // for not zero length data packet, expect to receive zero packet from host for status stage. + { + p_hpcd->OUT_ep[0].xfer_len = 0; + USBD_EPx_Receive_Zero_Packet(USBx_BASE, 0); + } + else + { +// USBx_OUTEP(0)->DOEPDMA = (uint32_t)p_hpcd->Setup; + if (p_hpcd->Init.dma_enable) + { + USBx_OUTEP(0)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + } + + return HAL_OK; +} + + + +static HAL_StatusTypeDef USBD_EPx_Write_FIFO_And_Send_OnePacket(USB_OTG_GlobalTypeDef *USBx, uint32_t ep_num, uint32_t * pdata, uint16_t length, uint16_t ep_max_words) +{ + uint32_t USBx_BASE, i, length_words; + + + length_words = length/4; + USBx_BASE = (uint32_t)(USBx); + + USBx_INEP(ep_num)->DIEPTSIZ = BIT29; + + USBx_INEP(ep_num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(ep_num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & (length) ); + + USBx_INEP(ep_num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + while(1) + { + if ( (USBx_INEP(ep_num)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= ep_max_words) + { + for ( i = 0; i < length_words; i++) + { + USBx_DFIFO(ep_num) = pdata[i]; + } + + if(length%4) + { + USBx_DFIFO(ep_num) = pdata[i]; + } + break; + } + } + return HAL_OK; +} + + + +static HAL_StatusTypeDef USBD_EPx_Write_FIFO_And_Send_OnePacket_DMA(USB_OTG_GlobalTypeDef *USBx, uint32_t ep_num, uint32_t * pdata, uint16_t length, uint16_t ep_max_words) +{ + uint32_t USBx_BASE, i, length_words; + + length_words = length/4; + USBx_BASE = (uint32_t)(USBx); + + if(0 != length) + { + USBx_INEP(ep_num)->DIEPDMA = (uint32_t)(pdata); + } + USBx_INEP(ep_num)->DIEPTSIZ = BIT29; + + USBx_INEP(ep_num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(ep_num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & (length) ); + + USBx_INEP(ep_num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + return HAL_OK; +} + + + +// check whether device is ready to receive data +uint32_t USBD_EPx_Has_Receive_Data_Started(void * p_hpcd, uint32_t ep_num) +{ + uint32_t USBx_BASE, epint; + + USBx_BASE = (uint32_t)( ( (PCD_HandleTypeDef *)p_hpcd)->Instance); + + return (USBx_OUTEP((uint32_t)ep_num)->DOEPCTL & BIT31); +} + +// check whether Host has sent data to out EP +uint32_t USBD_EPx_Host_Sent_Data_to_OutEP(void * p_hpcd, uint32_t ep_num) +{ + uint32_t USBx_BASE, epint; + + USBx_BASE = (uint32_t)( ( (PCD_HandleTypeDef *)p_hpcd)->Instance); + + epint = USBx_OUTEP((uint32_t)ep_num)->DOEPINT; + + return (epint & (BIT0|BIT4|BIT8|BIT13) ); +} + +// clear flags of out ep +void USBD_EPx_Clear_Received_Data(void * p_hpcd, uint32_t ep_num) +{ + uint32_t USBx_BASE, epint; + + USBx_BASE = (uint32_t)( ( (PCD_HandleTypeDef *)p_hpcd)->Instance); + + USBx_OUTEP((uint32_t)ep_num)->DOEPINT = BIT0|BIT4|BIT8|BIT13; +} + +//Get Out EP error information +uint32_t USBD_EPx_Get_Out_EP_Error(void * p_hpcd, uint32_t ep_num) +{ + uint32_t USBx_BASE, epint; + + USBx_BASE = (uint32_t)( ( (PCD_HandleTypeDef *)p_hpcd)->Instance); + + return (USBx_OUTEP((uint32_t)ep_num)->DOEPINT & (BIT2|BIT8|BIT12) ); +} + +//Clear Out EP error information +void USBD_EPx_Clear_Out_EP_Error(void * p_hpcd, uint32_t ep_num) +{ + uint32_t USBx_BASE, epint; + + USBx_BASE = (uint32_t)( ( (PCD_HandleTypeDef *)p_hpcd)->Instance); + + USBx_OUTEP((uint32_t)ep_num)->DOEPINT = (BIT2|BIT8|BIT12); +} + + +HAL_StatusTypeDef USBD_EPx_Send_Data(void *hpcd, uint32_t ep_num, uint8_t * data, uint16_t length) +{ + uint32_t USBx_BASE, length_sent, epint; + uint32_t *p_Src; + USB_OTG_EPTypeDef *ep; + PCD_HandleTypeDef *p_hpcd; + USB_OTG_GlobalTypeDef * p_OTG; + uint32_t i; + + p_hpcd = (PCD_HandleTypeDef *) hpcd; + + USBx_BASE = (uint32_t)((PCD_HandleTypeDef *)p_hpcd->Instance); + p_OTG = (USB_OTG_GlobalTypeDef * )USBx_BASE; + + if(length > 0) + { + if (0 != ( (uint32_t)data % 4) ) + { + memcpy(Send_Array_32Align, data, length); + p_Src = Send_Array_32Align; + } + else + { + p_Src = (uint32_t *)data; + } + } + + ep = &p_hpcd->IN_ep[ep_num & 0x0F]; + ep->xfer_count = 0; + ep->xfer_len = length; + + // for zero length packet, USBD_EPx_Write_FIFO_And_Send will not write data to FIFO. + do + { + if (length > ep->maxpacket) + { + length_sent = ep->maxpacket; + } + else + { + length_sent = length; + } + + CLEAR_IN_EP_INTR(ep_num & 0x0F, USB_OTG_DIEPINT_XFRC); + + if (p_hpcd->Init.dma_enable) + { + USBD_EPx_Write_FIFO_And_Send_OnePacket_DMA( (USB_OTG_GlobalTypeDef *)USBx_BASE, ep_num & 0x0F, p_Src, length_sent, ep->maxpacket/4); + } + else + { + USBD_EPx_Write_FIFO_And_Send_OnePacket( (USB_OTG_GlobalTypeDef *)USBx_BASE, ep_num & 0x0F, p_Src, length_sent, ep->maxpacket/4); + } + i = 0; + p_OTG->GINTSTS = USB_OTG_GINTSTS_SOF | USB_OTG_GINTSTS_USBRST | USB_OTG_GINTSTS_USBSUSP; + + while(1) + { + epint = USB_ReadDevInEPInterrupt( (USB_OTG_GlobalTypeDef *)USBx_BASE, ep_num & 0x0F); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + CLEAR_IN_EP_INTR(ep_num & 0x0F, USB_OTG_DIEPINT_XFRC); + break; + } + + if (p_OTG->GINTSTS & USB_OTG_GINTSTS_SOF) + { + p_OTG->GINTSTS = USB_OTG_GINTSTS_SOF; + i++; + + if (i >= 800) // 125us * 800 = 100ms + { + goto SEND_ERROR_TIMEOUT; + } + } + + if (p_OTG->GINTSTS & (USB_OTG_GINTSTS_USBRST|USB_OTG_GINTSTS_USBSUSP) ) + { + return HAL_ERROR; + } + } + + ep->xfer_count += length_sent; + length = length - length_sent; + p_Src = p_Src + (length_sent + 3)/4; + + } + while(ep->xfer_count < ep->xfer_len); + + return HAL_OK; + + SEND_ERROR_TIMEOUT: + CLEAR_IN_EP_INTR(ep_num & 0x0F, USB_OTG_DIEPINT_XFRC); + USBx_INEP(ep_num)->DIEPTSIZ = 0; + if (USBx_INEP(ep_num)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep_num)->DIEPCTL = (USBx_INEP(ep_num)->DIEPCTL | (USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_EPDIS) ) & (~BIT31); + } + else + { + USBx_INEP(ep_num)->DIEPCTL = (USBx_INEP(ep_num)->DIEPCTL | (USB_OTG_DIEPCTL_SNAK) ) & (~BIT31); + } + HAL_SimpleDelay(5); + while(USBx_INEP(ep_num)->DIEPCTL & BIT31); + + (void)USB_FlushTxFifo(p_hpcd->Instance , (uint32_t)ep_num & EP_ADDR_MSK); + + return HAL_TIMEOUT; +} + + + +static HAL_StatusTypeDef USBD_EPx_Write_FIFO_And_Send_Ex(USB_OTG_GlobalTypeDef *USBx, uint32_t ep_num, uint32_t ep_max, uint32_t * pdata, uint16_t length) +{ + uint32_t USBx_BASE, i, j, k, length_words, max_packet_size_words, packet_count; + + length_words = length/4; + if (length%4) + { + length_words += 1; + } + + USBx_BASE = (uint32_t)(USBx); + + USBx_INEP(ep_num)->DIEPTSIZ = BIT29; + + packet_count = length / ep_max; + max_packet_size_words = ep_max/4; + + if (length%ep_max) + { + packet_count += 1; + } + + k = 0; + + USBx_INEP(ep_num)->DIEPTSIZ |= (( packet_count) << 19); + USBx_INEP(ep_num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & (length) ); + + USBx_INEP(ep_num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPENA|USB_OTG_DIEPCTL_CNAK); + + + for(i = 0; i < packet_count;) + { + if ( (USBx_INEP(ep_num)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= max_packet_size_words) + { + for(j = 0; j < max_packet_size_words; j++) + { + USBx_DFIFO(ep_num) = pdata[k]; + k++; + if (k == length_words) + { + return HAL_OK; + } + } + i++; + } + else + { + + } + + } + + return HAL_OK; +} + + +// the packet_count = length / ep_max should <= 8 +HAL_StatusTypeDef USBD_EPx_Send_Data_Ex(void *hpcd, uint32_t ep_num, uint32_t ep_max, uint8_t * data, uint16_t length) +{ + uint32_t USBx_BASE, length_sent, epint; + uint32_t *p_Src; + USB_OTG_EPTypeDef *ep; + PCD_HandleTypeDef *p_hpcd; + USB_OTG_GlobalTypeDef * p_OTG; + uint32_t i; + + p_hpcd = (PCD_HandleTypeDef *) hpcd; + + USBx_BASE = (uint32_t)((PCD_HandleTypeDef *)p_hpcd->Instance); + + p_OTG = (USB_OTG_GlobalTypeDef * )USBx_BASE; + + p_Src = (uint32_t *)data; + + ep = &p_hpcd->IN_ep[ep_num & 0x0F]; + ep->xfer_count = 0; + ep->xfer_len = length; + + i = 0; + CLEAR_IN_EP_INTR(ep_num & 0x0F, USB_OTG_DIEPINT_XFRC); + p_OTG->GINTSTS = USB_OTG_GINTSTS_SOF | USB_OTG_GINTSTS_USBRST | USB_OTG_GINTSTS_USBSUSP; + + USBD_EPx_Write_FIFO_And_Send_Ex( (USB_OTG_GlobalTypeDef *)USBx_BASE, ep_num & 0x0F, ep_max, p_Src, length); + + while ( ( (USBx_INEP(ep_num)->DIEPTSIZ) >> 19) & 0x3FFU ); // wait all data in txfifo has been read + + while(1) + { + epint = USB_ReadDevInEPInterrupt( (USB_OTG_GlobalTypeDef *)USBx_BASE, ep_num & 0x0F); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + CLEAR_IN_EP_INTR(ep_num & 0x0F, USB_OTG_DIEPINT_XFRC); + break; + } + + if (p_OTG->GINTSTS & USB_OTG_GINTSTS_SOF) + { + p_OTG->GINTSTS = USB_OTG_GINTSTS_SOF; + i++; + + if (i >= 800) // 125us * 800 = 100ms + { + goto SEND_ERROR_TIMEOUT; + } + } + + if (p_OTG->GINTSTS & (USB_OTG_GINTSTS_USBRST|USB_OTG_GINTSTS_USBSUSP) ) + { + return HAL_ERROR; + } + } + + return HAL_OK; + + SEND_ERROR_TIMEOUT: + CLEAR_IN_EP_INTR(ep_num & 0x0F, USB_OTG_DIEPINT_XFRC); + USBx_INEP(ep_num)->DIEPTSIZ = 0; + if (USBx_INEP(ep_num)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep_num)->DIEPCTL = (USBx_INEP(ep_num)->DIEPCTL | (USB_OTG_DIEPCTL_SNAK | USB_OTG_DIEPCTL_EPDIS) ) & (~BIT31); + } + else + { + USBx_INEP(ep_num)->DIEPCTL = (USBx_INEP(ep_num)->DIEPCTL | (USB_OTG_DIEPCTL_SNAK) ) & (~BIT31); + } + HAL_SimpleDelay(5); + while(USBx_INEP(ep_num)->DIEPCTL & BIT31); + + (void)USB_FlushTxFifo(p_hpcd->Instance , (uint32_t)ep_num & EP_ADDR_MSK); + + return HAL_TIMEOUT; +} + + + +HAL_StatusTypeDef USBD_EPx_Receive_Zero_Packet(uint32_t base_address, uint32_t epnum) +{ + uint32_t USBx_BASE, i; + + USBx_BASE = base_address; + + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (0)); + + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + + return HAL_OK; +} + + + + +uint8_t USB_GetIdStatus(USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GOTGCTL>>USB_OTG_GOTGCTL_CIDSTS_Pos)&0x01); +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS1) || defined (USB_OTG_HS2) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal.c new file mode 100644 index 0000000000000000000000000000000000000000..4329471051fc00d155a224c8c4bd3e95d54311af --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal.c @@ -0,0 +1,140 @@ +/****************************************************************************** +*@file : hal.c +*@brief : This is the common part of the HAL initialization +******************************************************************************/ + +#include "hal.h" + +static __IO uint32_t g_msTick = 0; +HAL_SysTickHandleTypeDef g_systickHandle; + +/****************************************************************************** +*@brief : init hal library +*@param : none +*@return: none +******************************************************************************/ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Init the low level hardware */ + HAL_MspInit(); + + /* Set Interrupt Group Priority */ + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + __HAL_RCC_EFUSE1_CLK_ENABLE(); + + HAL_RCC_GetSysCoreClockFreq(); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is RCH) */ + HAL_InitTick(TICK_INT_PRIORITY, TICK_PERIOD_MS); + + #if (DATA_ACCELERATE_ENABLE == 1) + System_EnableDAccelerate(); + #endif + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +*@brief : deinit hal library +*@param : none +*@return: none +******************************************************************************/ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Initialize the MSP +*@param : none +*@return: none +******************************************************************************/ +__attribute__((weak)) void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + + +/****************************************************************************** +*@brief : DeInitializes the MSP +*@param : none +*@return: none +******************************************************************************/ +__attribute__((weak)) void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + + +/****************************************************************************** +*@brief : This function configures the source of the time base. +* The time source is configured to have 1ms time base with a dedicated Tick interrupt priority. +*@note : This function is called automatically at the beginning of program after +* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). +*@note : In the default implementation, SysTick timer is the source of time base. +* It is used to generate interrupts at regular time intervals. +* Care must be taken if HAL_Delay() is called from a peripheral ISR process, +* The SysTick interrupt must have higher priority (numerically lower) +* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. +* The function is declared as __weak to be overwritten in case of other +* implementation in user file. +*@param : TickPriority: Tick interrupt priority. +*@retval: HAL status +******************************************************************************/ +__attribute__((weak)) HAL_StatusTypeDef HAL_InitTick(uint32_t intPrio, uint32_t msPeriod) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + g_systickHandle.freq = SystemCoreClock; + if (HAL_SYSTICK_Config(g_systickHandle.freq / (1000U / msPeriod)) > 0U) + { + return HAL_ERROR; + } + + g_systickHandle.period = SysTick->LOAD; + g_systickHandle.clkPerUs = g_systickHandle.freq / 1000000; + g_systickHandle.clkPerMs = g_systickHandle.freq / 1000; + g_systickHandle.msPeriod = msPeriod; + g_systickHandle.usPer65536Clk = 65536 / g_systickHandle.clkPerUs; + + /* Configure the SysTick IRQ priority */ + if (intPrio >= (1UL << __NVIC_PRIO_BITS)) + { + intPrio = (1UL << __NVIC_PRIO_BITS)-1; + } + HAL_NVIC_SetPriority(SysTick_IRQn, intPrio, 0U); + g_systickHandle.intPrio = intPrio; + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +*@brief : ͨwhileѭʱ +*@param : delay: whileѭ +*@ret : +******************************************************************************/ +void HAL_SimpleDelay(volatile uint32_t delay) +{ + while(delay--) + { + ; + } +} + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_adc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..cbfc8b5662cab0b510c177bbf8596827149e1711 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_adc.c @@ -0,0 +1,1305 @@ + +/****************************************************************************** +* @file : HAL_ADC.c +* @version : 1.0 +* @date : 2022.10.29 +* @brief : ADC HAL module driver +* +* @history : +* 2022.10.25 lwq create +* +******************************************************************************/ +#include "hal.h" + + +#ifdef HAL_ADC_MODULE_ENABLED + + + +/****************************************************************************** +* @brief : This function handles ADC interrupt request. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: none +******************************************************************************/ +__weak void HAL_ADC_IRQCallback(ADC_HandleTypeDef* hadc) +{ + +} + +/****************************************************************************** +* @brief : Handle ADC interrupt request. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: None +******************************************************************************/ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + HAL_ADC_IRQCallback(hadc); +} + + +/****************************************************************************** +* @brief : Initialize the ADC MSP. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: none +******************************************************************************/ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* + NOTE : This function should be modified by the user. + the HAL_ADC_MspInit can be implemented in the user file. + */ + UNUSED(hadc); +} + +/****************************************************************************** +* @brief : Deinitialize the ADC MSP. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: none +******************************************************************************/ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* + NOTE : This function should be modified by the user. + the HAL_ADC_MspDeInit can be implemented in the user file. + */ + UNUSED(hadc); +} + + /****************************************************************************** +* @brief : Init the ADC module. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the ADC handle allocation */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ConConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OverMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OverSampMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.AnalogWDGEn)); + assert_param(IS_ADC_CLOCKSOURCE(hadc->Init.ClockSource)); + assert_param(IS_ADC_CLOCKDIV(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); + assert_param(IS_ADC_RIGHTBITSHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + if(hadc->Instance == ADC3) + { + tmpADC_Common = ADC3_COMMON; + } + else + { + tmpADC_Common = ADC12_COMMON; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC, DMA */ + HAL_ADC_MspInit(hadc); + + /* ADC regulator enable */ + SET_BIT(hadc->Instance->CR2,ADC_CR2_ADCVREGEN); + HAL_SimpleDelay(50000);//delay 20us + + /* Release Reset AFE */ + SET_BIT(hadc->Instance->CR2,ADC_CR2_ADCRSTN); + + /* Select clock source */ + MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_CLKMODE_Msk, hadc->Init.ClockSource); + + /* Set Clock DIV */ + MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_ADCDIV_Msk, ((hadc->Init.ClockPrescaler - 1) << ADC_CCR_ADCDIV_Pos)); + + + if(hadc->Init.ChannelEn & ADC_CHANNEL_VBAT_EN) + { + SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);//Enable VBAT + } + else if(hadc->Init.ChannelEn & ADC_CHANNEL_VREF_EN) + { + SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFINTEN);//Enable VREF + } + else if(hadc->Init.ChannelEn & ADC_CHANNEL_TEMP_EN) + { + SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);//Enable TS + } + + //Resolution + hadc->Instance->CR2 &= ~(ADC_CR2_RES); + hadc->Instance->CR2 |= hadc->Init.Resolution; + + /* Set ADC data alignment */ + hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + hadc->Instance->CR2 |= hadc->Init.DataAlign; + + //Set continued convert mode + if(hadc->Init.ConConvMode) + { + SET_BIT(hadc->Instance->CR1,ADC_CR1_CONT); + } + else + { + CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_CONT); + } + //Set DMA mode + MODIFY_REG(hadc->Instance->CR1, ADC_CR1_DMA_Msk, (hadc->Init.DMAMode << ADC_CR1_DMA_Pos)); + //Set Discontinued convert mode + if(hadc->Init.DiscontinuousConvMode) + { + /* Enable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + + /* Set the number of channels to be converted in discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM_Msk); + hadc->Instance->CR1 |= ((hadc->Init.NbrOfDiscConversion-1) <Instance->CR1 &= ~(ADC_CR1_DISCEN); + } + + //Overflow + if(hadc->Init.OverMode) + { + SET_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD); + } + else + { + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD); + } + //Over Sample Set + if(hadc->Init.OverSampMode) + { + MODIFY_REG(hadc->Instance->CR2,ADC_CR2_OVSR_Msk,hadc->Init.Oversampling.Ratio<Instance->CR2,ADC_CR2_OVSS_Msk,hadc->Init.Oversampling.RightBitShift<Instance->CR2,ADC_CR2_OVSE); // Regular channel over sample en. + if(hadc->Init.Oversampling.TriggeredMode) + { + SET_BIT(hadc->Instance->CR2,ADC_CR2_TROVS); // N times sample every trig. + } + else + { + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_TROVS); // 1 time sample every trig. + } + } + + //ExTrigSel set + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR1 &= ~(ADC_CR1_EXTSEL_Msk); + hadc->Instance->CR1 |= hadc->Init.ExternalTrigConv << ADC_CR1_EXTSEL_Pos; + + /* Select external trigger polarity */ + hadc->Instance->CR1 &= ~(ADC_CR1_EXTEN_Msk); + hadc->Instance->CR1 |= hadc->Init.ExternalTrigConvEdge << ADC_CR1_EXTEN_Pos; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR1 &= ~(ADC_CR1_EXTSEL_Msk); + hadc->Instance->CR1 &= ~(ADC_CR1_EXTEN_Msk); + } + + //Clear the sequence length. + CLEAR_BIT(hadc->Instance->SQR1,ADC_SQR1_L); //Clear the sequence length. + + return HAL_OK; +} + + +/****************************************************************************** +* @brief : DeInit the ADC module. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + /* Check the ADC handle allocation */ + if (hadc == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + HAL_ADC_MspDeInit(hadc); + + hadc->ChannelNum = 0; + hadc->ConvCpltCallback = NULL; + hadc->InjectedConvCpltCallback = NULL; + hadc->LevelOutOfWindowCallback = NULL; + memset(&hadc->Init, 0, sizeof(hadc->Init)); + + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Config the regular channel. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @param : sConfig : pointer to a ADC_ChannelConfTypeDef structure that contains +* the configuration information for ADC channel +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + __IO uint32_t *Reg_ADC_OFR; + + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_SEQUENCE(sConfig->Sq)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OverSampMode)); + assert_param(IS_FUNCTIONAL_STATE(sConfig->Diff)); + assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); + assert_param(IS_ADC_OFFSET(sConfig->Offset)); + assert_param(IS_ADC_OFFSET_CALCULATE(sConfig->OffsetCalculate)); + assert_param(IS_ADC_OFFSET_SIGN(sConfig->Offsetsign)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->ChannelNum)); + assert_param(IS_ADC_SMPCLOCK(sConfig->Smp)); + + //In hardware oversampling mode, the offset compensation function is ignored + if((sConfig->OffsetNumber != ADC_OFR_NONE) && (hadc->Init.OverSampMode)) + { + return HAL_ERROR; + } + /* Differential mode set*/ + if(sConfig->Diff) + { + SET_BIT(hadc->Instance->DIFSEL, 1 << sConfig->Channel); + } + else + { + CLEAR_BIT(hadc->Instance->DIFSEL, 1 << sConfig->Channel); + } + + /* Set Rule Sequence Conversion Order */ + if((sConfig->Sq >= 1)&&(sConfig->Sq <= 5)) + { + MODIFY_REG(hadc->Instance->SQR1,(ADC_SQR1_SQ1_Msk << (5*(sConfig->Sq - 1))), \ + (sConfig->Channel << (5*sConfig->Sq))); + } + else if((sConfig->Sq >= 6)&&(sConfig->Sq <= 11)) + { + MODIFY_REG(hadc->Instance->SQR2,(ADC_SQR2_SQ6_Msk << (5*(sConfig->Sq-6))), \ + (sConfig->Channel << (5*(sConfig->Sq-6)))); + } + else if((sConfig->Sq >= 12)&&(sConfig->Sq <= 16)) + { + MODIFY_REG(hadc->Instance->SQR3,(ADC_SQR3_SQ12_Msk << (5*(sConfig->Sq-12))), \ + (sConfig->Channel << (5*(sConfig->Sq-12)))); + } + else + { + return HAL_ERROR; + } + /* Set the length of the regular channel sequence */ + MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L_Msk, (hadc->ChannelNum-1)); + + /* Set the SMPR to every register*/ + if(sConfig->Channel <= ADC_CHANNEL_7) + { + MODIFY_REG(hadc->Instance->SMPR1,(ADC_SMPR1_SMP0_Msk << (4*sConfig->Channel )), \ + (sConfig->Smp << (4*sConfig->Channel ))); + } + else if((sConfig->Channel >= ADC_CHANNEL_8)&&(sConfig->Channel <= ADC_CHANNEL_15)) + { + MODIFY_REG(hadc->Instance->SMPR2,(ADC_SMPR2_SMP8_Msk << (4*(sConfig->Channel-8))), \ + (sConfig->Smp << (4*(sConfig->Channel-8)))); + } + else if((sConfig->Channel >= ADC_CHANNEL_16)&&(sConfig->Channel <= ADC_CHANNEL_18)) + { + MODIFY_REG(hadc->Instance->SMPR3,(ADC_SMPR3_SMP16_Msk << (4*(sConfig->Channel-16))), \ + (sConfig->Smp << (4*(sConfig->Channel-16)))); + } + else + { + return HAL_ERROR; + } + + /*set Offset */ + if (sConfig->OffsetNumber != ADC_OFR_NONE) + { + MODIFY_REG(hadc->Instance->OFR[sConfig->OffsetNumber], 0XFFFFFFFF, \ + (ADC_OFRX_OFFSETY_EN |(sConfig->Channel<OffsetCalculate |sConfig->Offsetsign |sConfig->Offset)); + } + else + { + hadc->Instance->OFR[0] &= ~ADC_OFRX_OFFSETY_EN; + hadc->Instance->OFR[1] &= ~ADC_OFRX_OFFSETY_EN; + hadc->Instance->OFR[2] &= ~ADC_OFRX_OFFSETY_EN; + hadc->Instance->OFR[3] &= ~ADC_OFRX_OFFSETY_EN; + } + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Enable and start the ADC convertion. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + if(hadc == NULL) + { + return HAL_ERROR; + } + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + + hadc->Instance->SR = (ADC_SR_AWD | ADC_SR_JEOG | ADC_SR_JEOC | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_EOC | ADC_SR_EOSMP | ADC_SR_ADRDY); + + /* Enable the ADC */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_EN)); + + /* Wait ADC ready */ + while(!(hadc->Instance->SR & ADC_SR_ADRDY)); + + if(hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) + { + /* Start covertion */ + hadc->Instance->CR1 |= ADC_CR1_SWSTART; + } + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Stop ADC conversion of regular group (and injected channels in +* case of auto_injection mode), disable ADC peripheral. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_STP)); + } + + /* Disable the ADC peripheral */ + (CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_EN)); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY); + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Enable ADC, start conversion of regular group with interruption. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OverMode)); + + /* Enable the ADC */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EN); + /* Wait ADC ready */ + while(!(hadc->Instance->SR & ADC_SR_ADRDY)); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_EOG | ADC_SR_EOC); + + hadc->Instance->IE |= (ADC_IE_EOCIE | ADC_IE_EOGIE); + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is + ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.OverMode) + { + hadc->Instance->SR |= ADC_SR_OVERF; + hadc->Instance->IE |= ADC_IE_OVERFIE; + } + + if(hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART); + } + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Stop ADC conversion of regular group (and injected group in +* case of auto_injection mode), disable interrution of +* end-of-conversion, disable ADC peripheral. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ConConvMode)); + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_STP)); + } + + /* Disable the ADC peripheral */ + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_EN); + + /* Disable rehular interruptions */ + hadc->Instance->IE &= ~(ADC_IE_EOCIE | ADC_IE_EOGIE); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_EOG | ADC_SR_EOC); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : ADC retrieve conversion value intended to be used with polling or interruption. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @return: the ADC covert result +******************************************************************************/ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + return (hadc->Instance->DR); +} + +/****************************************************************************** +* @brief : Polling to get the results of the ADC converter. +* @param : hadc : pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for ADC module. +* @param : pData : Destination Buffer address. +* @param : Length : Number of data to be transferred from ADC peripheral to memory. +* @param : Timeout : Polling timeout. +* @return: the ADC covert result +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout) +{ + uint32_t tmp_hal_status; + __IO uint32_t uiTimeout; + + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + if(HAL_ADC_Start(hadc) != HAL_OK) + { + return HAL_ERROR; + } + if(!pData) + { + return HAL_ERROR; + } + hadc->AdcResults = pData; + uiTimeout = Timeout; + + while(Length) + { + tmp_hal_status = hadc->Instance->SR; + if(tmp_hal_status & ADC_SR_EOC) + { + *hadc->AdcResults = hadc->Instance->DR; + hadc->Instance->SR = ADC_SR_EOC; + hadc->AdcResults++; + Length--; + } + if(tmp_hal_status & ADC_SR_OVERF) + { + hadc->Instance->SR = ADC_SR_OVERF; + } + if(tmp_hal_status & ADC_SR_EOG) + { + hadc->Instance->SR = ADC_SR_EOG; + break; + } + + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + return HAL_TIMEOUT; + } + } + } + + HAL_ADC_Stop(hadc); + + return HAL_OK; +} + + +/****************************************************************************** +* @brief: Configures for the selected ADC injected channel its corresponding +* rank in the sequencer and its sample time. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: sConfigInjected: ADC configuration structure for injected channel. +* @return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiff)); + assert_param(IS_ADC_JDR_NUMBER(sConfigInjected->InjectedOffsetNumber)); + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_SMPCLOCK(sConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_ADC_EXT_TRIG(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_EXT_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + assert_param(IS_ADC_OFFSET(sConfigInjected->InjectedOffset)); + assert_param(IS_ADC_OFFSET_CALCULATE(sConfigInjected->InjectedOffsetCalculate)); + assert_param(IS_ADC_OFFSET_SIGN(sConfigInjected->InjectedOffsetSign)); + assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); + assert_param(IS_ADC_RIGHTBITSHIFT(sConfigInjected->InjecOversampling.RightBitShift)); + + //In hardware oversampling mode, the offset compensation function is ignored + if((sConfigInjected->InjectedOffsetNumber!= ADC_JDR_NONE) && (sConfigInjected->InjecOversamplingMode)) + { + return HAL_ERROR; + } + /* JDISCEN and JAUTO bits can't be set at the same time */ + if((sConfigInjected->InjectedDiscontinuousConvMode) && (sConfigInjected->AutoInjectedConv)) + { + return HAL_ERROR; + } + /* DISCEN and JAUTO bits can't be set at the same time */ + if((hadc->Init.DiscontinuousConvMode) && (sConfigInjected->AutoInjectedConv)) + { + return HAL_ERROR; + } + + /* Diff Channel COnfig */ + if(sConfigInjected->InjectedDiff) + { + SET_BIT(hadc->Instance->DIFSEL,1<InjectedChannel); + } + else + { + CLEAR_BIT(hadc->Instance->DIFSEL,1<InjectedChannel); + } + + /* Set the SMPR to every register*/ + if (sConfigInjected->InjectedChannel <= ADC_CHANNEL_7) + { + MODIFY_REG(hadc->Instance->SMPR1,(ADC_SMPR1_SMP0_Msk << (4*sConfigInjected->InjectedChannel )), \ + (sConfigInjected->InjectedSamplingTime << (4*sConfigInjected->InjectedChannel ))); + } + else if(sConfigInjected->InjectedChannel>ADC_CHANNEL_7 || sConfigInjected->InjectedChannel<=ADC_CHANNEL_15) + { + MODIFY_REG(hadc->Instance->SMPR2,(ADC_SMPR2_SMP8_Msk << (4*(sConfigInjected->InjectedChannel-8))), \ + (sConfigInjected->InjectedSamplingTime << (4*(sConfigInjected->InjectedChannel-8)))); + } + else if(sConfigInjected->InjectedChannel>ADC_CHANNEL_16 || sConfigInjected->InjectedChannel<=ADC_CHANNEL_18) + { + MODIFY_REG(hadc->Instance->SMPR3,(ADC_SMPR3_SMP16_Msk << (4*(sConfigInjected->InjectedChannel-16))), \ + (sConfigInjected->InjectedSamplingTime<< (4*(sConfigInjected->InjectedChannel-16)))); + } + else + { + return HAL_ERROR; + } + /*---------------------------- ADCx JSQR Configuration -----------------*/ + //JL configuration + hadc->Instance->JSQR &= ~(ADC_JSQR_JL); + hadc->Instance->JSQR |= (sConfigInjected->InjectedNbrOfConversion-1)<Instance->JSQR |= sConfigInjected->InjectedChannel <<(5*sConfigInjected->InjectedRank); + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(sConfigInjected->ExternalTrigInjecConv != ADC_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->JSQR &= ~(ADC_JSQR_JEXTSEL); + hadc->Instance->JSQR |= sConfigInjected->ExternalTrigInjecConv << ADC_JSQR_JEXTSEL_Pos; + + /* Select external trigger polarity */ + hadc->Instance->JSQR &= ~(ADC_JSQR_JEXTEN); + hadc->Instance->JSQR |= sConfigInjected->ExternalTrigInjecConvEdge << ADC_JSQR_JEXTEN_Pos; + } + else + { + /* Reset the external trigger */ + hadc->Instance->JSQR &= ~(ADC_JSQR_JEXTSEL); + hadc->Instance->JSQR &= ~(ADC_JSQR_JEXTEN); + } + + //JAUTO configuration + if (sConfigInjected->AutoInjectedConv) + { + /* Enable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 |= ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); + } + + //InjectedDiscontinuousConvMode + if (sConfigInjected->InjectedDiscontinuousConvMode) + { + /* Enable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 |= ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); + } + + /*set Offset */ + if (sConfigInjected->InjectedOffsetNumber != ADC_OFR_NONE) + { + MODIFY_REG(hadc->Instance->OFR[sConfigInjected->InjectedOffsetNumber], 0XFFFFFFFF, \ + (ADC_OFRX_OFFSETY_EN |(sConfigInjected->InjectedChannel<InjectedOffsetCalculate | sConfigInjected->InjectedOffsetSign | \ + sConfigInjected->InjectedOffset)); + } + + //Oversampling + if (sConfigInjected->InjecOversamplingMode) + { + MODIFY_REG(hadc->Instance->CR2,ADC_CR2_OVSR_Msk,sConfigInjected->InjecOversampling.Ratio<Instance->CR2,ADC_CR2_OVSS_Msk,sConfigInjected->InjecOversampling.RightBitShift<Instance->CR2,ADC_CR2_JOVSE); // Inject channel over sample en. + } + else + { + CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_JOVSE); // Inject channel over sample Disable. + } + + return HAL_OK; +} + +/****************************************************************************** +* @brief: Enables the selected ADC software start conversion of the injected channels. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +{ + uint32_t tmp1 = 0U, tmp2 = 0U; + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_AWD | ADC_SR_JEOG | ADC_SR_JEOC | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_EOC | ADC_SR_EOSMP | ADC_SR_ADRDY); + + /* Enable the ADC */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EN); + + /* Wait ADC ready */ + while(!(hadc->Instance->SR & ADC_SR_ADRDY)); + + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Start covertion */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_JSWSTART); + } + + return HAL_OK; +} + + +/****************************************************************************** +* @brief: Stop ADC conversion of regular group (and injected channels in +* case of auto_injection mode), disable ADC peripheral. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ConConvMode)); + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_STP)); + } + + /* Disable the ADC peripheral */ + CLEAR_BIT(hadc->Instance->CR2, (ADC_CR2_EN)); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_AWD | ADC_SR_JEOG | ADC_SR_JEOC | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_EOC | ADC_SR_EOSMP | ADC_SR_ADRDY); + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +* @brief: Enable ADC, start conversion of injected channel with interruption. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + uint32_t tmp1 = 0U, tmp2 = 0U; + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + /* Enable the ADC */ + SET_BIT(hadc->Instance->CR2, (ADC_CR2_EN)); + /* Wait ADC ready */ + while(!(hadc->Instance->SR & ADC_SR_ADRDY)); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_JEOC | ADC_SR_JEOG); + + hadc->Instance->IE |= (ADC_IE_JEOCIE | ADC_IE_JEOGIE); + + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR1 |= ADC_CR1_JSWSTART; + } + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief: Stop ADC conversion of regular group (and injected group in +* case of auto_injection mode), disable interrution of +* end-of-conversion, disable ADC peripheral. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ConConvMode)); + + if(hadc->Init.ConConvMode) + { + /* Set stop flag */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_STP); + /* Waitting stop flag be cleared */ + while(READ_BIT(hadc->Instance->CR2, ADC_CR2_STP)); + } + + /* Disable the ADC peripheral */ + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_EN); + + /* Disable Inject interruptions */ + hadc->Instance->IE &= ~(ADC_IE_JEOCIE | ADC_IE_JEOGIE); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_JEOG | ADC_SR_JEOC); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief: Gets the converted value from data register of injected channel. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: InjectedRank: the ADC injected rank. +* This parameter can be one of the following values: +* @arg ADC_INJECTED_RANK_1: Injected Channel1 selected +* @arg ADC_INJECTED_RANK_2: Injected Channel2 selected +* @arg ADC_INJECTED_RANK_3: Injected Channel3 selected +* @arg ADC_INJECTED_RANK_4: Injected Channel4 selected +* @return: the ADC covert result +******************************************************************************/ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +{ + __IO uint32_t tmp = 0U; + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Clear injected group conversion flag to have similar behaviour as */ + /* regular group: reading data register also clears end of conversion flag. */ + hadc->Instance->SR = ADC_SR_JEOC; + + /* Return the selected ADC converted value */ + tmp = hadc->Instance->JDR[InjectedRank-1]; + + + return tmp; +} + +/****************************************************************************** +* @brief: Poll for injected conversion complete +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: Timeout: Timeout value in millisecond. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_InjectedPolling(ADC_HandleTypeDef* hadc, uint32_t InjectedRank, uint32_t* pData, uint32_t Length, uint32_t Timeout) +{ + uint32_t tmp_hal_status; + __IO uint32_t uiTimeout; + + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + if(HAL_ADC_Start(hadc) != HAL_OK) return HAL_ERROR; + if(!pData) return HAL_ERROR; + + hadc->AdcResults = pData; + uiTimeout = Timeout; + + while(Length) + { + tmp_hal_status = hadc->Instance->SR; + if(tmp_hal_status & ADC_SR_JEOC) + { + HAL_ADCEx_InjectedGetValue(hadc,InjectedRank); + hadc->Instance->SR = ADC_SR_JEOC; + hadc->AdcResults++; + Length--; + } + + if(tmp_hal_status & ADC_SR_OVERF) + { + hadc->Instance->SR = ADC_SR_OVERF; + } + if(tmp_hal_status & ADC_SR_JEOG) + { + hadc->Instance->SR = ADC_SR_JEOG; + break; + } + + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + + /****************************************************************************** +* @brief: Enable ADC, start conversion of regular group and transfer result through DMA +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: pData : Destination Buffer address. +* @param: Length : Number of data to be transferred from ADC peripheral to memory. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if (READ_BIT(hadc->Instance->CR1,ADC_CR1_DMA) == 0UL) + { + if(READ_BIT(hadc->Instance->CR2, ADC_CR2_EN)) + { + /* Disable ADC */ + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_EN); + } + + /* Enable ADC DMA mode */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_DMA); + } + + /* Enable the ADC peripheral */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EN); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_AWD | ADC_SR_JEOG | ADC_SR_JEOC | ADC_SR_OVERF | \ + ADC_SR_EOG | ADC_SR_EOC | ADC_SR_EOSMP | ADC_SR_ADRDY); + + /* Disable all interruptions before enabling the desired ones */ + hadc->Instance->IE &= ~(ADC_IE_EOSMPIE | ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | \ + ADC_IE_JEOCIE | ADC_IE_JEOGIE | ADC_IE_AWDIE); + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Return function status */ + return tmp_hal_status; +} + +/****************************************************************************** +* @brief: Configures the ADC multi-mode +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: multimode: pointer to an ADC_MultiModeTypeDef structure that contains +* the configuration information for multimode. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +{ + ADC_Common_TypeDef *tmpADC_Common; + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_MODE(multimode->Mode)); + assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + + + if(hadc->Instance == ADC3) + { + tmpADC_Common = ADC3_COMMON; + } + else + { + tmpADC_Common = ADC12_COMMON; + } + + /* Set ADC mode */ + tmpADC_Common->CCR &= ~(ADC_CCR_DUALMOD_Msk); + tmpADC_Common->CCR |= multimode->Mode << ADC_CCR_DUALMOD_Pos; + + /* Set the ADC DMA access mode */ + tmpADC_Common->CCR &= ~(ADC_CCR_DMADUAL_Msk); + tmpADC_Common->CCR |= multimode->DMAAccessMode << ADC_CCR_DMADUAL_Pos; + + /* Set delay between two sampling phases */ + tmpADC_Common->CCR &= ~(ADC_CCR_DELAY_Msk); + tmpADC_Common->CCR |= multimode->TwoSamplingDelay << ADC_CCR_DELAY_Pos; + + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief: Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral +* This function must be used only with the ADC master. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. +* @param: Length: The length of data to be transferred from ADC peripheral to memory. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + ADC_Common_TypeDef *tmpADC_Common; + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + + if(hadc->Instance == ADC3) + { + tmpADC_Common = ADC3_COMMON; + } + else + { + tmpADC_Common = ADC12_COMMON; + } + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if (READ_BIT(hadc->Instance->CR1,ADC_CR1_DMA) == 0UL) + { + if(READ_BIT(hadc->Instance->CR2, ADC_CR2_EN)) + { + /* Disable ADC */ + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_EN); + } + + /* Enable ADC DMA mode */ + SET_BIT(hadc->Instance->CR1,ADC_CR1_DMA); + } + + /* Enable the ADC peripheral */ + SET_BIT(hadc->Instance->CR2, ADC_CR2_EN); + + /* Clear the SR register */ + hadc->Instance->SR = (ADC_SR_AWD | ADC_SR_JEOG | ADC_SR_JEOC | ADC_SR_OVERF | \ + ADC_SR_EOG | ADC_SR_EOC | ADC_SR_EOSMP | ADC_SR_ADRDY); + + /* Disable all interruptions before enabling the desired ones */ + hadc->Instance->IE &= ~(ADC_IE_EOSMPIE | ADC_IE_EOCIE | ADC_IE_EOGIE | \ + ADC_IE_OVERFIE | ADC_IE_JEOCIE | ADC_IE_JEOGIE | ADC_IE_AWDIE); + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); + + /* Return function status */ + return tmp_hal_status; + +} + + +/****************************************************************************** +* @brief: Config the analog watchdog. +* @param: hadc: pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param: AnalogWDGConfig : pointer to a ADC_AnalogWDGConfTypeDef structure that contains +* the configuration information for ADC analog watchdog. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(hadc->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.AnalogWDGEn)); + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->RegularChannel)); + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->InjectChannel)); + assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_ADC_THRESHOLD(AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_THRESHOLD(AnalogWDGConfig->LowThreshold)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + + + if (hadc->Init.AnalogWDGEn) + { + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + hadc->Instance->CR1 &= (~(ADC_CR1_AWDSGL_Msk | ADC_CR1_JAWDEN_Msk | ADC_CR1_AWDEN_Msk)); + + /* Set the analog watchdog enable mode */ + hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; + + /* Configure ADC analog watchdog interrupt */ + if(AnalogWDGConfig->ITMode) + { + hadc->Instance->IE |= ADC_IE_AWDIE; + } + else + { + hadc->Instance->IE &= ~ADC_IE_AWDIE; + } + + if(AnalogWDGConfig->WatchdogMode & ADC_CR1_AWDSGL) + { + /* Select the analog watchdog regular channel */ + if(AnalogWDGConfig->WatchdogMode & ADC_CR1_AWDEN) + { + /* Clear AWDCH bits */ + hadc->Instance->CR1 &= (~ADC_CR1_AWDCH_Msk); + hadc->Instance->CR1 |= AnalogWDGConfig->RegularChannel; + } + /* Select the analog watchdog inject channel */ + if(AnalogWDGConfig->WatchdogMode & ADC_CR1_JAWDEN) + { + /* Clear AWDCH bits */ + hadc->Instance->CR1 &= (~ADC_CR1_AWDJCH_Msk); + hadc->Instance->CR1 |= (AnalogWDGConfig->InjectChannel << ADC_CR1_AWDJCH_Pos); + } + } + } + + if(AnalogWDGConfig->Diff) + { + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold<<16; + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold<<16; + } + else + { + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + } + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +* @brief: Checks whether the specified ADC flag is set or not. +* @param: ADCx: where x can be 1/2/3 to select the ADC peripheral. +* @param: ADC_FLAG: specifies the flag to check. +* @return: The new state of ADC_FLAG (SET or RESET). +******************************************************************************/ +FlagStatus HAL_ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(ADCx)); + assert_param(IS_ADC_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/****************************************************************************** +* @brief: Clears the ADCx's pending flags. +* @param: ADCx: where x can be 1/2/3 to select the ADC peripheral. +* @param: ADC_FLAG: specifies the flag to clear. +* @return: None +******************************************************************************/ +void HAL_ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(ADCx)); + assert_param(IS_ADC_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->SR = ADC_FLAG; +} + + +/****************************************************************************** +* @brief: Enables or disables the specified ADC interrupts. +* @param: ADCx: where x can be 1/2/3 to select the ADC peripheral. +* @param: ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. +* @param: NewState: new state of the specified ADC interrupts. +* This parameter can be: ENABLE or DISABLE. +* @return: None. +******************************************************************************/ +void HAL_ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT_FLAG(ADC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->IE |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->IE &= (~ADC_IT); + } +} + +/****************************************************************************** +* @brief: Checks whether the specified ADC interrupt has occurred or not. +* @param: ADCx: where x can be 1/2/3 to select the ADC peripheral. +* @param: ADC_IT: specifies the ADC interrupt source to check. +* @return: The new state of ADC_FLAG (SET or RESET). +******************************************************************************/ +ITStatus HAL_ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(ADCx)); + assert_param(IS_ADC_IT_FLAG(ADC_IT)); + + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->IE & ADC_IT) ; + + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & ADC_IT) != RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/****************************************************************************** +* @brief: Clears the ADC's interrupt pending bits. +* @param: ADCx: where x can be 1/2/3 to select the ADC peripheral. +* @param: ADC_IT: specifies the ADC interrupt pending bit to clear. +* @return: none +******************************************************************************/ +void HAL_ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + /* Check the parameters */ + assert_param(IS_ADC_INSTANCE(ADCx)); + assert_param(IS_ADC_IT_FLAG(ADC_IT)); + + if((ADCx->IE & ADC_IT)!= RESET) + { + /* Clear the interrupt pending bits in the RTC_SR register */ + ADCx->SR = ADC_IT; + } +} + +#endif + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_aes_20230713.lib b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_aes_20230713.lib new file mode 100644 index 0000000000000000000000000000000000000000..3b2b0ce578384cce1dccd137300c9915b8fbff1b Binary files /dev/null and b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_aes_20230713.lib differ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_aes_spi1.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_aes_spi1.c new file mode 100644 index 0000000000000000000000000000000000000000..b4c914fae0c57c6e47d15204bf9d7f5f922eca89 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_aes_spi1.c @@ -0,0 +1,1613 @@ +/****************************************************************************** +* File Name: aes.c +* Author: AisinoChip +* Data First Issued: 2020-06-17 +* Description: aes module driver +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_AES_SPI1_ENABLED + +#define SWAP32(a) ((a<<24)|((a&0x0000ff00)<<8)|((a&0x00ff0000)>>8)|(a>>24)) + + +uint32_t REG_IV1,REG_IV2,REG_IV3,REG_IV4; + +//const unsigned char S[256] = { +// 99, 124, 119, 123, 242, 107, 111, 197, 48, 1, 103, 43, 254, 215, 171, 118, +//202, 130, 201, 125, 250, 89, 71, 240, 173, 212, 162, 175, 156, 164, 114, 192, +//183, 253, 147, 38, 54, 63, 247, 204, 52, 165, 229, 241, 113, 216, 49, 21, +// 4, 199, 35, 195, 24, 150, 5, 154, 7, 18, 128, 226, 235, 39, 178, 117, +// 9, 131, 44, 26, 27, 110, 90, 160, 82, 59, 214, 179, 41, 227, 47, 132, +// 83, 209, 0, 237, 32, 252, 177, 91, 106, 203, 190, 57, 74, 76, 88, 207, +//208, 239, 170, 251, 67, 77, 51, 133, 69, 249, 2, 127, 80, 60, 159, 168, +// 81, 163, 64, 143, 146, 157, 56, 245, 188, 182, 218, 33, 16, 255, 243, 210, +//205, 12, 19, 236, 95, 151, 68, 23, 196, 167, 126, 61, 100, 93, 25, 115, +// 96, 129, 79, 220, 34, 42, 144, 136, 70, 238, 184, 20, 222, 94, 11, 219, +//224, 50, 58, 10, 73, 6, 36, 92, 194, 211, 172, 98, 145, 149, 228, 121, +//231, 200, 55, 109, 141, 213, 78, 169, 108, 86, 244, 234, 101, 122, 174, 8, +//186, 120, 37, 46, 28, 166, 180, 198, 232, 221, 116, 31, 75, 189, 139, 138, +//112, 62, 181, 102, 72, 3, 246, 14, 97, 53, 87, 185, 134, 193, 29, 158, +//225, 248, 152, 17, 105, 217, 142, 148, 155, 30, 135, 233, 206, 85, 40, 223, +//140, 161, 137, 13, 191, 230, 66, 104, 65, 153, 45, 15, 176, 84, 187, 22, +//}; + +//const unsigned char Si[256] = { +// 82, 9, 106, 213, 48, 54, 165, 56, 191, 64, 163, 158, 129, 243, 215, 251, +//124, 227, 57, 130, 155, 47, 255, 135, 52, 142, 67, 68, 196, 222, 233, 203, +// 84, 123, 148, 50, 166, 194, 35, 61, 238, 76, 149, 11, 66, 250, 195, 78, +// 8, 46, 161, 102, 40, 217, 36, 178, 118, 91, 162, 73, 109, 139, 209, 37, +//114, 248, 246, 100, 134, 104, 152, 22, 212, 164, 92, 204, 93, 101, 182, 146, +//108, 112, 72, 80, 253, 237, 185, 218, 94, 21, 70, 87, 167, 141, 157, 132, +//144, 216, 171, 0, 140, 188, 211, 10, 247, 228, 88, 5, 184, 179, 69, 6, +//208, 44, 30, 143, 202, 63, 15, 2, 193, 175, 189, 3, 1, 19, 138, 107, +// 58, 145, 17, 65, 79, 103, 220, 234, 151, 242, 207, 206, 240, 180, 230, 115, +//150, 172, 116, 34, 231, 173, 53, 133, 226, 249, 55, 232, 28, 117, 223, 110, +// 71, 241, 26, 113, 29, 41, 197, 137, 111, 183, 98, 14, 170, 24, 190, 27, +//252, 86, 62, 75, 198, 210, 121, 32, 154, 219, 192, 254, 120, 205, 90, 244, +// 31, 221, 168, 51, 136, 7, 199, 49, 177, 18, 16, 89, 39, 128, 236, 95, +// 96, 81, 127, 169, 25, 181, 74, 13, 45, 229, 122, 159, 147, 201, 156, 239, +//160, 224, 59, 77, 174, 42, 245, 176, 200, 235, 187, 60, 131, 83, 153, 97, +// 23, 43, 4, 126, 186, 119, 214, 38, 225, 105, 20, 99, 85, 33, 12, 125, +//}; + +//const unsigned char Logtable[256] = { +// 0, 0, 25, 1, 50, 2, 26, 198, 75, 199, 27, 104, 51, 238, 223, 3, +//100, 4, 224, 14, 52, 141, 129, 239, 76, 113, 8, 200, 248, 105, 28, 193, +//125, 194, 29, 181, 249, 185, 39, 106, 77, 228, 166, 114, 154, 201, 9, 120, +//101, 47, 138, 5, 33, 15, 225, 36, 18, 240, 130, 69, 53, 147, 218, 142, +//150, 143, 219, 189, 54, 208, 206, 148, 19, 92, 210, 241, 64, 70, 131, 56, +//102, 221, 253, 48, 191, 6, 139, 98, 179, 37, 226, 152, 34, 136, 145, 16, +//126, 110, 72, 195, 163, 182, 30, 66, 58, 107, 40, 84, 250, 133, 61, 186, +// 43, 121, 10, 21, 155, 159, 94, 202, 78, 212, 172, 229, 243, 115, 167, 87, +//175, 88, 168, 80, 244, 234, 214, 116, 79, 174, 233, 213, 231, 230, 173, 232, +// 44, 215, 117, 122, 235, 22, 11, 245, 89, 203, 95, 176, 156, 169, 81, 160, +//127, 12, 246, 111, 23, 196, 73, 236, 216, 67, 31, 45, 164, 118, 123, 183, +//204, 187, 62, 90, 251, 96, 177, 134, 59, 82, 161, 108, 170, 85, 41, 157, +//151, 178, 135, 144, 97, 190, 220, 252, 188, 149, 207, 205, 55, 63, 91, 209, +// 83, 57, 132, 60, 65, 162, 109, 71, 20, 42, 158, 93, 86, 242, 211, 171, +// 68, 17, 146, 217, 35, 32, 46, 137, 180, 124, 184, 38, 119, 153, 227, 165, +//103, 74, 237, 222, 197, 49, 254, 24, 13, 99, 140, 128, 192, 247, 112, 7, +//}; + +//const unsigned char Alogtable[256] = { +// 1, 3, 5, 15, 17, 51, 85, 255, 26, 46, 114, 150, 161, 248, 19, 53, +// 95, 225, 56, 72, 216, 115, 149, 164, 247, 2, 6, 10, 30, 34, 102, 170, +//229, 52, 92, 228, 55, 89, 235, 38, 106, 190, 217, 112, 144, 171, 230, 49, +// 83, 245, 4, 12, 20, 60, 68, 204, 79, 209, 104, 184, 211, 110, 178, 205, +// 76, 212, 103, 169, 224, 59, 77, 215, 98, 166, 241, 8, 24, 40, 120, 136, +//131, 158, 185, 208, 107, 189, 220, 127, 129, 152, 179, 206, 73, 219, 118, 154, +//181, 196, 87, 249, 16, 48, 80, 240, 11, 29, 39, 105, 187, 214, 97, 163, +//254, 25, 43, 125, 135, 146, 173, 236, 47, 113, 147, 174, 233, 32, 96, 160, +//251, 22, 58, 78, 210, 109, 183, 194, 93, 231, 50, 86, 250, 21, 63, 65, +//195, 94, 226, 61, 71, 201, 64, 192, 91, 237, 44, 116, 156, 191, 218, 117, +//159, 186, 213, 100, 172, 239, 42, 126, 130, 157, 188, 223, 122, 142, 137, 128, +//155, 182, 193, 88, 232, 35, 101, 175, 234, 37, 111, 177, 200, 67, 197, 84, +//252, 31, 33, 99, 165, 244, 7, 9, 27, 45, 119, 153, 176, 203, 70, 202, +// 69, 207, 74, 222, 121, 139, 134, 145, 168, 227, 62, 66, 198, 81, 243, 14, +// 18, 54, 90, 238, 41, 123, 141, 140, 143, 138, 133, 148, 167, 242, 13, 23, +// 57, 75, 221, 124, 132, 151, 162, 253, 28, 36, 108, 180, 199, 82, 246, 1, +//}; + +//const unsigned char iG[4][4] = { +//0x0e, 0x09, 0x0d, 0x0b, +//0x0b, 0x0e, 0x09, 0x0d, +//0x0d, 0x0b, 0x0e, 0x09, +//0x09, 0x0d, 0x0b, 0x0e, +//}; + +//const unsigned long rcon[30] = { +// 0x01,0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, +// 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91 }; + + + +#define MAXROUNDS 14 +#define MAXKC 8 +#define BLOCK_ROW 4 +#define BLOCK_COLUMN 4 +#define BLOCK_LENGTH 16 +#define SWAP_OFFSET 241 +#define KEY_OFFSET 242 + +/************************************************************************ + * function : delay + * Description: delay for a while. + * input : + * count: count to decrease + * return: none + ************************************************************************/ +void delay(uint32_t count) +{ + volatile uint32_t delay_count; + + delay_count = count; + + while(delay_count--); +} + + +void aes_memory_copy(uint32_t *psrc, uint32_t *pdst, uint32_t len) +{ + uint32_t i; + + for (i =0; i < len; i ++) + { + *pdst ++ = *psrc ++; + } +} + +void aes_memory_copy_u8(uint8_t *psrc, uint8_t *pdst, uint32_t len) +{ + uint32_t i; + + for (i =0; i < len; i ++) + { + *pdst ++ = *psrc ++; + } +} + +/****************************************************************************** +*@brief : set key for aes +*@param : keyin : pointer to buffer of key +*@param : key_len : select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) +*@param : swap_en : AES_SWAP_ENABLE, AES_SWAP_DISABLE +*@return: None +******************************************************************************/ +void HAL_AES_SPI_SetKey(uint32_t *keyin, uint8_t key_len, uint8_t swap_en) +{ + /* Enable Clock */ + __HAL_RCC_AES_SPI1_CLK_ENABLE(); + + AES->CTRL = 0x00; + if(AES_SPI_SWAP_ENABLE == swap_en) + { + AES->CTRL |= 0x10; + } + + if(AES_SPI_KEY_192 == key_len) + { + AES->CTRL |= (1 << 6); + + } + else if(AES_SPI_KEY_256 == key_len) + { + AES->CTRL |= (2 << 6); + } + + AES->KEYIN = keyin[0]; + AES->KEYIN = keyin[1]; + AES->KEYIN = keyin[2]; + AES->KEYIN = keyin[3]; + + if(AES_SPI_KEY_192 == key_len) + { + AES->KEYIN = keyin[4]; + AES->KEYIN = keyin[5]; + } + else if(AES_SPI_KEY_256 == key_len) + { + AES->KEYIN = keyin[4]; + AES->KEYIN = keyin[5]; + AES->KEYIN = keyin[6]; + AES->KEYIN = keyin[7]; + } + + AES->CTRL |= 0x02;//key setup + while((AES->STATE & 0x02) == 0); + AES->STATE = 0x02; + + __HAL_RCC_AES_SPI1_CLK_DISABLE(); +} + +void HAL_AES_SPI_SetKey_U8(uint8_t *keyin, uint8_t key_len, uint8_t swap_en) +{ + /* Enable Clock */ + __HAL_RCC_AES_SPI1_CLK_ENABLE(); + + AES->CTRL = 0x00; + + if(AES_SPI_SWAP_ENABLE == swap_en) + { + AES->CTRL |= 0x10; + } + + if(AES_SPI_KEY_192 == key_len) + { + AES->CTRL |= (1 << 6); + } + else if(AES_SPI_KEY_256 == key_len) + { + AES->CTRL |= (2 << 6); + } + + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + + if(AES_SPI_KEY_192 == key_len) + { + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + } + else if(AES_SPI_KEY_256 == key_len) + { + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + AES->KEYIN = (keyin[3] << 24) | (keyin[2] << 16) | (keyin[1] << 8) | keyin[0]; + keyin += 4; + } + + AES->CTRL |= 0x02;//key setup + while((AES->STATE & 0x02) == 0); + AES->STATE = 0x02; + + __HAL_RCC_AES_SPI1_CLK_DISABLE(); +} + +void aes_func(uint32_t *indata, uint32_t * outdata, uint8_t mode) +{ + AES->DATAIN = indata[ 0 ]; + AES->DATAIN = indata[ 1 ]; + AES->DATAIN = indata[ 2 ]; + AES->DATAIN = indata[ 3 ]; + + AES->CTRL |= 0x01; + while((AES->STATE & 0x01) == 0); + AES->STATE = 0x01; + + outdata[ 0 ] = AES->DATAOUT; + outdata[ 1 ] = AES->DATAOUT; + outdata[ 2 ] = AES->DATAOUT; + outdata[ 3 ] = AES->DATAOUT; + + if(AES_SPI_CBC_MODE == mode) + { + AES->STATE |= 0x04;//clear cbc flg + } +} + + +void aes_func_u8(uint8_t *indata, uint8_t * outdata, uint8_t mode) +{ + uint32_t result; + + AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; + AES->DATAIN = (indata[7] << 24) | (indata[6] << 16) | (indata[5] << 8) | indata[4]; + AES->DATAIN = (indata[11] << 24) | (indata[10] << 16) | (indata[9] << 8) | indata[8]; + AES->DATAIN = (indata[15] << 24) | (indata[14] << 16) | (indata[13] << 8) | indata[12]; + + AES->CTRL |= 0x01; + while((AES->STATE & 0x01) == 0); + AES->STATE = 0x01; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + if(AES_SPI_CBC_MODE == mode) + { + AES->STATE |= 0x04;//clear cbc flg + } +} + + +uint32_t aes_func_dfa(uint32_t *indata, uint32_t * outdata, uint8_t mode) +{ + uint8_t delay_num; + uint8_t rnd; + uint32_t temp_buffer[4]; + + //frist time + aes_func(indata, outdata, mode); + + //delay random time + HAL_HRNG_GetHrng(&rnd, 1); + delay_num = rnd & 0xf; + delay(delay_num); + + //second time + aes_func(indata, temp_buffer, mode); + + if( (outdata[0] == temp_buffer[0]) && + (outdata[1] == temp_buffer[1]) && + (outdata[2] == temp_buffer[2]) && + (outdata[3] == temp_buffer[3]) + ) + { + delay_num = (rnd >> 4) & 0xf; + delay(delay_num); + + if( (outdata[0] == temp_buffer[0]) && + (outdata[1] == temp_buffer[1]) && + (outdata[2] == temp_buffer[2]) && + (outdata[3] == temp_buffer[3]) + ) + { + return AES_SPI_PASS; + } + } + outdata[0] = 0; + outdata[1] = 0; + outdata[2] = 0; + outdata[3] = 0; + + return AES_SPI_FAIL; +} + +uint32_t aes_func_dfa_u8(uint8_t *indata, uint8_t * outdata, uint8_t mode) +{ + uint8_t delay_num; + uint8_t rnd; + uint8_t temp_buffer[16]; + uint8_t i,j; + + //frist time + aes_func_u8(indata, outdata, mode); + + //delay random time + HAL_HRNG_GetHrng(&rnd, 1); + delay_num = rnd & 0xf; + delay(delay_num); + + //second time + aes_func_u8(indata, temp_buffer, mode); + + for( i = 0; i < 16; i ++) + { + if(outdata[i] != temp_buffer[i]) + { + for ( j = 0; j < 16; j ++) + { + outdata[j] = 0; + } + return AES_SPI_FAIL; + } + } + + delay_num = (rnd >> 4) & 0xf; + delay(delay_num); + + for( i = 0; i < 16; i ++) + { + if(outdata[i] != temp_buffer[i]) + { + for ( j = 0; j < 16; j ++) + { + outdata[j] = 0; + } + return AES_SPI_FAIL; + } + } + + return AES_SPI_PASS; +} + + +void aes_cbc_mode_set(uint32_t * pdata, uint8_t mode) +{ + if(AES_SPI_CBC_MODE == mode) + { + AES->CTRL |= 0x20; + REG_IV1 = pdata[0]; + REG_IV2 = pdata[1]; + REG_IV3 = pdata[2]; + REG_IV4 = pdata[3]; + } + else + { + AES->CTRL &= (~0x20); + } +} + +uint32_t aes_crypt_security( + uint32_t *indata, + uint32_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint32_t *iv +) +{ + uint32_t * pSrcData, *pDstData; + uint32_t i; + uint32_t indata_bk[4]; + uint32_t temp_iv[4]; + + __HAL_RCC_HRNG_CLK_ENABLE(); + + if(operation == AES_SPI_DECRYPTION)//decrypt + { + AES->CTRL |= 0x04; + } + else + { + AES->CTRL &= (~0x04); + } + + AES->CTRL |= ( 1 << 8); //VAES enable + AES->CTRL &= 0xffff01ff; + AES->CTRL |= (1 << 9); //4round + + pSrcData = indata; + pDstData = outdata; + + if(AES_SPI_ECB_MODE == mode) //ECB + { + aes_cbc_mode_set(iv, mode); + for ( i = 0; i < block_len; i ++) + { + aes_memory_copy(pSrcData, indata_bk, 4); + if(aes_func_dfa(indata_bk, pDstData,mode) != AES_SPI_PASS) + { + return AES_SPI_FAIL; + } + + __HAL_RCC_HRNG_CLK_ENABLE(); + + pSrcData += 4; + pDstData += 4; + } + } + else //CBC + { + if(operation == AES_SPI_ENCRYPTION) + { + aes_cbc_mode_set(iv, mode); //IV + aes_memory_copy(pSrcData, indata_bk ,4); + + indata_bk[0] = REG_IV1 ^ indata_bk[0]; + indata_bk[1] = REG_IV2 ^ indata_bk[1]; + indata_bk[2] = REG_IV3 ^ indata_bk[2]; + indata_bk[3] = REG_IV4 ^ indata_bk[3]; + + if(aes_func_dfa(indata_bk, pDstData, mode) != AES_SPI_PASS) + { + return AES_SPI_FAIL; + } + + __HAL_RCC_HRNG_CLK_ENABLE(); + + block_len -- ; + while(block_len -- ) + { + aes_cbc_mode_set(pDstData, mode); //IV + pSrcData += 4; + pDstData += 4; + aes_memory_copy(pSrcData, indata_bk ,4); + + indata_bk[0] = REG_IV1 ^ indata_bk[0]; + indata_bk[1] = REG_IV2 ^ indata_bk[1]; + indata_bk[2] = REG_IV3 ^ indata_bk[2]; + indata_bk[3] = REG_IV4 ^ indata_bk[3]; + + if( aes_func_dfa( indata_bk, pDstData, mode) != AES_SPI_PASS ) + { + return AES_SPI_FAIL; + } + + __HAL_RCC_HRNG_CLK_ENABLE(); + + } + } + else//decryption + { + aes_memory_copy(pSrcData, indata_bk ,4); + aes_cbc_mode_set(iv, mode); //IV + temp_iv[0] = indata_bk[0]; + temp_iv[1] = indata_bk[1]; + temp_iv[2] = indata_bk[2]; + temp_iv[3] = indata_bk[3]; + if( aes_func_dfa( indata_bk, pDstData,mode) != AES_SPI_PASS ) + { + return AES_SPI_FAIL; + } + + __HAL_RCC_HRNG_CLK_ENABLE(); + + + pDstData[0] = REG_IV1 ^ pDstData[0]; + pDstData[1] = REG_IV2 ^ pDstData[1]; + pDstData[2] = REG_IV3 ^ pDstData[2]; + pDstData[3] = REG_IV4 ^ pDstData[3]; + + block_len --; + + while(block_len --) + { + aes_cbc_mode_set(indata_bk, mode); + pSrcData += 4; + pDstData += 4; + aes_memory_copy(pSrcData, indata_bk ,4); + + temp_iv[0] = indata_bk[0]; + temp_iv[1] = indata_bk[1]; + temp_iv[2] = indata_bk[2]; + temp_iv[3] = indata_bk[3]; + + if( aes_func_dfa( indata_bk, pDstData, mode) != AES_SPI_PASS ) + { + return AES_SPI_FAIL; + } + + __HAL_RCC_HRNG_CLK_ENABLE(); + + + pDstData[0] = REG_IV1 ^ pDstData[0]; + pDstData[1] = REG_IV2 ^ pDstData[1]; + pDstData[2] = REG_IV3 ^ pDstData[2]; + pDstData[3] = REG_IV4 ^ pDstData[3]; + + } + } + } + + //__HAL_RCC_HRNG_CLK_DISABLE(); + return AES_SPI_PASS; +} + + + +void aes_cbc_mode_set_u8(uint8_t * pdata, uint8_t mode) +{ + if(AES_SPI_CBC_MODE == mode) + { + AES->CTRL |= 0x20; + REG_IV1 = (pdata[3] << 24) | (pdata[2] << 16) | (pdata[1] << 8) | pdata[0]; + pdata += 4; + REG_IV2 = (pdata[3] << 24) | (pdata[2] << 16) | (pdata[1] << 8) | pdata[0]; + pdata += 4; + REG_IV3 = (pdata[3] << 24) | (pdata[2] << 16) | (pdata[1] << 8) | pdata[0]; + pdata += 4; + REG_IV4 = (pdata[3] << 24) | (pdata[2] << 16) | (pdata[1] << 8) | pdata[0]; + pdata += 4; + } + else + { + AES->CTRL &= (~0x20); + } + +} + +uint32_t aes_crypt_security_u8( + uint8_t *indata, + uint8_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint8_t *iv +) +{ + uint8_t * pSrcData, *pDstData; + uint32_t i; + uint8_t indata_bk[16]; +// uint32_t temp[4]; + + __HAL_RCC_HRNG_CLK_ENABLE(); + + if(operation == AES_SPI_DECRYPTION)//decrypt + { + AES->CTRL |= 0x04; + } + else + { + AES->CTRL &= (~0x04); + } + + AES->CTRL |= ( 1 << 8); //VAES enable + AES->CTRL &= 0xffff01ff; + AES->CTRL |= (1 << 9); //4round + + pSrcData = indata; + pDstData = outdata; + + if(AES_SPI_ECB_MODE == mode) + { + for ( i = 0; i < block_len; i ++) + { + aes_memory_copy_u8(pSrcData, indata_bk, 16); + if(aes_func_dfa_u8(indata_bk, pDstData, mode) != AES_SPI_PASS) + { + return AES_SPI_FAIL; + } + pSrcData += 16; + pDstData += 16; + } + } + else //CBC + { + if(operation == AES_SPI_ENCRYPTION) + { + aes_cbc_mode_set_u8(iv, mode); //ʼIV + aes_memory_copy_u8(pSrcData, indata_bk, 16); + +// temp[0] = REG_IV1 ^((indata_bk[3] << 24) | (indata_bk[2] << 16) | (indata_bk[1] << 8) | indata_bk[0]); +// temp[1] = REG_IV2 ^((indata_bk[7] << 24) | (indata_bk[6] << 16) | (indata_bk[5] << 8) | indata_bk[4]); +// temp[2] = REG_IV3 ^((indata_bk[11] << 24) | (indata_bk[10] << 16) | (indata_bk[9] << 8) | indata_bk[8]); +// temp[3] = REG_IV4 ^((indata_bk[15] << 24) | (indata_bk[14] << 16) | (indata_bk[13] << 8) | indata_bk[12]); + +// indata_bk[3] = (temp[0] >> 24) & 0xff; +// indata_bk[2] = (temp[0] >> 16) & 0xff; +// indata_bk[1] = (temp[0] >> 8) & 0xff; +// indata_bk[0] = (temp[0]) & 0xff; + +// indata_bk[7] = (temp[1] >> 24) & 0xff; +// indata_bk[6] = (temp[1] >> 16) & 0xff; +// indata_bk[5] = (temp[1] >> 8) & 0xff; +// indata_bk[4] = (temp[1]) & 0xff; +// +// indata_bk[11] = (temp[2] >> 24) & 0xff; +// indata_bk[10] = (temp[2] >> 16) & 0xff; +// indata_bk[9] = (temp[2] >> 8) & 0xff; +// indata_bk[8] = (temp[2]) & 0xff; + +// indata_bk[15] = (temp[3] >> 24) & 0xff; +// indata_bk[14] = (temp[3] >> 16) & 0xff; +// indata_bk[13] = (temp[3] >> 8) & 0xff; +// indata_bk[12] = (temp[3]) & 0xff; + + if(aes_func_dfa_u8(indata_bk, pDstData, mode) != AES_SPI_PASS) + { + return AES_SPI_FAIL; + } + block_len -- ; + while(block_len -- ) + { + aes_cbc_mode_set_u8(pDstData, mode); + pSrcData += 16; + pDstData += 16; + aes_memory_copy_u8(pSrcData, indata_bk, 16); + +// temp[0] = REG_IV1 ^ ((indata_bk[3] << 24) | (indata_bk[2] << 16) | (indata_bk[1] << 8) | indata_bk[0]); +// temp[1] = REG_IV2 ^ ((indata_bk[7] << 24) | (indata_bk[6] << 16) | (indata_bk[5] << 8) | indata_bk[4]); +// temp[2] = REG_IV3 ^ ((indata_bk[11] << 24) | (indata_bk[10] << 16) | (indata_bk[9] << 8) | indata_bk[8]); +// temp[3] = REG_IV4 ^ ((indata_bk[15] << 24) | (indata_bk[14] << 16) | (indata_bk[13] << 8) | indata_bk[12]); +// +// indata_bk[3] = (temp[0] >> 24) & 0xff; +// indata_bk[2] = (temp[0] >> 16) & 0xff; +// indata_bk[1] = (temp[0] >> 8) & 0xff; +// indata_bk[0] = (temp[0]) & 0xff; + +// indata_bk[7] = (temp[1] >> 24) & 0xff; +// indata_bk[6] = (temp[1] >> 16) & 0xff; +// indata_bk[5] = (temp[1] >> 8) & 0xff; +// indata_bk[4] = (temp[1]) & 0xff; +// +// indata_bk[11] = (temp[2] >> 24) & 0xff; +// indata_bk[10] = (temp[2] >> 16) & 0xff; +// indata_bk[9] = (temp[2] >> 8) & 0xff; +// indata_bk[8] = (temp[2]) & 0xff; + +// indata_bk[15] = (temp[3] >> 24) & 0xff; +// indata_bk[14] = (temp[3] >> 16) & 0xff; +// indata_bk[13] = (temp[3] >> 8) & 0xff; +// indata_bk[12] = (temp[3]) & 0xff; + + if( aes_func_dfa_u8( indata_bk, pDstData, mode) != AES_SPI_PASS ) + { + return AES_SPI_FAIL; + } + } + } + else//decryption + { + aes_memory_copy_u8(pSrcData, indata_bk, 16); //bufferֵindata_bk + aes_cbc_mode_set_u8(iv, mode); + + if( aes_func_dfa_u8( indata_bk, pDstData,mode) != AES_SPI_PASS ) + { + return AES_SPI_FAIL; + } + +// temp[0] = REG_IV1 ^ ((pDstData[3] << 24) | (pDstData[2] << 16) | (pDstData[1] << 8) | pDstData[0]); +// temp[1] = REG_IV2 ^ ((pDstData[7] << 24) | (pDstData[6] << 16) | (pDstData[5] << 8) | pDstData[4]); +// temp[2] = REG_IV3 ^ ((pDstData[11] << 24) | (pDstData[10] << 16) | (pDstData[9] << 8) | pDstData[8]); +// temp[3] = REG_IV4 ^ ((pDstData[15] << 24) | (pDstData[14] << 16) | (pDstData[13] << 8) | pDstData[12]); +// +// pDstData[3] = (temp[0] >> 24) & 0xff; +// pDstData[2] = (temp[0] >> 16) & 0xff; +// pDstData[1] = (temp[0] >> 8) & 0xff; +// pDstData[0] = (temp[0]) & 0xff; + +// pDstData[7] = (temp[1] >> 24) & 0xff; +// pDstData[6] = (temp[1] >> 16) & 0xff; +// pDstData[5] = (temp[1] >> 8) & 0xff; +// pDstData[4] = (temp[1]) & 0xff; +// +// pDstData[11] = (temp[2] >> 24) & 0xff; +// pDstData[10] = (temp[2] >> 16) & 0xff; +// pDstData[9] = (temp[2] >> 8) & 0xff; +// pDstData[8] = (temp[2]) & 0xff; + +// pDstData[15] = (temp[3] >> 24) & 0xff; +// pDstData[14] = (temp[3] >> 16) & 0xff; +// pDstData[13] = (temp[3] >> 8) & 0xff; +// pDstData[12] = (temp[3]) & 0xff; + + block_len --; + + while(block_len --) + { + aes_cbc_mode_set_u8(indata_bk, mode); + + pSrcData += 16; + pDstData += 16; + + aes_memory_copy_u8(pSrcData, indata_bk, 16); + + if( aes_func_dfa_u8( indata_bk, pDstData, mode) != AES_SPI_PASS ) + { + return AES_SPI_FAIL; + } + +// temp[0] = REG_IV1 ^ ((pDstData[3] << 24) | (pDstData[2] << 16) | (pDstData[1] << 8) | pDstData[0]); +// temp[1] = REG_IV2 ^ ((pDstData[7] << 24) | (pDstData[6] << 16) | (pDstData[5] << 8) | pDstData[4]); +// temp[2] = REG_IV3 ^ ((pDstData[11] << 24) | (pDstData[10] << 16) | (pDstData[9] << 8) | pDstData[8]); +// temp[3] = REG_IV4 ^ ((pDstData[15] << 24) | (pDstData[14] << 16) | (pDstData[13] << 8) | pDstData[12]); + +// pDstData[3] = (temp[0] >> 24) & 0xff; +// pDstData[2] = (temp[0] >> 16) & 0xff; +// pDstData[1] = (temp[0] >> 8) & 0xff; +// pDstData[0] = (temp[0]) & 0xff; + +// pDstData[7] = (temp[1] >> 24) & 0xff; +// pDstData[6] = (temp[1] >> 16) & 0xff; +// pDstData[5] = (temp[1] >> 8) & 0xff; +// pDstData[4] = (temp[1]) & 0xff; +// +// pDstData[11] = (temp[2] >> 24) & 0xff; +// pDstData[10] = (temp[2] >> 16) & 0xff; +// pDstData[9] = (temp[2] >> 8) & 0xff; +// pDstData[8] = (temp[2]) & 0xff; + +// pDstData[15] = (temp[3] >> 24) & 0xff; +// pDstData[14] = (temp[3] >> 16) & 0xff; +// pDstData[13] = (temp[3] >> 8) & 0xff; +// pDstData[12] = (temp[3]) & 0xff; + } + } + } + + //__HAL_RCC_HRNG_CLK_DISABLE(); //disable hrng clk + + return AES_SPI_PASS; +} + +void aes_crypt_normal( + uint32_t *indata, + uint32_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint32_t *iv +) +{ + uint32_t i,j; + uint32_t temp_iv[4]; + uint32_t ctr_o[4]; + uint32_t cnt[4]; + + if(operation == AES_SPI_DECRYPTION)//decrypt + { + AES->CTRL |= 0x04; + } + else + { + AES->CTRL &= (~0x04); + } + + if(AES_SPI_CBC_MODE == mode) + { + AES->CTRL |= 0x20; + AES->IVIN = iv[0]; + AES->IVIN = iv[1]; + AES->IVIN = iv[2]; + AES->IVIN = iv[3]; + } + else if(AES_SPI_CTR_MODE == mode) + { +// AES->CTRL = 0x1000; //CTR mode +// AES->CTRL |= (1<<14); //addr auto en,0x4000 + AES->CTRL |= 0x5000; //CTR mode,addr auto en + AES->CTRL &= (~0x04);//encrypt + AES->STARTADDR = iv[0]; + AES->ENDADDR = iv[1]; + AES->INIDATA = iv[2]; + AES->ADDR = iv[3]; + } + else //ECB + { + AES->CTRL &= (~0x20); + } + + i = 0; + for( j = block_len; j > 0; j-- ) + { + if(AES_SPI_CTR_MODE != mode) + { + AES->DATAIN = indata[ i ]; + AES->DATAIN = indata[ i + 1 ]; + AES->DATAIN = indata[ i + 2 ]; + AES->DATAIN = indata[ i + 3 ]; + } + + AES->CTRL |= 0x01; + while( (AES->STATE & 0x01) == 0); + AES->STATE = 0x01; + + if(AES_SPI_CTR_MODE == mode) + { + ctr_o[0] = AES->DATAOUT; + ctr_o[1] = AES->DATAOUT; + ctr_o[2] = AES->DATAOUT; + ctr_o[3] = AES->DATAOUT; + +// printf("ctr_o[0] = 0x%x\n",ctr_o[0]); +// printf("ctr_o[1] = 0x%x\n",ctr_o[1]); +// printf("ctr_o[2] = 0x%x\n",ctr_o[2]); +// printf("ctr_o[3] = 0x%x\n",ctr_o[3]); +// printf("\n"); + + outdata[ i ] = ctr_o[0] ^ indata[ i ]; + outdata[ i + 1] = ctr_o[1] ^ indata[ i + 1]; + outdata[ i + 2] = ctr_o[2] ^ indata[ i + 2]; + outdata[ i + 3] = ctr_o[3] ^ indata[ i + 3]; + +// indata += 4; +// outdata += 4; + } + else + { + outdata[ i ] = AES->DATAOUT; + outdata[ i + 1] = AES->DATAOUT; + outdata[ i + 2] = AES->DATAOUT; + outdata[ i + 3] = AES->DATAOUT; + } + + i += 4; + } + + AES->STATE |= 0x04;//clear cbc flg +} + + +void aes_crypt_normal_u8( + uint8_t *indata, + uint8_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint8_t *iv +) +{ + uint32_t j, result; + uint32_t temp_iv[4]; + + if(AES_SPI_CBC_MODE == mode) + { + AES->CTRL |= 0x20; + AES->IVIN = (iv[3] << 24) | (iv[2] << 16) | (iv[1] << 8) | iv[0]; + iv += 4; + AES->IVIN = (iv[3] << 24) | (iv[2] << 16) | (iv[1] << 8) | iv[0]; + iv += 4; + AES->IVIN = (iv[3] << 24) | (iv[2] << 16) | (iv[1] << 8) | iv[0]; + iv += 4; + AES->IVIN = (iv[3] << 24) | (iv[2] << 16) | (iv[1] << 8) | iv[0]; + iv += 4; +// if(operation == AES_DECRYPTION)//decrypt +// { +// AES->CTRL |= 0x04; //decrypt +// aes_cbc_mode_set_u8(iv,mode); //ʼIV + +// for( j = block_len; j > 0; j-- ) +// { +// temp_iv[0] = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; +// temp_iv[1] = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; +// temp_iv[2] = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; +// temp_iv[3] = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; + +// AES->DATAIN = temp_iv[0]; +// AES->DATAIN = temp_iv[1]; +// AES->DATAIN = temp_iv[2]; +// AES->DATAIN = temp_iv[3]; +// +// AES->CTRL |= 0x01; +// while((AES->STATE & 0x01) == 0); +// AES->STATE = 0x01; + +// result = REG_IV1 ^ (AES->DATAOUT); +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; +// +// result = REG_IV2 ^ (AES->DATAOUT); +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; + +// result = REG_IV3 ^ (AES->DATAOUT); +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; +// +// result = REG_IV4 ^ (AES->DATAOUT); +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; +// +// REG_IV1 = temp_iv[0]; +// REG_IV2 = temp_iv[1]; +// REG_IV3 = temp_iv[2]; +// REG_IV4 = temp_iv[3]; +// } +// } +// else //cbc, encrypt +// { +// AES->CTRL &= (~0x04); //encrypt +// aes_cbc_mode_set_u8(iv,mode); //ʼIV + +// for( j = block_len; j > 0; j-- ) +// { +// AES->DATAIN = ((indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]) ^ REG_IV1; //0x37A5AB3E +// indata += 4; +// AES->DATAIN = ((indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]) ^ REG_IV2; //0x0C32BA71 +// indata += 4; +// AES->DATAIN = ((indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]) ^ REG_IV3; //0x6F177462 +// indata += 4; +// AES->DATAIN = ((indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]) ^ REG_IV4; //0x8596B344 +// indata += 4; +// +// AES->CTRL |= 0x01; +// while((AES->STATE & 0x01) == 0); +// AES->STATE = 0x01; + +// result = AES->DATAOUT; //0x099ed143 +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// REG_IV1 = result; //IV +// outdata += 4; + +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// REG_IV2 = result; //IV +// outdata += 4; + +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// REG_IV3 = result; //IV +// outdata += 4; +// +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// REG_IV4 = result; //IV +// outdata += 4; +// } +// } + } + else //ECB mode + { + AES->CTRL &= (~0x20); +// if(operation == AES_DECRYPTION)//decrypt +// { +// AES->CTRL |= 0x04; +// } +// else +// { +// AES->CTRL &= (~0x04); +// } +// +// for( j = block_len; j > 0; j-- ) +// { +// AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; +// AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; +// AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; +// AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; +// indata += 4; + +// AES->CTRL |= 0x01; +// while((AES->STATE & 0x01) == 0); +// AES->STATE = 0x01; + +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; + +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; + +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; + +// result = AES->DATAOUT; +// outdata[3] = (result >> 24) & 0xff; +// outdata[2] = (result >> 16) & 0xff; +// outdata[1] = (result >> 8) & 0xff; +// outdata[0] = (result) & 0xff; +// outdata += 4; +// } + + } + + if(operation == AES_SPI_DECRYPTION)//decrypt + { + AES->CTRL |= 0x04; + } + else + { + AES->CTRL &= (~0x04); + } + + for( j = block_len; j > 0; j-- ) + { + AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; + indata += 4; + AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; + indata += 4; + AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; + indata += 4; + AES->DATAIN = (indata[3] << 24) | (indata[2] << 16) | (indata[1] << 8) | indata[0]; + indata += 4; + + AES->CTRL |= 0x01; + while( (AES->STATE & 0x01) == 0); + AES->STATE = 0x01; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + + result = AES->DATAOUT; + outdata[3] = (result >> 24) & 0xff; + outdata[2] = (result >> 16) & 0xff; + outdata[1] = (result >> 8) & 0xff; + outdata[0] = (result) & 0xff; + outdata += 4; + } + + AES->STATE |= 0x04;//clear cbc flg +} + + +uint32_t HAL_AES_SPI_Crypt( + uint32_t *indata, + uint32_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint32_t *iv, + uint32_t security_mode +) +{ + uint32_t flag; + + /* Enable Clock */ + __HAL_RCC_AES_SPI1_CLK_ENABLE(); + + if(security_mode == AES_SPI_NORMAL_MODE) + { + aes_crypt_normal(indata, outdata, block_len, operation, mode, iv); + __HAL_RCC_AES_SPI1_CLK_DISABLE(); + return AES_SPI_PASS; + } + else + { + __HAL_RCC_HRNG_CLK_ENABLE(); + + flag = aes_crypt_security(indata, outdata, block_len, operation, mode, iv); + + __HAL_RCC_HRNG_CLK_DISABLE(); + __HAL_RCC_AES_SPI1_CLK_DISABLE(); + + return flag; + } +} + + +uint32_t HAL_AES_SPI_Crypt_U8( + uint8_t *indata, + uint8_t *outdata, + uint32_t block_len, + uint8_t operation, + uint8_t mode, + uint8_t *iv, + uint32_t security_mode +) +{ + uint32_t flag; + + /* Enable Clock */ + __HAL_RCC_AES_SPI1_CLK_ENABLE(); + + if(security_mode == AES_SPI_NORMAL_MODE) + { + aes_crypt_normal_u8(indata, outdata, block_len, operation, mode, iv); + __HAL_RCC_AES_SPI1_CLK_DISABLE(); + return AES_SPI_PASS; + } + else + { + flag = aes_crypt_security_u8(indata, outdata, block_len, operation, mode, iv); + __HAL_RCC_AES_SPI1_CLK_DISABLE(); + return flag; + } +} + + + + +//uint32_t aes_crypt_CTR(uint32_t *indata, uint32_t *outdata, uint32_t block_len, uint8_t operation, uint32_t *ctr_iv, uint32_t *counter_val) +//{ +// uint32_t ctr_o[4]; +// uint32_t i; +// uint32_t cnt[4]; +// for(i = 0; i < 4; i++) +// { +// cnt[i] = ctr_iv[i]; +// } +// +// if(block_len == 0) +// { +// return AES_FAIL; +// } +// +//// enable_module(BIT_AES); +//// REG_AESCTRL = 0; +//// REG_UAC_CTRL = 0x0; +// +// /* Enable Clock */ +// __HAL_RCC_AESSPI1_CLK_ENABLE(); +// + +// for(i = 0; i < block_len; i++) +// { +// printf("cnt = 0x%08x %08x %08x %08x\n",cnt[0],cnt[1],cnt[2],cnt[3]); +// aes_func(cnt, ctr_o, AES_ECB_MODE); +// printf("ctr_o = 0x%08x %08x %08x %08x\n",ctr_o[0],ctr_o[1],ctr_o[2],ctr_o[3]); +// printf("indata = 0x%08x %08x %08x %08x\n\n",indata[0],indata[1],indata[2],indata[3]); + +// outdata[0] = ctr_o[0] ^ indata[0]; +// outdata[1] = ctr_o[1] ^ indata[1]; +// outdata[2] = ctr_o[2] ^ indata[2]; +// outdata[3] = ctr_o[3] ^ indata[3]; +// printf("outdata = 0x%08x %08x %08x %08x\n\n",outdata[0],outdata[1],outdata[2],outdata[3]); +// +// indata += 4; +// outdata += 4; +// cnt[3]++; +// if(cnt[3] == 0x00000000) +// cnt[2]++; +// } +// +// disable_module(BIT_AES); +// +// return AES_PASS; +//} + +/****************************************************************************** + + * Name: aes_set_key + * Function: aes_set_key + * Input: + keyin -- pointer to buffer of key + key_len -- select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) + swap_en -- AES_SWAP_ENABLE, AES_SWAP_DISABLE + * Return: None +*******************************************************************************/ +void HAL_AES_SetKey_CTR(uint32_t *keyin, uint8_t key_len, uint32_t *iv, uint8_t swap_en) +{ + /* Enable Clock */ + __HAL_RCC_AES_SPI1_CLK_ENABLE(); + + AES_SPI1->CTRL = (1<<13);// sel high 5 bit +// AES->CTRL = 0x1000; //CTR mode + + if(AES_SPI_SWAP_ENABLE == swap_en) + { + AES_SPI1->CTRL |= 0x10; + } + + if(AES_SPI_KEY_192 == key_len) + { + AES_SPI1->CTRL |= (1 << 6); + } + else if(AES_SPI_KEY_256 == key_len) + { + AES_SPI1->CTRL |= (2 << 6); + } + + //key128 + AES_SPI1->KEYIN = keyin[0]; + AES_SPI1->KEYIN = keyin[1]; + AES_SPI1->KEYIN = keyin[2]; + AES_SPI1->KEYIN = keyin[3]; + + if(AES_SPI_KEY_192 == key_len) + { +// AES->CTRL |= (1 << 6); + AES_SPI1->KEYIN = keyin[4]; + AES_SPI1->KEYIN = keyin[5]; + } + else if(AES_SPI_KEY_256 == key_len) + { +// AES->CTRL |= (2 << 6); + AES_SPI1->KEYIN = keyin[4]; + AES_SPI1->KEYIN = keyin[5]; + AES_SPI1->KEYIN = keyin[6]; + AES_SPI1->KEYIN = keyin[7]; + } + + AES_SPI1->STARTADDR = iv[0]; + AES_SPI1->ENDADDR = iv[1]; + AES_SPI1->INIDATA = iv[2]; + AES_SPI1->ADDR = iv[3]; + +// __HAL_RCC_AESSPI1_CLK_DISABLE(); + +} + +void HAL_AES_SPI_Crypt_CTR( + uint32_t *indata, + uint32_t *outdata, + uint32_t *iv, + uint32_t block_len, + uint8_t auto_en +) +{ + uint32_t i,j; + uint32_t ctr_o[4]; + uint32_t cnt[4]; + + /* Enable Clock */ + __HAL_RCC_AES_SPI1_CLK_ENABLE(); + + AES_SPI1->CTRL &= (~0x04);//encrypt + AES_SPI1->CTRL |= (1<<13);//AES mode + + if(AES_SPI_ADDR_AUTO_ENABLE == auto_en) + { +// AES_SPI->CTRL = 0x1000; //CTR EN, CTR mode +// AES_SPI->CTRL |= 0x4000; + AES_SPI1->CTRL |= (1<<14);//ADDR auto + AES_SPI1->CTRL |= (1<<12);//CTR EN, CTR mode + } + else + { + AES_SPI1->CTRL &= ~0x1000; //clr CTR mode + AES_SPI1->CTRL &= ~(1<<5); //clr CBC mode + AES_SPI1->CTRL &= ~(1<<14);//clr addr_auto + for(i = 0; i < 4; i++) + { + cnt[i] = iv[i]; + } +//printf("222 -- AES->CTRL = 0x%x\n",AES->CTRL); + + } + + AES_SPI1->STARTADDR = iv[0]; + AES_SPI1->ENDADDR = iv[1]; + AES_SPI1->INIDATA = iv[2]; + AES_SPI1->ADDR = iv[3]; + +// i = 0; + for( j = block_len; j > 0; j-- ) + { + if(AES_SPI_ADDR_AUTO_DISABLE == auto_en) + { +// AES->STARTADDR = cnt[0]; +// AES->ENDADDR = cnt[1]; +// AES->INIDATA = cnt[2]; +// AES->ADDR = cnt[3]; +// printf("cnt[3] = 0x%x\n",cnt[3]); + AES_SPI1->DATAIN = cnt[ 0]; + AES_SPI1->DATAIN = cnt[ 1 ]; + AES_SPI1->DATAIN = cnt[ 2 ]; + AES_SPI1->DATAIN = cnt[ 3 ]; + +// printf("cnt[0] = 0x%x\n",cnt[0]); +// printf("cnt[1] = 0x%x\n",cnt[1]); +// printf("cnt[2] = 0x%x\n",cnt[2]); +// printf("cnt[3] = 0x%x\n",cnt[3]); + } + + AES_SPI1->CTRL |= 0x01; + while( (AES_SPI1->STATE & 0x01) == 0); + AES_SPI1->STATE = 0x01; + + ctr_o[0] = AES_SPI1->DATAOUT; + ctr_o[1] = AES_SPI1->DATAOUT; + ctr_o[2] = AES_SPI1->DATAOUT; + ctr_o[3] = AES_SPI1->DATAOUT; + +// printf("ctr_o[0] = 0x%x\n",ctr_o[0]); +// printf("ctr_o[1] = 0x%x\n",ctr_o[1]); +// printf("ctr_o[2] = 0x%x\n",ctr_o[2]); +// printf("ctr_o[3] = 0x%x\n",ctr_o[3]); +// printf("\n"); +// +// printf("indata[0] = 0x%x\n",indata[0]); +// printf("indata[1] = 0x%x\n",indata[1]); +// printf("indata[2] = 0x%x\n",indata[2]); +// printf("indata[3] = 0x%x\n",indata[3]); +// printf("\n"); + + outdata[0] = ctr_o[0] ^ indata[0]; + outdata[1] = ctr_o[1] ^ indata[1]; + outdata[2] = ctr_o[2] ^ indata[2]; + outdata[3] = ctr_o[3] ^ indata[3]; + +// printf("outdata[0] = 0x%x\n",outdata[0]); +// printf("outdata[1] = 0x%x\n",outdata[1]); +// printf("outdata[2] = 0x%x\n",outdata[2]); +// printf("outdata[3] = 0x%x\n",outdata[3]); +// printf("\n"); + + indata += 4; + outdata += 4; + + if(AES_SPI_ADDR_AUTO_DISABLE == auto_en) + { + cnt[3] += 0x10; +// cnt[3] += 0x1; + } + + } + + __HAL_RCC_AES_SPI1_CLK_DISABLE(); +} + +//otfdec_en : 1: select PUF + RANDOM 3: UID+RANDOM +//write only once after sysreset +void otfdec_en(uint8_t otfdec_en, uint8_t spi_sel) +{ + AES_SPI1->OTFDEC_CTRL = otfdec_en; + AES_SPI1->OTFDEC_SPI_CTRL = spi_sel; + +// printf("spi_sel = 0x%x\n", spi_sel); +// printf("AES_SPI1->OTFDEC_CTRL = 0x%x\n", AES_SPI1->OTFDEC_SPI_CTRL); + +} + +void otfdec_encrypt1(uint32_t *datain, uint32_t start_addr, uint32_t length,uint32_t *dataout) +{ + uint32_t i; + uint32_t ctr_o[4]; + uint32_t addr; + uint8_t otfdec_en; + + + otfdec_en = AES_SPI1->OTFDEC_CTRL; +// AES_SPI1->ENDADDR = MEM_ADDR + FIRST_SIZE -1; //32k + + if(otfdec_en) + { + AES_SPI1->CTRL = 0x8000;//encrypt + + addr = start_addr; + AES_SPI1->ADDR = addr; + for( i = length; i > 0; i-- ) + { + AES_SPI1->ADDR1 = addr; + addr += 16; + AES_SPI1->CTRL |= 0x01; + while( (AES_SPI1->STATE & 0x01) == 0); + AES_SPI1->STATE = 0x01; + + ctr_o[3] = AES_SPI1->DATAOUT1; + ctr_o[2] = AES_SPI1->DATAOUT1; + ctr_o[1] = AES_SPI1->DATAOUT1; + ctr_o[0] = AES_SPI1->DATAOUT1; + + dataout[0] = ctr_o[0] ^ datain[0]; + dataout[1] = ctr_o[1] ^ datain[1]; + dataout[2] = ctr_o[2] ^ datain[2]; + dataout[3] = ctr_o[3] ^ datain[3]; +// if(i==length) +// { +// str_printf("ctr_o[0] is 0x%x!\n",ctr_o[0]); +// str_printf("datain[0] is 0x%x!\n",datain[0]); +// str_printf("dataout[0] is 0x%x!\n",dataout[0]); +// } + datain += 4; + dataout += 4; + + } + } + else + { + for( i = 0; i <(length<<2); i++) + { + dataout[i] = datain[i]; + } + } +} + +void otfdec_encrypt(uint32_t *datain, uint32_t start_addr, uint32_t length,uint32_t *dataout) +{ + uint32_t i; + uint32_t ctr_o[4]; + uint32_t addr; + uint8_t otfdec_en; + + + otfdec_en = AES_SPI1->OTFDEC_CTRL; +// AES_SPI1->ENDADDR2 = MEM_ADDR + SECOND_SIZE -1; //128k + + if(otfdec_en) + { + AES_SPI1->CTRL = 0x000;//encrypt + + addr = start_addr; + + for( i = length; i > 0; i-- ) + { + AES_SPI1->ADDR = addr; + addr += 16; + AES_SPI1->CTRL |= 0x01; + while( (AES_SPI1->STATE & 0x01) == 0); + AES_SPI1->STATE = 0x01; + + ctr_o[0] = AES_SPI1->DATAOUT; + ctr_o[1] = AES_SPI1->DATAOUT; + ctr_o[2] = AES_SPI1->DATAOUT; + ctr_o[3] = AES_SPI1->DATAOUT; + + dataout[0] = ctr_o[0] ^ datain[0]; + dataout[1] = ctr_o[1] ^ datain[1]; + dataout[2] = ctr_o[2] ^ datain[2]; + dataout[3] = ctr_o[3] ^ datain[3]; +// if(i==length) +// { +// str_printf("ctr_o[0] is 0x%x!\n",ctr_o[0]); +// str_printf("datain[0] is 0x%x!\n",datain[0]); +// str_printf("dataout[0] is 0x%x!\n",dataout[0]); +// } + datain += 4; + dataout += 4; + + } + } + else + { + for( i = 0; i <(length<<2); i++) + { + dataout[i] = datain[i]; + } + } +} + + +//write only once after sysreset +void otfdec_uid_set_key(uint32_t *uid, uint32_t *random) +{ + AES_SPI1->UID = uid[0]; + AES_SPI1->UID = uid[1]; + AES_SPI1->UID = uid[2]; + AES_SPI1->UID = uid[3]; + + AES_SPI1->RAND0 = random[0]; + AES_SPI1->RAND1 = random[1]; + AES_SPI1->ENDADDR = MEM_ADDR + FIRST_SIZE -1; //32k +} + +void otfdec_uid_set_key2(uint32_t *key2, uint32_t *random) +{ + AES_SPI1->KEYIN2 = key2[0]; + AES_SPI1->KEYIN2 = key2[1]; + AES_SPI1->KEYIN2 = key2[2]; + AES_SPI1->KEYIN2 = key2[3]; + + AES_SPI1->RAND2 = random[0]; + AES_SPI1->RAND3 = random[1]; + + AES_SPI1->ENDADDR2 = MEM_ADDR + SECOND_SIZE -1; //128k +} + +void otfdec_uid_set_key3(uint32_t *key3) +{ + AES_SPI1->KEYIN3 = key3[0]; + AES_SPI1->KEYIN3 = key3[1]; + AES_SPI1->KEYIN3 = key3[2]; + AES_SPI1->KEYIN3 = key3[3]; +} + +void otfdec_update_random23(uint32_t *random) +{ + uint32_t temp; + AES_SPI1->OTFDEC_SPI_CTRL |= 0x20; + temp = AES_SPI1->OTFDEC_SPI_CTRL; + random[0] = AES_SPI1->RAND2; + random[1] = AES_SPI1->RAND3; +} + + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cde.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cde.c new file mode 100644 index 0000000000000000000000000000000000000000..28f046ea2e0bd6403b674665a512e4cb33e58c98 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cde.c @@ -0,0 +1,38 @@ +/****************************************************************************** +*@file : hal_cde.c +*@brief : cde module file +*@ver : 1.0.0 +*@date : 2023.2.3 +******************************************************************************/ + +//ARMCC command line options: --target=arm-arm-none-eabi -mcpu=cortex-m33+cdecpN +//for example: --target=arm-arm-none-eabi -mcpu=cortex-m33+cdecp0 + +//fromelf command line option: --coprocN=CDE +//for example: fromelf.exe --bin -c --cpu=8.1-M.Main.mve.fp --coproc0=CDE --output ./Objects/Project.bin ./Objects/Project.axf +//for example: fromelf.exe --bin -c --cpu=cortex-m33 --coproc0=CDE --output ./Objects/Project.bin ./Objects/Project.axf + + +#include "hal.h" + +/****************************************************************************** +*@brief : enable coopration processor number +*@param : num : coopration processor number +*@return: none +******************************************************************************/ +void HAL_CDE_EnableCPx(int num) +{ + SCB->CPACR |= (3UL << num*2); //0xE000ED88 + HAL_SimpleDelay(10); +} + +/****************************************************************************** +*@brief : enable coopration processor number +*@param : num : coopration processor number +*@return: none +******************************************************************************/ +void HAL_CDE_DisableCPx(int num) +{ + SCB->CPACR &= ~(3UL << num*2); //0xE000ED88 + HAL_SimpleDelay(10); +} diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_comp.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_comp.c new file mode 100644 index 0000000000000000000000000000000000000000..98eea88ce491cc6e9f22839afa415116b996f3c4 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_comp.c @@ -0,0 +1,269 @@ + +/****************************************************************************** +*@file : hal_comp.c +*@brief : COMP HAL module driver. +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_COMP_MODULE_ENABLED + +/****************************************************************************** +*@brief : COMP MSP Initialization.such as module clock, IO share, ... +* COMP1 VinP: PB0, PB2 +* COMP1 VinM: DAC1,PB1,PC4,VREF_AVDD +* COMP1 Vout: PA11(AF5), PB8(AF1), PC5(AF14), PE12(AF15), PF4(AF5) +*@param : hcomp: COMP handle +*@return: None +******************************************************************************/ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) +{ + //Prevent unused argument(s) compilation warning + UNUSED(hcomp); + + //NOTE : This function should not be modified. + //when the callback is needed,the HAL_COMP_MspInit could be implemented in the user file +} + +/****************************************************************************** +*@brief : COMP MSP De-Initialization. +*@param : hcomp: COMP handle +*@return: None +******************************************************************************/ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp) +{ + //Prevent unused argument(s) compilation warning + UNUSED(hcomp); + + //NOTE : This function should not be modified. + //when the callback is needed,the HAL_COMP_MspDeInit could be implemented in the user file +} + +/****************************************************************************** +*@brief : Initialize the COMP. +*@note : If the selected comparator is locked, initialization can't be performed. +* To unlock the configuration, perform a module reset. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp) +{ + uint32_t tempReg; + + if(hcomp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_COMP_INSTANCE(hcomp->Instance)); + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_COMP_MspInit(hcomp); + + //check lock status + if(hcomp->Instance->CR & COMP_CR_LOCK) + { + return HAL_ERROR; + } + + tempReg = 0; + + assert_param(IS_COMP_POLARITY(hcomp->Init.Polarity)); + assert_param(IS_COMP_BLANKSEL(hcomp->Init.BlankSel)); + assert_param(IS_COMP_HYS(hcomp->Init.HYS)); + tempReg |= ((hcomp->Init.Polarity & COMP_CR_POLARITY_Msk) | \ + (hcomp->Init.BlankSel & COMP_CR_BLANKSEL_Msk) | \ + (hcomp->Init.HYS & COMP_CR_HYS_Msk)); + + assert_param(IS_COMP_INPSEL(hcomp->Init.InPSel)); + tempReg |= hcomp->Init.InPSel & COMP_CR_INPSEL_Msk; + + assert_param(IS_COMP_INMSEL(hcomp->Init.InMSel)); + tempReg |= hcomp->Init.InMSel & COMP_CR_INMSEL_Msk; + + + if(hcomp->Init.InMSel == COMP_INMSEL_VREF_AVDD) + { + assert_param(IS_COMP_CRVSEL(hcomp->Init.CrvSel)); + assert_param(IS_COMP_CRVEN(hcomp->Init.CrvEn)); + tempReg |= ((hcomp->Init.CrvSel & COMP_CR_CRV_SEL_Msk) | \ + (hcomp->Init.CrvEn & COMP_CR_CRV_EN_Msk)); + + if(hcomp->Init.CrvEn == COMP_CRV_ENABLE) + { + assert_param(IS_COMP_CRVCFG(hcomp->Init.CrvCfg)); + tempReg |= hcomp->Init.CrvCfg << COMP_CR_CRV_CFG_Pos; + } + } + + assert_param(IS_COMP_FLTEN(hcomp->Init.FltEn)); + tempReg |= hcomp->Init.FltEn & COMP_CR_FLTEN_Msk; + if(hcomp->Init.FltEn == COMP_FLT_ENABLE) + { + assert_param(IS_COMP_FLTTIME(hcomp->Init.FltTime)); + tempReg |= hcomp->Init.FltTime & COMP_CR_FLTTIME_Msk; + } + + CLEAR_BIT(hcomp->Instance->CR, COMP_CR_EN); //disable + + //Write the COMP_CR register + WRITE_REG(hcomp->Instance->CR,tempReg); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : de-Initialize the COMP. +*@note : If the selected comparator is locked, de-initialization can't be performed. +* To unlock the configuration, perform a module reset. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp) +{ + if(hcomp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_COMP_INSTANCE(hcomp->Instance)); + + //check lock status + if(hcomp->Instance->CR & COMP_CR_LOCK) + { + return HAL_ERROR; + } + + /* Set COMP_CSR register to reset value */ + WRITE_REG(hcomp->Instance->CR, 0x00000000UL); + + HAL_COMP_MspDeInit(hcomp); + + memset(&hcomp->Init, 0, sizeof(hcomp->Init)); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Enable comparator. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp) +{ + if(hcomp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_COMP_INSTANCE(hcomp->Instance)); + + //check lock status + if(hcomp->Instance->CR & COMP_CR_LOCK) + { + return HAL_ERROR; + } + + SET_BIT(hcomp->Instance->CR, COMP_CR_EN); //enable + + return HAL_OK; +} + +/****************************************************************************** +*@brief : disable comparator. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp) +{ + if(hcomp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_COMP_INSTANCE(hcomp->Instance)); + + //check lock status + if(hcomp->Instance->CR & COMP_CR_LOCK) + { + return HAL_ERROR; + } + + CLEAR_BIT(hcomp->Instance->CR, COMP_CR_EN); //disable + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Get the output level of the comparator. the value is stored in hcomp. +*@param : hcomp: COMP handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp) +{ + if(hcomp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_COMP_INSTANCE(hcomp->Instance)); + + hcomp->OutputLevelOrg = (hcomp->Instance->SR & COMP_SR_VCOUT1_ORG) ? 1 : 0; + hcomp->OutputLevel = (hcomp->Instance->SR & COMP_SR_VCOUT1) ? 1 : 0; + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : start comparator. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + return(HAL_COMP_Enable(hcomp)); +} + + +/****************************************************************************** +*@brief : stop comparator. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + return(HAL_COMP_Disable(hcomp)); +} + + +/****************************************************************************** +*@brief : lock comparator. +*@param : hcomp: COMP handle +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp) +{ + __IO uint32_t *pCRx; + + if(hcomp == NULL) + { + return HAL_ERROR; + } + + assert_param(IS_COMP_INSTANCE(hcomp->Instance)); + + //check lock status + if(hcomp->Instance->CR & COMP_CR_LOCK) + { + return HAL_OK; + } + + SET_BIT(hcomp->Instance->CR, COMP_CR_LOCK); //lock + + return HAL_OK; +} + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cordic_20231027.lib b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cordic_20231027.lib new file mode 100644 index 0000000000000000000000000000000000000000..38f3b1c48319fbd7e4e314088b4b530da0898d50 Binary files /dev/null and b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cordic_20231027.lib differ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cortex.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cortex.c new file mode 100644 index 0000000000000000000000000000000000000000..8a2e069bba155fee7f0f9a04f91c1b352f164e64 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_cortex.c @@ -0,0 +1,478 @@ +/****************************************************************************** +*@file : hal_cortex.c +*@brief : CORTEX HAL module driver +******************************************************************************/ + + +#include "hal.h" + +#if (__MPU_PRESENT == 1) +static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionInit); +static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit); +#endif /* __MPU_PRESENT */ + +/****************************************************************************** +*@brief : Sets the priority grouping field (preemption priority and subpriority) using the required unlock sequence. +*@param : PriorityGroup: The priority grouping bits length. +* This parameter can be one of the following values: +* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority, 4 bits for subpriority +* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority, 3 bits for subpriority +* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority +* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bits for subpriority +* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bits for subpriority +*@note : When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. +* The pending IRQ priority will be managed only by the subpriority. +*@ret : none +******************************************************************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/****************************************************************************** +*@brief : Sets the priority of an interrupt. +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@param : PreemptPriority: The preemption priority for the IRQn channel. +* This parameter can be a value between 0 and 15. +* A lower priority value indicates a higher priority +*@param : SubPriority: he subpriority level for the IRQ channel. +* This parameter can be a value between 0 and 15. +* A lower priority value indicates a higher priority. +*@ret : None +******************************************************************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00U; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/****************************************************************************** +*@brief : Enables a device specific interrupt in the NVIC interrupt controller. +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@ret : None +******************************************************************************/ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/****************************************************************************** +*@brief : Disables a device specific interrupt in the NVIC interrupt controller. +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@ret : None +******************************************************************************/ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + + +/****************************************************************************** +*@brief : Initiates a system reset request to reset the MCU. +*@ret : None +******************************************************************************/ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/****************************************************************************** +*@brief : Initializes the System Timer and its interrupt, and starts the System Tick Timer. +* Counter is in free running mode to generate periodic interrupts. +*@param : TicksNum: Specifies the ticks Number of ticks between two interrupts. +*@ret : None +******************************************************************************/ +HAL_StatusTypeDef HAL_SYSTICK_Config(uint32_t TicksNum) +{ + if(SysTick_Config(TicksNum)==0) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if (__MPU_PRESENT == 1U) + +/****************************************************************************** +*@brief : Enable the MPU. +*@param : MPU_Control: Specifies the control mode of the MPU during hard fault, +* NMI, FAULTMASK and privileged access to the default memory +* This parameter can be one of the following values: +* @arg MPU_HFNMI_PRIVDEF_NONE +* @arg MPU_HARDFAULT_NMI +* @arg MPU_PRIVILEGED_DEFAULT +* @arg MPU_HFNMI_PRIVDEF +*@ret : None +******************************************************************************/ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/****************************************************************************** +*@brief : Disables the MPU. +*@ret : None +******************************************************************************/ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + + +/****************************************************************************** +*@brief : Initializes and configures the Region and the memory to be protected. +*@param : MPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains +* the initialization and configuration information. +*@ret : None +******************************************************************************/ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit) +{ + MPU_ConfigRegion(MPU, MPU_RegionInit); +} + +/****************************************************************************** +*@brief : Initialize and configure the memory attributes. +*@param : MPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains +* the initialization and configuration information. +*@ret : None +******************************************************************************/ +void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU, MPU_AttributesInit); +} + +static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionInit) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable)); + + /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ + __DMB(); + + /* Set the Region number */ + MPUx->RNR = MPU_RegionInit->Number; + + if (MPU_RegionInit->Enable != MPU_REGION_DISABLE) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable)); + + MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); + } + else + { + MPUx->RBAR = 0U; + MPUx->RLAR = 0U; + } +} + +static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + __IO uint32_t *mair; + uint32_t attr_values; + uint32_t attr_number; + + /* Check the parameters */ + assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_AttributesInit->Number)); + /* No need to check Attributes value as all 0x0..0xFF possible */ + + /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */ + __DMB(); + + if(MPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + mair = &(MPUx->MAIR0); + attr_number = MPU_AttributesInit->Number; + } + else + { + /* Program MPU_MAIR1 */ + mair = &(MPUx->MAIR1); + attr_number = (uint32_t)MPU_AttributesInit->Number - 4U; + } + + attr_values = *(mair); + attr_values &= ~(0xFFU << (attr_number * 8U)); + *(mair) = attr_values | ((uint32_t)MPU_AttributesInit->Attributes << (attr_number * 8U)); +} + + +// default mpu attrs +const uint8_t MPU_attrs[8] = +{ + MPU_ATTR_NO_CACHE, + MPU_ATTR_WRITE_THROUGH, + MPU_ATTR_WRITE_BACK, + MPU_ATTR_DEVICE, + 0, + 0, + 0, + 0 +}; + +/****************************************************************************** +*@brief : MPU config. +*@param : MPU_configInit: mpu config init parameter +*@return: void +******************************************************************************/ +void HAL_MPU_Config(MPU_ConfigInitTypeDef *MPU_configInit) +{ + uint32_t i,j,count,attrIndex; + uint32_t ctrl; + MPU_RegionConfigTypeDef *pRegion; + + HAL_MPU_Disable(); + + __DMB(); + + //Config Memory Attributes + MPU->MAIR0 = MPU_attrs[0] | (MPU_attrs[1]<<8) | (MPU_attrs[2]<<16) | (MPU_attrs[3]<<24); + MPU->MAIR1 = MPU_attrs[4] | (MPU_attrs[5]<<8) | (MPU_attrs[6]<<16) | (MPU_attrs[7]<<24); + + count = MPU_configInit->RegionCount; + if(count>8) + { + count = 8; + } + + for(i=0; iRegionConfigs + i; + + //get index by attribute + attrIndex = 0; //default attr index + for(j=0;j<8;j++) + { + if(MPU_attrs[j] == pRegion->Attr) + { + attrIndex = j; + break; + } + } + + //config region + MPU->RNR = i; + + MPU->RBAR = ((pRegion->BaseAddr & MPU_RBAR_BASE_Msk) | + ((pRegion->Access<Execute<RLAR = ((pRegion->LimitAddr & MPU_RLAR_LIMIT_Msk) | + ((attrIndex<RNR = i; + MPU->RBAR = 0; + MPU->RLAR = 0; + } + + + ctrl = (((MPU_configInit->PrivDef<HfNmi<AIRCR [10:8] PRIGROUP field) +******************************************************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/****************************************************************************** +*@brief : Gets the priority of an interrupt. +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@param : PriorityGroup: The priority grouping bits length. +* This parameter can be one of the following values: +* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority, 4 bits for subpriority +* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority, 3 bits for subpriority +* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 2 bits for subpriority +* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 1 bits for subpriority +* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 0 bits for subpriority +*@param : pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). +*@param : pSubPriority: Pointer on the Subpriority value (starting from 0). +*@ret : None +******************************************************************************/ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/****************************************************************************** +*@brief : Sets Pending bit of an external interrupt. +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@ret : None +******************************************************************************/ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/****************************************************************************** +*@brief : Gets Pending Interrupt (reads the pending register in the NVIC +* and returns the pending bit for the specified interrupt). +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@ret : status: - 0 Interrupt status is not pending. +* - 1 Interrupt status is pending. +******************************************************************************/ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/****************************************************************************** +*@brief : Clears the pending bit of an external interrupt. +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@ret : None +******************************************************************************/ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/****************************************************************************** +*@brief : Gets active interrupt ( reads the active register in NVIC and returns the active bit). +*@param : IRQn: External interrupt number. +* This parameter can be an enumerator of IRQn_Type enumeration +*@ret : status: - 0 Interrupt status is not pending. +* - 1 Interrupt status is pending. +******************************************************************************/ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/****************************************************************************** +*@brief : Configures the SysTick clock source. +*@param : CLKSource specifies the SysTick clock source. +* This parameter can be one of the following values: +* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. +* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. +*@ret : None +******************************************************************************/ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + + +/****************************************************************************** +*@brief : This function handles SYSTICK interrupt request. +*@ret : None +******************************************************************************/ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/****************************************************************************** +*@brief : SYSTICK callback. +*@ret : None +******************************************************************************/ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_crc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..17c3f2f215b13a8db0b5f790ec2009266428f6cc --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_crc.c @@ -0,0 +1,83 @@ +/* + ****************************************************************************** + * @file HAL_Crc.c + * @author AisinoChip Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 AisinoChip. + * All rights reserved. + ****************************************************************************** +*/ +#include "hal.h" + +#ifdef HAL_CRC_ENABLED + +/****************************************************************************** +*@brief : Initialize NFM +*@param : hnfm: pointer to the NFM handle +*@return: None +******************************************************************************/ +void HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + __HAL_RCC_CRC_CLK_ENABLE(); + hcrc->Instance->CTRL = hcrc->Init.PolyRev | hcrc->Init.OutxorRev | hcrc->Init.InitRev | hcrc->Init.RsltRev | + hcrc->Init.DataRev | hcrc->Init.PolyLen | hcrc->Init.DataLen; + + hcrc->Instance->INIT = hcrc->Init.InitData; + hcrc->Instance->OUTXOR = hcrc->Init.OutXorData; + hcrc->Instance->POLY = hcrc->Init.PolyData; +} + +/****************************************************************************** +*@brief : Calculate the crc calue of input data +*@param : hcrc: pointer to the CRC handle +*@return: CRC value +******************************************************************************/ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc) +{ + int crc_cnt; + __HAL_RCC_CRC_CLK_ENABLE(); + + if(CRC_DATA_LEN_2B == hcrc->Init.DataLen) + { + crc_cnt = hcrc->CRC_Data_Len>>1; + while(crc_cnt--) + { + hcrc->Instance->DATA = *((uint16_t*)hcrc->CRC_Data_Buff); + hcrc->CRC_Data_Buff +=2; + } + } + else if(CRC_DATA_LEN_4B == hcrc->Init.DataLen) + { + crc_cnt = hcrc->CRC_Data_Len>>2; + while(crc_cnt--) + { + hcrc->Instance->DATA = *((uint32_t*)hcrc->CRC_Data_Buff); + hcrc->CRC_Data_Buff +=4; + } + } + else + { + crc_cnt = hcrc->CRC_Data_Len; + while(crc_cnt--) + { + hcrc->Instance->DATA = *((uint8_t*)hcrc->CRC_Data_Buff++); + } + } + __HAL_RCC_CRC_CLK_DISABLE(); + return (hcrc->Instance->DATA); + +} + +#endif + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dac.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..fb10a1ae98150da50afa717bc71e7750258376fe --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dac.c @@ -0,0 +1,944 @@ +/****************************************************************************** +* @file : hal_dac.c +* @version : 1.0 +* @date : 2022.10.29 +* @brief : DAC HAL module driver +******************************************************************************/ +#include "hal_dac.h" + +#ifdef HAL_DAC_MODULE_ENABLED +/****************************************************************************** +* @brief : This function uses the interruption of DMA underrun. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @return: none +******************************************************************************/ +__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) +{ + if((hdac->Instance->SR & DAC_SR_DMAUDR1) == DAC_SR_DMAUDR1 + || (hdac->Instance->SR & DAC_SR_DMAUDR2) == DAC_SR_DMAUDR2) + { +// printfS("DMA underrun happened\r\n"); + //clear the DMA underrun + hdac->Instance->SR |= DAC_SR_DMAUDR1 | DAC_SR_DMAUDR2; + } +} + +/****************************************************************************** +* @brief : Initialize the DAC MSP. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @return: none +******************************************************************************/ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_MspInit can be implemented in the user file + */ + UNUSED(hdac); +} + +/****************************************************************************** +* @brief : DAC MSP De-Initialization. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @return: none +******************************************************************************/ +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +{ + /* + NOTE : This function should be modified by the user. + the HAL_DAC_MspDeInit can be implemented in the user file. + */ + UNUSED(hdac); + +} + +/****************************************************************************** +* @brief : Initializes the CAN peripheral according to the specified parameters in the DAC_HandleTypeDef. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + + HAL_DAC_MspInit(hdac); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Deinitialize the DAC peripheral registers to their default reset values. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + + HAL_DAC_MspDeInit(hdac); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Configures the selected DAC channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : sConfig : DAC configuration structure +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +{ + uint32_t tmpreg1, tmpreg2; + uint32_t tickstart = 0U; + uint32_t ConnectOnChipPeripheral=0U; + uint32_t connectOnChip; + /* Check the DAC parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_TRIGGER(sConfig->SawtoothStepTrigger)); + + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); + if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) + { + assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); + } + assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); + + if(sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) + { + /* output buffer on */ + assert_param(IS_DAC_CHIP_CONNECTION_BUFON(sConfig->DAC_ConnectOnChipPeripheral)); + } + else + { + /* output buffer off */ + if((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) + { + /* Sample and hold mode */ + assert_param(IS_DAC_CHIP_CONNECTION_SHMODE_BUFOFF(sConfig->DAC_ConnectOnChipPeripheral)); + + assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); + assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); + assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); + } + else + { + /* Normal mode */ + assert_param(IS_DAC_CHIP_CONNECTION_NORMALMODE_BUFOFF(sConfig->DAC_ConnectOnChipPeripheral)); + } + } + + + assert_param(IS_DAC_CHANNEL(Channel)); + + /* ## sample, hold, refresh ---------------------------------------------------------- */ + if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) + /* Sample on old configuration */ + { + /* SampleTime */ + if (Channel == DAC_CHANNEL_1) + { + hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; + } + else /* Channel 2 */ + { + hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; + } + + /* HoldTime */ + MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); + /* RefreshTime */ + MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); + } + + /* ## CCR---------------------------------------------------------------------------- */ + if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) + /* USER TRIMMING */ + { + /* Get the DAC CCR value */ + tmpreg1 = hdac->Instance->CCR; + /* Clear trimming value */ + tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); + /* Configure for the selected trimming offset */ + tmpreg2 = sConfig->DAC_TrimmingValue; + /* Calculate CCR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CCR */ + hdac->Instance->CCR = tmpreg1; + } + else + { + /* factory trimming in NVR,read to DAC_CCR */ + uint8_t trim_val; + HAL_StatusTypeDef ret; + if(hdac->Instance == DAC1) + ret = HAL_EFUSE_ReadByte(EFUSE1, 0x76 + (Channel >> 4), &trim_val, 100000); + else + ret = HAL_EFUSE_ReadByte(EFUSE1, 0x78 + (Channel >> 4), &trim_val, 100000); + + if(ret == HAL_OK) + MODIFY_REG(hdac->Instance->CCR, DAC_CCR_OTRIM1 << (Channel & 0x10UL), trim_val << (Channel & 0x10UL)); + } + + /* ## MCR---------------------------------------------------------------------------- */ + /* Get the DAC MCR value */ + tmpreg1 = hdac->Instance->MCR; + /* Clear DAC_MCR_MODEx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ + + if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) + { + connectOnChip = 0x00000000UL; + } + else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) + { + connectOnChip = DAC_MCR_MODE1_0; + } + else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ + { + if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) + { + if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) + { + connectOnChip = DAC_MCR_MODE1_0; + } + else + { + connectOnChip = 0x00000000UL; + } + } + else + { + connectOnChip = DAC_MCR_MODE1_0; + } + } + + tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); + /* Clear DAC_MCR_DMADOUBLEx */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: DMA double data mode */ + tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL; + /* Clear DAC_MCR_SINFORMATx */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: Signed format */ + tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL; + + /* Calculate MCR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC MCR */ + hdac->Instance->MCR = tmpreg1; + + /* ## CR ---------------------------------------------------------------------------- */ + /* DAC in normal operating mode hence clear DAC Calibraion bit DAC_CR_CENx */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); + + /* Get the DAC CR value */ + tmpreg1 = hdac->Instance->CR; + /* Clear TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + tmpreg2 = sConfig->DAC_Trigger; + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CR */ + hdac->Instance->CR = tmpreg1; + + /* Disable wave generation */ + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + + /* ## STMODR---------------------------------------------------------------------------- */ + + /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to SawtoothResetTrigger & SawtoothStepTrigger values */ + tmpreg2 = ((sConfig->SawtoothResetTrigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; + tmpreg2 |= ((sConfig->SawtoothStepTrigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos; + + /* Modify STMODR register value depending on DAC_Channel */ + MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1) << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL)); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : Enables DAC and starts conversion of channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + uint32_t tmp1 = 0U, tmp2 = 0U; + + if (Channel == DAC_CHANNEL_1) + { + hdac->Instance->CR|=DAC_CR_EN1; + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR|=DAC_SWTRIGR_SWTRIG1; + } + } + else + { + hdac->Instance->CR|=DAC_CR_EN2; + tmp1 = hdac->Instance->CR & DAC_CR_TEN2; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) + { + /* Enable the selected DAC software conversion */ + hdac->Instance->SWTRIGR|=DAC_SWTRIGR_SWTRIG2; + } + } + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : Disables DAC and stop conversion of channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + if (Channel == DAC_CHANNEL_1) + { + hdac->Instance->CR &= ~DAC_CR_EN1; + } + else + { + hdac->Instance->CR &= ~DAC_CR_EN2; + } + + /* Return function status */ + return HAL_OK; +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +* @brief : Enables DAC and starts conversion of channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @param : pData: The destination peripheral Buffer address. +* @param : Length: The length of data to be transferred from memory to DAC peripheral +* @param : Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values: +* @arg DAC_ALIGN_8B_R @arg DAC_ALIGN_12B_L @arg DAC_ALIGN_12B_R +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) +{ + HAL_StatusTypeDef status; + uint32_t DstAddr = 0U; + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + if (Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + /* Enable the selected DAC channel2 DMA request */ + hdac->Instance->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1 | DAC_CR_DMAUDIE1; + /* Case of use of channel 1 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, DstAddr, Length); + } + else if(Channel == DAC_CHANNEL_2) + { + /* Enable the DAC DMA underrun interrupt */ + /* Enable the selected DAC channel2 DMA request */ + hdac->Instance->CR |= DAC_CR_EN2 | DAC_CR_DMAEN2 | DAC_CR_DMAUDIE2; + + /* Case of use of channel 1 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, DstAddr, Length); + } + else/* DualChannel */ + { + hdac->Instance->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1 | DAC_CR_DMAUDIE1 | DAC_CR_EN2 ; + /* Case of use of channel_1 DMA change two DAC channel */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12RD; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR12LD; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + DstAddr = (uint32_t)&hdac->Instance->DHR8RD; + break; + default: + break; + } + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, DstAddr, Length); + } + /* Return function status */ + return status; +} + + +/****************************************************************************** +* @brief : Disables DAC and stop conversion of channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + /* Disable the DMA Channel */ + /* Channel1 is used */ + if(Channel == DAC_CHANNEL_1) + { + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + /* Disable the Peripheral */ + hdac->Instance->CR&=~DAC_CR_EN1; + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + + else if(Channel == DAC_CHANNEL_2) /* Channel2 is used for */ + { + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + hdac->Instance->CR&=~DAC_CR_EN2; + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + else + { + hdac->Instance->CR &= ~DAC_CR_DMAEN1; + hdac->Instance->CR &= ~DAC_CR_DMAEN2; + /* Disable the Peripheral */ + hdac->Instance->CR&=~DAC_CR_EN1; + hdac->Instance->CR&=~DAC_CR_EN2; + status = HAL_DMA_Abort(hdac->DMA_Handle1) | HAL_DMA_Abort(hdac->DMA_Handle2); + } + + /* Return function status */ + return status; +} +#endif + +/****************************************************************************** +* @brief : Set the specified data holding register value for DAC channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @param : Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values: +* @arg DAC_ALIGN_8B_R @arg DAC_ALIGN_12B_L @arg DAC_ALIGN_12B_R +* @param : Data: The destination peripheral data. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); + } + + /* Calculate and set dual DAC data holding register value */ +// if (Alignment == DAC_ALIGN_12B_L) +// { +// Data = (uint32_t)Data << 4; +// } + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Set the specified data holding register value for dual DAC channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @param : Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values: +* @arg DAC_ALIGN_8B_R @arg DAC_ALIGN_12B_L @arg DAC_ALIGN_12B_R +* @param : Data1: The destination peripheral data1. +* @param : Data2: The destination peripheral data2. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data, tmp; + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + /* DAC Ĵַ */ + tmp = (uint32_t)hdac->Instance; + /* Alignment϶ӦļĴƫƣDAC_DHR12RD DAC_DHR12LD DAC_DHR8RD */ + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : Returns the last data output value of the selected DAC channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : This parameter can be one of the following values: @arg DAC_CHANNEL_1 @argDAC_CHANNEL_2 +* @return: The selected DAC channel data output value +******************************************************************************/ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + if(Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } + +} + +/****************************************************************************** +* @brief : Returns the last data output value of two DAC channels. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @return: The two DAC channels data output value +******************************************************************************/ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + uint32_t tmp = 0U; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16U; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +/****************************************************************************** +* @brief : Enable or disable the selected DAC channel wave generation. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel:The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @param : Amplitude: Amplitude Select max triangle amplitude. This parameter can be one of the following values: +* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 +* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 +* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 +* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 +* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 +* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 +* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 +* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 +* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 +* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 +* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 +* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + /* Enable the triangle wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE_TRIANGLE | Amplitude) << (Channel & 0x10UL)); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : Enable or disable the selected DAC channel wave generation. +* @param : hdac: pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel: The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @param : Amplitude: Amplitude Unmask DAC channel LFSR for noise wave generation. This parameter can be one of the following values: +* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation +* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation +* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + /* Enable the noise wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE_NOISE | Amplitude) << (Channel & 0x10UL)); + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : Run the self calibration of one DAC channel. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : sConfig : sConfig DAC channel configuration structure +* @param : Channel : The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + HAL_StatusTypeDef status = HAL_OK; + + __IO uint32_t tmp; + uint32_t trimmingvalue; + uint32_t laststatus=0; + uint32_t nowstatus=0; + + SET_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); + } + + *(__IO uint32_t *) tmp = 0x0800U; + + /* Enable the selected DAC channel calibration */ + /* i.e. set DAC_CR_CENx bit */ + SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + /* Init trimming counter */ + /* Medium value ,trimmingvalue:0-31(0x1f)*/ + for(trimmingvalue = 0; trimmingvalue < 32; trimmingvalue++) + { + /* Set candidate trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + + HAL_SimpleDelay(50000); + + laststatus=nowstatus; + nowstatus=(hdac->Instance->SR & (DAC_SR_CALFLAG1 << (Channel & 0x10UL)))>>(DAC_SR_CALFLAG1_Pos +Channel); + /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ + /* i.e. minimum time needed between two calibration steps */ + if (nowstatus == 1 && laststatus == 0) + { + break; + } + } + + /* Disable the selected DAC channel calibration */ + /* i.e. clear DAC_CR_CENx bit */ + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + /* Disable the selected DAC channel */ + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); + + sConfig->DAC_TrimmingValue = trimmingvalue; + sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; + + return status; +} + + + +/****************************************************************************** +* @brief : Set the trimming mode and trimming value (user trimming mode applied). +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : sConfig : sConfig DAC channel configuration structure +* @param : Channel : The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @param : NewTrimmingValue: DAC new trimming value +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_Calibration_TRIM(NewTrimmingValue)); + + /* Check the DAC handle allocation */ + if (hdac == NULL) + { + status = HAL_ERROR; + } + else + { + /* Set new trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); + /* Update trimming mode */ + sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; + sConfig->DAC_TrimmingValue = NewTrimmingValue; + } + return status; +} + + + +/****************************************************************************** +* @brief : Return the DAC trimming value. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @return: Trimming value : range: 0->31 +******************************************************************************/ +uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Retrieve trimming */ + return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); +} + +/****************************************************************************** +* @brief : Enables or disables the selected DAC channel Sawtooth wave generation. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @param : Polarity : Sawtooth direction. @arg DAC_SAWTOOTH_POLARITY_DECREMENT, @arg DAC_SAWTOOTH_POLARITY_INCREMENT +* @param : ResetData : Sawtooth reset value +* @param : StepData : Sawtooth increasing/decreasing value +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity, uint32_t ResetData, uint32_t StepData) +{ + /* Check the parameters */ + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity)); + + if (Channel == DAC_CHANNEL_1) + { + /* Configure the sawtooth wave generation data parameters */ + MODIFY_REG(hdac->Instance->STR1, DAC_STR1_STINCDATA1 | DAC_STR1_STDIR1 | DAC_STR1_STRSTDATA1, \ + (StepData << DAC_STR1_STINCDATA1_Pos) | Polarity | (ResetData << DAC_STR1_STRSTDATA1_Pos)); + } + else + { + /* Configure the sawtooth wave generation data parameters */ + MODIFY_REG(hdac->Instance->STR2, DAC_STR2_STINCDATA2 | DAC_STR2_STDIR2 | DAC_STR2_STRSTDATA2, \ + (StepData << DAC_STR2_STINCDATA2_Pos) | Polarity | (ResetData << DAC_STR2_STRSTDATA2_Pos)); + } + + /* Enable the sawtooth wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1) << (Channel & 0x10UL), (uint32_t)(DAC_CR_WAVE_SAWTOOTH) << (Channel & 0x10UL)); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : DAC channel Sawtooth wave Reset by software. +* @param : hdac : pointer to a DAC_HandleTypeDef structure that contains +* the configuration information for DAC module. +* @param : Channel : The selected DAC channel. his parameter can be one of the following values: +* @arg DAC_CHANNEL_1: DAC Channel1 selected +* @arg DAC_CHANNEL_2: DAC Channel2 selected +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataResetBySoftware(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + + if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0U /* SW TRIGGER */) + { + if (Channel == DAC_CHANNEL_1) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + else + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @brief Trig sawtooth wave step + * @note This function allows to generate step in sawtooth wave in case of + * SW trigger has been configured for this usage. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (1) + * + * (1) On this STM32 serie, parameter not available on all instances. + * Refer to device datasheet for channels availability. + * @retval HAL status + */ +/* + úǾݲ +*/ +HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_DAC_INSTANCE(hdac->Instance)); + assert_param(IS_DAC_CHANNEL(Channel)); + + if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0U /* SW TRIGGER */) + { + + if (Channel == DAC_CHANNEL_1) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB1); + } + else + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB2); + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +#endif /* HAL_DAC_MODULE_ENABLED */ \ No newline at end of file diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dcmi.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dcmi.c new file mode 100644 index 0000000000000000000000000000000000000000..18924a3cc2f76def8fcb11ee9acf0a4daf22bc19 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dcmi.c @@ -0,0 +1,863 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dcmi.c + * @author MCD Application Team + * @brief DCMI HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the Digital Camera Interface (DCMI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The sequence below describes how to use this driver to capture image + from a camera module connected to the DCMI Interface. + This sequence does not take into account the configuration of the + camera module, which should be made before to configure and enable + the DCMI to capture images. + + (#) Program the required configuration through following parameters: + horizontal and vertical polarity, pixel clock polarity, Capture Rate, + Synchronization Mode, code of the frame delimiter and data width + using HAL_DCMI_Init() function. + + (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR + register to the destination memory buffer. + + (#) Program the required configuration through following parameters: + DCMI mode, destination memory Buffer address and the data length + and enable capture using HAL_DCMI_Start_DMA() function. + + (#) Optionally, configure and Enable the CROP feature to select a rectangular + window from the received image using HAL_DCMI_ConfigCrop() + and HAL_DCMI_EnableCROP() functions + + (#) The capture can be stopped using HAL_DCMI_Stop() function. + + (#) To control DCMI state you can use the function HAL_DCMI_GetState(). + + *** DCMI HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DCMI HAL driver. + + (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral. + (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral. + (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags. + (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags. + (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts. + (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts. + (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not. + + [..] + (@) You can refer to the DCMI HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hal.h" +static __attribute__ ((aligned (4))) DMA_LinkTypeDef g_dma_node[10]; +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ +/** @defgroup DCMI DCMI + * @brief DCMI HAL module driver + * @{ + */ + +#ifdef HAL_DCMI_MODULE_ENABLED + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define HAL_TIMEOUT_DCMI_STOP 14U /* Set timeout to 1s */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void DCMI_DMAError(DMA_HandleTypeDef *hdma); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DCMI_Exported_Functions DCMI Exported Functions + * @{ + */ + +/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DCMI + (+) De-initialize the DCMI + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the DCMI according to the specified + * parameters in the DCMI_InitTypeDef and create the associated handle. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) +{ + /* Check the DCMI peripheral state */ + if(hdcmi == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); + assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); + assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); + assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); + assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); + assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate)); + assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); + assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); + + if(hdcmi->State == HAL_DCMI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hdcmi->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_DCMI_MspInit(hdcmi); + } + + /* Change the DCMI state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Set DCMI parameters */ + /* Configures the HS, VS, DE and PC polarity */ + hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | + DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | + DCMI_CR_ESS); + hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \ + hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \ + hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \ + hdcmi->Init.JPEGMode); + + if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) + { + hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | + ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)| + ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) | + ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC)); + } + + /* Enable the Line, Vsync, Error and Overrun interrupts */ + __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); + + /* Update error code */ + hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; + + /* Initialize the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Deinitializes the DCMI peripheral registers to their default reset + * values. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) +{ + /* DeInit the low level hardware */ + HAL_DCMI_MspDeInit(hdcmi); + + /* Update error code */ + hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; + + /* Initialize the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdcmi); + + return HAL_OK; +} + +/** + * @brief Initializes the DCMI MSP. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval None + */ +__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMI_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the DCMI MSP. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval None + */ +__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMI_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ +/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure destination address and data length and + Enables DCMI DMA request and enables DCMI capture + (+) Stop the DCMI capture. + (+) Handles DCMI interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables DCMI DMA request and enables DCMI capture + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. + * @param pData The destination memory Buffer address (LCD Frame buffer). + * @param Length The length of capture to be transferred. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) +{ + DMA_LinkInitTypeDef DMA_LinkInit; + + /* Check function parameters */ + assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); + + /* Process Locked */ + __HAL_LOCK(hdcmi); + + /* Lock the DCMI peripheral state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Enable DCMI by setting DCMIEN bit */ + __HAL_DCMI_ENABLE(hdcmi);/*TF.03*/ + + /* Configure the DCMI Mode */ + hdcmi->Instance->CR &= ~(DCMI_CR_CM); + hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode); + + /* Set the DMA memory0 conversion complete callback */ + hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt; + + /* Set the DMA error callback */ + hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; + + /* Set the dma abort callback */ + hdcmi->DMA_Handle->XferAbortCallback = NULL; + + if(Length <= 0xFFFFU) + { + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length); + } + else /* DMA LINK Mode */ + { + + /* Initialize transfer parameters */ + hdcmi->XferCount = 0U; + hdcmi->XferSize = Length; + + /* Get the number of buffer */ + while(hdcmi->XferSize > 0xFFFFU) + { + hdcmi->XferSize = (hdcmi->XferSize >>1); + hdcmi->XferCount+=2; + } + + for (uint8_t j = 0; j < hdcmi->XferCount; j++) + { + if (j == (hdcmi->XferCount - 1)) + { + DMA_LinkInit.TransferSize = hdcmi->XferSize; + DMA_LinkInit.RawInt = DMA_RAWINT_ENABLE; + } + else + { + DMA_LinkInit.RawInt = DMA_RAWINT_DISABLE; + DMA_LinkInit.TransferSize = hdcmi->XferSize; + } + DMA_LinkInit.SrcIncDec = hdcmi->DMA_Handle->Init.SrcIncDec; + DMA_LinkInit.DestIncDec = hdcmi->DMA_Handle->Init.DestIncDec; + DMA_LinkInit.SrcWidth = hdcmi->DMA_Handle->Init.SrcWidth; + DMA_LinkInit.DestWidth = hdcmi->DMA_Handle->Init.DestWidth; + DMA_LinkInit.SrcBurst = hdcmi->DMA_Handle->Init.SrcBurst; + DMA_LinkInit.DestBurst = hdcmi->DMA_Handle->Init.DestBurst; + DMA_LinkInit.NextMaster = DMA_NEXTMASTER_1; + DMA_LinkInit.SrcAddr = (uint32_t)&hdcmi->Instance->DR; + DMA_LinkInit.DestAddr = (uint32_t)pData+hdcmi->XferSize*4*j; + DMA_LinkInit.Next = 0u; + + HAL_DMA_InitLink(&g_dma_node[j], &DMA_LinkInit); + } + for (uint8_t i = 0; i < (hdcmi->XferCount - 1); i++) + { + HAL_DMA_SetLinkNext(&g_dma_node[i], &g_dma_node[i + 1]); + } + + /* DMA */ + HAL_DMA_Start_Link(hdcmi->DMA_Handle, &g_dma_node[0]); + } + + /* Enable Capture */ + hdcmi->Instance->CR |= DCMI_CR_CAPTURE;/*TF.13*/ + + /* Release Lock */ + __HAL_UNLOCK(hdcmi); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disable DCMI DMA request and Disable DCMI capture + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) +{ + __IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP; + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdcmi); + + /* Lock the DCMI peripheral state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Disable Capture */ + hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); + + /* Check if the DCMI capture effectively disabled */ + do + { + if (count-- == 0U) + { + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; + + status = HAL_TIMEOUT; + } + } + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); + + /* Disable the DCMI */ + __HAL_DCMI_DISABLE(hdcmi); + + /* Disable the DMA */ + HAL_DMA_Abort(hdcmi->DMA_Handle); + + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + /* Return function status */ + return status; +} + +/** + * @brief Suspend DCMI capture + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) +{ + __IO uint32_t count = SystemCoreClock / HAL_TIMEOUT_DCMI_STOP; + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdcmi); + + if(hdcmi->State == HAL_DCMI_STATE_BUSY) + { + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_SUSPENDED; + + /* Disable Capture */ + hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); + + /* Check if the DCMI capture effectively disabled */ + do + { + if (count-- == 0U) + { + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_READY; + + status = HAL_TIMEOUT; + break; + } + } + while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); + } + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + /* Return function status */ + return status; +} + +/** + * @brief Resume DCMI capture + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) +{ + /* Process locked */ + __HAL_LOCK(hdcmi); + + if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED) + { + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Disable Capture */ + hdcmi->Instance->CR |= DCMI_CR_CAPTURE; + } + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles DCMI interrupt request. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for the DCMI. + * @retval None + */ + +void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) +{ + uint32_t isr_value = READ_REG(hdcmi->Instance->MIS); + + /* Synchronization error interrupt management *******************************/ + if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI) + { + /* Clear the Synchronization error flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); + + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_ERROR; + /* Set the synchronization error callback */ + hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; + /* Abort the DMA Transfer */ + HAL_DMA_Abort(hdcmi->DMA_Handle); + } + /* Overflow interrupt management ********************************************/ + if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) + { + /* Clear the Overflow flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); + + /* Update error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; + + /* Change DCMI state */ + hdcmi->State = HAL_DCMI_STATE_ERROR; + + /* Set the overflow callback */ + hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; + + /* Abort the DMA Transfer */ + HAL_DMA_Abort(hdcmi->DMA_Handle); + + + + } + /* Line Interrupt management ************************************************/ + if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI) + { + /* Clear the Line interrupt flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); + + /* Line interrupt Callback */ + HAL_DCMI_LineEventCallback(hdcmi); + } + /* VSYNC interrupt management ***********************************************/ + if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI) + { + /* Clear the VSYNC flag */ + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); + + /* VSYNC Callback */ + HAL_DCMI_VsyncEventCallback(hdcmi); + } + /* FRAME interrupt management ***********************************************/ + if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) + { + /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ + if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) + { + /* Disable the Line, Vsync, Error and Overrun interrupts */ + __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); + } + __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); + /* Disable the Frame interrupt */ + __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME); + + /* Frame Callback */ + HAL_DCMI_FrameEventCallback(hdcmi); + } +} + +/** + * @brief Error DCMI callback. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval None + */ +__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval None + */ +__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMI_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief VSYNC Event callback. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval None + */ +__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMI_VsyncEventCallback could be implemented in the user file + */ +} + +/** + * @brief Frame Event callback. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval None + */ +__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdcmi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DCMI_FrameEventCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== +[..] This section provides functions allowing to: + (+) Configure the CROP feature. + (+) Enable/Disable the CROP feature. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DCMI CROP coordinate. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param X0 DCMI window X offset + * @param Y0 DCMI window Y offset + * @param XSize DCMI Pixel per line + * @param YSize DCMI Line number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) +{ + /* Process Locked */ + __HAL_LOCK(hdcmi); + + /* Lock the DCMI peripheral state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_DCMI_WINDOW_COORDINATE(X0)); + assert_param(IS_DCMI_WINDOW_COORDINATE(YSize)); + assert_param(IS_DCMI_WINDOW_COORDINATE(XSize)); + assert_param(IS_DCMI_WINDOW_HEIGHT(Y0)); + + /* Configure CROP */ + hdcmi->Instance->CWSIZE = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE)); + hdcmi->Instance->CWSTRT = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST)); + + /* Initialize the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + return HAL_OK; +} + +/** + * @brief Disable the Crop feature. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) +{ + /* Process Locked */ + __HAL_LOCK(hdcmi); + + /* Lock the DCMI peripheral state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Disable DCMI Crop feature */ + hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP; + + /* Change the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + return HAL_OK; +} + +/** + * @brief Enable the Crop feature. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) +{ + /* Process Locked */ + __HAL_LOCK(hdcmi); + + /* Lock the DCMI peripheral state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Enable DCMI Crop feature */ + hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP; + + /* Change the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DCMI state. + (+) Get the specific DCMI error flag. + +@endverbatim + * @{ + */ + +/** + * @brief Return the DCMI state + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval HAL state + */ +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi) +{ + return hdcmi->State; +} + +/** + * @brief Return the DCMI error code + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @retval DCMI Error Code + */ +uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi) +{ + return hdcmi->ErrorCode; +} + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DCMI_Private_Functions DCMI Private Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Enable the Frame interrupt */ + __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); + + /* When snapshot mode, set dcmi state to ready */ + if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) + { + hdcmi->State= HAL_DCMI_STATE_READY; + } + +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DCMI_DMAError(DMA_HandleTypeDef *hdma) +{ + DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + + /* Initialize the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + + /* DCMI error Callback */ + HAL_DCMI_ErrorCallback(hdcmi); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DCMI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dlyb.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dlyb.c new file mode 100644 index 0000000000000000000000000000000000000000..d7b95a884f6fd94be8213ce537d486e33ff9e85e --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dlyb.c @@ -0,0 +1,92 @@ +/* + ****************************************************************************** + * @file HAL_DLYB.c + * @version V1.0.0 + * @date 2020 + * @brief DLYB HAL module driver. + * This file provides firmware functions to config phase shift of SDIO + * . + ****************************************************************************** +*/ +#include "hal.h" + + +/********************************************************************************* +* Function : HAL_DLYB_Enable +* Description : Enable DLYB for phase shif of SDIO clk. +* Input : hdlyb: DLYB handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_DLYB_Enable(DLYB_TypeDef *hdlyb) +{ + uint32_t len; + uint32_t i, t; + uint32_t clkn; + uint32_t delay_unit; + uint32_t sel; + + hdlyb->DLYB_REG_CTRL = (DEN_ENABLE | SEN_ENABLE); //DEN and SEN enable + hdlyb->DLYB_REG_CFGR &= ~(0x0F); +// SDMMC_DLYB_REG_CFGR |= (12<<0); //SEL +// hdlyb->DLYB_REG_CFGR = (12<<0); //SEL + + for(t=0; t<=DLYB_SEL_MAX; t++) + { + hdlyb->DLYB_REG_CFGR = (t<<0); //SEL + + for(i=0; iDLYB_REG_CFGR =((hdlyb->DLYB_REG_CFGR & (~(0x7FUL<<8))) | (i<<8)); //UNIT + while(!(hdlyb->DLYB_REG_CFGR&(1UL<<31))); //wait LENF + len = ((hdlyb->DLYB_REG_CFGR>>16)&0x0FFF); + if((len&0x7FF) && ((len&(3<<10)) != (3<<10))) + { + delay_unit = i; + break; + } + } + } + + if(t>DLYB_SEL_MAX) + { + return HAL_ERROR; + } + + t=10; + for(i=0; i<11; i++) + { + if(len&(1<DLYB_REG_CTRL = 0; + + hdlyb->DLYB_REG_CTRL = (DEN_ENABLE | SEN_ENABLE); //DEN and SEN enable + hdlyb->DLYB_REG_CFGR = ((delay_unit<<8) | (sel<<0)); + hdlyb->DLYB_REG_CTRL = DEN_ENABLE; + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_DLYB_Disable +* Description : Disable DLYB. +* Input : hdlyb: DLYB handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_DLYB_Disable(DLYB_TypeDef *hdlyb) +{ + hdlyb->DLYB_REG_CTRL = 0; + + return HAL_OK; +} + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dma.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..57ab7841b701dd160051d4816956ffed249dfba6 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dma.c @@ -0,0 +1,746 @@ +/****************************************************************************** +*@file : hal_dma.c +*@brief : DMA HAL module driver. +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_DMA_MODULE_ENABLED + +/****************************************************************************** +*@brief : This function handles DMA interrupt request. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for DMA module. +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Channel has been interrupted */ + if (hdma->DMA->INTSTATUS & (1UL << hdma->Channel)) + { + /* Transfer complete interrupt */ + if ((hdma->DMA->INTTCSTATUS & (1UL << hdma->Channel)) && (hdma->Instance->CXCONFIG & DMA_CXCONFIG_ITC)) + { + hdma->DMA->INTTCCLR = (1UL << hdma->Channel); + if (hdma->XferCpltCallback) + { + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer half interrupt */ + if ((hdma->DMA->INTTCSTATUS & ((1UL << hdma->Channel) << 8)) && (hdma->Instance->CXCONFIG & DMA_CXCONFIG_IHFTC)) + { + hdma->DMA->INTTCCLR = 1UL << (hdma->Channel + 8); + if (hdma->XferHalfCpltCallback) + { + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer error interrupt */ + if ((hdma->DMA->INTERRSTATUS & (1UL << hdma->Channel)) && (hdma->Instance->CXCONFIG & DMA_CXCONFIG_IE)) + { + hdma->DMA->INTERRCLR = (1UL << hdma->Channel); + if (hdma->XferErrorCallback) + { + hdma->XferErrorCallback(hdma); + } + } + } +} + +/****************************************************************************** +*@brief : Initialize the DMA according to the specified. +* parameters in the DMA_InitTypeDef and create the associated handle. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t RequestID; + + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_FUNCTIONAL_STATE(hdma->Init.Lock)); + assert_param(IS_DMA_DATAFLOW(hdma->Init.DataFlow)); + assert_param(IS_DMA_SRCINCDEC(hdma->Init.SrcIncDec)); + assert_param(IS_DMA_DESTINCDEC(hdma->Init.DestIncDec)); + assert_param(IS_DMA_SRCWIDTH(hdma->Init.SrcWidth)); + assert_param(IS_DMA_DESTWIDTH(hdma->Init.DestWidth)); + assert_param(IS_DMA_SRCBURST(hdma->Init.SrcBurst)); + assert_param(IS_DMA_DESTBURST(hdma->Init.DestBurst)); + assert_param(IS_DMA_SRCMASTER(hdma->Init.SrcMaster)); + assert_param(IS_DMA_DESTMASTER(hdma->Init.DestMaster)); + + /* Init the low level hardware : clock */ + HAL_DMA_MspInit(hdma); + + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel0)) + { + /* Check the parameters */ + assert_param(IS_DMA_REQ1ID(hdma->Init.DataFlow, hdma->Init.ReqID)); + + /* DMA1 */ + hdma->Channel = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA1_Channel0)) >> 5; + hdma->DMA = DMA1; + } + else + { + /* Check the parameters */ + assert_param(IS_DMA_REQ2ID(hdma->Init.DataFlow, hdma->Init.ReqID)); + + /* DMA2 */ + hdma->Channel = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA2_Channel0)) >> 5; + hdma->DMA = DMA2; + } + + /* Enable DMA */ + hdma->DMA->CONFIG |= DMA_CONFIG_EN; + + /* Clear Channel Config */ + hdma->Instance->CXCONFIG = 0; + + if (hdma->Init.DataFlow == DMA_DATAFLOW_M2P) + { + RequestID = hdma->Init.ReqID << DMA_CXCONFIG_DESTPERIPH_Pos; + } + else if (hdma->Init.DataFlow == DMA_DATAFLOW_P2M) + { + RequestID = hdma->Init.ReqID << DMA_CXCONFIG_SRCPERIPH_Pos; + } + else + { + RequestID = 0; + } + + hdma->Instance->CXCONFIG = hdma->Init.DataFlow | RequestID | hdma->Init.SrcMaster | hdma->Init.DestMaster; + if (hdma->Init.Lock) + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_LOCK; + + /* Config Channel Control */ + hdma->Instance->CXCTRL = DMA_CXCTRL_RITEN; + + /* Source or Desination address increase */ + hdma->Instance->CXCTRL |= (hdma->Init.DestIncDec | hdma->Init.SrcIncDec); + + /* Source or Desination date width */ + hdma->Instance->CXCTRL |= (hdma->Init.DestWidth | hdma->Init.SrcWidth); + + /* Source or Desination burst size */ + hdma->Instance->CXCTRL |= hdma->Init.SrcBurst | hdma->Init.DestBurst; + + if (hdma->Init.Mode == DMA_MODE_NORMAL) + hdma->Instance->CXLLI = 0; + else + { + /* Check the parameters */ + assert_param(IS_DMA_NEXTMASTER(hdma->Init.NextMaster)); + + hdma->Instance->CXLLI = hdma->Init.NextMaster; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DeInitializes the DMA peripheral. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* DeInit the low level hardware */ + HAL_DMA_MspDeInit(hdma); + + hdma->Instance->CXCONFIG = 0U; + hdma->Instance->CXCTRL = 0U; + hdma->Instance->CXSRCADDR = 0U; + hdma->Instance->CXDESTADDR = 0U; + hdma->Instance->CXLLI = 0U; + + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + hdma->DMA = 0U; + hdma->Channel = 0U; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the DMA MSP. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_DMA_MspInit(DMA_HandleTypeDef *hdma) +{ + UNUSED(hdma); +} + +/****************************************************************************** +*@brief : DeInitialize the DMA MSP. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_DMA_MspDeInit(DMA_HandleTypeDef *hdma) +{ + UNUSED(hdma); +} + +/****************************************************************************** +*@brief : Register callbacks. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : CallbackID: User Callback identifier +* This parameter can be a combination of @ref DMA_XfeCallbackID. +* @arg DMA_CALLBACKID_CPLT: Transfer completion interrupt callback function. +* @arg DMA_CALLBACKID_HALFCPLT: Half transfer completion interrupt callback function. +* @arg DMA_CALLBACKID_ERROR: Error interrupt callback function. +* @arg DMA_CALLBACKID_ABORT: Abort callback function. +*@param : pCallback: callback function. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, uint32_t CallbackID, \ + void (* pCallback)(struct __DMA_HandleTypeDef * hdma)) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CALLBACK(CallbackID)); + + switch (CallbackID) + { + case DMA_CALLBACKID_CPLT: + + hdma->XferCpltCallback = pCallback; + break; + + case DMA_CALLBACKID_HALFCPLT: + + hdma->XferHalfCpltCallback = pCallback; + break; + + case DMA_CALLBACKID_ERROR: + + hdma->XferErrorCallback = pCallback; + break; + + case DMA_CALLBACKID_ABORT: + + hdma->XferAbortCallback = pCallback; + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : UnRegister callbacks. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : CallbackID: User Callback identifier +* This parameter can be a combination of @ref DMA_XfeCallbackID. +* @arg DMA_CALLBACKID_CPLT: Transfer completion interrupt callback function. +* @arg DMA_CALLBACKID_HALFCPLT: Half transfer completion interrupt callback function. +* @arg DMA_CALLBACKID_ERROR: Error interrupt callback function. +* @arg DMA_CALLBACKID_ABORT: Abort callback function. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, uint32_t CallbackID) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CALLBACK(CallbackID)); + + switch (CallbackID) + { + case DMA_CALLBACKID_CPLT: + + hdma->XferCpltCallback = NULL; + break; + + case DMA_CALLBACKID_HALFCPLT: + + hdma->XferHalfCpltCallback = NULL; + break; + + case DMA_CALLBACKID_ERROR: + + hdma->XferErrorCallback = NULL; + break; + + case DMA_CALLBACKID_ABORT: + + hdma->XferAbortCallback = NULL; + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Starts the DMA Transfer. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : SrcAddr: The source memory Buffer address. +*@param : DestAddr: The destination memory Buffer address. +*@param : Size: The length of data to be transferred from source to destination. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DestAddr, uint32_t TransferSize) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_SRCADDR(SrcAddr)); + assert_param(IS_DMA_DESTADDR(DestAddr)); + assert_param(IS_DMA_TRANSFERSIZE(TransferSize)); + + /* DMA Channel Disable */ + hdma->Instance->CXCONFIG &= ~DMA_CXCONFIG_EN; + + /* Set source address and desination address */ + hdma->Instance->CXSRCADDR = SrcAddr; + hdma->Instance->CXDESTADDR = DestAddr; + + /* Set Transfer Size */ + hdma->Instance->CXCTRL = (hdma->Instance->CXCTRL & ~DMA_TRANSFER_SIZE) | (TransferSize << DMA_CXCTRL_TRANSFERSIZE_Pos); + + /* Set Next Link */ + if (hdma->Init.Mode == DMA_MODE_NORMAL) + { + hdma->Instance->CXLLI = 0; + } + else + { + hdma->Instance->CXLLI = (hdma->Instance->CXLLI & ~DMA_CXLLI_LLI) | ((uint32_t)(&hdma->Link) & DMA_CXLLI_LLI); + + hdma->Link.SrcAddr = hdma->Instance->CXSRCADDR; + hdma->Link.DestAddr = hdma->Instance->CXDESTADDR; + hdma->Link.Next = hdma->Instance->CXLLI; + hdma->Link.Ctrl = (hdma->Instance->CXCTRL & ~DMA_TRANSFER_SIZE) | (TransferSize << DMA_CXCTRL_TRANSFERSIZE_Pos); + } + + /* Disable interrupt */ + hdma->Instance->CXCONFIG &= ~(DMA_CXCONFIG_IHFTC | DMA_CXCONFIG_ITC | DMA_CXCONFIG_IE); + + /* DMA Channel Enable */ + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_EN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the DMA Transfer with interrupt enabled. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : SrcAddr: The source memory Buffer address. +*@param : DestAddr: The destination memory Buffer address. +*@param : Size: The length of data to be transferred from source to destination. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddr, uint32_t DestAddr, uint32_t TransferSize) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_SRCADDR(SrcAddr)); + assert_param(IS_DMA_DESTADDR(DestAddr)); + assert_param(IS_DMA_TRANSFERSIZE(TransferSize)); + + /* DMA Channel Disable */ + hdma->Instance->CXCONFIG &= ~DMA_CXCONFIG_EN; + + /* Set source address and desination address */ + hdma->Instance->CXSRCADDR = SrcAddr; + hdma->Instance->CXDESTADDR = DestAddr; + + /* Set Transfer Size and enable LLI interrupt */ + hdma->Instance->CXCTRL = (hdma->Instance->CXCTRL & ~DMA_CXCTRL_TRANSFERSIZE) | (TransferSize << DMA_CXCTRL_TRANSFERSIZE_Pos); + + /* Enable interrupt */ + hdma->Instance->CXCONFIG &= ~DMA_CXCONFIG_IHFTC; + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_ITC | DMA_CXCONFIG_IE; + + if (hdma->XferHalfCpltCallback) + { + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_IHFTC; + } + + /* Set Next Link */ + if (hdma->Init.Mode == DMA_MODE_NORMAL) + { + hdma->Instance->CXLLI = 0; + } + else + { + hdma->Instance->CXLLI = ((uint32_t)(&hdma->Link) & DMA_CXLLI_LLI) | (hdma->Instance->CXLLI & DMA_CXLLI_LM); + hdma->Link.SrcAddr = hdma->Instance->CXSRCADDR; + hdma->Link.DestAddr = hdma->Instance->CXDESTADDR; + hdma->Link.Next = hdma->Instance->CXLLI; + hdma->Link.Ctrl = (hdma->Instance->CXCTRL & ~DMA_CXCTRL_TRANSFERSIZE) | (TransferSize << DMA_CXCTRL_TRANSFERSIZE_Pos); + } + + /* DMA Channel Enable */ + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_EN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize linked list. +*@param : Link: Initialize linked list node. +*@param : Link_Init: pointer to an DMA_LinkInitTypeDef structure that contains +* the configuration information for the specified Link. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_InitLink(DMA_LinkTypeDef *Link, DMA_LinkInitTypeDef *Link_Init) +{ + /* Check the parameters */ + assert_param(Link != NULL); + assert_param(Link_Init != NULL); + assert_param(IS_DMA_SRCADDR(Link_Init->SrcAddr)); + assert_param(IS_DMA_DESTADDR(Link_Init->DestAddr)); + assert_param(IS_DMA_NEXT(Link_Init->Next)); + assert_param(IS_DMA_NEXTMASTER(Link_Init->NextMaster)); + assert_param(IS_DMA_RAWIT(Link_Init->RawInt)); + assert_param(IS_DMA_SRCINCDEC(Link_Init->SrcIncDec)); + assert_param(IS_DMA_DESTINCDEC(Link_Init->DestIncDec)); + assert_param(IS_DMA_SRCWIDTH(Link_Init->SrcWidth)); + assert_param(IS_DMA_DESTWIDTH(Link_Init->DestWidth)); + assert_param(IS_DMA_SRCBURST(Link_Init->SrcBurst)); + assert_param(IS_DMA_DESTBURST(Link_Init->DestBurst)); + assert_param(IS_DMA_TRANSFERSIZE(Link_Init->TransferSize)); + + Link->SrcAddr = Link_Init->SrcAddr; + Link->DestAddr = Link_Init->DestAddr; + Link->Next = (Link_Init->Next & DMA_CXLLI_LLI) | Link_Init->NextMaster; + Link->Ctrl = Link_Init->RawInt | Link_Init->SrcIncDec | Link_Init->DestIncDec | \ + Link_Init->SrcWidth | Link_Init->DestWidth | Link_Init->SrcBurst | \ + Link_Init->DestBurst | Link_Init->TransferSize ; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Set the next node of the linked node. +*@param : Curr: current linked node. +*@param : Next: next linked node. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_SetLinkNext(DMA_LinkTypeDef *Curr, DMA_LinkTypeDef *Next) +{ + /* Check the parameters */ + assert_param(IS_DMA_NEXT(Curr)); + assert_param(IS_DMA_NEXT(Next)); + + Curr->Next = (Curr->Next & ~DMA_CXLLI_LLI) | ((uint32_t)Next & DMA_CXLLI_LLI); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DMA link transfer start. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : Link: First node of linked list. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start_Link(DMA_HandleTypeDef *hdma, DMA_LinkTypeDef *Link) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(Link != NULL); + + /* DMA Channel Disable */ + hdma->Instance->CXCONFIG &= ~DMA_CXCONFIG_EN; + + /* Set source address and desination address */ + hdma->Instance->CXSRCADDR = Link->SrcAddr; + hdma->Instance->CXDESTADDR = Link->DestAddr; + + /* Set Next Link */ + hdma->Instance->CXLLI = Link->Next; + + /* Set Transfer Size */ + hdma->Instance->CXCTRL = Link->Ctrl; + + hdma->Instance->CXCONFIG &= ~(DMA_CXCONFIG_IHFTC | DMA_CXCONFIG_ITC | DMA_CXCONFIG_IE); + + /* DMA Channel Enable */ + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_EN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DMA link transfer start. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : Link: First node of linked list. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Start_Link_IT(DMA_HandleTypeDef *hdma, DMA_LinkTypeDef *Link) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(Link != NULL); + + /* DMA Channel Disable */ + hdma->Instance->CXCONFIG &= ~DMA_CXCONFIG_EN; + + /* Set source address and desination address */ + hdma->Instance->CXSRCADDR = Link->SrcAddr; + hdma->Instance->CXDESTADDR = Link->DestAddr; + hdma->Instance->CXLLI = Link->Next; + hdma->Instance->CXCTRL = Link->Ctrl; + + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_ITC | DMA_CXCONFIG_IE; + hdma->Instance->CXCONFIG &= ~DMA_CXCONFIG_IHFTC; + if (hdma->XferHalfCpltCallback) + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_IHFTC; + + /* DMA Channel Enable */ + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_EN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Abort the DMA Transfer . +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable interrupt */ + hdma->Instance->CXCONFIG &= ~(DMA_CXCONFIG_IHFTC | DMA_CXCONFIG_ITC | DMA_CXCONFIG_IE); + + /* DMA Channel Abort */ + hdma->Instance->CXCONFIG |= DMA_CXCONFIG_HALT; + + /* Wait until data clearing in FIFO */ + timeout = DMA_ABORT_TIMEOUT; + while (hdma->Instance->CXCONFIG & DMA_CXCONFIG_ACTIVE) + { + if (timeout-- == 0) + return HAL_ERROR; + } + + /* Disable interrupt */ + hdma->Instance->CXCONFIG &= ~(DMA_CXCONFIG_HALT | DMA_CXCONFIG_EN); + /* Clear TC ERR Falg */ + hdma->DMA->INTTCCLR |= (1UL << hdma->Channel) | (1UL << (hdma->Channel + 8)); + hdma->DMA->INTERRCLR |= (1UL << hdma->Channel); + + /* Wait until the channel is closed */ + timeout = DMA_ABORT_TIMEOUT; + while (hdma->DMA->ENCHSTATUS & (1U << hdma->Channel)) + { + if (timeout-- == 0) + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Enable interrupt. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : IT: interrupt +* This parameter can be a combination of @ref DMA_IT. +* @arg DMA_IT_TC: transmission completion interrupt. +* @arg DMA_IT_HTC: indicating half transmission completion interrupt. +* @arg DMA_IT_ERR: error interrupt. +* @arg DMA_IT_RAW: raw interrupt. +*@return: HAL status +******************************************************************************/ +FunctionalState HAL_DMA_GetITSource(DMA_HandleTypeDef *hdma, uint32_t IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_IT(IT)); + + if ((hdma->Instance->CXCONFIG & IT) == 0) + return (DISABLE); + else + return (ENABLE); +} + +/****************************************************************************** +*@brief : Enable interrupt. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : IT: interrupt +* This parameter can be a combination of @ref DMA_IT. +* @arg DMA_IT_TC: transmission completion interrupt. +* @arg DMA_IT_HTC: indicating half transmission completion interrupt. +* @arg DMA_IT_ERR: error interrupt. +* @arg DMA_IT_RAW: raw interrupt. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_EnableIT(DMA_HandleTypeDef *hdma, uint32_t IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_IT(IT)); + + hdma->Instance->CXCONFIG |= IT; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Disable interrupt. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : IT: interrupt +* This parameter can be a combination of @ref DMA_IT. +* @arg DMA_IT_TC: transmission completion interrupt. +* @arg DMA_IT_HTC: indicating half transmission completion interrupt. +* @arg DMA_IT_ERR: error interrupt. +* @arg DMA_IT_RAW: raw interrupt. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_DisableIT(DMA_HandleTypeDef *hdma, uint32_t IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_IT(IT)); + + hdma->Instance->CXCONFIG &= ~IT; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Clear the DMA flag. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : Flag: DMA flag +* This parameter can be a combination of the following: +* @arg DMA_FLAG_TC: indicating transmission completion interrupt occur. +* @arg DMA_FLAG_HTC: indicating half transmission completion interrupt occur. +* @arg DMA_FLAG_ERR: indicating error interrupt occur. +* @arg DMA_FLAG_RTC: indicating raw transmission completion interrupt occur. +* @arg DMA_FLAG_RHTC: indicating raw half transmission completion interrupt occur. +* @arg DMA_FLAG_RERR: indicating raw error interrupt occur. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_DMA_ClearFlag(DMA_HandleTypeDef *hdma, uint32_t Flag) +{ + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_FLAG(Flag)); + + if (Flag &( DMA_FLAG_TC | DMA_FLAG_RTC)) + hdma->DMA->INTTCCLR = 1UL << hdma->Channel; + if (Flag &( DMA_FLAG_HTC | DMA_FLAG_RHTC)) + hdma->DMA->INTTCCLR = 1UL << (hdma->Channel + 8); + if (Flag &( DMA_FLAG_ERR | DMA_FLAG_RERR)) + hdma->DMA->INTERRCLR = 1UL << hdma->Channel; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Returns the DMA flag. +*@param : hdma: pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA Channel. +*@param : Flag: DMA flag +* This parameter can be a combination of the following: +* @arg DMA_FLAG_IT: indicating transmission completion interrupt or error interrupt occur. +* @arg DMA_FLAG_TC: indicating transmission completion interrupt occur. +* @arg DMA_FLAG_HTC: indicating half transmission completion interrupt occur. +* @arg DMA_FLAG_ERR: indicating error interrupt occur. +* @arg DMA_FLAG_RTC: indicating raw transmission completion interrupt occur. +* @arg DMA_FLAG_RHTC: indicating raw half transmission completion interrupt occur. +* @arg DMA_FLAG_RERR: indicating raw error interrupt occur. +*@return: DMA flag +******************************************************************************/ +FlagStatus HAL_DMA_GetFlag(DMA_HandleTypeDef *hdma, uint32_t Flag) +{ + uint32_t Status; + + /* Check the parameters */ + assert_param(IS_DMA_HANDLE(hdma)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_FLAG(Flag)); + + Status = 0; + if (Flag & DMA_FLAG_TC) + { + if (hdma->DMA->INTTCSTATUS & (1UL << hdma->Channel)) + Status |= DMA_FLAG_TC; + } + if (Flag & DMA_FLAG_HTC) + { + if (hdma->DMA->INTTCSTATUS & (1UL << (hdma->Channel + 8))) + Status |= DMA_FLAG_HTC; + } + if (Flag & DMA_FLAG_ERR) + { + if (hdma->DMA->INTERRSTATUS & (1UL << hdma->Channel)) + Status |= DMA_FLAG_ERR; + } + if (Flag & DMA_FLAG_RTC) + { + if (hdma->DMA->RAWINTTCSTATUS & (1UL << hdma->Channel)) + Status |= DMA_FLAG_RTC; + } + if (Flag & DMA_FLAG_RHTC) + { + if (hdma->DMA->RAWINTTCSTATUS & (1UL << (hdma->Channel + 8))) + Status |= DMA_FLAG_RHTC; + } + if (Flag & DMA_FLAG_RERR) + { + if (hdma->DMA->RAWINTERRSTATUS & (1UL << hdma->Channel)) + Status |= DMA_FLAG_RERR; + } + + return (Status); +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dma2d.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dma2d.c new file mode 100644 index 0000000000000000000000000000000000000000..11d610e2e70399598e298087d70d24fdcd483cd1 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dma2d.c @@ -0,0 +1,1614 @@ +/****************************************************************************** +*@file : hal_dma2d.c +*@brief : GPIO HAL module driver. +******************************************************************************/ + + +#include "hal.h" + +#ifdef HAL_DMA2D_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup DMA2D_Private_Constants DMA2D Private Constants + * @{ + */ + +/** @defgroup DMA2D_TimeOut DMA2D Time Out + * @{ + */ +#define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */ +#define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */ +/** + * @} + */ + +/** @defgroup DMA2D_Shifts DMA2D Shifts + * @{ + */ +#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */ +#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */ + +#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */ +#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */ + +#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */ +#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */ +#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */ + +#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */ +#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */ +#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */ + +#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */ + +#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */ +#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */ + +#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */ +#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */ + +#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */ + +#define DMA2D_POSITION_FGPFCCR_CSS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CSS) /*!< Required left shift to set foreground Chroma sub-sampling */ +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup DMA2D_Private_Functions_Prototypes + * @{ + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DMA2D + (+) De-initialize the DMA2D + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA2D according to the specified + * parameters in the DMA2D_InitTypeDef and create the associated handle. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) +{ + /* Check the DMA2D peripheral state */ + if(hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); + assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); + assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); + assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); + + __HAL_RCC_DMA2D_CLK_ENABLE(); + __HAL_RCC_DMA2D_RESET(); + + if(hdma2d->State == HAL_DMA2D_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hdma2d->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_DMA2D_MspInit(hdma2d); + } + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* DMA2D CR register configuration -------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); + + /* DMA2D OPFCCR register configuration ---------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); + + /* DMA2D OOR register configuration ------------------------------------------*/ + MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); + + /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/ + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI)); + + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS)); + +// SET_BIT(hdma2d->Instance->CR, DMA2D_CR_AHB_LOCK); //DMA2D lock function have influence on ltdc display + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Deinitializes the DMA2D peripheral registers to their default reset + * values. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ + +HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) +{ + + /* Check the DMA2D peripheral state */ + if(hdma2d == NULL) + { + return HAL_ERROR; + } + + /* Abort DMA2D transfer if any */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) + { + if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) + { + /* Issue when aborting DMA2D transfer */ + return HAL_ERROR; + } + } + else + { + /* Abort background CLUT loading if any */ + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK) + { + /* Issue when aborting background CLUT loading */ + return HAL_ERROR; + } + } + else + { + /* Abort foreground CLUT loading if any */ + if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) + { + if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK) + { + /* Issue when aborting foreground CLUT loading */ + return HAL_ERROR; + } + } + } + } + + + + /* Carry on with de-initialization of low level hardware */ + HAL_DMA2D_MspDeInit(hdma2d); + + /* Reset DMA2D control registers*/ + hdma2d->Instance->CR = 0; + hdma2d->Instance->FGOR = 0; + hdma2d->Instance->BGOR = 0; + hdma2d->Instance->FGPFCCR = 0; + hdma2d->Instance->BGPFCCR = 0; + hdma2d->Instance->OPFCCR = 0; + + /* Update error code */ + hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Initializes the DMA2D MSP. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspInit can be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the DMA2D MSP. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_MspDeInit can be implemented in the user file. + */ +} + +/** + * @} + */ + + +/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer. + (+) Configure the source for foreground and background, destination address + and data size then start a MultiBuffer DMA2D transfer. + (+) Configure the pdata, destination address and data size then + start the DMA2D transfer with interrupt. + (+) Configure the source for foreground and background, destination address + and data size then start a MultiBuffer DMA2D transfer with interrupt. + (+) Abort DMA2D transfer. + (+) Suspend DMA2D transfer. + (+) Resume DMA2D transfer. + (+) Enable CLUT transfer. + (+) Configure CLUT loading then start transfer in polling mode. + (+) Configure CLUT loading then start transfer in interrupt mode. + (+) Abort DMA2D CLUT loading. + (+) Suspend DMA2D CLUT loading. + (+) Resume DMA2D CLUT loading. + (+) Poll for transfer complete. + (+) handle DMA2D interrupt request. + (+) Transfer watermark callback. + (+) CLUT Transfer Complete callback. + + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA2D Transfer. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata: Configure the source memory Buffer address if + * Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. + * @param DstAddress: The destination memory Buffer address. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the DMA2D Transfer with interrupt enabled. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param pdata: Configure the source memory Buffer address if + * the Memory-to-Memory or Memory-to-Memory with pixel format + * conversion mode is selected, or configure + * the color value if Register-to-Memory mode is selected. + * @param DstAddress: The destination memory Buffer address. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the multi-source DMA2D Transfer. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1: The source memory Buffer address for the foreground layer. + * @param SrcAddress2: The source memory Buffer address for the background layer. + * @param DstAddress: The destination memory Buffer address. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure DMA2D Stream source2 address */ + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Start the multi-source DMA2D Transfer with interrupt enabled. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param SrcAddress1: The source memory Buffer address for the foreground layer. + * @param SrcAddress2: The source memory Buffer address for the background layer. + * @param DstAddress: The destination memory Buffer address. + * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Height: The height of data to be transferred from source to destination (expressed in number of lines). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINE(Height)); + assert_param(IS_DMA2D_PIXEL(Width)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure DMA2D Stream source2 address */ + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + + /* Enable the transfer complete, transfer error and configuration error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + + /* Enable the Peripheral */ + __HAL_DMA2D_ENABLE(hdma2d); + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D Transfer. + * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t tickstart = 0; + + /* Abort the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing ??has no + effect on START bitvalue). */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the DMA2D is effectively disabled */ + while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D Transfer. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t tickstart = 0; + + /* Suspend the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing ??has no + effect on START bitvalue). */ + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the DMA2D is effectively suspended */ + while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ + && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no tranfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D Transfer. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) +{ + /* Check the SUSP and START bits */ + if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) + { + /* Ongoing transfer is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + + /* Resume the DMA2D transfer */ + /* START bit is reset to make sure not to set it again, in the event the HW clears it + between the register read and the register write by the CPU (writing ??has no + effect on START bitvalue). */ + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); + + return HAL_OK; +} + + +/** + * @brief Enable the DMA2D CLUT Transfer. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + if(LayerIdx == 0) + { + /* Enable the background CLUT loading */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + else + { + /* Enable the foreground CLUT loading */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + + +/** + * @brief Start DMA2D CLUT Loading. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == 0) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading with interrupt enabled. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == 0) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Abort the DMA2D CLUT loading. + * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart = 0; + __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */ + + + /* Abort the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == 1) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is aborted */ + while((*reg & mask) != RESET) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + + /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + + /* Change the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Suspend the DMA2D CLUT loading. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + uint32_t tickstart = 0; + __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + uint32_t mask = DMA2D_BGPFCCR_START; /* by default, set to background constant */ + + + /* Suspend the CLUT loading */ + SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + /* If foreground CLUT loading is considered, update local variables */ + if(LayerIdx == 1) + { + reg = &(hdma2d->Instance->FGPFCCR); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the CLUT loading is suspended */ + while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \ + && ((*reg & mask) == mask)) + { + if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + if ((*reg & mask) != RESET) + { + hdma2d->State = HAL_DMA2D_STATE_SUSPEND; + } + else + { + /* Make sure SUSP bit is cleared since it is meaningless + when no tranfer is on-going */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA2D CLUT loading. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + /* Check the SUSP and START bits for background or foreground CLUT loading */ + if(LayerIdx == 0) + { + /* Background CLUT loading suspension check */ + if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + else + { + /* Foreground CLUT loading suspension check */ + if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) + && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)) + { + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } + } + + /* Resume the CLUT loading */ + CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); + + return HAL_OK; +} + + +/** + + * @brief Polling for transfer complete or CLUT loading. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) +{ + uint32_t tickstart = 0; + __IO uint32_t isrflags = 0x0; + + /* Polling for DMA2D transfer */ + if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) + { + if ((isrflags & DMA2D_FLAG_CE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the transfer and configuration error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + /* Polling for CLUT loading (foreground or background) */ + if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) || + ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET)) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET) + { + isrflags = READ_REG(hdma2d->Instance->ISR); + if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET) + { + if ((isrflags & DMA2D_FLAG_CAE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + } + if ((isrflags & DMA2D_FLAG_CE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + } + if ((isrflags & DMA2D_FLAG_TE) != RESET) + { + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + } + /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_ERROR; + } + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; + + /* Change the DMA2D state */ + hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear the transfer complete and CLUT loading flags */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} +/** + * @brief Handle DMA2D interrupt request. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL status + */ +void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) +{ + uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); + uint32_t crflags = READ_REG(hdma2d->Instance->CR); + + /* Transfer Error Interrupt management ***************************************/ + if ((isrflags & DMA2D_FLAG_TE) != RESET) + { + if ((crflags & DMA2D_IT_TE) != RESET) + { + /* Disable the transfer Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; + + /* Clear the transfer error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Configuration Error Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_CE) != RESET) + { + if ((crflags & DMA2D_IT_CE) != RESET) + { + /* Disable the Configuration Error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); + + /* Clear the Configuration error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* CLUT access Error Interrupt management ***********************************/ + if ((isrflags & DMA2D_FLAG_CAE) != RESET) + { + if ((crflags & DMA2D_IT_CAE) != RESET) + { + /* Disable the CLUT access error interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); + + /* Clear the CLUT access error flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferErrorCallback != NULL) + { + /* Transfer error Callback */ + hdma2d->XferErrorCallback(hdma2d); + } + } + } + /* Transfer watermark Interrupt management **********************************/ + if ((isrflags & DMA2D_FLAG_TW) != RESET) + { + if ((crflags & DMA2D_IT_TW) != RESET) + { + /* Disable the transfer watermark interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Clear the transfer watermark flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); + + /* Transfer watermark Callback */ + HAL_DMA2D_LineEventCallback(hdma2d); + } + } + /* Transfer Complete Interrupt management ************************************/ + if ((isrflags & DMA2D_FLAG_TC) != RESET) + { + if ((crflags & DMA2D_IT_TC) != RESET) + { + /* Disable the transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); + + /* Clear the transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + if(hdma2d->XferCpltCallback != NULL) + { + /* Transfer complete Callback */ + hdma2d->XferCpltCallback(hdma2d); + } + } + } + /* CLUT Transfer Complete Interrupt management ******************************/ + if ((isrflags & DMA2D_FLAG_CTC) != RESET) + { + if ((crflags & DMA2D_IT_CTC) != RESET) + { + /* Disable the CLUT transfer complete interrupt */ + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); + + /* Clear the CLUT transfer complete flag */ + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); + + /* Update error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; + + /* Change DMA2D state */ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + /* CLUT Transfer complete Callback */ + HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); + } + } + +} + +/** + * @brief Transfer watermark callback. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + hdma2d->LineEvtCallback(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_LineEventCallback can be implemented in the user file. + */ +} + +/** + * @brief CLUT Transfer Complete callback. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval None + */ +__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma2d); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the DMA2D foreground or background layer parameters. + (+) Configure the DMA2D CLUT transfer. + (+) Configure the line watermark + (+) Configure the dead time value. + (+) Enable or disable the dead time value functionality. + + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA2D Layer according to the specified + * parameters in the DMA2D_InitTypeDef and create the associated handle. + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) +{ + DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; + + uint32_t regMask = 0, regValue = 0; + + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset)); + if(hdma2d->Init.Mode != DMA2D_R2M) + { + assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode)); + if(hdma2d->Init.Mode != DMA2D_M2M) + { + assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode)); + } + } + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* DMA2D BGPFCR register configuration -----------------------------------*/ + /* Prepare the value to be written to the BGPFCCR register */ + + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM) | \ + (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI) | \ + (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS); + + regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS; + + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + regValue |= ((pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA) & DMA2D_BGPFCCR_ALPHA); + } + else + { + regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA); + } + + /* Configure the background DMA2D layer */ + if(LayerIdx == 0) + { + /* Write DMA2D BGPFCCR register */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); + + /* DMA2D BGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); + + /* DMA2D BGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); + } + } + /* Configure the foreground DMA2D layer */ + else + { + /* Write DMA2D FGPFCCR register */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); + + /* DMA2D FGOR register configuration -------------------------------------*/ + WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); + + /* DMA2D FGCOLR register configuration -------------------------------------*/ + if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) + { + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + } + } + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure the DMA2D CLUT Transfer. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx: DMA2D Layer index. + * This parameter can be one of the following values: + * 0(background) / 1(foreground) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if(LayerIdx == 0) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM))); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM))); + } + + /* Set the DMA2D state to Ready*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + + +/** + * @brief Configure the line watermark. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param Line: Line Watermark configuration (maximum 16-bit long value expected). + * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. + * @note The transfer watermark interrupt is disabled once it has occurred. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LINEWATERMARK(Line)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Sets the Line watermark configuration */ + WRITE_REG(hdma2d->Instance->LWR, Line); + + /* Enable the Line interrupt */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); + + /* Initialize the DMA2D state*/ + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Enable DMA2D dead time feature. + * @param hdma2d: DMA2D handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR EN bit */ + SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Disable DMA2D dead time feature. + * @param hdma2d: DMA2D handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Clear DMA2D_AMTCR EN bit */ + CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @brief Configure dead time. + * @note The dead time value represents the guaranteed minimum number of cycles between + * two consecutive transactions on the AHB bus. + * @param hdma2d: DMA2D handle. + * @param DeadTime: dead time value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) +{ + /* Process Locked */ + __HAL_LOCK(hdma2d); + + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Set DMA2D_AMTCR DT field */ + MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT)); + + hdma2d->State = HAL_DMA2D_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma2d); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to : + (+) Get the DMA2D state + (+) Get the DMA2D error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA2D state + * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @retval HAL state + */ +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) +{ + return hdma2d->State; +} + +/** + * @brief Return the DMA2D error code + * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for DMA2D. + * @retval DMA2D Error Code + */ +uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) +{ + return hdma2d->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA2D_Private_Functions DMA2D Private Functions + * @{ + */ + +/** + * @brief Set the DMA2D transfer parameters. + * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the specified DMA2D. + * @param pdata: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param Width: The width of data to be transferred from source to destination. + * @param Height: The height of data to be transferred from source to destination. + * @retval HAL status + */ +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +{ + uint32_t tmp = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + uint32_t tmp3 = 0; + uint32_t tmp4 = 0; + + /* Configure DMA2D data size */ + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL))); + + /* Configure DMA2D destination address */ + WRITE_REG(hdma2d->Instance->OMAR, DstAddress); + + /* Register to memory DMA2D mode selected */ + if (hdma2d->Init.Mode == DMA2D_R2M) + { + tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; + tmp2 = pdata & DMA2D_OCOLR_RED_1; + tmp3 = pdata & DMA2D_OCOLR_GREEN_1; + tmp4 = pdata & DMA2D_OCOLR_BLUE_1; + + /* Prepare the value to be written to the OCOLR register according to the color mode */ + if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) + { + tmp = (tmp3 | tmp2 | tmp1| tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) + { + tmp = (tmp3 | tmp2 | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) + { + tmp2 = (tmp2 >> 19); + tmp3 = (tmp3 >> 10); + tmp4 = (tmp4 >> 3 ); + tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4); + } + else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) + { + tmp1 = (tmp1 >> 31); + tmp2 = (tmp2 >> 19); + tmp3 = (tmp3 >> 11); + tmp4 = (tmp4 >> 3 ); + tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4); + } + else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ + { + tmp1 = (tmp1 >> 28); + tmp2 = (tmp2 >> 20); + tmp3 = (tmp3 >> 12); + tmp4 = (tmp4 >> 4 ); + tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4); + } + /* Write to DMA2D OCOLR register */ + WRITE_REG(hdma2d->Instance->OCOLR, tmp); + } + else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ + { + /* Configure DMA2D source address */ + WRITE_REG(hdma2d->Instance->FGMAR, pdata); + } +} + +/** + * @} + */ +#endif /* HAL_DMA2D_MODULE_ENABLED */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dwt.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dwt.c new file mode 100644 index 0000000000000000000000000000000000000000..4fbaf2e7e6110a7967a4ded6b28af8d5c634ceec --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_dwt.c @@ -0,0 +1,69 @@ +/****************************************************************************** +*@file : hal_dwt.c +*@brief : DataWatchpoint andTrace +******************************************************************************/ + +#include "hal_dwt.h" + +#ifdef HAL_DWT_MODULE_ENABLED + +uint32_t HAL_DWT_clkPerUs, HAL_DWT_clkPerMs; + + +void HAL_DWT_Init(void) +{ + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;//ʹDWT裬ں˵ԼĴDEM_CRλ24ƣд1ʹ + DWT->CYCCNT = 0; //ʹCYCCNTĴ֮ǰ0 + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;//ʹCYCCNTĴDWT_CTRLλ0ƣд1ʹܡ + HAL_DWT_clkPerUs = SystemCoreClock/1000000; + HAL_DWT_clkPerMs = SystemCoreClock/1000; +} + + + +uint32_t HAL_DWT_GetClkDelay(uint32_t startClkTick) +{ + return (DWT->CYCCNT - startClkTick); +} + +uint32_t HAL_DWT_GetUsDelay(uint32_t startClkTick) +{ + return (DWT->CYCCNT - startClkTick)/HAL_DWT_clkPerUs; +} + +uint32_t HAL_DWT_GetMsDelay(uint32_t startClkTick) +{ + return (DWT->CYCCNT - startClkTick)/HAL_DWT_clkPerMs; +} + + +void HAL_DWT_DelayClks(uint32_t clks) +{ + uint32_t startClkTick; + + startClkTick = DWT->CYCCNT; + while(DWT->CYCCNT - startClkTick < clks); +} + +void HAL_DWT_DelayUs(uint32_t us) +{ + uint32_t clks,startClkTick; + + startClkTick = DWT->CYCCNT; + clks = HAL_DWT_clkPerUs*us; + while(DWT->CYCCNT - startClkTick < clks); +} + +void HAL_DWT_DelayMs(uint32_t ms) +{ + while(ms--) + { + HAL_DWT_DelayClks(HAL_DWT_clkPerMs); + } +} + +#endif + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_efuse.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_efuse.c new file mode 100644 index 0000000000000000000000000000000000000000..1379ef86a32e3ff18d3d7e6ebd46ef7c9cff19a4 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_efuse.c @@ -0,0 +1,441 @@ +/****************************************************************************** +*@file : hal_efuse.c +*@brief : EFUSE HAL module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_EFUSE_MODULE_ENABLED + +/****************************************************************************** +*@brief : Initializes the EFUSEx peripheral according to the specified parameters +* in the EFUSE_Init. +*@param : EFUSEx: where x can be (A..F) to select the EFUSE peripheral. +*@param : EFUSE_Init: pointer to an EFUSE_InitTypeDef structure that contains +* the configuration information for the specified EFUSE peripheral. +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_EFUSE_Init(EFUSE_TypeDef *EFUSEx) +{ + + /* Check the parameters */ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + + if(EFUSEx == EFUSE1) + { + __HAL_RCC_EFUSE1_CLK_ENABLE(); + + } + else if(EFUSEx == EFUSE2) + { + __HAL_RCC_EFUSE2_CLK_ENABLE(); + + } + if ((RCC->RCHCR & (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return HAL_ERROR; + + HAL_EFUSE_PowerUpSpTimeCfg(EFUSEx,11*EFUSE_1US_TIMES); + HAL_EFUSE_PowerDownHdCfg(EFUSEx,2*EFUSE_1US_TIMES); + HAL_EFUSE_ProWaitTimeCfg(EFUSEx,2*EFUSE_1US_TIMES); + HAL_EFUSE_ProTimeCfg(EFUSEx,4*EFUSE_1US_TIMES); + //wtim:4*4+3*2+1+11=34us(0x55),ʵ36us + //pt*bit+pw*(bit-1)+st+pu + + return HAL_OK; +} + +/****************************************************************************** +*@brief : De-initializes the EFUSEx peripheral registers to their default reset values. +*@param : EFUSEx: where x can be (A..F) to select the EFUSE peripheral. +*@param : EFUSE_Pin: specifies the port bit to be written. +*@return: None +******************************************************************************/ +void HAL_EFUSE_DeInit(EFUSE_TypeDef *EFUSEx) +{ + + /* Check the parameters */ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + + if(EFUSEx == EFUSE1) + { + __HAL_RCC_EFUSE1_RESET(); + __HAL_RCC_EFUSE1_CLK_DISABLE(); + } + else if(EFUSEx == EFUSE2) + { + __HAL_RCC_EFUSE2_RESET(); + __HAL_RCC_EFUSE2_CLK_DISABLE(); + } + +} + +/****************************************************************************** +*@brief : Write data(in byte) of byteaddr. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : byteaddr: specifies the byteaddr to be write. +*@param : data: specifies the data written to byteaddr. +*@param : timeout: specifies the time wait for write byte to complete +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_EFUSE_WriteByte(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t data,uint32_t timeout) +{ + + /* Check the parameters */ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + assert_param(IS_EFUSE_BYTE_ADDR(byteaddr)); + + if (RCC->RCHCR & RCC_RCHCR_RCHDIV) + return HAL_ERROR;//֧RCH 16Ƶ + + if ((RCC->RCHCR & (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return HAL_ERROR; + + while((!(EFUSEx->SR & EFUSE_SR_PREREAD_DONE)) && timeout--); + if(timeout == 0) + { + return HAL_TIMEOUT; + } + + EFUSEx->AR = byteaddr; + + EFUSEx->DWR = data; + + EFUSEx->CTRL = EFUSE_WBYTE; + + EFUSEx->CTRL |= EFUSE_CTRL_TRIG; + + while( (!(EFUSEx->SR&EFUSE_SR_UNPG)) && (!(EFUSEx->SR&EFUSE_SR_DONE)) && timeout--); + EFUSEx->CLR |=EFUSE_CLR_CDONE|EFUSE_CLR_CUNPG; + + + if(timeout == 0) + { + return HAL_TIMEOUT; + } + else + { + return HAL_OK; + } + +} +/****************************************************************************** +*@brief : Write multiple data(in byte) of byteaddr. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : byteaddr: specifies the byteaddr to be write. +*@param : data: specifies the data written to byteaddr. +*@param : timeout: specifies the time wait for write byte to complete +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_EFUSE_WriteBytes(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t* data,uint32_t len,uint32_t timeout) +{ + uint32_t time_byte = timeout; + + /* Check the parameters */ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + assert_param(IS_EFUSE_BYTE_ADDR(byteaddr)); + + if (RCC->RCHCR & RCC_RCHCR_RCHDIV) + return HAL_ERROR;//֧RCH 16Ƶ + + if ((RCC->RCHCR & (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return HAL_ERROR; + + while((!(EFUSEx->SR & EFUSE_SR_PREREAD_DONE)) && timeout--); + if(timeout == 0) + { + return HAL_TIMEOUT; + } + + + EFUSEx->CTRL = EFUSE_WBYTE; + + for(uint32_t i=0; iAR = byteaddr+i; + + EFUSEx->DWR = *(data+i); + + EFUSEx->CTRL |= EFUSE_CTRL_TRIG; + + while( (!(EFUSEx->SR&EFUSE_SR_UNPG)) && (!(EFUSEx->SR&EFUSE_SR_DONE)) && time_byte--); + EFUSEx->CLR |=EFUSE_CLR_CDONE|EFUSE_CLR_CUNPG; + + if(time_byte == 0) + { + return HAL_TIMEOUT; + } + + time_byte = timeout; + } + + return HAL_OK; + +} +/****************************************************************************** +*@brief : Read data(in byte) of byteaddr. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : byteaddr: specifies the byteaddr to be read. +*@param : data: the data read from byteaddr. +*@param : timeout: specifies the time wait for read byte to complete +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_EFUSE_ReadByte(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t* data,uint32_t timeout) +{ + + /* Check the parameters */ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + assert_param(IS_EFUSE_BYTE_ADDR(byteaddr)); + + while((!(EFUSEx->SR & EFUSE_SR_PREREAD_DONE)) && timeout--); + if(timeout == 0) + { + return HAL_TIMEOUT; + } + + + EFUSEx->AR = byteaddr; + + EFUSEx->CTRL = EFUSE_RBYTE; + + EFUSEx->CTRL |= EFUSE_CTRL_TRIG; + + while( (!(EFUSEx->SR&EFUSE_SR_DONE)) && timeout--); + + *data = EFUSEx->DR; + + EFUSEx->CLR |=EFUSE_CLR_CDONE; + + if(timeout == 0) + { + return HAL_TIMEOUT; + } + else + { + return HAL_OK; + } + +} + +/****************************************************************************** +*@brief : Read multiple data(in byte) of byteaddr. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : byteaddr: specifies the byteaddr to be read. +*@param : data: the data read from byteaddr. +*@param : timeout: specifies the time wait for read byte to complete +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_EFUSE_ReadBytes(EFUSE_TypeDef *EFUSEx,uint16_t byteaddr,uint8_t* data,uint32_t len,uint32_t timeout) +{ + uint32_t time_byte = timeout; + + /* Check the parameters */ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + assert_param(IS_EFUSE_BYTE_ADDR(byteaddr)); + + while((!(EFUSEx->SR & EFUSE_SR_PREREAD_DONE)) && timeout--); + if(timeout == 0) + { + return HAL_TIMEOUT; + } + + EFUSEx->CTRL = EFUSE_RBYTE; + + for(uint32_t i=0; iAR = byteaddr+i; + + EFUSEx->CTRL |= EFUSE_CTRL_TRIG; + + while( (!(EFUSEx->SR&EFUSE_SR_DONE)) && time_byte--); + + if(time_byte == 0) + { + return HAL_TIMEOUT; + } + + *(data+i) = EFUSEx->DR; + EFUSEx->CLR |=EFUSE_CLR_CDONE; + time_byte = timeout; + } + + return HAL_OK; + +} + +/****************************************************************************** +*@brief : Config EFUSE write protection. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@return: None +******************************************************************************/ +void HAL_EFUSE_WpEnable(EFUSE_TypeDef *EFUSEx) +{ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + EFUSEx->WP = 0xEF59A6CB; + +} + +/****************************************************************************** +*@brief : Config EFUSE read protection(0~15 byte). +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@return: None +******************************************************************************/ +void HAL_EFUSE_RpEnable(EFUSE_TypeDef *EFUSEx) +{ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + EFUSEx->DSDP = 0xACF56B49; + +} + +/****************************************************************************** +*@brief : Read data from data shadow register. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : str_addr:where x can be (0..15), specifies the first data shadow register to be read. +*@param : len: specifies the number of data shadow register to be read. +*@param : data: the data read from of data shadow register. +*@return: None +******************************************************************************/ +void HAL_EFUSE_ReadDsr(EFUSE_TypeDef *EFUSEx,uint8_t str_addr,uint8_t len,uint8_t* data) +{ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + + if(str_addr+len >16) + return; + if(len==0) + return; + + for(uint8_t i=0; iDSR[str_addr+i])&0xff; + } + +} + +/****************************************************************************** +*@brief : Config EFUSE byte write protection. +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@return: None +******************************************************************************/ +void HAL_EFUSE_ByteWpEnable(EFUSE_TypeDef *EFUSEx) +{ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + EFUSEx->BYTEWP = 0xC98E1A6D; + +} +/****************************************************************************** +*@brief : Config EFUSE Power Up Set Up Time +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : us: 1000 times Power Up Time in microsecond mode. +*@return: None +******************************************************************************/ +void HAL_EFUSE_PowerUpSpTimeCfg(EFUSE_TypeDef *EFUSEx, uint32_t us) +{ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + assert_param(us>=1*EFUSE_1US_TIMES); + uint16_t avdd_sp; + uint32_t rch_freq,goal_freq; + rch_freq=(64000000/8); + goal_freq=(1000000*EFUSE_1US_TIMES/us); + if(rch_freq<=goal_freq) + avdd_sp=0; + else + avdd_sp=rch_freq/goal_freq-1; + MODIFY_REG(EFUSEx->PGCFG,EFUSE_PGCFG_AVDD_SP,avdd_sp<=1*EFUSE_1US_TIMES); + uint16_t avdd_hd; + uint32_t rch_freq,goal_freq; + rch_freq=(64000000/8); + goal_freq=(1000000*EFUSE_1US_TIMES/us); + if(rch_freq<=goal_freq) + avdd_hd=0; + else + avdd_hd=rch_freq/goal_freq-1; + MODIFY_REG(EFUSEx->PGCFG,EFUSE_PGCFG_AVDD_HD,avdd_hd<=1*EFUSE_1US_TIMES); + uint16_t pgwt; + uint32_t rch_freq,goal_freq; + rch_freq=(64000000/8); + goal_freq=(1000000*EFUSE_1US_TIMES/us); + if(rch_freq<=goal_freq) + pgwt=0; + else + pgwt=rch_freq/goal_freq-1; + MODIFY_REG(EFUSEx->PGCFG,EFUSE_PGCFG_PGWT,pgwt<=3*EFUSE_1US_TIMES && us<=5*EFUSE_1US_TIMES); + uint16_t pgt; + uint32_t rch_freq,goal_freq; + rch_freq=(64000000/8); + goal_freq=(1000000*EFUSE_1US_TIMES/us); + if(rch_freq<=goal_freq) + pgt=0; + else + pgt=rch_freq/goal_freq-1; + MODIFY_REG(EFUSEx->PGCFG,EFUSE_PGCFG_PGT,pgt<SR & flag) + return SET; + else + return RESET; + +} +/****************************************************************************** +*@brief : Clear state of flag in EFUSE SR register +*@param : EFUSEx: where x can be (1..2) to select the EFUSE peripheral. +*@param : flag: EFUSE_UNPG_FLAG/EFUSE_DONE_FLAG +*@return: None +******************************************************************************/ +void HAL_EFUSE_ClrState(EFUSE_TypeDef *EFUSEx, uint32_t flag) +{ + assert_param(IS_EFUSE_ALL_INSTANCE(EFUSEx)); + assert_param(IS_EFUSE_CLR_FLAG(flag)); + EFUSEx->CLR = flag; + +} +#endif /* HAL_EFUSE_MODULE_ENABLED */ + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_eth.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_eth.c new file mode 100644 index 0000000000000000000000000000000000000000..a1d5283b8d78ceb56f1cb81394e489336ed5cb10 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_eth.c @@ -0,0 +1,4663 @@ +/****************************************************************************** +*@file : hal_eth.c +*@brief : ETH HAL module driver. +******************************************************************************/ +#include "math.h" +#include "hal.h" + +#ifdef HAL_ETH_MODULE_ENABLED + +static HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); +static HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_TestDelay(void); +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tempreg; + uint32_t timeout; + + assert_param(heth); + + if (heth->State == HAL_ETH_STATE_RESET) + { + HAL_ETH_MspInit(heth); + } + + heth->State = HAL_ETH_STATE_BUSY; + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + // Mediaӿѡ + if (heth->Init.MediaInterface == ETH_MEDIA_INTERFACE_MII) + SYSCFG->SYSCR &= ~SYSCFG_SYSCR_EPIS; + else if (heth->Init.MediaInterface == ETH_MEDIA_INTERFACE_RMII) + SYSCFG->SYSCR = (SYSCFG->SYSCR & ~SYSCFG_SYSCR_EPIS) | SYSCFG_SYSCR_EPIS_2; + else + return HAL_ERROR; + + SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SWR); + timeout = ETH_TIMEOUT_SWRESET; + while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SWR) != (uint32_t)RESET) + { + if(--timeout == 0) + { + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + heth->State= HAL_ETH_STATE_ERROR; + return HAL_ERROR; + } + } + + HAL_ETH_RxClockDelayConfig(heth, heth->Init.Delay.Uint, heth->Init.Delay.Len); + + if (HAL_ETH_SetMACAddrConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetSpeedConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetDuplexModeConfig(heth) != HAL_OK) + return HAL_ERROR; + + // SMIʱ + if (HAL_ETH_ConfigSMI(heth) != HAL_OK) + return HAL_ERROR; + + if (HAL_ETH_SetMACConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetDMAConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetAddrFilterConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetVLANFilterConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetL3L4FilterConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetMMCConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetPMTConfig(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_SetPTPConfig(heth) != HAL_OK) + return HAL_ERROR; + + /* Set Receive Buffs Len (must be a multiple of 4) */ + if ((heth->Init.RxBuffLen % 0x4U) != 0x0U) + { + heth->ErrorCode = HAL_ETH_ERROR_PARAM; + heth->State = HAL_ETH_STATE_ERROR; + return HAL_ERROR; + } + + if (HAL_ETH_DMATxDescListInit(heth) != HAL_OK) + return HAL_ERROR; + if (HAL_ETH_DMARxDescListInit(heth) != HAL_OK) + return HAL_ERROR; + + heth->ErrorCode = HAL_ETH_ERROR_NONE; + heth->State = HAL_ETH_STATE_READY; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + heth->State = HAL_ETH_STATE_BUSY; + + HAL_ETH_MspDeInit(heth); + + heth->State= HAL_ETH_STATE_RESET; + + return HAL_OK; +} + +__attribute__((weak)) void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ +} + +__attribute__((weak)) void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ +} + + + +HAL_StatusTypeDef HAL_ETH_InitDefaultParamter(ETH_HandleTypeDef *heth) +{ + memset((void *)heth, 0, sizeof(ETH_HandleTypeDef)); + + heth->Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; + heth->Init.AutoNegotiation = ENABLE; + heth->Init.PhyAddress = 0; + + HAL_ETH_InitSpeedDefaultParamter(heth); + + HAL_ETH_InitDuplexModeDefaultParamter(heth); + + HAL_ETH_InitMACAddrDefaultParamter(heth); + + // + HAL_ETH_InitFilterDefaultParamter(heth); + + // MMC + HAL_ETH_InitMMCDefaultParamter(heth); + + // PMT + HAL_ETH_InitPMTDefaultParamter(heth); + + // PTP + HAL_ETH_InitPTPDefaultParamter(heth); + + // LPI + HAL_ETH_SetLPIDefaultConfig(heth); + + // MACĬֵ + HAL_ETH_InitMACDefaultParamter(heth); + + // DMAĬֵ + HAL_ETH_InitDMADefaultParamter(heth); + + return HAL_OK; +} + +// **************************************************************************** +// +// Speed +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitSpeedDefaultParamter(ETH_HandleTypeDef *heth) +{ + heth->Init.Speed = ETH_SPEED_100M; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetSpeedConfig(ETH_HandleTypeDef *heth) +{ + if ((heth->Instance)->MACCR & ETH_MACCR_FES) + heth->Init.Speed = ETH_SPEED_100M; + else + heth->Init.Speed = ETH_SPEED_10M; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetSpeedConfig(ETH_HandleTypeDef *heth) +{ + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + + if (heth->Init.Speed == ETH_SPEED_100M) + (heth->Instance)->MACCR |= ETH_MACCR_FES; + else + (heth->Instance)->MACCR &= ~ETH_MACCR_FES; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetSpeedDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitSpeedDefaultParamter(heth); + HAL_ETH_SetSpeedConfig(heth); + + return HAL_OK; +} + +// **************************************************************************** +// +// Duplex Mode +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitDuplexModeDefaultParamter(ETH_HandleTypeDef *heth) +{ + heth->Init.DuplexMode = ETH_MODE_FULL_DUPLEX; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetDuplexModeConfig(ETH_HandleTypeDef *heth) +{ + if ((heth->Instance)->MACCR & ETH_MACCR_DM) + heth->Init.DuplexMode = ETH_MODE_FULL_DUPLEX; + else + heth->Init.DuplexMode = ETH_MODE_HALF_DUPLEX; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetDuplexModeConfig(ETH_HandleTypeDef *heth) +{ + assert_param(IS_ETH_SPEED(heth->Init.DuplexMode)); + + if (heth->Init.DuplexMode != ETH_MODE_HALF_DUPLEX) + (heth->Instance)->MACCR |= ETH_MACCR_DM; + else + (heth->Instance)->MACCR &= ~ETH_MACCR_DM; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetDuplexModeDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitDuplexModeDefaultParamter(heth); + HAL_ETH_SetDuplexModeConfig(heth); + + return HAL_OK; +} + + +// **************************************************************************** +// +// MAC Address +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitMACAddrDefaultParamter(ETH_HandleTypeDef *heth) +{ + memset((void *)heth->Init.MACAddr, 0xffu, 6); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetMACAddrConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + tmpreg = (heth->Instance)->MACA0HR; + heth->Init.MACAddr[5] = (tmpreg >> 8) & 0xffu; + heth->Init.MACAddr[4] = (tmpreg >> 0) & 0xffu; + + tmpreg = (heth->Instance)->MACA0LR; + heth->Init.MACAddr[3] = (tmpreg >> 24) & 0xffu; + heth->Init.MACAddr[2] = (tmpreg >> 16) & 0xffu; + heth->Init.MACAddr[1] = (tmpreg >> 8) & 0xffu; + heth->Init.MACAddr[0] = (tmpreg >> 0) & 0xffu; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetMACAddrConfig(ETH_HandleTypeDef *heth) +{ + (heth->Instance)->MACA0HR = ETH_MACA0HR_AE | \ + ((uint32_t)heth->Init.MACAddr[5] << 8) | \ + ((uint32_t)heth->Init.MACAddr[4] << 0); + + // MACA1LR + (heth->Instance)->MACA0LR = ((uint32_t)heth->Init.MACAddr[3] << 24) | \ + ((uint32_t)heth->Init.MACAddr[2] << 16) | \ + ((uint32_t)heth->Init.MACAddr[1] << 8) | \ + ((uint32_t)heth->Init.MACAddr[0] << 0); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetMACAddrDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitMACAddrDefaultParamter(heth); + HAL_ETH_SetMACAddrConfig(heth); + + return HAL_OK; +} + + +// **************************************************************************** +// +// Interrupt +// +// **************************************************************************** + +#include "main.h" +__attribute__((weak)) void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_MMCCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_LPISendEntryCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_LPISendExitCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_LPIRecvEntryCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_LPIRecvExitCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +__attribute__((weak)) void HAL_ETH_WakeupCallback(ETH_HandleTypeDef *heth) +{ + (void)(heth); +} + +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + volatile uint32_t temp; + + /* Frame received */ + if (ETH->DMASR & ETH_DMASR_RS) + { + if (ETH->DMAIER & ETH_DMAIER_RIE) + { + HAL_ETH_RxCpltCallback(heth); + + ETH->DMASR = ETH_DMASR_RS | ETH_DMASR_NIS; + return; + } + } + + /* Frame transmitted */ + if (ETH->DMASR & ETH_DMASR_TS) + { + if (ETH->DMAIER & ETH_DMAIER_TIE) + { + HAL_ETH_TxCpltCallback(heth); + + ETH->DMASR = ETH_DMASR_TS | ETH_DMASR_NIS; + return; + } + } + + /* ETH DMA Error */ + if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMASR_AIS)) + { + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMAIER_AISE)) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + + if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMASR_FBES)) + { + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_RPSS | ETH_DMASR_TPSS)); + + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE); + + __HAL_ETH_DMA_CLEAR_FLAG(heth, ETH_DMASR_FBES | ETH_DMASR_RPSS | ETH_DMASR_TPSS | ETH_DMASR_AIS); + + heth->State = HAL_ETH_STATE_ERROR; + } + else + { + + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, ( ETH_DMASR_ETS | ETH_DMASR_RWTS | ETH_DMASR_RBUS | \ + ETH_DMASR_TUS | ETH_DMASR_ROS | ETH_DMASR_TJTS)); + + __HAL_ETH_DMA_CLEAR_FLAG(heth, ETH_DMASR_ETS | ETH_DMASR_RWTS | ETH_DMASR_RBUS | ETH_DMASR_TUS | \ + ETH_DMASR_ROS | ETH_DMASR_TJTS | ETH_DMASR_AIS); + } + + HAL_ETH_DMAErrorCallback(heth); + } + } + #ifdef ETH_PMT_SUPPORT + if (READ_BIT(heth->Instance->MACISR, ETH_MACISR_PMTS)) + { + if (READ_BIT(heth->Instance->MACIMR, ETH_MACIMR_PIM) == 0) + { + temp = (heth->Instance)->MACPMTCSR; + } + } + #endif + #ifdef ETH_MMC_SUPPORT + if (READ_BIT(heth->Instance->MMCTIR, ETH_MMCTIR_TGFIS)) + { + if (READ_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFIM) == 0) + { + heth->MMCCounter.TxGoodFrame = (heth->Instance)->MMCTGFCR; + } + } + if (READ_BIT(heth->Instance->MMCRIR, ETH_MMCRIR_RGUFIS)) + { + if (READ_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFIM) == 0) + { + heth->MMCCounter.RxGoodUnicast = (heth->Instance)->MMCRGUFCR; + } + } + #endif + #ifdef ETH_LPI_SUPPORT + if (READ_BIT(heth->Instance->DMASR, ETH_DMASR_LPIS)) + { + temp = heth->Instance->MACLPICSR; + if (temp & ETH_MACLPICSR_TLPIEN) + { + HAL_ETH_LPISendEntryCallback(heth); + } + if (temp & ETH_MACLPICSR_TLPIEX) + { + HAL_ETH_LPISendExitCallback(heth); + } + if (temp & ETH_MACLPICSR_RLPIEN) + { + HAL_ETH_LPIRecvEntryCallback(heth); + } + if (temp & ETH_MACLPICSR_RLPIEX) + { + HAL_ETH_LPIRecvExitCallback(heth); + } + } + #endif + +} + +void HAL_ETH_WakeupIRQHandler(ETH_HandleTypeDef *heth) +{ + volatile uint32_t temp; + + temp = (heth->Instance)->MACPMTCSR; + + /* Enable the DMA reception */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; + /* Enable the DMA transmission */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; + /* Enable the MAC transmission */ + (heth->Instance)->MACCR |= ETH_MACCR_TE; + + HAL_ETH_WakeupCallback(heth); +} + +// **************************************************************************** +// +// data transmission +// +// **************************************************************************** + +//ʼ +static HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + uint32_t i; + uint32_t buff; + ETH_DMADescTypeDef *tx_desc; + + if (heth->Init.TxDescNbr == 0) + return HAL_ERROR; + + if (heth->Init.TxBuffNbr != 0) + { + if (heth->Init.TxDescListMode == ETH_DESC_LIST_MODE_RING) + { + if (heth->Init.TxBuffNbr < (heth->Init.TxDescNbr << 1)) + return HAL_ERROR; + } + else + { + if (heth->Init.TxBuffNbr < heth->Init.TxDescNbr) + return HAL_ERROR; + } + } + + buff = (uint32_t)heth->Init.TxBuff; + + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; iInit.TxDescNbr; i++) + { + tx_desc = heth->Init.TxDesc + i; + + WRITE_REG(tx_desc->DESC0, 0); + WRITE_REG(tx_desc->DESC1, 0); + WRITE_REG(tx_desc->DESC2, 0); + WRITE_REG(tx_desc->DESC3, 0); + WRITE_REG(tx_desc->DESC4, 0); + WRITE_REG(tx_desc->DESC5, 0); + WRITE_REG(tx_desc->DESC6, 0); + WRITE_REG(tx_desc->DESC7, 0); + WRITE_REG(tx_desc->Buff1, 0); + WRITE_REG(tx_desc->Buff2, 0); + + if (heth->Init.TxDescListMode == ETH_DESC_LIST_MODE_RING) + { + if (i == (heth->Init.TxDescNbr - 1)) + SET_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_TER); + + if (heth->Init.TxBuffNbr != 0) + { + WRITE_REG(tx_desc->Buff1, buff + (heth->Init.TxBuffLen * (i << 1))); + WRITE_REG(tx_desc->Buff2, buff + (heth->Init.TxBuffLen * ((i << 1) + 1))); + } + + if ((heth->Init.TxBuffTab != 0) && (heth->Init.TxBuffNodeNbr != 0)) + { + heth->Init.TxBuffTab[(i << 1) + 0].Buff = (uint8_t *)tx_desc->Buff1; + heth->Init.TxBuffTab[(i << 1) + 0].Len = 0; + heth->Init.TxBuffTab[(i << 1) + 0].next = 0; + heth->Init.TxBuffTab[(i << 1) + 1].Buff = (uint8_t *)tx_desc->Buff2; + heth->Init.TxBuffTab[(i << 1) + 1].Len = 0; + heth->Init.TxBuffTab[(i << 1) + 1].next = 0; + } + } + else + { + SET_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_TCH); + + // next desc + if (i == (heth->Init.TxDescNbr - 1)) + WRITE_REG(tx_desc->DESC3, (uint32_t)heth->Init.TxDesc); + else + WRITE_REG(tx_desc->DESC3, (uint32_t)(tx_desc + 1)); + + if (heth->Init.TxBuffNbr != 0) + WRITE_REG(tx_desc->Buff1, buff + (heth->Init.TxBuffLen * i)); + + WRITE_REG(tx_desc->Buff2, tx_desc->DESC3); + + if ((heth->Init.TxBuffTab != 0) && (heth->Init.TxBuffNodeNbr != 0)) + { + heth->Init.TxBuffTab[i].Buff = (uint8_t *)tx_desc->Buff1; + heth->Init.TxBuffTab[i].Len = 0; + heth->Init.TxBuffTab[i].next = 0; + } + } + } + + heth->TxDescList.TxDescTab = heth->Init.TxDesc; + heth->TxDescList.CurTxDesc = 0; + + /* Set Transmit Descriptor List Address Register */ + (heth->Instance)->DMATDLAR = (uint32_t)heth->Init.TxDesc; + + return HAL_OK; +} + +//ʼ +static HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) +{ + uint32_t i; + uint32_t buff_addr; + ETH_DMADescTypeDef *rx_desc; + + if ((heth->Init.RxDescNbr == 0) || (heth->Init.RxBuffTab == 0)) + return HAL_ERROR; + + if (heth->Init.RxDescListMode == ETH_DESC_LIST_MODE_RING) + { + if (heth->Init.RxBuffNbr < (heth->Init.RxDescNbr << 1)) + return HAL_ERROR; + if (heth->Init.RxBuffNodeNbr < (heth->Init.RxDescNbr << 1)) + return HAL_ERROR; + } + else + { + if (heth->Init.RxBuffNbr < heth->Init.RxDescNbr) + return HAL_ERROR; + if (heth->Init.RxBuffNodeNbr < heth->Init.RxDescNbr) + return HAL_ERROR; + } + + buff_addr = (uint32_t)heth->Init.RxBuff; + + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; iInit.RxDescNbr; i++) + { + rx_desc = heth->Init.RxDesc + i; + + WRITE_REG(rx_desc->DESC0, 0); + WRITE_REG(rx_desc->DESC1, 0); + WRITE_REG(rx_desc->DESC2, 0); + WRITE_REG(rx_desc->DESC3, 0); + WRITE_REG(rx_desc->DESC4, 0); + WRITE_REG(rx_desc->DESC5, 0); + WRITE_REG(rx_desc->DESC6, 0); + WRITE_REG(rx_desc->DESC7, 0); + WRITE_REG(rx_desc->Buff1, 0); + WRITE_REG(rx_desc->Buff2, 0); + + if (heth->Int.Rx == DISABLE) + SET_BIT(rx_desc->DESC0, ETH_DMA_RX_DESC1_DIC); + + if (heth->Init.RxDescListMode == ETH_DESC_LIST_MODE_RING) + { + if (i == (heth->Init.RxDescNbr - 1)) + SET_BIT(rx_desc->DESC1, ETH_DMA_RX_DESC1_RER); + + // buff len + MODIFY_REG(rx_desc->DESC1, ETH_DMA_RX_DESC1_RBS1, (heth->Init.RxBuffLen << ETH_DMA_RX_DESC1_RBS1_Pos)); + MODIFY_REG(rx_desc->DESC1, ETH_DMA_RX_DESC1_RBS2, (heth->Init.RxBuffLen << ETH_DMA_RX_DESC1_RBS2_Pos)); + + // rx buff + WRITE_REG(rx_desc->DESC2, buff_addr + (heth->Init.RxBuffLen * (i << 1))); + WRITE_REG(rx_desc->DESC3, buff_addr + (heth->Init.RxBuffLen * ((i << 1) + 1))); + + heth->Init.RxBuffTab[(i << 1) + 0].Buff = (uint8_t *)rx_desc->DESC2; + heth->Init.RxBuffTab[(i << 1) + 0].Len = 0; + heth->Init.RxBuffTab[(i << 1) + 0].next = 0; + heth->Init.RxBuffTab[(i << 1) + 1].Buff = (uint8_t *)rx_desc->DESC3; + heth->Init.RxBuffTab[(i << 1) + 1].Len = 0; + heth->Init.RxBuffTab[(i << 1) + 1].next = 0; + } + else + { + SET_BIT(rx_desc->DESC1, ETH_DMA_RX_DESC1_RCH); + + // next desc + if (i == (heth->Init.RxDescNbr - 1)) + WRITE_REG(rx_desc->DESC3, (uint32_t)heth->Init.RxDesc); + else + WRITE_REG(rx_desc->DESC3, (uint32_t)(rx_desc + 1)); + + // buff len + MODIFY_REG(rx_desc->DESC1, ETH_DMA_RX_DESC1_RBS1, (heth->Init.RxBuffLen << ETH_DMA_RX_DESC1_RBS1_Pos)); + + // rx buff + WRITE_REG(rx_desc->DESC2, buff_addr + (heth->Init.RxBuffLen * i)); + + heth->Init.RxBuffTab[i].Buff = (uint8_t *)rx_desc->DESC2; + heth->Init.RxBuffTab[i].Len = 0; + heth->Init.RxBuffTab[i].next = 0; + } + + WRITE_REG(rx_desc->Buff1, rx_desc->DESC2); + WRITE_REG(rx_desc->Buff2, rx_desc->DESC3); + + SET_BIT(rx_desc->DESC0, ETH_DMA_RX_DESC0_OWN); + + } + + heth->RxDescList.RxDescTab = heth->Init.RxDesc; + heth->RxDescList.CurRxDesc = 0; + heth->RxDescList.FirstRxDesc = 0; + heth->RxDescList.RxDescNbr = 0; + + /* Set Transmit Descriptor List Address Register */ + (heth->Instance)->DMARDLAR = (uint32_t)heth->Init.RxDesc; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetTxBuff(ETH_HandleTypeDef *heth, ETH_BuffTypeDef **buff) +{ + uint32_t i; + uint32_t index; + uint32_t tx_buff_index; + uint32_t tx_buff_next_index; + uint32_t tx_buff_first_index; + ETH_InitTypeDef *init; + ETH_BuffTypeDef *tx_buff; + ETH_TxDescListTypeDef *tx_desc_list; + ETH_DMADescTypeDef *tx_desc; + uint32_t timeout; + + if ((heth == NULL) || (buff == NULL)) + return HAL_ERROR; + + init = &heth->Init; + + tx_desc_list = (ETH_TxDescListTypeDef *)&heth->TxDescList; + index = tx_desc_list->CurTxDesc; + tx_desc = &tx_desc_list->TxDescTab[index]; + + if (init->TxDescListMode == ETH_DESC_LIST_MODE_RING) + *buff = &init->TxBuffTab[index << 1]; + else + *buff = &init->TxBuffTab[index]; + tx_buff = init->TxBuffTab; + for (i=0; iTxDescNbr; i++) + { + if (READ_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_OWN)) + break; + + if (init->TxDescListMode == ETH_DESC_LIST_MODE_RING) + { + tx_buff_index = index << 1; + tx_buff_next_index = tx_buff_index; + if (++tx_buff_next_index >= init->TxBuffNodeNbr) + tx_buff_next_index = 0; + + tx_buff[tx_buff_index].Buff = (uint8_t *)tx_desc->Buff1; + tx_buff[tx_buff_index].Len = init->TxBuffLen; + tx_buff[tx_buff_index].next = &init->TxBuffTab[tx_buff_next_index]; + + tx_buff_index = tx_buff_next_index; + if (++tx_buff_next_index >= init->TxBuffNodeNbr) + tx_buff_next_index = 0; + + tx_buff[tx_buff_index].Buff = (uint8_t *)tx_desc->Buff1; + tx_buff[tx_buff_index].Len = init->TxBuffLen; + tx_buff[tx_buff_index].next = &init->TxBuffTab[tx_buff_next_index]; + } + else + { + tx_buff_index = index; + tx_buff_next_index = tx_buff_index; + if (++tx_buff_next_index >= init->TxBuffNodeNbr) + tx_buff_next_index = 0; + + tx_buff[tx_buff_index].Buff = (uint8_t *)tx_desc->Buff1; + tx_buff[tx_buff_index].Len = init->TxBuffLen; + tx_buff[tx_buff_index].next = &init->TxBuffTab[tx_buff_next_index]; + } + + index++; + if (index >= init->TxDescNbr) + index = 0; + tx_desc = &tx_desc_list->TxDescTab[index]; + } + if (i == 0) + *buff = 0; + else + tx_buff[tx_buff_index].next = 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_BuffTypeDef *buff, uint32_t mode, ETH_TxStatusTypeDef *pStatus) +{ + uint32_t i; + uint32_t len; + uint32_t index; + uint32_t nbr; + uint32_t desc0; + ETH_InitTypeDef *init; + ETH_TxDescListTypeDef *tx_desc_list; + ETH_DMADescTypeDef *tx_desc; + ETH_TxConfigTypeDef *pTxConfig; + uint32_t timeout; + + if ((heth == NULL) || (buff == NULL) || (buff->Buff == NULL) || (buff->Len == 0)) + return HAL_ERROR; + + init = &heth->Init; + + if ((mode & ETH_TX_MODE_DATA_COPY) && (init->TxBuffNbr == 0)) + return HAL_ERROR; + + nbr = 0; + tx_desc_list = (ETH_TxDescListTypeDef *)&heth->TxDescList; + index = tx_desc_list->CurTxDesc; + tx_desc = &tx_desc_list->TxDescTab[index]; + pTxConfig = &heth->TxConfig; + + for (i=0; iTxDescNbr; i++) + { + if (READ_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_OWN)) + return HAL_BUSY; + +// desc0 = tx_desc->DESC0 & (ETH_DMA_TX_DESC0_TER | ETH_DMA_TX_DESC0_TCH); + desc0 = 0; + if (mode & (ETH_TX_MODE_WAIT_TX_COMPLETE | ETH_TX_MODE_TIMESTAMP)) + { + SET_BIT(heth->Instance->DMAIER , ETH_DMAIER_NISE | ETH_DMAIER_TIE); + } + SET_BIT(desc0, ETH_DMA_TX_DESC0_IC); + + + MODIFY_REG(desc0, ETH_DMA_TX_DESC0_CIC, (uint32_t)pTxConfig->AutoChecksum << ETH_DMA_TX_DESC0_CIC_Pos); + + if (init->TxDescListMode != ETH_DESC_LIST_MODE_RING) + SET_BIT(desc0, ETH_DMA_TX_DESC0_TCH); + else if (index == (init->TxDescNbr - 1)) + SET_BIT(desc0, ETH_DMA_TX_DESC0_TER); + + if (nbr == 0) + { + SET_BIT(desc0, ETH_DMA_TX_DESC0_FS); + if (pTxConfig->AutoCRC == 0) + SET_BIT(desc0, ETH_DMA_TX_DESC0_DC); + if (pTxConfig->AutoPad == 0) + SET_BIT(desc0, ETH_DMA_TX_DESC0_DP); + if (mode & ETH_TX_MODE_TIMESTAMP) + SET_BIT(desc0, ETH_DMA_TX_DESC0_TTSE); + } + WRITE_REG(tx_desc->DESC0, desc0); + + // buff1 len + if (buff->Len > init->TxBuffLen) + len = init->TxBuffLen; + else + len = buff->Len; + buff->Len -= len; + WRITE_REG(tx_desc->DESC1, len << ETH_DMA_TX_DESC1_TBS1_Pos); + + // buffer 1 + if (mode & ETH_TX_MODE_DATA_COPY) + { + // copy + WRITE_REG(tx_desc->DESC2, tx_desc->Buff1); + memcpy((void *)tx_desc->DESC2, (void *)buff->Buff, len); + } + else + { + // ַcopy + WRITE_REG(tx_desc->DESC2, (uint32_t)buff->Buff); + } + buff->Buff += len; + + while (1) + { + if ((buff->Len != 0) || (buff->next == 0)) + break; + buff = buff->next; + } + + // buffer 2 + if (init->TxDescListMode == ETH_DESC_LIST_MODE_RING) + { + if (buff->Len != 0) + { + // buff2 len + if (buff->Len > init->TxBuffLen) + len = init->TxBuffLen; + else + len = buff->Len; + buff->Len -= len; + MODIFY_REG(tx_desc->DESC1, ETH_DMA_TX_DESC1_TBS2, (len << ETH_DMA_TX_DESC1_TBS2_Pos)); + + if (mode & ETH_TX_MODE_DATA_COPY) + { + // ֵcopy + WRITE_REG(tx_desc->DESC3, tx_desc->Buff2); + memcpy((void *)tx_desc->DESC3, (void *)buff->Buff, len); + } + else + { + // ַcopy + WRITE_REG(tx_desc->DESC3, (uint32_t)buff->Buff); + } + buff->Buff += len; + + while (1) + { + if ((buff->Len != 0) || (buff->next == 0)) + break; + buff = buff->next; + } + } + } + nbr++; + + if (buff->Len == 0) + break; + + index++; + if (index >= init->TxDescNbr) + index = 0; + tx_desc = &tx_desc_list->TxDescTab[index]; + } + SET_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_LS); + + index = tx_desc_list->CurTxDesc; + tx_desc = &tx_desc_list->TxDescTab[index]; + while (nbr--) + { + SET_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_OWN); + + index++; + if (index >= init->TxDescNbr) + index = 0; + tx_desc = &tx_desc_list->TxDescTab[index]; + } + tx_desc_list->CurTxDesc = index; + + (heth->Instance)->DMASR = ETH_DMASR_TBUS; + (heth->Instance)->DMATPDR = 0; + + // ȴ + if (mode & (ETH_TX_MODE_WAIT_TX_COMPLETE | ETH_TX_MODE_TIMESTAMP)) + { + index = tx_desc_list->CurTxDesc; + if (index == 0) + index = init->TxDescNbr - 1; + else + index--; + tx_desc = &tx_desc_list->TxDescTab[index]; + + timeout = 0xffffffff; + while (1) + { + if (READ_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_OWN) == 0) + break; + timeout--; + if (timeout == 0) + return HAL_ERROR; + } + if (pStatus) + { + pStatus->Status0 = READ_REG(tx_desc->DESC0); + if (READ_BIT(tx_desc->DESC0, ETH_DMA_TX_DESC0_TTSS)) + { + pStatus->TimestampValid = ENABLE; + pStatus->Timestamp.sec = READ_REG(tx_desc->DESC7); + pStatus->Timestamp.nsec = (int32_t)READ_REG(tx_desc->DESC6); + } + else + { + pStatus->TimestampValid = DISABLE; + } + } + } + + return HAL_OK; +} + +/** + * @brief Checks for received Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval 1: A Packet is received + * 0: no Packet received + */ +HAL_StatusTypeDef HAL_ETH_Receive(ETH_HandleTypeDef *heth, ETH_BuffTypeDef **buff, ETH_RxStatusTypeDef *pStatus) +{ + uint32_t i; + uint32_t first_desc_index; + uint32_t desc_nbr; + uint32_t desc_index; + uint32_t first_rx_buff_index; + uint32_t curr_rx_buff_index; + uint32_t next_rx_buff_index; + uint32_t desc0; + uint32_t packet_len; + uint32_t desc_len; + uint32_t len; + ETH_InitTypeDef *init; + ETH_BuffTypeDef *rx_buff; + ETH_DMADescTypeDef *rx_desc; + ETH_RxDescListTypeDef *rx_desc_list; + + rx_desc_list = &heth->RxDescList; + + if(rx_desc_list->RxDescNbr != 0U) + return HAL_OK; + + *buff = 0; + init = &heth->Init; + rx_buff = init->RxBuffTab; + while (1) + { + desc_index = rx_desc_list->CurRxDesc; + desc_nbr = 0; + first_desc_index = 0; + rx_desc = &rx_desc_list->RxDescTab[desc_index]; + packet_len = 0; + desc_len = 0; + len = 0; + first_rx_buff_index = 0; + + for (i=0; iRxDescNbr; i++) + { + if (READ_BIT(rx_desc->DESC0, ETH_DMA_RX_DESC0_OWN)) + { + if (desc_nbr == 0) + return HAL_OK; + break; + } + + desc0 = READ_REG(rx_desc->DESC0); + + if (READ_BIT(desc0, ETH_DMA_RX_DESC0_LS)) + { + if (READ_BIT(desc0, ETH_DMA_RX_DESC0_FS)) + { + if (desc_nbr) + break; + desc_nbr = 1; + + first_desc_index = desc_index; + packet_len = (desc0 & ETH_DMA_RX_DESC0_FL) >> ETH_DMA_RX_DESC0_FL_Pos; + + if (init->RxDescListMode == ETH_DESC_LIST_MODE_RING) + first_rx_buff_index = desc_index << 1; + else + first_rx_buff_index = desc_index; + } + else + { + desc_nbr++; + if (desc_nbr == 1) + break; + + packet_len = (desc0 & ETH_DMA_RX_DESC0_FL) >> ETH_DMA_RX_DESC0_FL_Pos; + if (packet_len < len) + break; + packet_len -= len; + } + + if (init->RxDescListMode == ETH_DESC_LIST_MODE_RING) + { + if (packet_len > (init->RxBuffLen << 1)) + break; + + first_rx_buff_index = desc_index << 1; + + if (packet_len <= init->RxBuffLen) + { + rx_buff[curr_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[curr_rx_buff_index].Len = packet_len; + rx_buff[curr_rx_buff_index].next = 0; + } + else + { + packet_len -= init->RxBuffLen; + + next_rx_buff_index = curr_rx_buff_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[curr_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[curr_rx_buff_index].Len = init->RxBuffLen; + rx_buff[curr_rx_buff_index].next = &rx_buff[next_rx_buff_index]; + + rx_buff[next_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff2; + rx_buff[next_rx_buff_index].Len = packet_len; + rx_buff[next_rx_buff_index].next = 0; + } + } + else + { + if (packet_len > init->RxBuffLen) + break; + + rx_buff[desc_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[desc_index].Len = packet_len; + rx_buff[desc_index].next = 0; + } + + desc_index++; + if (desc_index >= init->RxDescNbr) + desc_index = 0; + + rx_desc_list->CurRxDesc = desc_index; + rx_desc_list->FirstRxDesc = first_desc_index; + rx_desc_list->RxDescNbr = 1; + + *buff = &init->RxBuffTab[first_rx_buff_index]; + if (pStatus) + { + pStatus->Status0 = rx_desc->DESC0; + if (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_EDFE)) + { + if (READ_BIT(rx_desc->DESC0, ETH_DMA_RX_DESC0_TSV)) + { + pStatus->TimestampValid = ENABLE; + pStatus->Timestamp.sec = rx_desc->DESC7; + pStatus->Timestamp.nsec = (int32_t)rx_desc->DESC6; + } + } + } + return HAL_OK; + } + else if (READ_BIT(desc0, ETH_DMA_RX_DESC0_FS)) + { + if (desc_nbr) + break; + desc_nbr = 1; + + first_desc_index = desc_index; + len = 0; + + if (init->RxDescListMode == ETH_DESC_LIST_MODE_RING) + { + len += init->RxBuffLen << 1; + + curr_rx_buff_index = desc_index << 1; + + next_rx_buff_index = curr_rx_buff_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[curr_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[curr_rx_buff_index].Len = init->RxBuffLen; + rx_buff[curr_rx_buff_index].next = &rx_buff[next_rx_buff_index]; + + curr_rx_buff_index = next_rx_buff_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[curr_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff2; + rx_buff[curr_rx_buff_index].Len = init->RxBuffLen; + rx_buff[curr_rx_buff_index].next = &rx_buff[next_rx_buff_index]; + } + else + { + len += init->RxBuffLen; + + next_rx_buff_index = desc_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[desc_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[desc_index].Len = init->RxBuffLen; + rx_buff[desc_index].next = &rx_buff[next_rx_buff_index]; + } + + desc_index++; + if (desc_index >= init->RxDescNbr) + desc_index = 0; + rx_desc = &rx_desc_list->RxDescTab[desc_index]; + } + else + { + desc_nbr++; + if (desc_nbr == 1) + break; + + if (init->RxDescListMode == ETH_DESC_LIST_MODE_RING) + { + len += init->RxBuffLen << 1; + + curr_rx_buff_index = desc_index << 1; + + next_rx_buff_index = curr_rx_buff_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[curr_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[curr_rx_buff_index].Len = init->RxBuffLen; + rx_buff[curr_rx_buff_index].next = &rx_buff[next_rx_buff_index]; + + curr_rx_buff_index = next_rx_buff_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[curr_rx_buff_index].Buff = (uint8_t *)rx_desc->Buff2; + rx_buff[curr_rx_buff_index].Len = init->RxBuffLen; + rx_buff[curr_rx_buff_index].next = &rx_buff[next_rx_buff_index]; + } + else + { + len += init->RxBuffLen; + + next_rx_buff_index = desc_index; + next_rx_buff_index++; + if (next_rx_buff_index >= init->RxBuffNodeNbr) + next_rx_buff_index = 0; + + rx_buff[desc_index].Buff = (uint8_t *)rx_desc->Buff1; + rx_buff[desc_index].Len = init->RxBuffLen; + rx_buff[desc_index].next = &rx_buff[next_rx_buff_index]; + } + + desc_index++; + if (desc_index >= init->RxDescNbr) + desc_index = 0; + rx_desc = &rx_desc_list->RxDescTab[desc_index]; + } + } + + desc_index = rx_desc_list->CurRxDesc; + rx_desc = &rx_desc_list->RxDescTab[desc_index]; + + while (desc_nbr--) + { + WRITE_REG(rx_desc->DESC2, rx_desc->Buff1); + WRITE_REG(rx_desc->DESC3, rx_desc->Buff2); + + SET_BIT(rx_desc->DESC0, ETH_DMA_RX_DESC0_OWN); + + desc_index++; + if (desc_index >= init->RxDescNbr) + desc_index = 0; + rx_desc = &rx_desc_list->RxDescTab[desc_index]; + } + + rx_desc_list->CurRxDesc = desc_index; + rx_desc_list->FirstRxDesc = 0; + rx_desc_list->RxDescNbr = 0; + } +} + + +/** +* @brief This function gives back Rx Desc of the last received Packet +* to the DMA, so ETH DMA will be able to use these descriptors +* to receive next Packets. +* It should be called after processing the received Packet. +* @param heth: pointer to a ETH_HandleTypeDef structure that contains +* the configuration information for ETHERNET module +* @retval HAL status. +*/ +HAL_StatusTypeDef HAL_ETH_ReleaseRxDescriptors(ETH_HandleTypeDef *heth) +{ + uint32_t desc_nbr; + uint32_t desc_index; + ETH_InitTypeDef *init; + ETH_DMADescTypeDef *rx_desc; + ETH_RxDescListTypeDef *rx_desc_list; + + rx_desc_list = &heth->RxDescList; + desc_nbr = rx_desc_list->RxDescNbr; + + if(desc_nbr == 0U) + return HAL_OK; + + init = &heth->Init; + + desc_index = rx_desc_list->FirstRxDesc; + + while (desc_nbr--) + { + rx_desc = &rx_desc_list->RxDescTab[desc_index]; + + WRITE_REG(rx_desc->DESC2, rx_desc->Buff1); + WRITE_REG(rx_desc->DESC3, rx_desc->Buff2); + + SET_BIT(rx_desc->DESC0, ETH_DMA_RX_DESC0_OWN); + + desc_index++; + if (desc_index >= init->RxDescNbr) + desc_index = 0; + } + + rx_desc_list->CurRxDesc = desc_index; + rx_desc_list->FirstRxDesc = 0; + rx_desc_list->RxDescNbr = 0; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +// ETHʼ +// hethETH_HandleTypeDefṹָ룻 +// ޣ +// HAL_OKɹ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +{ +// if (heth->State != HAL_ETH_STATE_RESET) +// return HAL_ERROR; + + heth->State = HAL_ETH_STATE_BUSY; + + /* Enable the MAC transmission */ + (heth->Instance)->MACCR |= ETH_MACCR_TE; + + /* Enable the MAC reception */ + (heth->Instance)->MACCR |= ETH_MACCR_RE; + + /* Set the Flush Transmit FIFO bit */ +// (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; + + /* Enable the DMA transmission */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; + + /* Enable the DMA reception */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; + + __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_AISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE)); + + heth->State= HAL_ETH_STATE_READY; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +// ETHֹͣ +// hethETH_HandleTypeDefṹָ룻 +// ޣ +// HAL_OKɹ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ +// if (heth->State != HAL_ETH_STATE_RESET) +// return HAL_ERROR; + + heth->State = HAL_ETH_STATE_BUSY; + + /* Disable the DMA transmission */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; + + /* Disable the DMA reception */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; + + /* Disable the MAC reception */ + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + + /* Set the Flush Transmit FIFO bit */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; + + /* Disable the MAC transmission */ + (heth->Instance)->MACCR &= ~ETH_MACCR_TE; + + heth->State = HAL_ETH_STATE_READY; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +// ȡ̫״̬ +// hethETH_HandleTypeDefṹָ룻 +// ޣ +// ̫״̬ +// ע +// **************************************************************************** + +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + /* Return ETH state */ + return heth->State; +} + +// **************************************************************************** +// +// Filter +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitAddrFilterDefaultParamter(ETH_HandleTypeDef *heth) +{ + ETH_AddrFilterTypeDef *pAddrFilterConfig = &heth->FilterConfig.Addr; + + // ַ + pAddrFilterConfig->Addr[0].Enable = DISABLE; + pAddrFilterConfig->Addr[0].GroupFilter = DISABLE; + pAddrFilterConfig->Addr[0].PerfectSourAddr = DISABLE; + pAddrFilterConfig->Addr[0].GroupMask = 0; + pAddrFilterConfig->Addr[0].Addr[0] = 0xFFU; + pAddrFilterConfig->Addr[0].Addr[1] = 0xFFU; + pAddrFilterConfig->Addr[0].Addr[2] = 0xFFU; + pAddrFilterConfig->Addr[0].Addr[3] = 0xFFU; + pAddrFilterConfig->Addr[0].Addr[4] = 0xFFU; + pAddrFilterConfig->Addr[0].Addr[5] = 0xFFU; + pAddrFilterConfig->Addr[1].Enable = DISABLE; + pAddrFilterConfig->Addr[1].GroupFilter = DISABLE; + pAddrFilterConfig->Addr[1].PerfectSourAddr = DISABLE; + pAddrFilterConfig->Addr[1].GroupMask = 0; + pAddrFilterConfig->Addr[1].Addr[0] = 0; + pAddrFilterConfig->Addr[1].Addr[1] = 0; + pAddrFilterConfig->Addr[1].Addr[2] = 0; + pAddrFilterConfig->Addr[1].Addr[3] = 0; + pAddrFilterConfig->Addr[1].Addr[4] = 0; + pAddrFilterConfig->Addr[1].Addr[5] = 0; + pAddrFilterConfig->Addr[2].Enable = DISABLE; + pAddrFilterConfig->Addr[2].GroupFilter = DISABLE; + pAddrFilterConfig->Addr[2].PerfectSourAddr = DISABLE; + pAddrFilterConfig->Addr[2].GroupMask = 0; + pAddrFilterConfig->Addr[2].Addr[0] = 0; + pAddrFilterConfig->Addr[2].Addr[1] = 0; + pAddrFilterConfig->Addr[2].Addr[2] = 0; + pAddrFilterConfig->Addr[2].Addr[3] = 0; + pAddrFilterConfig->Addr[2].Addr[4] = 0; + pAddrFilterConfig->Addr[2].Addr[5] = 0; + pAddrFilterConfig->ReceiveAll = DISABLE; + pAddrFilterConfig->HashPerfectFilter = DISABLE; + pAddrFilterConfig->SourceAddrFilter = DISABLE; + pAddrFilterConfig->SourceAddrInverseFilter = DISABLE; + pAddrFilterConfig->PassControlPackets = ETH_PASS_CONTROL_BLOCK_ALL; // ã֡˵пưֹǴﵽӦó + pAddrFilterConfig->BroadcastFramesReception = ENABLE; // ʹܣ㲥֡ + pAddrFilterConfig->PassAllMulticast = DISABLE; + pAddrFilterConfig->DestAddrInverseFilter = DISABLE; + pAddrFilterConfig->HushMulticastFramesFilter = DISABLE; + pAddrFilterConfig->HashUnicastFramesFilter = DISABLE; + pAddrFilterConfig->PromiscuousMode = DISABLE; + pAddrFilterConfig->HashTable[0] = 0; + pAddrFilterConfig->HashTable[1] = 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetAddrFilterConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_AddrFilterTypeDef *pAddrFilterConfig = &heth->FilterConfig.Addr; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pAddrFilterConfig, 0, sizeof(ETH_AddrFilterTypeDef)); + + // MACA1HR + tmpreg = (heth->Instance)->MACA1HR; + + if (tmpreg & ETH_MACA1HR_AE) + pAddrFilterConfig->Addr[0].Enable = ENABLE; + else + pAddrFilterConfig->Addr[0].Enable = DISABLE; + + if (tmpreg & ETH_MACA1HR_MBC) + { + pAddrFilterConfig->Addr[0].GroupFilter = ENABLE; + pAddrFilterConfig->Addr[0].GroupMask = (tmpreg & ETH_MACA1HR_MBC) >> ETH_MACA1HR_MBC_Pos; + } + else + { + pAddrFilterConfig->Addr[0].GroupFilter = DISABLE; + pAddrFilterConfig->Addr[0].GroupMask = 0; + } + + if (tmpreg & ETH_MACA1HR_SA) + pAddrFilterConfig->Addr[0].PerfectSourAddr = ENABLE; + else + pAddrFilterConfig->Addr[0].PerfectSourAddr = DISABLE; + + pAddrFilterConfig->Addr[0].Addr[5] = (tmpreg >> 8) & 0xff; + pAddrFilterConfig->Addr[0].Addr[4] = (tmpreg >> 0) & 0xff; + + // MACA1LR + tmpreg = (heth->Instance)->MACA1LR; + pAddrFilterConfig->Addr[0].Addr[3] = (tmpreg >> 24) & 0xff; + pAddrFilterConfig->Addr[0].Addr[2] = (tmpreg >> 16) & 0xff; + pAddrFilterConfig->Addr[0].Addr[1] = (tmpreg >> 8) & 0xff; + pAddrFilterConfig->Addr[0].Addr[0] = (tmpreg >> 0) & 0xff; + + // MACA2HR + tmpreg = (heth->Instance)->MACA2HR; + + if (tmpreg & ETH_MACA1HR_AE) + pAddrFilterConfig->Addr[1].Enable = ENABLE; + else + pAddrFilterConfig->Addr[1].Enable = DISABLE; + + if (tmpreg & ETH_MACA1HR_MBC) + { + pAddrFilterConfig->Addr[1].GroupFilter = ENABLE; + pAddrFilterConfig->Addr[1].GroupMask = (tmpreg & ETH_MACA1HR_MBC) >> ETH_MACA1HR_MBC_Pos; + } + else + { + pAddrFilterConfig->Addr[1].GroupFilter = DISABLE; + pAddrFilterConfig->Addr[1].GroupMask = 0; + } + + if (tmpreg & ETH_MACA1HR_SA) + pAddrFilterConfig->Addr[1].PerfectSourAddr = ENABLE; + else + pAddrFilterConfig->Addr[1].PerfectSourAddr = DISABLE; + + pAddrFilterConfig->Addr[1].Addr[5] = (tmpreg >> 8) & 0xff; + pAddrFilterConfig->Addr[1].Addr[4] = (tmpreg >> 0) & 0xff; + + // MACA2LR + tmpreg = (heth->Instance)->MACA2LR; + pAddrFilterConfig->Addr[1].Addr[3] = (tmpreg >> 24) & 0xff; + pAddrFilterConfig->Addr[1].Addr[2] = (tmpreg >> 16) & 0xff; + pAddrFilterConfig->Addr[1].Addr[1] = (tmpreg >> 8) & 0xff; + pAddrFilterConfig->Addr[1].Addr[0] = (tmpreg >> 0) & 0xff; + + // MACA3HR + tmpreg = (heth->Instance)->MACA3HR; + + if (tmpreg & ETH_MACA1HR_AE) + pAddrFilterConfig->Addr[2].Enable = ENABLE; + else + pAddrFilterConfig->Addr[2].Enable = DISABLE; + + if (tmpreg & ETH_MACA1HR_MBC) + { + pAddrFilterConfig->Addr[2].GroupFilter = ENABLE; + pAddrFilterConfig->Addr[2].GroupMask = (tmpreg & ETH_MACA1HR_MBC) >> ETH_MACA1HR_MBC_Pos; + } + else + { + pAddrFilterConfig->Addr[2].GroupFilter = DISABLE; + pAddrFilterConfig->Addr[2].GroupMask = 0; + } + + if (tmpreg & ETH_MACA1HR_SA) + pAddrFilterConfig->Addr[2].PerfectSourAddr = ENABLE; + else + pAddrFilterConfig->Addr[2].PerfectSourAddr = DISABLE; + + pAddrFilterConfig->Addr[2].Addr[5] = (tmpreg >> 8) & 0xff; + pAddrFilterConfig->Addr[2].Addr[4] = (tmpreg >> 0) & 0xff; + + // MACA3LR + tmpreg = (heth->Instance)->MACA3LR; + pAddrFilterConfig->Addr[2].Addr[3] = (tmpreg >> 24) & 0xff; + pAddrFilterConfig->Addr[2].Addr[2] = (tmpreg >> 16) & 0xff; + pAddrFilterConfig->Addr[2].Addr[1] = (tmpreg >> 8) & 0xff; + pAddrFilterConfig->Addr[2].Addr[0] = (tmpreg >> 0) & 0xff; + + // MACFFR + tmpreg = (heth->Instance)->MACFFR; + + if (tmpreg & ETH_MACFFR_RA) + pAddrFilterConfig->ReceiveAll = ENABLE; + else + pAddrFilterConfig->ReceiveAll = DISABLE; + + if (tmpreg & ETH_MACFFR_HPF) + pAddrFilterConfig->HashPerfectFilter = ENABLE; + else + pAddrFilterConfig->HashPerfectFilter = DISABLE; + + if (tmpreg & ETH_MACFFR_SAF) + pAddrFilterConfig->SourceAddrFilter = ENABLE; + else + pAddrFilterConfig->SourceAddrFilter = DISABLE; + + if (tmpreg & ETH_MACFFR_SAIF) + pAddrFilterConfig->SourceAddrInverseFilter = ENABLE; + else + pAddrFilterConfig->SourceAddrInverseFilter = DISABLE; + + if ((tmpreg & ETH_MACFFR_PCF) == 0) + pAddrFilterConfig->PassControlPackets = ETH_PASS_CONTROL_BLOCK_ALL; + else if ((tmpreg & ETH_MACFFR_PCF) == ETH_MACFFR_PCF_0) + pAddrFilterConfig->PassControlPackets = ETH_PASS_CONTROL_FORWARD_ALL_EXCEPT_PAUSE_FRAME; + else if ((tmpreg & ETH_MACFFR_PCF) == ETH_MACFFR_PCF_1) + pAddrFilterConfig->PassControlPackets = ETH_PASS_CONTROL_FORWARD_ALL; + else if ((tmpreg & ETH_MACFFR_PCF) == (ETH_MACFFR_PCF_1 | ETH_MACFFR_PCF_0)) + pAddrFilterConfig->PassControlPackets = ETH_PASS_CONTROL_FORWARD_PASSED_ADDR_FILTER; + + if (tmpreg & ETH_MACFFR_DBF) + pAddrFilterConfig->BroadcastFramesReception = DISABLE; + else + pAddrFilterConfig->BroadcastFramesReception = ENABLE; + + if (tmpreg & ETH_MACFFR_PAM) + pAddrFilterConfig->PassAllMulticast = ENABLE; + else + pAddrFilterConfig->PassAllMulticast = DISABLE; + + if (tmpreg & ETH_MACFFR_DAIF) + pAddrFilterConfig->DestAddrInverseFilter = ENABLE; + else + pAddrFilterConfig->DestAddrInverseFilter = DISABLE; + + if (tmpreg & ETH_MACFFR_HMC) + pAddrFilterConfig->HushMulticastFramesFilter = ENABLE; + else + pAddrFilterConfig->HushMulticastFramesFilter = DISABLE; + + if (tmpreg & ETH_MACFFR_HUC) + pAddrFilterConfig->HashUnicastFramesFilter = ENABLE; + else + pAddrFilterConfig->HashUnicastFramesFilter = DISABLE; + + if (tmpreg & ETH_MACFFR_PR) + pAddrFilterConfig->PromiscuousMode = ENABLE; + else + pAddrFilterConfig->PromiscuousMode = DISABLE; + + // MACHTHR + pAddrFilterConfig->HashTable[1] = (heth->Instance)->MACHTHR; + + // MACHTLR + pAddrFilterConfig->HashTable[0] = (heth->Instance)->MACHTLR; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// MAC +// hethETH_HandleTypeDefṹָ룻 +// dmaconfýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetAddrFilterConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_AddrFilterTypeDef *pAddrFilterConfig = &heth->FilterConfig.Addr; + + if (heth == NULL) + return (HAL_ERROR); + + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[0].Enable)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[1].Enable)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[2].Enable)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->ReceiveAll)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->HashPerfectFilter)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->SourceAddrFilter)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->SourceAddrInverseFilter)); + assert_param(IS_ETH_PASS_CONTROL_PACKETS(pAddrFilterConfig->PassControlPackets)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->BroadcastFramesReception)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->PassAllMulticast)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->DestAddrInverseFilter)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->HushMulticastFramesFilter)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->HashUnicastFramesFilter)); + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->PromiscuousMode)); + + // MACA1HR + if (pAddrFilterConfig->Addr[0].Enable == DISABLE) + { + (heth->Instance)->MACA1HR = 0; + (heth->Instance)->MACA1LR = 0; + } + else + { + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[0].GroupFilter)); + + tmpreg = ETH_MACA1HR_AE; + if (pAddrFilterConfig->Addr[0].GroupFilter == DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[0].PerfectSourAddr)); + + if (pAddrFilterConfig->Addr[0].PerfectSourAddr != DISABLE) + tmpreg |= ETH_MACA1HR_SA; + } + else + { + assert_param(IS_ETH_ADDR_FILTER_GROUP_MASK(pAddrFilterConfig->Addr[0].GroupMask)); + + tmpreg |= pAddrFilterConfig->Addr[0].GroupMask << ETH_MACA1HR_MBC_Pos; + } + + (heth->Instance)->MACA1HR = tmpreg | \ + ((uint32_t)pAddrFilterConfig->Addr[0].Addr[5] << 8) | \ + ((uint32_t)pAddrFilterConfig->Addr[0].Addr[4] << 0); + + // MACA1LR + (heth->Instance)->MACA1LR = ((uint32_t)pAddrFilterConfig->Addr[0].Addr[3] << 24) | \ + ((uint32_t)pAddrFilterConfig->Addr[0].Addr[2] << 16) | \ + ((uint32_t)pAddrFilterConfig->Addr[0].Addr[1] << 8) | \ + ((uint32_t)pAddrFilterConfig->Addr[0].Addr[0] << 0); + } + + // MACA1HR + if (pAddrFilterConfig->Addr[1].Enable == DISABLE) + { + (heth->Instance)->MACA2HR = 0; + (heth->Instance)->MACA2LR = 0; + } + else + { + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[1].GroupFilter)); + + tmpreg = ETH_MACA2HR_AE; + if (pAddrFilterConfig->Addr[1].GroupFilter == DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[1].PerfectSourAddr)); + + if (pAddrFilterConfig->Addr[1].PerfectSourAddr != DISABLE) + tmpreg |= ETH_MACA2HR_SA; + } + else + { + assert_param(IS_ETH_ADDR_FILTER_GROUP_MASK(pAddrFilterConfig->Addr[1].GroupMask)); + + tmpreg |= pAddrFilterConfig->Addr[1].GroupMask << ETH_MACA2HR_MBC_Pos; + } + + (heth->Instance)->MACA2HR = tmpreg | \ + ((uint32_t)pAddrFilterConfig->Addr[1].Addr[5] << 8) | \ + ((uint32_t)pAddrFilterConfig->Addr[1].Addr[4] << 0); + + // MACA2LR + (heth->Instance)->MACA2LR = ((uint32_t)pAddrFilterConfig->Addr[1].Addr[3] << 24) | \ + ((uint32_t)pAddrFilterConfig->Addr[1].Addr[2] << 16) | \ + ((uint32_t)pAddrFilterConfig->Addr[1].Addr[1] << 8) | \ + ((uint32_t)pAddrFilterConfig->Addr[1].Addr[0] << 0); + } + + // MACA3HR + if (pAddrFilterConfig->Addr[2].Enable == DISABLE) + { + (heth->Instance)->MACA3HR = 0; + (heth->Instance)->MACA3LR = 0; + } + else + { + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[2].GroupFilter)); + + tmpreg = ETH_MACA3HR_AE; + if (pAddrFilterConfig->Addr[2].GroupFilter == DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(pAddrFilterConfig->Addr[2].PerfectSourAddr)); + + if (pAddrFilterConfig->Addr[2].PerfectSourAddr != DISABLE) + tmpreg |= ETH_MACA3HR_SA; + } + else + { + assert_param(IS_ETH_ADDR_FILTER_GROUP_MASK(pAddrFilterConfig->Addr[2].GroupMask)); + + tmpreg |= pAddrFilterConfig->Addr[2].GroupMask << ETH_MACA3HR_MBC_Pos; + } + + (heth->Instance)->MACA3HR = tmpreg | \ + ((uint32_t)pAddrFilterConfig->Addr[2].Addr[5] << 8) | \ + ((uint32_t)pAddrFilterConfig->Addr[2].Addr[4] << 0); + + // MACA3LR + (heth->Instance)->MACA3LR = ((uint32_t)pAddrFilterConfig->Addr[2].Addr[3] << 24) | \ + ((uint32_t)pAddrFilterConfig->Addr[2].Addr[2] << 16) | \ + ((uint32_t)pAddrFilterConfig->Addr[2].Addr[1] << 8) | \ + ((uint32_t)pAddrFilterConfig->Addr[2].Addr[0] << 0); + } + + // MACFFR + tmpreg = (heth->Instance)->MACFFR; + tmpreg &= ~(ETH_MACFFR_RA | ETH_MACFFR_HPF | ETH_MACFFR_SAF | ETH_MACFFR_PCF | ETH_MACFFR_DBF | \ + ETH_MACFFR_PAM | ETH_MACFFR_DAIF | ETH_MACFFR_HMC | ETH_MACFFR_HUC | ETH_MACFFR_PR); + + if (pAddrFilterConfig->ReceiveAll != DISABLE) + tmpreg |= ETH_MACFFR_RA; + + if (pAddrFilterConfig->HashPerfectFilter != DISABLE) + tmpreg |= ETH_MACFFR_HPF; + + if (pAddrFilterConfig->SourceAddrFilter != DISABLE) + tmpreg |= ETH_MACFFR_SAF; + + if (pAddrFilterConfig->SourceAddrInverseFilter != DISABLE) + tmpreg |= ETH_MACFFR_SAIF; + + if (pAddrFilterConfig->PassControlPackets == ETH_PASS_CONTROL_BLOCK_ALL) + tmpreg |= 0U; + else if (pAddrFilterConfig->PassControlPackets == ETH_PASS_CONTROL_FORWARD_ALL_EXCEPT_PAUSE_FRAME) + tmpreg |= ETH_MACFFR_PCF_0; + else if (pAddrFilterConfig->PassControlPackets == ETH_PASS_CONTROL_FORWARD_ALL) + tmpreg |= ETH_MACFFR_PCF_1; + else if (pAddrFilterConfig->PassControlPackets == ETH_PASS_CONTROL_FORWARD_PASSED_ADDR_FILTER) + tmpreg |= ETH_MACFFR_PCF_1 | ETH_MACFFR_PCF_0; + + if (pAddrFilterConfig->BroadcastFramesReception == DISABLE) + tmpreg |= ETH_MACFFR_DBF; + + if (pAddrFilterConfig->PassAllMulticast != DISABLE) + tmpreg |= ETH_MACFFR_PAM; + + if (pAddrFilterConfig->DestAddrInverseFilter != DISABLE) + tmpreg |= ETH_MACFFR_DAIF; + + if (pAddrFilterConfig->HushMulticastFramesFilter != DISABLE) + tmpreg |= ETH_MACFFR_HMC; + + if (pAddrFilterConfig->HashUnicastFramesFilter != DISABLE) + tmpreg |= ETH_MACFFR_HUC; + + if (pAddrFilterConfig->PromiscuousMode != DISABLE) + tmpreg |= ETH_MACFFR_PR; + + (heth->Instance)->MACFFR = tmpreg; + + // MACHTHR + (heth->Instance)->MACHTHR = (uint32_t)pAddrFilterConfig->HashTable[1]; + + // MACHTLR + (heth->Instance)->MACHTLR = (uint32_t)pAddrFilterConfig->HashTable[0]; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetAddrFilterDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitAddrFilterDefaultParamter(heth); + + return HAL_ETH_SetAddrFilterConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_InitVLANFilterDefaultParamter(ETH_HandleTypeDef *heth) +{ + ETH_VLANFilterTypeDef *pVLANFilterConfig = &heth->FilterConfig.VLAN; + + // VLAN + pVLANFilterConfig->Enable = DISABLE; + pVLANFilterConfig->Hash = DISABLE; + pVLANFilterConfig->SVLAN = DISABLE; + pVLANFilterConfig->InverseMatch = DISABLE; + pVLANFilterConfig->Comparison12Bits = DISABLE; + pVLANFilterConfig->Tag = 0; + pVLANFilterConfig->HashTable = 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetVLANFilterConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_VLANFilterTypeDef *pVLANFilterConfig = &heth->FilterConfig.VLAN; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pVLANFilterConfig, 0, sizeof(ETH_VLANFilterTypeDef)); + + // MACFFR + tmpreg = (heth->Instance)->MACFFR; + + if (tmpreg & ETH_MACFFR_VTFE) + pVLANFilterConfig->Enable = ENABLE; + else + pVLANFilterConfig->Enable = DISABLE; + + // MACVLANTR + tmpreg = (heth->Instance)->MACVLANTR; + + if (tmpreg & ETH_MACVLANTR_VTHM) + pVLANFilterConfig->Hash = ENABLE; + else + pVLANFilterConfig->Hash = DISABLE; + + if (tmpreg & ETH_MACVLANTR_ESVL) + pVLANFilterConfig->SVLAN = ENABLE; + else + pVLANFilterConfig->SVLAN = DISABLE; + + if (tmpreg & ETH_MACVLANTR_VTIM) + pVLANFilterConfig->InverseMatch = ENABLE; + else + pVLANFilterConfig->InverseMatch = DISABLE; + + if (tmpreg & ETH_MACVLANTR_ETV) + pVLANFilterConfig->Comparison12Bits = ENABLE; + else + pVLANFilterConfig->Comparison12Bits = DISABLE; + + pVLANFilterConfig->Tag = (tmpreg & ETH_MACVLANTR_VL) >> ETH_MACVLANTR_VL_Pos; + + // MACVHTR + pVLANFilterConfig->HashTable = ((heth->Instance)->MACVHTR & ETH_MACVHTR_CSVL) >> ETH_MACVHTR_CSVL_Pos; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// MAC +// hethETH_HandleTypeDefṹָ룻 +// dmaconfýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetVLANFilterConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_VLANFilterTypeDef *pVLANFilterConfig = &heth->FilterConfig.VLAN; + + if (heth == NULL) + return (HAL_ERROR); + + assert_param(IS_FUNCTIONAL_STATE(pVLANFilterConfig->Enable)); + assert_param(IS_FUNCTIONAL_STATE(pVLANFilterConfig->Hash)); + assert_param(IS_FUNCTIONAL_STATE(pVLANFilterConfig->SVLAN)); + assert_param(IS_FUNCTIONAL_STATE(pVLANFilterConfig->InverseMatch)); + assert_param(IS_FUNCTIONAL_STATE(pVLANFilterConfig->Comparison12Bits)); + assert_param(IS_ETH_VLAN_TAG(pVLANFilterConfig->Tag)); + assert_param(IS_ETH_VLAN_HASH_TABLE(pVLANFilterConfig->HashTable)); + + // MACFFR + tmpreg = (heth->Instance)->MACFFR; + tmpreg &= ~ETH_MACFFR_VTFE; + + if (pVLANFilterConfig->Enable != DISABLE) + tmpreg |= ETH_MACFFR_VTFE; + + (heth->Instance)->MACFFR = tmpreg; + + // MACVLANTR + tmpreg = 0; + + if (pVLANFilterConfig->Hash != DISABLE) + tmpreg |= ETH_MACVLANTR_VTHM; + + if (pVLANFilterConfig->SVLAN != DISABLE) + tmpreg |= ETH_MACVLANTR_ESVL; + + if (pVLANFilterConfig->InverseMatch != DISABLE) + tmpreg |= ETH_MACVLANTR_VTIM; + + if (pVLANFilterConfig->Comparison12Bits != DISABLE) + tmpreg |= ETH_MACVLANTR_ETV; + + tmpreg |= pVLANFilterConfig->Tag << ETH_MACVLANTR_VL_Pos; + + (heth->Instance)->MACVLANTR = (uint32_t)tmpreg; + + // MACVHTR + (heth->Instance)->MACVHTR = pVLANFilterConfig->HashTable; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetVLANFilterDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitVLANFilterDefaultParamter(heth); + + return HAL_ETH_SetVLANFilterConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_InitL3L4FilterDefaultParamter(ETH_HandleTypeDef *heth) +{ + uint32_t i; + ETH_L3FilterTypeDef *pL3Config; + ETH_L4FilterTypeDef *pL4Config; + + // Layer3 Layer4 + heth->FilterConfig.L3L4.Enable = DISABLE; + + for (i=0; i<2; i++) + { + if (i == 0) + pL3Config = &heth->FilterConfig.L3L4.L3[0]; + else + pL3Config = &heth->FilterConfig.L3L4.L3[1]; + + pL3Config->ProtocolIPV6 = DISABLE; + pL3Config->IPV4.SourAddrMatchEnable = DISABLE; + pL3Config->IPV4.SourAddrInverseMatch = DISABLE; + pL3Config->IPV4.SourAddrMatch = 0; + pL3Config->IPV4.DestAddrMatchEnable = DISABLE; + pL3Config->IPV4.DestAddrInverseMatch = DISABLE; + pL3Config->IPV4.DestAddrMatch = 0; + pL3Config->IPV4.Rsv1[0] = 0; + pL3Config->IPV4.Rsv1[1] = 0; + pL3Config->IPV4.SourAddr = 0; + pL3Config->IPV4.DestAddr = 0; + pL3Config->IPV4.Rsv2[0] = 0; + pL3Config->IPV4.Rsv2[1] = 0; + } + + for (i=0; i<2; i++) + { + if (i == 0) + pL4Config = &heth->FilterConfig.L3L4.L4[0]; + else + pL4Config = &heth->FilterConfig.L3L4.L4[1]; + + pL4Config->ProtocolUDP = DISABLE; + pL4Config->SourPortMatchEnable = DISABLE; + pL4Config->SourPortInverseMatch = DISABLE; + pL4Config->DestPortMatchEnable = DISABLE; + pL4Config->DestPortInverseMatch = DISABLE; + pL4Config->SourPort = 0; + pL4Config->DestPort = 0; + } + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetL3L4FilterConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_L3L4FilterTypeDef *pL3L4FilterConfig = &heth->FilterConfig.L3L4; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pL3L4FilterConfig, 0, sizeof(ETH_L3L4FilterTypeDef)); + + // MACFFR + tmpreg = (heth->Instance)->MACFFR; + + if (tmpreg & ETH_MACFFR_IPFE) + pL3L4FilterConfig->Enable = ENABLE; + else + pL3L4FilterConfig->Enable = DISABLE; + + // MACL3L4C0R + tmpreg = (heth->Instance)->MACL3L4C0R; + + if (tmpreg & ETH_MACL3L4C0R_L4DPIM0) + pL3L4FilterConfig->L4[0].DestPortInverseMatch = ENABLE; + else + pL3L4FilterConfig->L4[0].DestPortInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L4DPM0) + pL3L4FilterConfig->L4[0].DestPortMatchEnable = ENABLE; + else + pL3L4FilterConfig->L4[0].DestPortMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L4SPIM0) + pL3L4FilterConfig->L4[0].SourPortInverseMatch = ENABLE; + else + pL3L4FilterConfig->L4[0].SourPortInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L4SPM0) + pL3L4FilterConfig->L4[0].SourPortMatchEnable = ENABLE; + else + pL3L4FilterConfig->L4[0].SourPortMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L4PEN0) + pL3L4FilterConfig->L4[0].ProtocolUDP = ENABLE; + else + pL3L4FilterConfig->L4[0].ProtocolUDP = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3PEN0) + { + pL3L4FilterConfig->L3[0].ProtocolIPV6 = ENABLE; + + pL3L4FilterConfig->L3[0].IPV6.AddrMatch = (tmpreg & (ETH_MACL3L4C0R_L3HDBM0_0 | ETH_MACL3L4C0R_L3HDBM0_1 | ETH_MACL3L4C0R_L3HSBM0)) >> ETH_MACL3L4C0R_L3HSBM0_Pos; + + if (tmpreg & ETH_MACL3L4C0R_L3DAIM0) + pL3L4FilterConfig->L3[0].IPV6.DestAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV6.DestAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3DAM0) + pL3L4FilterConfig->L3[0].IPV6.DestAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV6.DestAddrMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3SAIM0) + pL3L4FilterConfig->L3[0].IPV6.SourAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV6.SourAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3SAM0) + pL3L4FilterConfig->L3[0].IPV6.SourAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV6.SourAddrMatchEnable = DISABLE; + + // MACL3A00R + pL3L4FilterConfig->L3[0].IPV6.Addr[0] = (heth->Instance)->MACL3A00R; + + // MACL3A10R + pL3L4FilterConfig->L3[0].IPV6.Addr[1] = (heth->Instance)->MACL3A10R; + + // MACL3A20R + pL3L4FilterConfig->L3[0].IPV6.Addr[2] = (heth->Instance)->MACL3A20R; + + // MACL3A30R + pL3L4FilterConfig->L3[0].IPV6.Addr[3] = (heth->Instance)->MACL3A30R; + + } + else + { + pL3L4FilterConfig->L3[0].ProtocolIPV6 = DISABLE; + + pL3L4FilterConfig->L3[0].IPV4.DestAddrMatch = (tmpreg & ETH_MACL3L4C0R_L3HDBM0) >> ETH_MACL3L4C0R_L3HDBM0_Pos; + + pL3L4FilterConfig->L3[0].IPV4.SourAddrMatch = (tmpreg & ETH_MACL3L4C0R_L3HSBM0) >> ETH_MACL3L4C0R_L3HSBM0_Pos; + + if (tmpreg & ETH_MACL3L4C0R_L3DAIM0) + pL3L4FilterConfig->L3[0].IPV4.DestAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV4.DestAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3DAM0) + pL3L4FilterConfig->L3[0].IPV4.DestAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV4.DestAddrMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3SAIM0) + pL3L4FilterConfig->L3[0].IPV4.SourAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV4.SourAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C0R_L3SAM0) + pL3L4FilterConfig->L3[0].IPV4.SourAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[0].IPV4.SourAddrMatchEnable = DISABLE; + + // MACL3A00R + pL3L4FilterConfig->L3[0].IPV4.SourAddr = (heth->Instance)->MACL3A00R; + + // MACL3A10R + pL3L4FilterConfig->L3[0].IPV4.DestAddr = (heth->Instance)->MACL3A10R; + + } + + // MACL4A0R + pL3L4FilterConfig->L4[0].DestPort = ((heth->Instance)->MACL4A0R & ETH_MACL4A0R_L4DP0) >> ETH_MACL4A0R_L4DP0_Pos; + + pL3L4FilterConfig->L4[0].SourPort = ((heth->Instance)->MACL4A0R & ETH_MACL4A0R_L4SP0) >> ETH_MACL4A0R_L4SP0_Pos; + + // MACL3L4C1R + tmpreg = (heth->Instance)->MACL3L4C1R; + + if (tmpreg & ETH_MACL3L4C1R_L4DPIM1) + pL3L4FilterConfig->L4[1].DestPortInverseMatch = ENABLE; + else + pL3L4FilterConfig->L4[1].DestPortInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L4DPM1) + pL3L4FilterConfig->L4[1].DestPortMatchEnable = ENABLE; + else + pL3L4FilterConfig->L4[1].DestPortMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L4SPIM1) + pL3L4FilterConfig->L4[1].SourPortInverseMatch = ENABLE; + else + pL3L4FilterConfig->L4[1].SourPortInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L4SPM1) + pL3L4FilterConfig->L4[1].SourPortMatchEnable = ENABLE; + else + pL3L4FilterConfig->L4[1].SourPortMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L4PEN1) + pL3L4FilterConfig->L4[1].ProtocolUDP = ENABLE; + else + pL3L4FilterConfig->L4[1].ProtocolUDP = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3PEN1) + { + pL3L4FilterConfig->L3[1].ProtocolIPV6 = ENABLE; + + pL3L4FilterConfig->L3[1].IPV6.AddrMatch = (tmpreg & (ETH_MACL3L4C1R_L3HDBM1_0 | ETH_MACL3L4C1R_L3HDBM1_1 | ETH_MACL3L4C1R_L3HSBM1)) >> ETH_MACL3L4C1R_L3HSBM1_Pos; + + if (tmpreg & ETH_MACL3L4C1R_L3DAIM1) + pL3L4FilterConfig->L3[1].IPV6.DestAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV6.DestAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3DAM1) + pL3L4FilterConfig->L3[1].IPV6.DestAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV6.DestAddrMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3SAIM1) + pL3L4FilterConfig->L3[1].IPV6.SourAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV6.SourAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3SAM1) + pL3L4FilterConfig->L3[1].IPV6.SourAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV6.SourAddrMatchEnable = DISABLE; + + // MACL3A01R + pL3L4FilterConfig->L3[1].IPV6.Addr[1] = (heth->Instance)->MACL3A01R; + + // MACL3A11R + pL3L4FilterConfig->L3[1].IPV6.Addr[1] = (heth->Instance)->MACL3A11R; + + // MACL3A21R + pL3L4FilterConfig->L3[1].IPV6.Addr[2] = (heth->Instance)->MACL3A21R; + + // MACL3A31R + pL3L4FilterConfig->L3[1].IPV6.Addr[3] = (heth->Instance)->MACL3A31R; + + } + else + { + pL3L4FilterConfig->L3[1].ProtocolIPV6 = DISABLE; + + pL3L4FilterConfig->L3[1].IPV4.DestAddrMatch = (tmpreg & ETH_MACL3L4C1R_L3HDBM1) >> ETH_MACL3L4C1R_L3HDBM1_Pos; + + pL3L4FilterConfig->L3[1].IPV4.SourAddrMatch = (tmpreg & ETH_MACL3L4C1R_L3HSBM1) >> ETH_MACL3L4C1R_L3HSBM1_Pos; + + if (tmpreg & ETH_MACL3L4C1R_L3DAIM1) + pL3L4FilterConfig->L3[1].IPV4.DestAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV4.DestAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3DAM1) + pL3L4FilterConfig->L3[1].IPV4.DestAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV4.DestAddrMatchEnable = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3SAIM1) + pL3L4FilterConfig->L3[1].IPV4.SourAddrInverseMatch = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV4.SourAddrInverseMatch = DISABLE; + + if (tmpreg & ETH_MACL3L4C1R_L3SAM1) + pL3L4FilterConfig->L3[1].IPV4.SourAddrMatchEnable = ENABLE; + else + pL3L4FilterConfig->L3[1].IPV4.SourAddrMatchEnable = DISABLE; + + // MACL3A01R + pL3L4FilterConfig->L3[1].IPV4.SourAddr = (heth->Instance)->MACL3A01R; + + // MACL3A11R + pL3L4FilterConfig->L3[1].IPV4.DestAddr = (heth->Instance)->MACL3A11R; + + } + + // MACL4A1R + pL3L4FilterConfig->L4[1].DestPort = ((heth->Instance)->MACL4A1R & ETH_MACL4A1R_L4DP1) >> ETH_MACL4A1R_L4DP1_Pos; + + pL3L4FilterConfig->L4[1].SourPort = ((heth->Instance)->MACL4A1R & ETH_MACL4A1R_L4SP1) >> ETH_MACL4A1R_L4SP1_Pos; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// MAC +// hethETH_HandleTypeDefṹָ룻 +// dmaconfýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetL3L4FilterConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_L3L4FilterTypeDef *pL3L4FilterConfig = &heth->FilterConfig.L3L4; + + if (heth == NULL) + return (HAL_ERROR); + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->Enable)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[0].ProtocolIPV6)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[1].ProtocolIPV6)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L4[0].ProtocolUDP)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L4[0].SourPortMatchEnable)); + assert_param(IS_ETH_SOUR_PORT(pL3L4FilterConfig->L4[0].SourPort)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L4[0].DestPortMatchEnable)); + assert_param(IS_ETH_DEST_PORT(pL3L4FilterConfig->L4[0].DestPort)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L4[1].ProtocolUDP)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L4[1].SourPortMatchEnable)); + assert_param(IS_ETH_SOUR_PORT(pL3L4FilterConfig->L4[1].SourPort)); + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L4[1].DestPortMatchEnable)); + assert_param(IS_ETH_DEST_PORT(pL3L4FilterConfig->L4[1].DestPort)); + + // MACFFR + tmpreg = (heth->Instance)->MACFFR; + + if (pL3L4FilterConfig->Enable != DISABLE) + tmpreg |= ETH_MACFFR_IPFE; + else + tmpreg &= ~ETH_MACFFR_IPFE; + + (heth->Instance)->MACFFR = tmpreg; + + // MACL3L4C0R + tmpreg = 0U; + + if (pL3L4FilterConfig->L4[0].ProtocolUDP != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L4PEN0; + + if (pL3L4FilterConfig->L4[0].DestPortMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L4DPM0; + + if (pL3L4FilterConfig->L4[0].DestPortInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L4DPIM0; + } + + if (pL3L4FilterConfig->L4[0].SourPortMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L4SPM0; + + if (pL3L4FilterConfig->L4[0].SourPortInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L4SPIM0; + } + + if (pL3L4FilterConfig->L3[0].ProtocolIPV6 != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L3PEN0; + + assert_param(IS_ETH_IPV6_ADDR_MASK(pL3L4FilterConfig->L3[0].IPV6.AddrMatch)); + + tmpreg |= pL3L4FilterConfig->L3[0].IPV6.AddrMatch << ETH_MACL3L4C0R_L3HSBM0_Pos; + + if (pL3L4FilterConfig->L3[0].IPV6.DestAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L3DAM0; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[0].IPV6.DestAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[0].IPV6.DestAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L3DAIM0; + } + + if (pL3L4FilterConfig->L3[0].IPV6.SourAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L3SAM0; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[0].IPV6.DestAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[0].IPV6.SourAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L3SAIM0; + } + + (heth->Instance)->MACL3L4C0R = tmpreg; + + // MACL3A00R + (heth->Instance)->MACL3A00R = pL3L4FilterConfig->L3[0].IPV6.Addr[0]; + + // MACL3A10R + (heth->Instance)->MACL3A10R = pL3L4FilterConfig->L3[0].IPV6.Addr[1]; + + // MACL3A20R + (heth->Instance)->MACL3A20R = pL3L4FilterConfig->L3[0].IPV6.Addr[2]; + + // MACL3A30R + (heth->Instance)->MACL3A30R = pL3L4FilterConfig->L3[0].IPV6.Addr[3]; + } + else + { + assert_param(IS_ETH_IPV4_SOUR_ADDR_MASK(pL3L4FilterConfig->L3[0].IPV4.SourAddrMatch)); + assert_param(IS_ETH_IPV4_DEST_ADDR_MASK(pL3L4FilterConfig->L3[0].IPV4.DestAddrMatch)); + + tmpreg |= pL3L4FilterConfig->L3[0].IPV4.DestAddrMatch << ETH_MACL3L4C0R_L3HDBM0_Pos; + + tmpreg |= pL3L4FilterConfig->L3[0].IPV4.SourAddrMatch << ETH_MACL3L4C0R_L3HSBM0_Pos; + + if (pL3L4FilterConfig->L3[0].IPV4.DestAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L3DAM0; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[0].IPV4.DestAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[0].IPV4.DestAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L3DAIM0; + } + + if (pL3L4FilterConfig->L3[0].IPV4.SourAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C0R_L3SAM0; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[0].IPV4.SourAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[0].IPV4.SourAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C0R_L3SAIM0; + } + + (heth->Instance)->MACL3L4C0R = tmpreg; + + // MACL3A00R + (heth->Instance)->MACL3A00R = pL3L4FilterConfig->L3[0].IPV4.SourAddr; + + // MACL3A10R + (heth->Instance)->MACL3A10R = pL3L4FilterConfig->L3[0].IPV4.DestAddr; + + // MACL3A20R + (heth->Instance)->MACL3A20R = 0; + + // MACL3A30R + (heth->Instance)->MACL3A30R = 0; + } + + // MACL4A0R + tmpreg = 0; + + tmpreg |= pL3L4FilterConfig->L4[0].DestPort << ETH_MACL4A0R_L4DP0_Pos; + + tmpreg |= pL3L4FilterConfig->L4[0].SourPort << ETH_MACL4A0R_L4SP0_Pos; + + (heth->Instance)->MACL4A0R = tmpreg; + + // MACL3L4C1R + tmpreg = 0U; + + if (pL3L4FilterConfig->L4[1].ProtocolUDP != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L4PEN1; + + if (pL3L4FilterConfig->L4[1].DestPortMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L4DPM1; + + if (pL3L4FilterConfig->L4[1].DestPortInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L4DPIM1; + } + + if (pL3L4FilterConfig->L4[1].SourPortMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L4SPM1; + + if (pL3L4FilterConfig->L4[1].SourPortInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L4SPIM1; + } + + if (pL3L4FilterConfig->L3[1].ProtocolIPV6 != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L3PEN1; + + assert_param(IS_ETH_IPV6_ADDR_MASK(pL3L4FilterConfig->L3[1].IPV6.AddrMatch)); + + tmpreg |= pL3L4FilterConfig->L3[1].IPV6.AddrMatch << ETH_MACL3L4C1R_L3HSBM1_Pos; + + if (pL3L4FilterConfig->L3[1].IPV6.DestAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L3DAM1; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[1].IPV6.DestAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[1].IPV6.DestAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L3DAIM1; + } + + if (pL3L4FilterConfig->L3[1].IPV6.SourAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L3SAM1; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[1].IPV6.DestAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[1].IPV6.SourAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L3SAIM1; + } + + (heth->Instance)->MACL3L4C1R = tmpreg; + + // MACL3A01R + (heth->Instance)->MACL3A01R = pL3L4FilterConfig->L3[1].IPV6.Addr[0]; + + // MACL3A11R + (heth->Instance)->MACL3A11R = pL3L4FilterConfig->L3[1].IPV6.Addr[1]; + + // MACL3A21R + (heth->Instance)->MACL3A21R = pL3L4FilterConfig->L3[1].IPV6.Addr[2]; + + // MACL3A31R + (heth->Instance)->MACL3A31R = pL3L4FilterConfig->L3[1].IPV6.Addr[3]; + } + else + { + assert_param(IS_ETH_IPV4_SOUR_ADDR_MASK(pL3L4FilterConfig->L3[1].IPV4.SourAddrMatch)); + assert_param(IS_ETH_IPV4_DEST_ADDR_MASK(pL3L4FilterConfig->L3[1].IPV4.DestAddrMatch)); + + tmpreg |= pL3L4FilterConfig->L3[1].IPV4.DestAddrMatch << ETH_MACL3L4C1R_L3HDBM1_Pos; + + tmpreg |= pL3L4FilterConfig->L3[1].IPV4.SourAddrMatch << ETH_MACL3L4C1R_L3HSBM1_Pos; + + if (pL3L4FilterConfig->L3[1].IPV4.DestAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L3DAM1; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[1].IPV4.DestAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[1].IPV4.DestAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L3DAIM1; + } + + if (pL3L4FilterConfig->L3[1].IPV4.SourAddrMatchEnable != DISABLE) + { + tmpreg |= ETH_MACL3L4C1R_L3SAM1; + + assert_param(IS_FUNCTIONAL_STATE(pL3L4FilterConfig->L3[1].IPV4.SourAddrInverseMatch)); + + if (pL3L4FilterConfig->L3[1].IPV4.SourAddrInverseMatch != DISABLE) + tmpreg |= ETH_MACL3L4C1R_L3SAIM1; + } + + (heth->Instance)->MACL3L4C1R = tmpreg; + + // MACL3A01R + (heth->Instance)->MACL3A01R = pL3L4FilterConfig->L3[1].IPV4.SourAddr; + + // MACL3A11R + (heth->Instance)->MACL3A11R = pL3L4FilterConfig->L3[1].IPV4.DestAddr; + + // MACL3A21R + (heth->Instance)->MACL3A21R = 0; + + // MACL3A31R + (heth->Instance)->MACL3A31R = 0; + } + + // MACL4A1R + tmpreg = 0; + + tmpreg |= pL3L4FilterConfig->L4[1].DestPort << ETH_MACL4A1R_L4DP1_Pos; + + tmpreg |= pL3L4FilterConfig->L4[1].SourPort << ETH_MACL4A1R_L4SP1_Pos; + + (heth->Instance)->MACL4A1R = tmpreg; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetL3L4FilterDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitL3L4FilterDefaultParamter(heth); + + return HAL_ETH_SetL3L4FilterConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_InitFilterDefaultParamter(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitAddrFilterDefaultParamter(heth); + HAL_ETH_InitVLANFilterDefaultParamter(heth); + HAL_ETH_InitL3L4FilterDefaultParamter(heth); + heth->FilterConfig.DropNonTCPUDP = DISABLE; + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetFilterConfig(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + if (HAL_ETH_GetAddrFilterConfig(heth) != HAL_OK) + return (HAL_ERROR); + + if (HAL_ETH_GetVLANFilterConfig(heth) != HAL_OK) + return (HAL_ERROR); + + if (HAL_ETH_GetL3L4FilterConfig(heth) != HAL_OK) + return (HAL_ERROR); + + if (heth->Instance->MACFFR & ETH_MACFFR_DNTU) + heth->FilterConfig.DropNonTCPUDP = ENABLE; + else + heth->FilterConfig.DropNonTCPUDP = DISABLE; + + return HAL_OK; +} + + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// MAC +// hethETH_HandleTypeDefṹָ룻 +// dmaconfýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetFilterConfig(ETH_HandleTypeDef *heth) +{ + assert_param(IS_FUNCTIONAL_STATE(heth->FilterConfig.DropNonTCPUDP)); + + if (heth == NULL) + return (HAL_ERROR); + + if (HAL_ETH_SetAddrFilterConfig(heth) != HAL_OK) + return (HAL_ERROR); + + if (HAL_ETH_SetVLANFilterConfig(heth) != HAL_OK) + return (HAL_ERROR); + + if (HAL_ETH_SetL3L4FilterConfig(heth) != HAL_OK) + return (HAL_ERROR); + + if (heth->FilterConfig.DropNonTCPUDP == DISABLE) + heth->Instance->MACFFR &= ~ETH_MACFFR_DNTU; + else + heth->Instance->MACFFR |= ETH_MACFFR_DNTU; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetFilterDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitFilterDefaultParamter(heth); + + return HAL_ETH_SetFilterConfig(heth); +} + +// **************************************************************************** +// +// VLAN +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitVLANDefaultParamter(ETH_HandleTypeDef *heth) +{ + ETH_VLANTypeDef *pVLANConfig = &heth->MACConfig.VLAN; + + pVLANConfig->Enable = DISABLE; + pVLANConfig->Mode = ETH_VLAN_MODE_NONE; + pVLANConfig->SVLAN = DISABLE; + pVLANConfig->Tag = 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetVLANConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_VLANTypeDef *pVLANConfig = &heth->MACConfig.VLAN; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pVLANConfig, 0, sizeof(ETH_VLANTypeDef)); + + // MACVTIRR + tmpreg = (heth->Instance)->MACVTIRR; + + if (tmpreg & ETH_MACVTIRR_CSVL) + pVLANConfig->SVLAN = ENABLE; + else + pVLANConfig->SVLAN = DISABLE; + + if (tmpreg & ETH_MACVTIRR_VLP) + pVLANConfig->Enable = ENABLE; + else + pVLANConfig->Enable = DISABLE; + + pVLANConfig->Mode = (tmpreg & ETH_MACVTIRR_VLC) >> ETH_MACVTIRR_VLC_Pos; + + pVLANConfig->Tag = (tmpreg & ETH_MACVTIRR_VLT) >> ETH_MACVTIRR_VLT_Pos; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// MAC +// hethETH_HandleTypeDefṹָ룻 +// dmaconfýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetVLANConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_VLANTypeDef *pVLANConfig = &heth->MACConfig.VLAN; + + if (heth == NULL) + return (HAL_ERROR); + + assert_param(IS_FUNCTIONAL_STATE(pVLANConfig->Enable)); + assert_param(IS_FUNCTIONAL_STATE(pVLANConfig->SVLAN)); + assert_param(IS_ETH_VLAN_MODE(pVLANConfig->Mode)); + assert_param(IS_ETH_VLAN_TAG(pVLANConfig->Tag)); + + // MACVTIRR + tmpreg = 0; + + if (pVLANConfig->SVLAN != DISABLE) + tmpreg |= ETH_MACVTIRR_CSVL; + + if (pVLANConfig->Enable != DISABLE) + tmpreg |= ETH_MACVTIRR_VLP; + + tmpreg |= pVLANConfig->Mode << ETH_MACVTIRR_VLC_Pos; + + tmpreg |= pVLANConfig->Tag << ETH_MACVTIRR_VLT_Pos; + + (heth->Instance)->MACVTIRR = (uint32_t)tmpreg; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetVLANDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitVLANDefaultParamter(heth); + + return HAL_ETH_SetVLANConfig(heth); +} + +// **************************************************************************** +// +// MAC +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitMACDefaultParamter(ETH_HandleTypeDef *heth) +{ + // MACĬֵ + + heth->MACConfig.SourceAddrControl = ETH_SOURCE_ADDRESS_REPLACE_ADDR0; // ãԴַ滻MACַ1Ĵ + heth->MACConfig.Support2KPacket = ENABLE; // ֹ2KݰIEEE 802.3as ֧ + heth->MACConfig.CRCStripTypePacket = ENABLE; // ֹ֡ CRC ȥ + heth->MACConfig.Watchdog = DISABLE; // ʹܣտŹ + heth->MACConfig.WatchdogTimeout = 1523U; // ãտŹʱ + heth->MACConfig.Jabber = DISABLE; // ʹܣjabberʱ + heth->MACConfig.JumboPacket = ENABLE; // ֹݰʹ + heth->MACConfig.InterFrameGap = ETH_INTERFRAME_GAP_96BIT; // ã֡96λ + heth->MACConfig.CarrierSense = DISABLE; // ʹܣز + heth->MACConfig.ReceiveOwn = ENABLE; // ʹܣ + heth->MACConfig.LoopbackMode = DISABLE; // ֹģʽ + heth->MACConfig.ChecksumOffload = ENABLE; // ã֡ TCP/UDP/ICMP ͷ IPv4 Уͼ + heth->MACConfig.RetryTransmission = ENABLE; // ʹܣ + heth->MACConfig.AutoPadCRCStrip = ENABLE; // ֹԶȥPADFCSֶ + heth->MACConfig.BackOffLimit = ETH_BACK_OFF_LIMIT_10; // ã10λ + heth->MACConfig.DeferralCheck = DISABLE; // ֹӳ + heth->MACConfig.PreambleLen = ETH_PREAMBLE_LEN_7B; // ֹͷ7ֽ + + HAL_ETH_InitVLANDefaultParamter(heth); + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// ȡMAC +// hethETH_HandleTypeDefṹָ룻 +// pMACConfigýṹָ룻 +// HAL_OKȡóɹ +// HAL_ERRORȡʧܣ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth) +{ + uint32_t err; + volatile uint32_t tmpreg = 0; + ETH_MACInitTypeDef *pMACConfig = &heth->MACConfig; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pMACConfig, 0, sizeof(ETH_MACInitTypeDef)); + err = 0; + + // MACCR + tmpreg = (heth->Instance)->MACCR; + + if ((tmpreg & ETH_MACCR_SARC_1) == 0) + pMACConfig->SourceAddrControl = ETH_SOURCE_ADDRESS_DISABLE; + else if ((tmpreg & ETH_MACCR_SARC) == (ETH_MACCR_SARC_1)) + pMACConfig->SourceAddrControl = ETH_SOURCE_ADDRESS_INSERT_ADDR0; + else if ((tmpreg & ETH_MACCR_SARC) == (ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1)) + pMACConfig->SourceAddrControl = ETH_SOURCE_ADDRESS_INSERT_ADDR1; + else if ((tmpreg & ETH_MACCR_SARC) == (ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0)) + pMACConfig->SourceAddrControl = ETH_SOURCE_ADDRESS_REPLACE_ADDR0; + else if ((tmpreg & ETH_MACCR_SARC) == (ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0)) + pMACConfig->SourceAddrControl = ETH_SOURCE_ADDRESS_REPLACE_ADDR1; + + if (tmpreg & ETH_MACCR_S2KP) + pMACConfig->Support2KPacket = ENABLE; + else + pMACConfig->Support2KPacket = DISABLE; + + if (tmpreg & ETH_MACCR_CSTF) + pMACConfig->CRCStripTypePacket = ENABLE; + else + pMACConfig->CRCStripTypePacket = DISABLE; + + if (((tmpreg & ETH_MACCR_WD) == 0) && ((heth->Instance)->MACWTR & ETH_MACWTR_PWE)) + pMACConfig->Watchdog = ENABLE; + else + pMACConfig->Watchdog = DISABLE; + + if (tmpreg & ETH_MACCR_JD) + pMACConfig->Jabber = ENABLE; + else + pMACConfig->Jabber = DISABLE; + + if (tmpreg & ETH_MACCR_JE) + pMACConfig->JumboPacket = ENABLE; + else + pMACConfig->JumboPacket = DISABLE; + + if ((tmpreg & ETH_MACCR_IFG) == 0) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_96BIT; + else if ((tmpreg & ETH_MACCR_IFG) == ETH_MACCR_IFG_0) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_88BIT; + else if ((tmpreg & ETH_MACCR_IFG) == ETH_MACCR_IFG_1) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_80BIT; + else if ((tmpreg & ETH_MACCR_IFG) == (ETH_MACCR_IFG_1 | ETH_MACCR_IFG_0)) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_72BIT; + else if ((tmpreg & ETH_MACCR_IFG) == ETH_MACCR_IFG_2) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_64BIT; + else if ((tmpreg & ETH_MACCR_IFG) == (ETH_MACCR_IFG_2 | ETH_MACCR_IFG_0)) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_56BIT; + else if ((tmpreg & ETH_MACCR_IFG) == (ETH_MACCR_IFG_2 | ETH_MACCR_IFG_1)) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_48BIT; + else if ((tmpreg & ETH_MACCR_IFG) == (ETH_MACCR_IFG_2 | ETH_MACCR_IFG_1 | ETH_MACCR_IFG_0)) + pMACConfig->InterFrameGap = ETH_INTERFRAME_GAP_40BIT; + + if (tmpreg & ETH_MACCR_CSD) + pMACConfig->JumboPacket = DISABLE; + else + pMACConfig->JumboPacket = ENABLE; + + if (tmpreg & ETH_MACCR_ROD) + pMACConfig->ReceiveOwn = DISABLE; + else + pMACConfig->ReceiveOwn = ENABLE; + + if (tmpreg & ETH_MACCR_LM) + pMACConfig->LoopbackMode = ENABLE; + else + pMACConfig->LoopbackMode = DISABLE; + + if (tmpreg & ETH_MACCR_IPCO) + pMACConfig->ChecksumOffload = ENABLE; + else + pMACConfig->ChecksumOffload = DISABLE; + + if (tmpreg & ETH_MACCR_DR) + pMACConfig->RetryTransmission = DISABLE; + else + pMACConfig->RetryTransmission = ENABLE; + + if (tmpreg & ETH_MACCR_APCS) + pMACConfig->AutoPadCRCStrip = ENABLE; + else + pMACConfig->AutoPadCRCStrip = DISABLE; + + if ((tmpreg & ETH_MACCR_BL) == 0) + pMACConfig->BackOffLimit = ETH_BACK_OFF_LIMIT_10; + else if ((tmpreg & ETH_MACCR_BL) == ETH_MACCR_BL_0) + pMACConfig->BackOffLimit = ETH_BACK_OFF_LIMIT_8; + else if ((tmpreg & ETH_MACCR_BL) == ETH_MACCR_BL_1) + pMACConfig->BackOffLimit = ETH_BACK_OFF_LIMIT_4; + else if ((tmpreg & ETH_MACCR_BL) == (ETH_MACCR_BL_1 | ETH_MACCR_BL_0)) + pMACConfig->BackOffLimit = ETH_BACK_OFF_LIMIT_1; + + if (tmpreg & ETH_MACCR_DC) + pMACConfig->DeferralCheck = ENABLE; + else + pMACConfig->DeferralCheck = DISABLE; + + if ((tmpreg & ETH_MACCR_PRELEN) == 0) + pMACConfig->PreambleLen = ETH_PREAMBLE_LEN_7B; + else if ((tmpreg & ETH_MACCR_BL) == ETH_MACCR_PRELEN_0) + pMACConfig->PreambleLen = ETH_PREAMBLE_LEN_5B; + else if ((tmpreg & ETH_MACCR_BL) == ETH_MACCR_PRELEN_1) + pMACConfig->PreambleLen = ETH_PREAMBLE_LEN_3B; + else + err = 1; + + // MACWTR + pMACConfig->WatchdogTimeout = ((heth->Instance)->MACWTR & ETH_MACWTR_WTO) >> ETH_MACWTR_WTO_Pos; + + err |= HAL_ETH_GetVLANConfig(heth); + + if (err == 0) + return HAL_OK; + else + return HAL_ERROR; +} + + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *pMACConfig); +// MAC +// hethETH_HandleTypeDefṹָ룻 +// dmaconfýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg = 0; + ETH_MACInitTypeDef *pMACConfig = &heth->MACConfig; + + if (heth == NULL) + return (HAL_ERROR); + + assert_param(IS_ETH_SOURCE_ADDR_CONTROL(pMACConfig->SourceAddrControl)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->Support2KPacket)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->CRCStripTypePacket)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->Watchdog)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->Jabber)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->JumboPacket)); + assert_param(IS_ETH_INTERFRAME_GAP(pMACConfig->InterFrameGap)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->CarrierSense)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->ReceiveOwn)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->LoopbackMode)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->ChecksumOffload)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->RetryTransmission)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->AutoPadCRCStrip)); + assert_param(IS_ETH_BACK_OFF_LIMIT(pMACConfig->BackOffLimit)); + assert_param(IS_FUNCTIONAL_STATE(pMACConfig->DeferralCheck)); + assert_param(IS_ETH_PREAMBLE_LEN(pMACConfig->PreambleLen)); + + // MACCR + tmpreg = (heth->Instance)->MACCR; + tmpreg &= 0x8520c90c; + + if (pMACConfig->SourceAddrControl == ETH_SOURCE_ADDRESS_DISABLE) + tmpreg |= 0U; + if (pMACConfig->SourceAddrControl == ETH_SOURCE_ADDRESS_INSERT_ADDR0) + tmpreg |= ETH_MACCR_SARC_1; + if (pMACConfig->SourceAddrControl == ETH_SOURCE_ADDRESS_INSERT_ADDR1) + tmpreg |= ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1; + if (pMACConfig->SourceAddrControl == ETH_SOURCE_ADDRESS_REPLACE_ADDR0) + tmpreg |= ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0; + if (pMACConfig->SourceAddrControl == ETH_SOURCE_ADDRESS_REPLACE_ADDR1) + tmpreg |= ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0; + + if (pMACConfig->Support2KPacket != DISABLE) + tmpreg |= ETH_MACCR_S2KP; + + if (pMACConfig->CRCStripTypePacket != DISABLE) + tmpreg |= ETH_MACCR_CSTF; + + if (pMACConfig->Watchdog == DISABLE) + tmpreg |= ETH_MACCR_WD; + + if (pMACConfig->Jabber != DISABLE) + tmpreg |= ETH_MACCR_JD; + + if (pMACConfig->JumboPacket != DISABLE) + tmpreg |= ETH_MACCR_JE; + + if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_96BIT) + tmpreg |= 0U; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_88BIT) + tmpreg |= ETH_MACCR_IFG_0; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_80BIT) + tmpreg |= ETH_MACCR_IFG_1; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_72BIT) + tmpreg |= ETH_MACCR_IFG_1 | ETH_MACCR_IFG_0; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_64BIT) + tmpreg |= ETH_MACCR_IFG_2; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_56BIT) + tmpreg |= ETH_MACCR_IFG_2 | ETH_MACCR_IFG_0; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_48BIT) + tmpreg |= ETH_MACCR_IFG_2 | ETH_MACCR_IFG_1; + else if (pMACConfig->InterFrameGap == ETH_INTERFRAME_GAP_40BIT) + tmpreg |= ETH_MACCR_IFG_2 | ETH_MACCR_IFG_1 | ETH_MACCR_IFG_0; + + if (pMACConfig->CarrierSense == DISABLE) + tmpreg |= ETH_MACCR_CSD; + + if (pMACConfig->ReceiveOwn == DISABLE) + tmpreg |= ETH_MACCR_ROD; + + if (pMACConfig->LoopbackMode != DISABLE) + tmpreg |= ETH_MACCR_LM; + + if (pMACConfig->ChecksumOffload != DISABLE) + tmpreg |= ETH_MACCR_IPCO; + + if (pMACConfig->RetryTransmission == DISABLE) + tmpreg |= ETH_MACCR_DR; + + if (pMACConfig->AutoPadCRCStrip != DISABLE) + tmpreg |= ETH_MACCR_APCS; + + if (pMACConfig->BackOffLimit == ETH_BACK_OFF_LIMIT_10) + tmpreg |= 0U; + else if (pMACConfig->BackOffLimit == ETH_BACK_OFF_LIMIT_8) + tmpreg |= ETH_MACCR_BL_0; + else if (pMACConfig->BackOffLimit == ETH_BACK_OFF_LIMIT_4) + tmpreg |= ETH_MACCR_BL_1; + else if (pMACConfig->BackOffLimit == ETH_BACK_OFF_LIMIT_1) + tmpreg |= ETH_MACCR_BL_1 | ETH_MACCR_BL_1; + + if (pMACConfig->DeferralCheck != DISABLE) + tmpreg |= ETH_MACCR_DC; + + if (pMACConfig->PreambleLen == ETH_PREAMBLE_LEN_7B) + tmpreg |= 0U; + else if (pMACConfig->PreambleLen == ETH_PREAMBLE_LEN_5B) + tmpreg |= ETH_MACCR_PRELEN_0; + else if (pMACConfig->PreambleLen == ETH_PREAMBLE_LEN_3B) + tmpreg |= ETH_MACCR_PRELEN_1; + + (heth->Instance)->MACCR = (uint32_t)tmpreg; + + // MACWTR + if (pMACConfig->Watchdog) + (heth->Instance)->MACWTR = ETH_MACWTR_PWE | ((pMACConfig->WatchdogTimeout << ETH_MACWTR_WTO_Pos) & ETH_MACWTR_WTO); + else + (heth->Instance)->MACWTR = (pMACConfig->WatchdogTimeout << ETH_MACWTR_WTO_Pos) & ETH_MACWTR_WTO; + + // VLAN + HAL_ETH_SetVLANConfig(heth); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetMACDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitMACDefaultParamter(heth); + + return HAL_ETH_SetMACConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_InitDMADefaultParamter(ETH_HandleTypeDef *heth) +{ +// memset((void *)&heth->DMAConfig, 0, sizeof(ETH_DMAInitTypeDef)); + + // DMAĬֵ + heth->DMAConfig.DropTCPIPChecksumErrorFrame = ENABLE; //ֹTCP/IPУ֡ + heth->DMAConfig.ReceiveStoreForward = ENABLE; //ʹܣմ洢ת + heth->DMAConfig.FlushReceivedFrame = ENABLE; //ֹֹˢ½֡ + heth->DMAConfig.TransmitStoreForward = ENABLE; //ʹܣʹ洢ת + heth->DMAConfig.TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_64BYTES; //ãֵƣ64ֽ + heth->DMAConfig.ForwardErrorFrames = DISABLE; //ֹת֡ + heth->DMAConfig.ForwardUndersizedGoodFrames = DISABLE; //ֹתСĺ֡ + heth->DMAConfig.ReceiveThresholdControl = ETH_RECEIVED_THRESHOLD_CONTROL_64BYTES; //ãֵƣ64ֽ + heth->DMAConfig.SecondFrameOperate = ENABLE; //ʹܣڶ֡ + + heth->DMAConfig.MixedBurst = DISABLE; //ֹͻ + heth->DMAConfig.AddressAlignedBeats = ENABLE; //ʹܣַ + heth->DMAConfig.PBL8xMode = DISABLE; //ֹ 8xPBL ģʽ + heth->DMAConfig.UseSeparatePBL = ENABLE; //ֹ ʹõ PBL + heth->DMAConfig.RxDMABurstLen = ETH_RX_DMA_BURST_LEN_32BEAT; //ã DMAͻճ:32ֽ + heth->DMAConfig.FixedBurst = ENABLE; //ʹܣ̶ͻ + heth->DMAConfig.RxTxPriorityRatio = ETH_RX_TX_PRIORITY_RATIO_4_1; //ã Rx Tx ȼ + heth->DMAConfig.TxDMABurstLen = ETH_TX_DMA_BURST_LEN_32BEAT; //ã DMAͻͳȣ32ֽ + heth->DMAConfig.EnhancedDescriptorFormat = ENABLE; //ʹܣǿʽ + heth->DMAConfig.DescriptorSkipLen = 0x02; //ãȣ0 + heth->DMAConfig.DMAArbitration = ETH_DMA_ARBITRATION_ROUNDROBIN; //ã DMAٲãѭ + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *pDMAConfig); +// ȡDMA +// hethETH_HandleTypeDefṹָ룻 +// pDMAConfigýṹָ룻 +// HAL_OKȡóɹ +// HAL_ERRORȡʧܣ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth) +{ + uint32_t err; + volatile uint32_t tmpreg = 0; + ETH_DMAInitTypeDef *pDMAConfig = &heth->DMAConfig; + + if (heth == NULL) + return (HAL_ERROR); + + err = 0; + + // DMAOMR + tmpreg = (heth->Instance)->DMAOMR; + + if (tmpreg & ETH_DMAOMR_DTCEFD) + pDMAConfig->DropTCPIPChecksumErrorFrame = ENABLE; + else + pDMAConfig->DropTCPIPChecksumErrorFrame = DISABLE; + + if (tmpreg & ETH_DMAOMR_RSF) + pDMAConfig->ReceiveStoreForward = ENABLE; + else + pDMAConfig->ReceiveStoreForward = DISABLE; + + if (tmpreg & ETH_DMAOMR_DFRF) + pDMAConfig->FlushReceivedFrame = DISABLE; + else + pDMAConfig->FlushReceivedFrame = ENABLE; + + if (tmpreg & ETH_DMAOMR_TSF) + pDMAConfig->TransmitStoreForward = ENABLE; + else + pDMAConfig->TransmitStoreForward = DISABLE; + + if ((tmpreg & ETH_DMAOMR_TTC) == 0) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_64BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == ETH_DMAOMR_TTC_0) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_128BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == ETH_DMAOMR_TTC_1) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_192BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == (ETH_DMAOMR_TTC_1 | ETH_DMAOMR_TTC_0)) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_256BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == ETH_DMAOMR_TTC_2) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_40BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == (ETH_DMAOMR_TTC_2 | ETH_DMAOMR_TTC_0)) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_32BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == (ETH_DMAOMR_TTC_2 | ETH_DMAOMR_TTC_1)) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_24BYTES; + else if ((tmpreg & ETH_DMAOMR_TTC) == (ETH_DMAOMR_TTC_2 | ETH_DMAOMR_TTC_1 | ETH_DMAOMR_TTC_0)) + pDMAConfig->TransmitThresholdControl = ETH_TRANSMIT_THRESHOLD_CONTROL_16BYTES; + + if (tmpreg & ETH_DMAOMR_FEF) + pDMAConfig->ForwardErrorFrames = ENABLE; + else + pDMAConfig->ForwardErrorFrames = DISABLE; + + if (tmpreg & ETH_DMAOMR_FUGF) + pDMAConfig->ForwardUndersizedGoodFrames = ENABLE; + else + pDMAConfig->ForwardUndersizedGoodFrames = DISABLE; + + if ((tmpreg & ETH_DMAOMR_RTC) == 0) + pDMAConfig->ReceiveThresholdControl = ETH_RECEIVED_THRESHOLD_CONTROL_64BYTES; + else if ((tmpreg & ETH_DMAOMR_RTC) == ETH_DMAOMR_RTC_0) + pDMAConfig->ReceiveThresholdControl = ETH_RECEIVED_THRESHOLD_CONTROL_32BYTES; + else if ((tmpreg & ETH_DMAOMR_RTC) == ETH_DMAOMR_RTC_1) + pDMAConfig->ReceiveThresholdControl = ETH_RECEIVED_THRESHOLD_CONTROL_96BYTES; + else if ((tmpreg & ETH_DMAOMR_RTC) == (ETH_DMAOMR_RTC_1 | ETH_DMAOMR_RTC_0)) + pDMAConfig->ReceiveThresholdControl = ETH_RECEIVED_THRESHOLD_CONTROL_128BYTES; + + + if (tmpreg & ETH_DMAOMR_OSF) + pDMAConfig->SecondFrameOperate = ENABLE; + else + pDMAConfig->SecondFrameOperate = DISABLE; + + // DMABMR + tmpreg = (heth->Instance)->DMABMR; + + if (tmpreg & ETH_DMABMR_MB) + pDMAConfig->MixedBurst = ENABLE; + else + pDMAConfig->MixedBurst = DISABLE; + + if (tmpreg & ETH_DMABMR_AAB) + pDMAConfig->AddressAlignedBeats = ENABLE; + else + pDMAConfig->AddressAlignedBeats = DISABLE; + + if (tmpreg & ETH_DMABMR_EPM) + pDMAConfig->PBL8xMode = ENABLE; + else + pDMAConfig->PBL8xMode = DISABLE; + + if (tmpreg & ETH_DMABMR_USP) + pDMAConfig->UseSeparatePBL = ENABLE; + else + pDMAConfig->UseSeparatePBL = DISABLE; + + if ((tmpreg & ETH_DMABMR_RDP) == ETH_DMABMR_RDP_0) + pDMAConfig->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_1BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == ETH_DMABMR_RDP_1) + pDMAConfig->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_2BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == ETH_DMABMR_RDP_2) + pDMAConfig->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_4BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == (ETH_DMABMR_RDP_3)) + pDMAConfig->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_8BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == (ETH_DMABMR_RDP_4)) + pDMAConfig->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_16BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == (ETH_DMABMR_RDP_5)) + pDMAConfig->RxDMABurstLen = ETH_RX_DMA_BURST_LEN_32BEAT; + else + err = 1; + + if (tmpreg & ETH_DMABMR_FB) + pDMAConfig->FixedBurst = ENABLE; + else + pDMAConfig->FixedBurst = DISABLE; + + if ((tmpreg & ETH_DMAOMR_RTC) == 0) + pDMAConfig->RxTxPriorityRatio = ETH_RX_TX_PRIORITY_RATIO_1_1; + else if ((tmpreg & ETH_DMAOMR_RTC) == ETH_DMABMR_PM_0) + pDMAConfig->RxTxPriorityRatio = ETH_RX_TX_PRIORITY_RATIO_2_1; + else if ((tmpreg & ETH_DMAOMR_RTC) == ETH_DMABMR_PM_1) + pDMAConfig->RxTxPriorityRatio = ETH_RX_TX_PRIORITY_RATIO_3_1; + else if ((tmpreg & ETH_DMAOMR_RTC) == (ETH_DMABMR_PM_1 | ETH_DMABMR_PM_0)) + pDMAConfig->RxTxPriorityRatio = ETH_RX_TX_PRIORITY_RATIO_4_1; + else + err = 1; + + if ((tmpreg & ETH_DMABMR_RDP) == ETH_DMABMR_PBL_0) + pDMAConfig->TxDMABurstLen = ETH_RX_DMA_BURST_LEN_1BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == ETH_DMABMR_PBL_1) + pDMAConfig->TxDMABurstLen = ETH_RX_DMA_BURST_LEN_2BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == ETH_DMABMR_PBL_2) + pDMAConfig->TxDMABurstLen = ETH_RX_DMA_BURST_LEN_4BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == (ETH_DMABMR_PBL_3)) + pDMAConfig->TxDMABurstLen = ETH_RX_DMA_BURST_LEN_8BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == (ETH_DMABMR_PBL_4)) + pDMAConfig->TxDMABurstLen = ETH_RX_DMA_BURST_LEN_16BEAT; + else if ((tmpreg & ETH_DMABMR_RDP) == (ETH_DMABMR_PBL_5)) + pDMAConfig->TxDMABurstLen = ETH_RX_DMA_BURST_LEN_32BEAT; + else + err = 1; + + if (tmpreg & ETH_DMABMR_EDFE) + pDMAConfig->EnhancedDescriptorFormat = ENABLE; + else + pDMAConfig->EnhancedDescriptorFormat = DISABLE; + + pDMAConfig->EnhancedDescriptorFormat = (tmpreg & ETH_DMABMR_EDFE) >> ETH_DMABMR_EDFE_Pos; + + pDMAConfig->DescriptorSkipLen = (tmpreg & ETH_DMABMR_DSL) >> ETH_DMABMR_DSL_Pos; + + if (tmpreg & ETH_DMABMR_DA) + pDMAConfig->DMAArbitration = ETH_DMA_ARBITRATION_RX_PRIOR_TX; + else + pDMAConfig->DMAArbitration = ETH_DMA_ARBITRATION_ROUNDROBIN; + + if (err == 0) + return HAL_OK; + else + return HAL_ERROR; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *pDMAConfig); +// DMA +// hethETH_HandleTypeDefṹָ룻 +// pDMAConfigýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg = 0; + ETH_DMAInitTypeDef *pDMAConfig = &heth->DMAConfig; + + if (heth == NULL) + return (HAL_ERROR); + + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->DropTCPIPChecksumErrorFrame)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->ReceiveStoreForward)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->FlushReceivedFrame)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(pDMAConfig->TransmitThresholdControl)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->ForwardErrorFrames)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVED_THRESHOLD_CONTROL(pDMAConfig->ReceiveThresholdControl)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->SecondFrameOperate)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->MixedBurst)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->AddressAlignedBeats)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->PBL8xMode)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->UseSeparatePBL)); + assert_param(IS_ETH_RX_DMA_BURST_LEN(pDMAConfig->RxDMABurstLen)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->FixedBurst)); + assert_param(IS_ETH_RX_TX_PRIORITY_RATIO(pDMAConfig->RxTxPriorityRatio)); + assert_param(IS_ETH_TX_DMA_BURST_LEN(pDMAConfig->TxDMABurstLen)); + assert_param(IS_FUNCTIONAL_STATE(pDMAConfig->EnhancedDescriptorFormat)); + assert_param(IS_ETH_DESCRIPTOR_SKIP_LEN(pDMAConfig->DescriptorSkipLen)); + assert_param(IS_ETH_DMA_ARBITRATION(pDMAConfig->DMAArbitration)); + + // DMAOMR + tmpreg = (heth->Instance)->DMAOMR; + tmpreg &= 0xF8DE3F23U; + + if (pDMAConfig->DropTCPIPChecksumErrorFrame != DISABLE) + tmpreg |= ETH_DMAOMR_DTCEFD; + + if (pDMAConfig->ReceiveStoreForward != DISABLE) + tmpreg |= ETH_DMAOMR_RSF; + + if (pDMAConfig->FlushReceivedFrame == DISABLE) + tmpreg |= ETH_DMAOMR_DFRF; + + if (pDMAConfig->TransmitStoreForward != DISABLE) + tmpreg |= ETH_DMAOMR_TSF; + + if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_64BYTES) + tmpreg |= 0; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_128BYTES) + tmpreg |= ETH_DMAOMR_TTC_0; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_192BYTES) + tmpreg |= ETH_DMAOMR_TTC_1; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_256BYTES) + tmpreg |= ETH_DMAOMR_TTC_1 | ETH_DMAOMR_TTC_0; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_40BYTES) + tmpreg |= ETH_DMAOMR_TTC_2; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_32BYTES) + tmpreg |= ETH_DMAOMR_TTC_2 | ETH_DMAOMR_TTC_0; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_24BYTES) + tmpreg |= ETH_DMAOMR_TTC_2 | ETH_DMAOMR_TTC_1; + else if (pDMAConfig->TransmitThresholdControl == ETH_TRANSMIT_THRESHOLD_CONTROL_16BYTES) + tmpreg |= ETH_DMAOMR_TTC_2 | ETH_DMAOMR_TTC_1 | ETH_DMAOMR_TTC_0; + + if (pDMAConfig->ForwardErrorFrames != DISABLE) + tmpreg |= ETH_DMAOMR_FEF; + + if (pDMAConfig->ForwardUndersizedGoodFrames != DISABLE) + tmpreg |= ETH_DMAOMR_FUGF; + + if (pDMAConfig->ReceiveThresholdControl == ETH_RECEIVED_THRESHOLD_CONTROL_64BYTES) + tmpreg |= 0; + else if (pDMAConfig->ReceiveThresholdControl == ETH_RECEIVED_THRESHOLD_CONTROL_32BYTES) + tmpreg |= ETH_DMAOMR_RTC_0; + else if (pDMAConfig->ReceiveThresholdControl == ETH_RECEIVED_THRESHOLD_CONTROL_96BYTES) + tmpreg |= ETH_DMAOMR_RTC_1; + else if (pDMAConfig->ReceiveThresholdControl == ETH_RECEIVED_THRESHOLD_CONTROL_128BYTES) + tmpreg |= ETH_DMAOMR_RTC_1 | ETH_DMAOMR_RTC_0; + + if (pDMAConfig->SecondFrameOperate != DISABLE) + tmpreg |= ETH_DMAOMR_OSF; + + (heth->Instance)->DMAOMR = (uint32_t)tmpreg; + + // DMABMR + tmpreg = 0; + + if (pDMAConfig->MixedBurst != DISABLE) + tmpreg |= ETH_DMABMR_MB; + + if (pDMAConfig->AddressAlignedBeats != DISABLE) + tmpreg |= ETH_DMABMR_AAB; + + if (pDMAConfig->PBL8xMode != DISABLE) + tmpreg |= ETH_DMABMR_EPM; + + if (pDMAConfig->UseSeparatePBL != DISABLE) + tmpreg |= ETH_DMABMR_USP; + + if (pDMAConfig->RxDMABurstLen == ETH_RX_DMA_BURST_LEN_1BEAT) + tmpreg |= ETH_DMABMR_RDP_0; + else if (pDMAConfig->RxDMABurstLen == ETH_RX_DMA_BURST_LEN_2BEAT) + tmpreg |= ETH_DMABMR_RDP_1; + else if (pDMAConfig->RxDMABurstLen == ETH_RX_DMA_BURST_LEN_4BEAT) + tmpreg |= ETH_DMABMR_RDP_2; + else if (pDMAConfig->RxDMABurstLen == ETH_RX_DMA_BURST_LEN_8BEAT) + tmpreg |= ETH_DMABMR_RDP_3; + else if (pDMAConfig->RxDMABurstLen == ETH_RX_DMA_BURST_LEN_16BEAT) + tmpreg |= ETH_DMABMR_RDP_4; + else if (pDMAConfig->RxDMABurstLen == ETH_RX_DMA_BURST_LEN_32BEAT) + tmpreg |= ETH_DMABMR_RDP_5; + + if (pDMAConfig->FixedBurst != DISABLE) + tmpreg |= ETH_DMABMR_FB; + + if (pDMAConfig->RxTxPriorityRatio == ETH_RX_TX_PRIORITY_RATIO_1_1) + tmpreg |= 0; + else if (pDMAConfig->RxTxPriorityRatio == ETH_RX_TX_PRIORITY_RATIO_2_1) + tmpreg |= ETH_DMABMR_PM_0; + else if (pDMAConfig->RxTxPriorityRatio == ETH_RX_TX_PRIORITY_RATIO_3_1) + tmpreg |= ETH_DMABMR_PM_1; + else if (pDMAConfig->RxTxPriorityRatio == ETH_RX_TX_PRIORITY_RATIO_4_1) + tmpreg |= ETH_DMABMR_PM_1 | ETH_DMABMR_PM_0; + + if (pDMAConfig->TxDMABurstLen == ETH_TX_DMA_BURST_LEN_1BEAT) + tmpreg |= ETH_DMABMR_PBL_0; + else if (pDMAConfig->TxDMABurstLen == ETH_TX_DMA_BURST_LEN_2BEAT) + tmpreg |= ETH_DMABMR_PBL_1; + else if (pDMAConfig->TxDMABurstLen == ETH_TX_DMA_BURST_LEN_4BEAT) + tmpreg |= ETH_DMABMR_PBL_2; + else if (pDMAConfig->TxDMABurstLen == ETH_TX_DMA_BURST_LEN_8BEAT) + tmpreg |= ETH_DMABMR_PBL_3; + else if (pDMAConfig->TxDMABurstLen == ETH_TX_DMA_BURST_LEN_16BEAT) + tmpreg |= ETH_DMABMR_PBL_4; + else if (pDMAConfig->TxDMABurstLen == ETH_TX_DMA_BURST_LEN_32BEAT) + tmpreg |= ETH_DMABMR_PBL_5; + + if (pDMAConfig->EnhancedDescriptorFormat != DISABLE) + tmpreg |= ETH_DMABMR_EDFE; + + tmpreg |= (pDMAConfig->DescriptorSkipLen << ETH_DMABMR_DSL_Pos) & ETH_DMABMR_DSL; + + if (pDMAConfig->DMAArbitration != ETH_DMA_ARBITRATION_ROUNDROBIN) + tmpreg |= ETH_DMABMR_DA; + else + tmpreg |= 0; + + (heth->Instance)->DMABMR = (uint32_t)tmpreg; + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_ETH_SetDMADefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitDMADefaultParamter(heth); + + return HAL_ETH_SetDMAConfig(heth); +} + +// **************************************************************************** +// +// Flow Control +// +// **************************************************************************** + +uint32_t HAL_ETH_GetFlowCtrlStatus(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (0); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return (1); + else + return (0); +} + +HAL_StatusTypeDef HAL_ETH_RecvFlowCtrlEnable(ETH_HandleTypeDef *heth, uint32_t pausetime) +{ + volatile uint32_t tmpreg; + + if (heth == NULL) + return (HAL_ERROR); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return HAL_ERROR; + + tmpreg = heth->Instance->MACFCR & ~ETH_MACFCR_PT; + + tmpreg |= (pausetime << ETH_MACFCR_PT_Pos) & ETH_MACFCR_PT; + tmpreg |= ETH_MACFCR_TFCE; + + heth->Instance->MACFCR = tmpreg | ETH_MACFCR_FCB_BPA; + +// heth->Instance->MACFCR |= ETH_MACFCR_FCB_BPA; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_RecvFlowCtrlDisable(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + + if (heth == NULL) + return (HAL_ERROR); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return HAL_ERROR; + + tmpreg = heth->Instance->MACFCR & ~ETH_MACFCR_PT; + + tmpreg |= ETH_MACFCR_TFCE; + + heth->Instance->MACFCR = tmpreg | ETH_MACFCR_FCB_BPA; + +// heth->Instance->MACFCR |= ETH_MACFCR_FCB_BPA; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SendFlowCtrlEnable(ETH_HandleTypeDef *heth, uint32_t unicast_pause_frame_detect) +{ + volatile uint32_t tmpreg; + + if (heth == NULL) + return (HAL_ERROR); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return HAL_ERROR; + + tmpreg = heth->Instance->MACFCR; + + if (unicast_pause_frame_detect) + tmpreg |= ETH_MACFCR_UPFD; + else + tmpreg &= ~ETH_MACFCR_UPFD; + + tmpreg |= ETH_MACFCR_RFCE; + + heth->Instance->MACFCR = tmpreg; + +// heth->Instance->MACFFR |= BIT7 | BIT6; + + + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SendFlowCtrlDisable(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return HAL_ERROR; + + heth->Instance->MACFCR &= ~(ETH_MACFCR_UPFD | ETH_MACFCR_RFCE); + + return HAL_OK; +} + +uint32_t HAL_ETH_GetBackPressureStatus(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (0); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return (1); + else + return (0); +} + +HAL_StatusTypeDef HAL_ETH_BackPressureEnable(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + if (heth->Instance->MACFCR & ETH_MACFCR_FCB_BPA) + return HAL_ERROR; + + heth->Instance->MACFCR |= ETH_MACFCR_TFCE | ETH_MACFCR_FCB_BPA; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_BackPressureDisable(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + heth->Instance->MACFCR &= ~(ETH_MACFCR_FCB_BPA); + heth->Instance->MACFCR &= ~(ETH_MACFCR_TFCE); + + return HAL_OK; +} + + +// **************************************************************************** +// +// MMC +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitMMCDefaultParamter(ETH_HandleTypeDef *heth) +{ + // MMC + heth->MMCConfig.UpdateForDroppedBroadcast = 0; + heth->MMCConfig.FullHalfPreset = 0; + heth->MMCConfig.Preset = 0; + heth->MMCConfig.ResetOnRead = 0; + heth->MMCConfig.StopRollover = 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetMMCCounter(ETH_HandleTypeDef *heth) +{ + ETH_MMCCounterTypeDef *pMMCCounter = &heth->MMCCounter; + + if (heth == NULL) + return (HAL_ERROR); + + pMMCCounter->TxGoodFrameSingleCollision = heth->Instance->MMCTGFSCCR; + pMMCCounter->TxGoodFrameMultipleCollision = heth->Instance->MMCTGFMCCR; + pMMCCounter->TxGoodFrame = heth->Instance->MMCTGFCR; + pMMCCounter->RxCRCErr = heth->Instance->MMCRFCECR; + pMMCCounter->RxAlignmentErr = heth->Instance->MMCRFAECR; + pMMCCounter->RxGoodUnicast = heth->Instance->MMCRGUFCR; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetMMCConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_MMCInitTypeDef *pMMCConfig = &heth->MMCConfig; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pMMCConfig, 0, sizeof(ETH_MMCInitTypeDef)); + tmpreg = heth->Instance->MMCCR; + + if (tmpreg & ETH_MMCCR_UCDBC) + pMMCConfig->UpdateForDroppedBroadcast = 1; + + if (tmpreg & ETH_MMCCR_CNTPRSTLVL) + pMMCConfig->FullHalfPreset = 1; + + if (tmpreg & ETH_MMCCR_CNTPRST) + pMMCConfig->Preset = 1; + + if (tmpreg & ETH_MMCCR_RSTONRD) + pMMCConfig->ResetOnRead = 1; + + if (tmpreg & ETH_MMCCR_CNTSTOPRO) + pMMCConfig->StopRollover = 1; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetMMCConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_MMCInitTypeDef *pMMCConfig = &heth->MMCConfig; + + if (heth == NULL) + return (HAL_ERROR); + + tmpreg = 0; + + if (pMMCConfig->UpdateForDroppedBroadcast) + SET_BIT(tmpreg, ETH_MMCCR_UCDBC); + + if (pMMCConfig->FullHalfPreset) + SET_BIT(tmpreg, ETH_MMCCR_CNTPRSTLVL); + + if (pMMCConfig->Preset) + SET_BIT(tmpreg, ETH_MMCCR_CNTPRST); + + if (pMMCConfig->ResetOnRead) + SET_BIT(tmpreg, ETH_MMCCR_RSTONRD); + + if (pMMCConfig->StopRollover) + SET_BIT(tmpreg, ETH_MMCCR_CNTSTOPRO); + + WRITE_REG(heth->Instance->MMCCR, tmpreg); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetMMCDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitMMCDefaultParamter(heth); + + return HAL_ETH_SetMMCConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_MMCFreezeCounter(ETH_HandleTypeDef *heth, FunctionalState cmd) +{ + assert_param(IS_FUNCTIONAL_STATE(cmd)); + + if (heth == NULL) + return (HAL_ERROR); + + if (cmd == DISABLE) + { + CLEAR_BIT(heth->Instance->MMCCR, ETH_MMCCR_CNTFREEZ); + } + else + { + SET_BIT(heth->Instance->MMCCR, ETH_MMCCR_CNTFREEZ); + } + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_MMCResetCounter(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + SET_BIT(heth->Instance->MMCCR, ETH_MMCCR_CNTRST); + + return HAL_OK; +} + + +// **************************************************************************** +// +// LPI +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitLPIDefaultParamter(ETH_HandleTypeDef *heth) +{ + // MMC + heth->LPIConfig.TxAuto = 0; + heth->LPIConfig.TxClockGateCtrlInvalid = 0; + heth->LPIConfig.EntryTime = 100; + heth->LPIConfig.ExtiTime = 10; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_GetLPIConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_LPITypeDef *pLPIConfig = &heth->LPIConfig; + + if (heth == NULL) + return (HAL_ERROR); + + memset((void *)pLPIConfig, 0, sizeof(ETH_LPITypeDef)); + + tmpreg = heth->Instance->MACLPICSR; + + if (tmpreg & ETH_MACLPICSR_LPITXA) + pLPIConfig->TxAuto = 1; + + if (SYSCFG->SYSCR & SYSCFG_SYSCR_ETHMAC_TX_CLKGE) + pLPIConfig->TxClockGateCtrlInvalid = 1; + + if (tmpreg & ETH_MACLPICSR_PLSEN) + pLPIConfig->EntryTime = (heth->Instance->MACLPITCR & ETH_MACLPITCR_LST) >> ETH_MACLPITCR_LST_Pos; + + pLPIConfig->ExtiTime = (heth->Instance->MACLPITCR & ETH_MACLPITCR_TWT) >> ETH_MACLPITCR_TWT_Pos; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetLPIConfig(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tmpreg; + ETH_LPITypeDef *pLPIConfig = &heth->LPIConfig; + + if (heth == NULL) + return (HAL_ERROR); + + if (pLPIConfig->TxClockGateCtrlInvalid) + SYSCFG->SYSCR |= SYSCFG_SYSCR_ETHMAC_TX_CLKGE; + else + SYSCFG->SYSCR &= ~SYSCFG_SYSCR_ETHMAC_TX_CLKGE; + + heth->Instance->MACLPITCR = (((uint32_t)pLPIConfig->EntryTime << ETH_MACLPITCR_LST_Pos) & ETH_MACLPITCR_LST) | \ + (((uint32_t)pLPIConfig->ExtiTime << ETH_MACLPITCR_TWT_Pos) & ETH_MACLPITCR_TWT); + + tmpreg = heth->Instance->MACLPICSR & ~(ETH_MACLPICSR_LPITXA | ETH_MACLPICSR_PLSEN); + + if (pLPIConfig->TxAuto) + tmpreg |= ETH_MACLPICSR_LPITXA; + + heth->Instance->MACLPICSR = tmpreg; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetLPIDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitLPIDefaultParamter(heth); + + return HAL_ETH_SetLPIConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_EnterLPIMode(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + heth->Instance->MACLPICSR |= ETH_MACLPICSR_LPIEN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_ExitLPIMode(ETH_HandleTypeDef *heth) +{ + if (heth == NULL) + return (HAL_ERROR); + + heth->Instance->MACLPICSR &= ~ETH_MACLPICSR_LPIEN; + + return HAL_OK; +} + + + +// **************************************************************************** +// +// PMT +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitPMTDefaultParamter(ETH_HandleTypeDef *heth) +{ + memset((void *)&heth->PMTConfig, 0, sizeof(ETH_PMTInitTypeDef)); + + return HAL_OK; +} +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_GetPMTConfig(ETH_HandleTypeDef *heth, ETH_PMTInitTypeDef *pPMTConfig); +// ȡPMT +// hethETH_HandleTypeDefṹָ룻 +// pPMTConfigýṹָ룻 +// HAL_OKȡóɹ +// HAL_ERRORȡʧܣ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_GetPMTConfig(ETH_HandleTypeDef *heth) +{ + uint32_t i; + uint32_t err; + volatile uint32_t tmpreg; + ETH_PMTInitTypeDef *pPMTConfig = &heth->PMTConfig; + + if (heth == NULL) + return (HAL_ERROR); + + err = 0; + (heth->Instance)->MACPMTCSR |= ETH_MACPMTCSR_RWFFPR; + + pPMTConfig->Filter[0].Mask = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[1].Mask = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[2].Mask = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[3].Mask = (heth->Instance)->MACRWUFF; + + tmpreg = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[0].Cmd = tmpreg & 0x0f; + pPMTConfig->Filter[1].Cmd = (tmpreg >> 8) & 0x0f; + pPMTConfig->Filter[2].Cmd = (tmpreg >> 16) & 0x0f; + pPMTConfig->Filter[3].Cmd = (tmpreg >> 24) & 0x0f; + + tmpreg = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[0].Offset = tmpreg & 0xff; + pPMTConfig->Filter[1].Offset = (tmpreg >> 8) & 0xff; + pPMTConfig->Filter[2].Offset = (tmpreg >> 16) & 0xff; + pPMTConfig->Filter[3].Offset = (tmpreg >> 24) & 0xff; + + tmpreg = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[0].CRC16 = tmpreg & 0xffff; + pPMTConfig->Filter[1].CRC16 = (tmpreg >> 16) & 0xffff; + + tmpreg = (heth->Instance)->MACRWUFF; + pPMTConfig->Filter[2].CRC16 = tmpreg & 0xffff; + pPMTConfig->Filter[3].CRC16 = (tmpreg >> 16) & 0xffff; + + if ((heth->Instance)->MACPMTCSR & ETH_MACPMTCSR_GU) + pPMTConfig->GlobalUnicast = 1; + else + pPMTConfig->GlobalUnicast = 0; + + + for (i=0; i<8; i++) + { + tmpreg = (heth->Instance)->MACRWUFF; + } + + for (i=0; i<4; i++) + { + if (pPMTConfig->Filter[i].Mask & BIT31) + { + err = 1; + break; + } + if (pPMTConfig->Filter[i].Offset < 12) + { + err = 1; + break; + } + } + + if (err == 0) + return HAL_OK; + else + return HAL_ERROR; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_SetPMTConfig(ETH_HandleTypeDef *heth, ETH_PMTInitTypeDef *pPMTConfig); +// PMT +// hethETH_HandleTypeDefṹָ룻 +// pPMTConfigýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetPMTConfig(ETH_HandleTypeDef *heth) +{ + uint32_t i; + uint32_t tmpreg; + ETH_PMTInitTypeDef *pPMTConfig = &heth->PMTConfig; + + if (heth == NULL) + return (HAL_ERROR); + + (heth->Instance)->MACPMTCSR |= ETH_MACPMTCSR_RWFFPR; + + for (i=0; i<4; i++) + { + (heth->Instance)->MACRWUFF = pPMTConfig->Filter[i].Mask; + } + + tmpreg = pPMTConfig->Filter[0].Cmd & 0x0f; + tmpreg |= (pPMTConfig->Filter[1].Cmd & 0x0f) << 8; + tmpreg |= (pPMTConfig->Filter[2].Cmd & 0x0f) << 16; + tmpreg |= (pPMTConfig->Filter[3].Cmd & 0x0f) << 24; + (heth->Instance)->MACRWUFF = tmpreg; + + tmpreg = pPMTConfig->Filter[0].Offset & 0xff; + tmpreg |= (pPMTConfig->Filter[1].Offset & 0xff) << 8; + tmpreg |= (pPMTConfig->Filter[2].Offset & 0xff) << 16; + tmpreg |= (pPMTConfig->Filter[3].Offset & 0xff) << 24; + (heth->Instance)->MACRWUFF = tmpreg; + + tmpreg = pPMTConfig->Filter[0].CRC16 & 0xffff; + tmpreg |= (pPMTConfig->Filter[1].CRC16 & 0xffff) << 16; + (heth->Instance)->MACRWUFF = tmpreg; + + tmpreg = pPMTConfig->Filter[2].CRC16 & 0xffff; + tmpreg |= (pPMTConfig->Filter[3].CRC16 & 0xffff) << 16; + (heth->Instance)->MACRWUFF = tmpreg; + + if (pPMTConfig->GlobalUnicast) + (heth->Instance)->MACPMTCSR |= BIT9; + else + (heth->Instance)->MACPMTCSR &= ~BIT9; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetPMTDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitPMTDefaultParamter(heth); + + return HAL_ETH_SetPMTConfig(heth); +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, uint32_t WakeupFrameEnable, uint32_t MagicPacketEnable); +// ģʽ +// hethETH_HandleTypeDefṹָ룻 +// WakeupModeģʽbit0жϻѣbit1¼ѣ +// WakeupFrameEnable֡ʹܣ +// MagicPacketEnableħʹܣ +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, uint32_t WakeupMode, uint32_t WakeupFrameEnable, uint32_t MagicPacketEnable) +{ + uint32_t tmpreg; + uint32_t timeout; + + if ((WakeupFrameEnable == 0) && (MagicPacketEnable == 0)) + return (HAL_ERROR); + + + /* Disable the DMA transmission */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; + + timeout = 0xffffff; + while ((heth->Instance)->DMASR & ETH_DMASR_TS) + { + if (--timeout == 0) + return (HAL_TIMEOUT); + } + + /* Disable the MAC transmission */ + (heth->Instance)->MACCR &= ~ETH_MACCR_TE; + + /* Disable the MAC reception */ + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + + timeout = 0xffffff; + while (((heth->Instance)->MACDBGR & ETH_MACDBGR_RFFL) != 0) + { + if (--timeout == 0) + return (HAL_TIMEOUT); + } + + /* Disable the DMA reception */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; + + __HAL_RCC_EXTI_CLK_ENABLE(); + + EXTI->RTENR2 &= ~BIT1; + EXTI->FTENR2 &= ~BIT1; + EXTI->PDR2 = BIT1; + if (WakeupMode & BIT0) + EXTI->IENR2 |= BIT1; + else + EXTI->IENR2 &= ~BIT1; + if (WakeupMode & BIT1) + EXTI->EENR2 |= BIT1; + else + EXTI->EENR2 &= ~BIT1; + EXTI->RTENR2 |= BIT1; + + if (WakeupMode) + (heth->Instance)->MACIMR &= ~ETH_MACIMR_PIM; + else + (heth->Instance)->MACIMR |= ETH_MACIMR_PIM; + + if (WakeupFrameEnable) + (heth->Instance)->MACPMTCSR |= ETH_MACPMTCSR_WFE; + else + (heth->Instance)->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + + if (MagicPacketEnable) + (heth->Instance)->MACPMTCSR |= ETH_MACPMTCSR_MPE; + else + (heth->Instance)->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + + (heth->Instance)->MACPMTCSR |= ETH_MACPMTCSR_PD; + + (heth->Instance)->MACCR |= ETH_MACCR_RE; + + return (HAL_OK); +} + + +// **************************************************************************** +// +// PTP +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_InitPTPDefaultParamter(ETH_HandleTypeDef *heth) +{ + uint32_t i; + + memset((void *)&heth->PTPConfig, 0, sizeof(ETH_PTPInitTypeDef)); + + heth->PTPConfig.IPV4Message = ENABLE; + heth->PTPConfig.DigitalRollover = ENABLE; + heth->PTPConfig.FineUpdate = ENABLE; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_GetPMTConfig(ETH_HandleTypeDef *heth, ETH_PMTInitTypeDef *pPMTConfig); +// ȡPMT +// hethETH_HandleTypeDefṹָ룻 +// pPMTConfigýṹָ룻 +// HAL_OKȡóɹ +// HAL_ERRORȡʧܣ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_GetPTPConfig(ETH_HandleTypeDef *heth) +{ + uint32_t i; + uint32_t err; + volatile uint32_t tmpreg; + ETH_PTPInitTypeDef *pPTPConfig = &heth->PTPConfig; + + if (heth == NULL) + return (HAL_ERROR); + + err = 0; + memset((void *)pPTPConfig, 0, sizeof(ETH_PTPInitTypeDef)); + + // PTPTSCR + tmpreg = (heth->Instance)->PTPTSCR; + + if (tmpreg & ETH_PTPTSCR_ASEN3) + pPTPConfig->Auxi[3] = ENABLE; + if (tmpreg & ETH_PTPTSCR_ASEN2) + pPTPConfig->Auxi[2] = ENABLE; + if (tmpreg & ETH_PTPTSCR_ASEN2) + pPTPConfig->Auxi[1] = ENABLE; + if (tmpreg & ETH_PTPTSCR_ASEN2) + pPTPConfig->Auxi[0] = ENABLE; + + if (tmpreg & ETH_PTPTSCR_EMAFPFF) + pPTPConfig->MACAddrFilter = ENABLE; + + pPTPConfig->Clock = (tmpreg & ETH_PTPTSCR_SPPFTS) >> ETH_PTPTSCR_SPPFTS_Pos; + + if (tmpreg & ETH_PTPTSCR_ESFMRTM) + pPTPConfig->MasterMessage = ENABLE; + + if (tmpreg & ETH_PTPTSCR_ETSFEM) + pPTPConfig->EventMessage = ENABLE; + + if (tmpreg & ETH_PTPTSCR_EPPFSIP4U) + pPTPConfig->IPV4Message = ENABLE; + + if (tmpreg & ETH_PTPTSCR_EPPFSIP6U) + pPTPConfig->IPV6Message = ENABLE; + + if (tmpreg & ETH_PTPTSCR_EPPEF) + pPTPConfig->EthernetFrame = ENABLE; + + if (tmpreg & ETH_PTPTSCR_TSPTPPSV2E) + pPTPConfig->Ver2 = ENABLE; + + if (tmpreg & ETH_PTPTSCR_TSR) + pPTPConfig->DigitalRollover = ENABLE; + + if (tmpreg & ETH_PTPTSCR_TSARFE) + pPTPConfig->AllFrames = ENABLE; + + if (tmpreg & ETH_PTPTSCR_TFCU) + pPTPConfig->FineUpdate = ENABLE; + + // PTPPPSCR + tmpreg = (heth->Instance)->PTPPPSCR ; + + if ((tmpreg & ETH_PTPPPSCR_TRGTMODSEL) == ETH_PTPPPSCR_TRGTMODSEL_0) + err = 1; + else + pPTPConfig->PPS.TargetTimeFunc = (tmpreg & ETH_PTPPPSCR_TRGTMODSEL) >> ETH_PTPPPSCR_TRGTMODSEL_Pos; + + if (tmpreg & ETH_PTPPPSCR_PPSEN) + { + pPTPConfig->PPS.Mode = ETH_PTP_PPS_OUTPUT_MODE_CMD; + pPTPConfig->PPS.Output.Cmd = (tmpreg & ETH_PTPPPSCR_PPSCMD) >> ETH_PTPPPSCR_PPSCMD_Pos; + } + else + { + pPTPConfig->PPS.Mode = ETH_PTP_PPS_OUTPUT_MODE_CTRL; + pPTPConfig->PPS.Output.Freq = (tmpreg & ETH_PTPPPSCR_PPSCTRL) >> ETH_PTPPPSCR_PPSCTRL_Pos; + } + + // PTPPPSIR + pPTPConfig->PPS.Interval = (heth->Instance)->PTPPPSIR; + + // PTPPPSWR + pPTPConfig->PPS.Width = (heth->Instance)->PTPPPSWR; + + if (err == 0) + return HAL_OK; + else + return HAL_ERROR; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_SetPMTConfig(ETH_HandleTypeDef *heth, ETH_PMTInitTypeDef *pPMTConfig); +// PMT +// hethETH_HandleTypeDefṹָ룻 +// pPMTConfigýṹָ룻 +// ޣ +// HAL_OKóɹ +// ע +// **************************************************************************** +HAL_StatusTypeDef HAL_ETH_SetPTPConfig(ETH_HandleTypeDef *heth) +{ + uint32_t i; + volatile uint32_t tmpreg; + ETH_PTPInitTypeDef *pPTPConfig = &heth->PTPConfig; + + if (heth == NULL) + return (HAL_ERROR); + + // PTPTSCR + tmpreg = (heth->Instance)->PTPTSCR & ~0x1e07ff02; + + if (pPTPConfig->Auxi[3] != DISABLE) + tmpreg |= ETH_PTPTSCR_ASEN3; + if (pPTPConfig->Auxi[2] != DISABLE) + tmpreg |= ETH_PTPTSCR_ASEN2; + if (pPTPConfig->Auxi[1] != DISABLE) + tmpreg |= ETH_PTPTSCR_ASEN1; + if (pPTPConfig->Auxi[0] != DISABLE) + tmpreg |= ETH_PTPTSCR_ASEN0; + + if (pPTPConfig->MACAddrFilter != DISABLE) + tmpreg |= ETH_PTPTSCR_EMAFPFF; + + tmpreg |= ((uint32_t)pPTPConfig->Clock << ETH_PTPTSCR_SPPFTS_Pos) & ETH_PTPTSCR_SPPFTS; + + if (pPTPConfig->MasterMessage != DISABLE) + tmpreg |= ETH_PTPTSCR_ESFMRTM; + + if (pPTPConfig->EventMessage != DISABLE) + tmpreg |= ETH_PTPTSCR_ETSFEM; + + if (pPTPConfig->IPV4Message != DISABLE) + tmpreg |= ETH_PTPTSCR_EPPFSIP4U; + + if (pPTPConfig->IPV6Message != DISABLE) + tmpreg |= ETH_PTPTSCR_EPPFSIP6U; + + if (pPTPConfig->EthernetFrame != DISABLE) + tmpreg |= ETH_PTPTSCR_EPPEF; + + if (pPTPConfig->Ver2 != DISABLE) + tmpreg |= ETH_PTPTSCR_TSPTPPSV2E; + + if (pPTPConfig->DigitalRollover != DISABLE) + { + tmpreg |= ETH_PTPTSCR_TSR; + ETH->PTPSSIR = 20u; + } + else + { + ETH->PTPSSIR = 43u; + } + + if (pPTPConfig->AllFrames != DISABLE) + tmpreg |= ETH_PTPTSCR_TSARFE; + + if (pPTPConfig->FineUpdate != DISABLE) + tmpreg |= ETH_PTPTSCR_TFCU; + + (heth->Instance)->PTPTSCR = tmpreg; + + // PTPTSCR + tmpreg = (heth->Instance)->PTPPPSCR & ~0x0000007f; + + tmpreg |= ((uint32_t)pPTPConfig->PPS.TargetTimeFunc << ETH_PTPPPSCR_TRGTMODSEL_Pos) & ETH_PTPPPSCR_TRGTMODSEL; + + if (pPTPConfig->PPS.Mode == ETH_PTP_PPS_OUTPUT_MODE_CMD) + { + tmpreg |= ETH_PTPPPSCR_PPSEN; + tmpreg |= ((uint32_t)pPTPConfig->PPS.Output.Cmd << ETH_PTPPPSCR_PPSCMD_Pos) & ETH_PTPPPSCR_PPSCMD; + } + else + { + tmpreg |= ((uint32_t)pPTPConfig->PPS.Output.Freq << ETH_PTPPPSCR_PPSCTRL_Pos) & ETH_PTPPPSCR_PPSCTRL; + } + + // PTPPPSIR + (heth->Instance)->PTPPPSIR = pPTPConfig->PPS.Interval; + + // PTPPPSWR + (heth->Instance)->PTPPPSWR = pPTPConfig->PPS.Width; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_SetPTPDefaultConfig(ETH_HandleTypeDef *heth) +{ + HAL_ETH_InitPTPDefaultParamter(heth); + + return HAL_ETH_SetPTPConfig(heth); +} + +HAL_StatusTypeDef HAL_ETH_PTPStart(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + uint64_t temp; + uint32_t timeout; + ETH_TypeDef *eth = heth->Instance; + + if (timestamp->nsec & BIT31) + return HAL_ERROR; + + // ֹʱж + eth->MACIMR |= ETH_MACIMR_TIM; + + // ʹʱ + eth->PTPTSCR |= ETH_PTPTSCR_TE; + + if (heth->PTPConfig.DigitalRollover) + eth->PTPSSIR = 20; + else + eth->PTPSSIR = 43; + + if (heth->PTPConfig.FineUpdate) + { + eth->PTPTSAR = (uint32_t)(pow(2,32) * 50000000 / HAL_RCC_GetHCLKFreq()); + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TARU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + eth->PTPTSCR |= ETH_PTPTSCR_TARU; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TARU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + eth->PTPTSCR |= ETH_PTPTSCR_TFCU; + } + else + { + eth->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TFCU); + } + + eth->PTPTSHUR = timestamp->sec; + if (heth->PTPConfig.DigitalRollover) + eth->PTPTSLUR = timestamp->nsec; + else + eth->PTPTSLUR = (uint32_t)((uint64_t)timestamp->nsec * 0x80000000 / 1000000000); + + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TI) + { + if (--timeout == 0) + return HAL_ERROR; + } + eth->PTPTSCR |= ETH_PTPTSCR_TI; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TI) + { + if (--timeout == 0) + return HAL_ERROR; + } + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPStop(ETH_HandleTypeDef *heth) +{ + uint32_t timeout; + ETH_TypeDef *eth = heth->Instance; + ETH_TimestampTypeDef timestamp; + + // ֹʱж + eth->MACIMR |= ETH_MACIMR_TIM; + + // ֹʱжϴ + eth->PTPTSCR &= ~ETH_PTPTSCR_TITE; + + // ֹʱ + eth->PTPTSCR &= ~ETH_PTPTSCR_TE; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPAdjFreq(ETH_HandleTypeDef *heth, int32_t freq) +{ + uint32_t sysclk; + uint32_t timeout; + ETH_TypeDef *eth = heth->Instance; + + sysclk = HAL_RCC_GetHCLKFreq(); + + if (freq >= 0) + { + sysclk += freq; + } + else + { + freq = -freq; + sysclk -= freq; + } + + eth->PTPTSAR = (uint32_t)(pow(2,32) * 50000000 / sysclk); + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TARU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + eth->PTPTSCR |= ETH_PTPTSCR_TARU; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TARU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPUpdateOffset(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + uint32_t sign; + uint32_t addend; + uint32_t timeout; + ETH_TypeDef *eth = heth->Instance; + + sign = 0; + if (timestamp->nsec & ETH_PTPTSLUR_AST) + { + sign = ETH_PTPTSLUR_AST; + timestamp->nsec &= ~ETH_PTPTSLUR_AST; + } + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TU) + { + if (--timeout == 0) + return HAL_ERROR; + } + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TI) + { + if (--timeout == 0) + return HAL_ERROR; + } + + /* read old addend register value*/ + addend = ETH->PTPTSAR; + + eth->PTPTSHUR = timestamp->sec; + if (heth->PTPConfig.DigitalRollover) + eth->PTPTSLUR = sign | (uint32_t)timestamp->nsec; + else + eth->PTPTSLUR = sign | (uint32_t)((uint64_t)timestamp->nsec * 0x80000000 / 1000000000); + + eth->PTPTSCR |= ETH_PTPTSCR_TU; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + // + ETH->PTPTSAR = addend; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TARU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + eth->PTPTSCR |= ETH_PTPTSCR_TARU; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TARU) + { + if (--timeout == 0) + return HAL_ERROR; + } + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPTimeSetTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + uint32_t sign; + uint32_t timeout; + ETH_TypeDef *eth = heth->Instance; + + sign = 0; + if (timestamp->nsec & ETH_PTPTSLUR_AST) + { + sign = ETH_PTPTSLUR_AST; + timestamp->nsec &= ~ETH_PTPTSLUR_AST; + } + + ETH->PTPTSHUR = timestamp->sec; + if (ETH->PTPTSCR & ETH_PTPTSCR_TSR) + ETH->PTPTSLUR = sign | timestamp->nsec; + else + ETH->PTPTSLUR = sign | (uint32_t)((uint64_t)timestamp->nsec * (uint64_t)0x80000000 / (uint64_t)1000000000); + + ETH->PTPTSCR |= ETH_PTPTSCR_TI; + + timeout = ETH_PTP_TIMEOUT; + while (eth->PTPTSCR & ETH_PTPTSCR_TI) + { + if (--timeout == 0) + return HAL_ERROR; + } + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPGetSystemTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + if (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSR) + timestamp->nsec = (int32_t)ETH->PTPTSLR; + else + timestamp->nsec = (int32_t)(((uint64_t)ETH->PTPTSLR * (uint64_t)1000000000) >> 31); + timestamp->sec = ETH->PTPTSHR; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPGetTargetTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + uint32_t timeout; + + timeout = ETH_PTP_TIMEOUT; + while (heth->Instance->PTPTTLR & ETH_PTPTTLR_TTRB ) + { + if (--timeout == 0) + return HAL_ERROR; + } + + if (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSR) + timestamp->nsec = (int32_t)ETH->PTPTTLR; + else + timestamp->nsec = (int32_t)(((uint64_t)ETH->PTPTTLR * (uint64_t)1000000000) >> 31); + timestamp->sec = ETH->PTPTTHR ; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPSetTargetTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + if (timestamp->nsec & ETH_PTPTSLUR_AST) + return HAL_ERROR; + + heth->Instance->PTPTTHR = timestamp->sec; + if (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSR) + heth->Instance->PTPTTLR = (uint32_t)timestamp->nsec; + else + heth->Instance->PTPTTLR = (uint32_t)((uint64_t)timestamp->nsec * (uint64_t)0x80000000 / (uint64_t)1000000000); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_ETH_PTPGetAuxiliaryTime(ETH_HandleTypeDef *heth, ETH_TimestampTypeDef *timestamp) +{ + if (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSR) + timestamp->nsec = (int32_t)ETH->PTPATSNR; + else + timestamp->nsec = (int32_t)(((uint64_t)ETH->PTPATSNR * (uint64_t)1000000000) >> 31); + timestamp->sec = ETH->PTPATSSR; + + return HAL_OK; +} + +uint32_t HAL_ETH_PTPGetAuxiTimeStatus(ETH_HandleTypeDef *heth, ETH_PTPAuxiTimeStatusTypeDef *status) +{ + volatile uint32_t tempreg; + + tempreg = heth->Instance->PTPTSSR; + + status->AuxiNbr = (tempreg & ETH_PTPTSSR_ATSNS) >> ETH_PTPTSSR_ATSNS_Pos; + + if (tempreg & ETH_PTPTSSR_ATSTM) + status->AuxiTriggerMissed = ENABLE; + else + status->AuxiTriggerMissed = DISABLE; + + if (tempreg & ETH_PTPTSSR_ATSTI_0) + status->AuxiTrigger[0] = ENABLE; + else + status->AuxiTrigger[0] = DISABLE; + + if (tempreg & ETH_PTPTSSR_ATSTI_1) + status->AuxiTrigger[1] = ENABLE; + else + status->AuxiTrigger[1] = DISABLE; + + if (tempreg & ETH_PTPTSSR_ATSTI_2) + status->AuxiTrigger[2] = ENABLE; + else + status->AuxiTrigger[2] = DISABLE; + + if (tempreg & ETH_PTPTSSR_ATSTI_3) + status->AuxiTrigger[3] = ENABLE; + else + status->AuxiTrigger[3] = DISABLE; + + return HAL_OK; +} + + +// **************************************************************************** +// +// SMI +// +// **************************************************************************** + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ConfigSMI(ETH_HandleTypeDef *heth) +// SMI +// hethETH_HandleTypeDefṹָ룻 +// ޣ +// HAL_OKóɹ +// HAL_ERRORʱƵʲЧΧ֮ڣ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_ConfigSMI(ETH_HandleTypeDef *heth) +{ + volatile uint32_t tempreg; + uint32_t hclk; + + //SMIʱ + tempreg = (heth->Instance)->MACMIIAR; + + tempreg &= ~ETH_MACMIIAR_CR; + + hclk = HAL_RCC_GetHCLKFreq(); + + if (hclk < 20000000) + return (HAL_ERROR); + else if (hclk < 35000000) + tempreg |= ETH_MACMIIAR_CR_1; + else if (hclk <= 60000000) + tempreg |= ETH_MACMIIAR_CR_1 | ETH_MACMIIAR_CR_0; + else if (hclk < 100000000) + tempreg |= 0; + else if (hclk < 150000000) + tempreg |= ETH_MACMIIAR_CR_0; + else if (hclk < 250000000) + tempreg |= ETH_MACMIIAR_CR_2; + else if (hclk < 300000000) + tempreg |= ETH_MACMIIAR_CR_2 | ETH_MACMIIAR_CR_0; + else + return (HAL_ERROR); + + (heth->Instance)->MACMIIAR = (uint32_t)tempreg; + + return (HAL_OK); +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); +// PHYĴ +// hethETH_HandleTypeDefṹָ룻 +// PHYRegĴַ +// RegValueָ룻 +// HAL_OKɹ +// HAL_BUSYæ +// HAL_TIMEOUTʱ +// HAL_ERRORPHYַ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *RegValue) +{ + volatile uint32_t tmpreg; + uint32_t tickstart = 0; + + if (READ_BIT(heth->Instance->MACMIIAR, ETH_MACMIIAR_MB)) + return HAL_BUSY; + + WRITE_REG(tmpreg, heth->Instance->MACMIIAR); + + MODIFY_REG(tmpreg, ETH_MACMIIAR_PA, (PHYAddr << ETH_MACMIIAR_PA_Pos)); + MODIFY_REG(tmpreg, ETH_MACMIIAR_MR, (PHYReg << ETH_MACMIIAR_MR_Pos)); + CLEAR_BIT(tmpreg, ETH_MACMIIAR_MW); + SET_BIT(tmpreg, ETH_MACMIIAR_MB); + WRITE_REG(heth->Instance->MACMIIAR, tmpreg); + + // ȴ + tickstart = HAL_GetTick(); + while(READ_BIT(heth->Instance->MACMIIAR, ETH_MACMIIAR_MB)) + { + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_PHY_WRITE) + return HAL_TIMEOUT; + } + + if (RegValue) + { + *RegValue = (uint16_t)(heth->Instance->MACMIIDR); + } + + heth->State = HAL_ETH_STATE_READY; + + return HAL_OK; +} + +// **************************************************************************** +// HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); +// дPHYĴ +// hethETH_HandleTypeDefṹָ룻 +// PHYRegĴַ +// RegValueдݣ +// ޣ +// HAL_OKдɹ +// HAL_BUSYæ +// HAL_TIMEOUTдʱ +// HAL_ERRORPHYַ +// ע +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue) +{ + volatile uint32_t tmpreg = 0; + uint32_t tickstart = 0; + + if (READ_BIT(heth->Instance->MACMIIAR, ETH_MACMIIAR_MB)) + return HAL_BUSY; + + WRITE_REG(tmpreg, heth->Instance->MACMIIAR); + + MODIFY_REG(tmpreg, ETH_MACMIIAR_PA, (PHYAddr << ETH_MACMIIAR_PA_Pos)); + MODIFY_REG(tmpreg, ETH_MACMIIAR_MR, (PHYReg << ETH_MACMIIAR_MR_Pos)); + SET_BIT(tmpreg, ETH_MACMIIAR_MW); + SET_BIT(tmpreg, ETH_MACMIIAR_MB); + + WRITE_REG(heth->Instance->MACMIIDR, RegValue); + + WRITE_REG(heth->Instance->MACMIIAR, tmpreg); + + //ȴд + tickstart = HAL_GetTick(); + while(READ_BIT(heth->Instance->MACMIIAR, ETH_MACMIIAR_MB)) + { + if((HAL_GetTick() - tickstart ) >= ETH_TIMEOUT_PHY_READ) + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +// **************************************************************************** +// +// Rx Delay +// +// **************************************************************************** + +HAL_StatusTypeDef HAL_ETH_RxClockDelayConfig(ETH_HandleTypeDef *heth, uint32_t uint, uint32_t len) +{ + SYSCFG->SYSCR |= SYSCFG_SYSCR_ETHMAC_RX_DLYSEL; + ETH_DLYB->CR = DLYB_CR_DEN; + ETH_DLYB->CR |= DLYB_CR_SEN; + ETH_DLYB->CFGR = ((uint << DLYB_CFGR_UNIT_Pos) & DLYB_CFGR_UNIT_Msk) | ((len << DLYB_CFGR_SEL_Pos) & DLYB_CFGR_SEL_Msk); + HAL_SimpleDelay(10); + ETH_DLYB->CR &= ~DLYB_CR_SEN; + + return HAL_OK; +} + + +#endif + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_exti.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_exti.c new file mode 100644 index 0000000000000000000000000000000000000000..5ff6c040453c38409c23a547b9fe0d88cd303d42 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_exti.c @@ -0,0 +1,431 @@ +/****************************************************************************** +*@file : hal_exti.c +*@brief : GPIO EXTI module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_EXTI_MODULE_ENABLED + +/****************************************************************************** +*@brief : EXTI interrupt request. +*@param : Line: Exti line number. +* This parameter can be a combination of @ref EXTI_Line. +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_EXTI_IRQHandler(uint32_t Line) +{ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + + if (Line < 32U) + { + if (EXTI->PDR1 & (1UL << Line)) + { + EXTI->PDR1 = 1UL << Line; + HAL_EXTI_LineCallback(Line); + } + } + else + { + if (EXTI->PDR2 & (1UL << (Line - 32))) + { + EXTI->PDR2 = 1UL << (Line - 32); + HAL_EXTI_LineCallback(Line); + } + } +} + +/****************************************************************************** +*@brief : EXTI interrupt callback. +*@param : Line: Exti line number. +* This parameter can be a combination of @ref EXTI_Line. +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_EXTI_LineCallback(uint32_t Line) +{ + UNUSED(Line); +} + +/****************************************************************************** +*@brief : Set configuration of a dedicated Exti line. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +* This parameter is only possible for line 0 to 15. +*@param : Line: Exti line number. +* This parameter can be a value of @ref EXTI_Line. +*@param : Mode: The Exit Mode to be configured for a core. + This parameter can be a value of @ref EXTI_Mode . +*@return: HAL Status +******************************************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(GPIO_TypeDef *GPIOx, uint32_t Line, uint32_t Mode) +{ + uint32_t mask1=0; + uint32_t mask2=0; + uint32_t source; + + /* Check the parameters */ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + assert_param(IS_EXTI_MODE(Mode)); + + /* disable interrupt and event */ + if (Line < 32U) + { + mask1 = 1UL << Line; + EXTI->IENR1 &= ~mask1; + EXTI->EENR1 &= ~mask1; + EXTI->RTENR1 &= ~mask1; + EXTI->FTENR1 &= ~mask1; + EXTI->PDR1 = mask1; + } + else + { + mask2 = 1UL << (Line - 32); + EXTI->IENR2 &= ~mask2; + EXTI->EENR2 &= ~mask2; + EXTI->RTENR2 &= ~mask2; + EXTI->FTENR2 &= ~mask2; + EXTI->PDR2 = mask2; + } + + /* Line0 ~ 15 trigger from GPIO */ + if (Line < 16U) + { + /* Check the parameters */ + assert_param(IS_EXTI_GPIO(GPIOx)); + + /* Configure EXTI source select */ + source = ((uint32_t)GPIOx - (uint32_t)GPIOA) >> 10; + + if (Line < 6U) + { + /* Line0 ~ 5 */ + EXTI->CR1 = (EXTI->CR1 & ~(0x1FUL << (Line * 5))) | (source << (Line * 5)); + } + else if (Line < 12U) + { + /* Line6 ~ 11 */ + EXTI->CR2 = (EXTI->CR2 & ~(0x1FUL << ((Line - 6) * 5))) | (source << ((Line - 6) * 5)); + } + else + { + /* Line12 ~ 15 */ + EXTI->CR3 = (EXTI->CR3 & ~(0x1FUL << ((Line - 12) * 5))) | (source << ((Line - 12) * 5)); + } + } + + if (Mode == EXTI_MODE_IT_RISING) + { + /* Interrupt rising edge mode */ + if (Line < 32U) + { + EXTI->RTENR1 |= mask1; + EXTI->IENR1 |= mask1; + } + else + { + EXTI->RTENR2 |= mask2; + EXTI->IENR2 |= mask2; + } + } + else if (Mode == EXTI_MODE_IT_FALLING) + { + /* Interrupt falling edge mode */ + if (Line < 32U) + { + EXTI->FTENR1 |= mask1; + EXTI->IENR1 |= mask1; + } + else + { + EXTI->FTENR2 |= mask2; + EXTI->IENR2 |= mask2; + } + } + else if (Mode == EXTI_MODE_IT_RISING_FALLING) + { + /* Interrupt rising and falling edge mode */ + if (Line < 32U) + { + EXTI->RTENR1 |= mask1; + EXTI->FTENR1 |= mask1; + EXTI->IENR1 |= mask1; + } + else + { + EXTI->RTENR2 |= mask2; + EXTI->FTENR2 |= mask2; + EXTI->IENR2 |= mask2; + } + } + else if (Mode == EXTI_MODE_EVT_RISING) + { + /* Event rising edge mode */ + if (Line < 32U) + { + EXTI->RTENR1 |= mask1; + EXTI->EENR1 |= mask1; + } + else + { + EXTI->RTENR2 |= mask2; + EXTI->EENR2 |= mask2; + } + } + else if (Mode == EXTI_MODE_EVT_FALLING) + { + /* Event falling edge mode */ + if (Line < 32U) + { + EXTI->FTENR1 |= mask1; + EXTI->EENR1 |= mask1; + } + else + { + EXTI->FTENR2 |= mask2; + EXTI->EENR2 |= mask2; + } + } + else if (Mode == EXTI_MODE_EVT_RISING_FALLING) + { + /* Event rising and falling edge mode */ + if (Line < 32U) + { + EXTI->RTENR1 |= mask1; + EXTI->FTENR1 |= mask1; + EXTI->EENR1 |= mask1; + } + else + { + EXTI->RTENR2 |= mask2; + EXTI->FTENR2 |= mask2; + EXTI->EENR2 |= mask2; + } + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Clear whole configuration of a dedicated Exti line. +*@param : Line: Exti line number. +* This parameter can be a value of @ref EXTI_Line. +*@return: HAL Status +******************************************************************************/ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(uint32_t Line) +{ + uint32_t mask1; + uint32_t mask2; + + /* Check the parameters */ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + + /* disable interrupt and event */ + if (Line < 32U) + { + mask1 = 1UL << Line; + EXTI->IENR1 &= ~mask1; + EXTI->EENR1 &= ~mask1; + EXTI->RTENR1 &= ~mask1; + EXTI->FTENR1 &= ~mask1; + EXTI->PDR1 = mask1; + } + else + { + mask2 = 1UL << (Line - 32); + EXTI->IENR2 &= ~mask2; + EXTI->EENR2 &= ~mask2; + EXTI->RTENR2 &= ~mask2; + EXTI->FTENR2 &= ~mask2; + EXTI->PDR2 = mask2; + } + + /* Line0 ~ 15 trigger from GPIO */ + if (Line < 16U) + { + if (Line < 6U) + { + /* Line0 ~ 5 */ + EXTI->CR1 = EXTI->CR1 & ~(0x1FUL << (Line * 5)); + } + else if (Line < 12U) + { + /* Line6 ~ 11 */ + EXTI->CR2 = EXTI->CR2 & ~(0x1FUL << ((Line - 6) * 5)); + } + else + { + /* Line12 ~ 15 */ + EXTI->CR3 = EXTI->CR3 & ~(0x1FUL << ((Line - 12) * 5)); + } + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Check whether the LINE of the specified GPIOx is configured. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +* This parameter is only possible for line 0 to 15. +*@param : Line: Exti line number. +* This parameter can be a value of @ref EXTI_Line. +*@return: configuration status +* This parameter can be a value of @ref FunctionalState. +* @arg ENABLE: Configured. +* @arg DISABLE: Not configured. +******************************************************************************/ +FunctionalState HAL_EXTI_IsConfigLine(GPIO_TypeDef *GPIOx, uint32_t Line) +{ + uint32_t mask1; + uint32_t mask2; + uint32_t source; + + /* Check the parameters */ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + + if (Line < 32U) + { + mask1 = 1UL << Line; + if (((EXTI->IENR1 & mask1) == 0) && ((EXTI->EENR1 & mask1) == 0)) + return (DISABLE); + } + else + { + mask2 = 1UL << (Line - 32); + if (((EXTI->IENR2 & mask2) == 0) && ((EXTI->EENR2 & mask2) == 0)) + return (DISABLE); + } + + if (Line >= 16U) + { + return (ENABLE); + } + + /* Line0 ~ 15 trigger from GPIO */ + + /* Check the parameters */ + assert_param(IS_EXTI_GPIO(GPIOx)); + + /* Configure EXTI source select */ + source = (GPIOx - GPIOA) >> 10; + + if (Line < 6U) + { + /* Line0 ~ 7 */ + if (((EXTI->CR1 >> (Line * 5)) & 0x1FU) == source) + return (ENABLE); + else + return (DISABLE); + } + else if (Line < 12U) + { + /* Line8 ~ 15 */ + if (((EXTI->CR2 >> ((Line - 6) * 5)) & 0x1FU) == source) + return (ENABLE); + else + return (DISABLE); + } + else + { + /* Line8 ~ 15 */ + if (((EXTI->CR3 >> ((Line - 12) * 5)) & 0x1FU) == source) + return (ENABLE); + else + return (DISABLE); + } +} + +/****************************************************************************** +*@brief : The specified Line generates a software interrupt. +*@param : Line: Exti line number. +* This parameter can be a combination of @ref EXTI_Line. +*@return: None. +******************************************************************************/ +void HAL_EXTI_GenerateSWI(uint32_t Line) +{ + uint32_t mask1; + uint32_t mask2; + + /* Check the parameters */ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + + if (Line < 32U) + { + mask1 = 1UL << Line; + EXTI->SWIER1 &= ~mask1; + EXTI->SWIER1 |= mask1; + } + else + { + mask2 = 1UL << (Line - 32); + EXTI->SWIER2 &= ~mask2; + EXTI->SWIER2 |= mask2; + } +} + +/****************************************************************************** +*@brief : Get interrupt pending bit of a dedicated line. +*@param : Line: Exti line number. +* This parameter can be a value of @ref EXTI_Line. +*@return: interrupt pending bit status +* This parameter can be a value of @ref FlagStatus. +* @arg SET: interrupt is pending. +* @arg RESET: interrupt is not pending. +******************************************************************************/ +FlagStatus HAL_EXTI_GetPending(uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + + if (Line < 32U) + { + if (EXTI->PDR1 & (1UL << Line)) + return (SET); + else + return (RESET); + } + else + { + if (EXTI->PDR2 & (1UL << (Line - 32))) + return (SET); + else + return (RESET); + } +} + +/****************************************************************************** +*@brief : Clear interrupt pending bit of a dedicated line. +*@param : Line: Exti line number. +* This parameter can be a combination of @ref EXTI_Line. +*@return: None. +******************************************************************************/ +void HAL_EXTI_ClearPending(uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_SINGLE_LINE(Line)); + + if (Line < 32U) + { + EXTI->PDR1 = 1UL << Line; + } + else + { + EXTI->PDR2 = 1UL << (Line - 32); + } +} + +/****************************************************************************** +*@brief : Clear all interrupt pending bit. +*@return: None. +******************************************************************************/ +void HAL_EXTI_ClearAllPending(void) +{ + /* Clear pending status */ + EXTI->PDR1 = 0xFFFFFFFF; + EXTI->PDR2 = 0x00000007; +} + + + +#endif /* HAL_EXTI_MODULE_ENABLED */ + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_fdcan.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_fdcan.c new file mode 100644 index 0000000000000000000000000000000000000000..ac83c224655bbb2c4ec7f59a064dcfb4833b7ee2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_fdcan.c @@ -0,0 +1,1116 @@ +#include "hal_fdcan.h" + +#ifdef HAL_FDCAN_MODULE_ENABLED + +__weak void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) +{ + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE); + HAL_FDCAN_RxBufferNewMessageCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_FULL) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_FULL); + HAL_FDCAN_RxBufferFullCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_OVERRUN) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_OVERRUN); + HAL_FDCAN_RxBufferOVCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_STB_COMPLETE) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_STB_COMPLETE); + HAL_FDCAN_TXSTBCompletedCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_PTB_COMPLETE) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_PTB_COMPLETE); + HAL_FDCAN_TXPTBCompletedCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_ALMOSTFULL) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_ALMOSTFULL); +// HAL_FDCAN_RxBufferAFCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); + HAL_FDCAN_TxAbortCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_ERROR) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_ERROR); + HAL_FDCAN_ErrorCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_BUS_ERROR) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_BUS_ERROR); + HAL_FDCAN_BusErrorCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_ERROR_PASSIVE) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_ERROR_PASSIVE); + HAL_FDCAN_ErrorPassiveCallback(hfdcan); + } + + if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_ARBITRATION_LOST) != 0U) + { + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_ARBITRATION_LOST); + HAL_FDCAN_ArbitrationLostCallback(hfdcan); + } + + if(__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TTCFG_REFMSGIF)) + { + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_REFMSGIF); + printfS("REFMSGIF\r\n"); + } + + if(__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TTCFG_WTIF)) + { + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_WTIF); + printfS("WTIF\r\n"); + } + + if(__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TTCFG_TTIF)) + { + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_TTIF); + HAL_FDCAN_TT_TimerTriggerCallback(hfdcan); + + } + + if(__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TTCFG_TEIF)) + { + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_TEIF); + printfS("TEIF\r\n"); + } + +} + + +/** + * @brief Initializes the FDCAN peripheral according to the specified + * parameters in the FDCAN_InitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_RX_BUF_MODE(hfdcan->Init.RxBufOverFlowMode)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Reset callbacks to legacy functions */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak + TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak + TxBufferAbortCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak + HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak + TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak + TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + + if (hfdcan->MspInitCallback == NULL) + { + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hfdcan->MspInitCallback(hfdcan); + } +#else + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspInit(hfdcan); + } +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Enter to RESET state */ + __HAL_FDCAN_ENTER_RESET_STATE(hfdcan); + + MODIFY_REG(hfdcan->Instance->CR, FDCAN_CR_FD_ISO, hfdcan->Init.FrameISOType); + + /* Set the nominal bit timing register */ + hfdcan->Instance->SBTR.b.PRESC = (uint8_t)hfdcan->Init.NominalPrescaler - 1; + hfdcan->Instance->SBTR.b.SJW = (uint8_t)hfdcan->Init.NominalSyncJumpWidth; + hfdcan->Instance->SBTR.b.SEG1 = (uint8_t)hfdcan->Init.NominalTimeSeg1 - 2; + hfdcan->Instance->SBTR.b.SEG2 = (uint8_t)hfdcan->Init.NominalTimeSeg2 - 1; + + /* If FD operation with BRS is selected, set the data bit timing register */ + hfdcan->Instance->FBTR.b.PRESC = (uint8_t)hfdcan->Init.DataPrescaler - 1; + hfdcan->Instance->FBTR.b.SJW = (uint8_t)hfdcan->Init.DataSyncJumpWidth; + hfdcan->Instance->FBTR.b.SEG1 = (uint8_t)hfdcan->Init.DataTimeSeg1 - 2; + hfdcan->Instance->FBTR.b.SEG2 = (uint8_t)hfdcan->Init.DataTimeSeg2 - 1; + + __HAL_FDCAN_EXIT_RESET_STATE(hfdcan); + + + if((hfdcan->Init.AutoRetransmission == DISABLE) || (hfdcan->Init.Mode == FDCAN_MODE_LBME)) + { + /* single shot mode */ + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TPSS); + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSSS); + } + else + { + /* Auto re-transmission */ + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_TPSS); + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_TSSS); + } + + if(hfdcan->Init.RxBufOverFlowMode == FDCAN_RX_BUF_BLOCKING) + { + /* 1 - The new message will not be stored */ + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_ROM); + } + else + { + /* 0 - The oldest message will be overwritten */ + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_ROM); + } + + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Reset FDCAN Operation Mode */ + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_LBME | FDCAN_CR_LBMI | FDCAN_CR_LOM | FDCAN_CR_SACK); + + SET_BIT(hfdcan->Instance->CR, hfdcan->Init.Mode); + + /* Initialize the error code */ + hfdcan->ErrorCode = ERR_FDCAN_NONE; + + /* Initialize the FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) +{ + /* Request leave initialisation */ + __HAL_FDCAN_EXIT_RESET_STATE(hfdcan); + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = ERR_FDCAN_NONE; + + /* Return function status */ + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) +{ + return HAL_OK; +} + + + +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig) +{ + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_NewConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_NewFilterTypeDef *sFilterConfig) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); +// assert_param(IS_FILTER_ID_TYPE(sFilterConfig->IdType)); + assert_param(IS_VALID_FILTER_INDEX(sFilterConfig->FilterIndex)); + + __HAL_FDCAN_ENTER_RESET_STATE(hfdcan); + + printfS("\r\n[%d]====================================:\r\n", sFilterConfig->FilterIndex); + + //MODIFY_REG(hfdcan->Instance->ACFCR.w, FDCAN_ACFCR_ACFADR_Msk, sFilterConfig->FilterIndex << FDCAN_ACFCR_ACFADR_Pos); + hfdcan->Instance->ACFCR.b.ACFADR = sFilterConfig->FilterIndex; + + switch(sFilterConfig->FilterType) + { + case FDCAN_FILTER_TYPE0: + hfdcan->Instance->ACFCR.b.SELMASK = 0; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type0.code32.w; + hfdcan->Instance->ACFCR.b.SELMASK = 1; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type0.mask32.w; + + hfdcan->Instance->ACFMODE &= (~((1 << sFilterConfig->FilterIndex) << 16)); //32bit + hfdcan->Instance->ACFMODE &= (~(1 << sFilterConfig->FilterIndex)); //mask + break; + + case FDCAN_FILTER_TYPE1: + hfdcan->Instance->ACFCR.b.SELMASK = 0; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type1.code32.w; + hfdcan->Instance->ACFCR.b.SELMASK = 1; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type1.code32_2.w; + + hfdcan->Instance->ACFMODE &= (~((1 << sFilterConfig->FilterIndex) << 16)); //32bit + hfdcan->Instance->ACFMODE |= (1 << sFilterConfig->FilterIndex); //mask Ч + break; + + case FDCAN_FILTER_TYPE2: + hfdcan->Instance->ACFCR.b.SELMASK = 0; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type2.code16.hw | (sFilterConfig->Filter.type2.code16_2.hw << 16); + hfdcan->Instance->ACFCR.b.SELMASK = 1; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type2.mask16.hw | (sFilterConfig->Filter.type2.mask16_2.hw << 16); + + hfdcan->Instance->ACFMODE |= (1 << sFilterConfig->FilterIndex) << 16; //16bit + hfdcan->Instance->ACFMODE &= (~(1 << sFilterConfig->FilterIndex)); //mask + break; + + case FDCAN_FILTER_TYPE3: + hfdcan->Instance->ACFCR.b.SELMASK = 0; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type3.code16.hw | (sFilterConfig->Filter.type3.code16_2.hw << 16); + hfdcan->Instance->ACFCR.b.SELMASK = 1; + hfdcan->Instance->ACODR = sFilterConfig->Filter.type3.code16_3.hw | (sFilterConfig->Filter.type3.code16_4.hw << 16); + + hfdcan->Instance->ACFMODE |= (1 << sFilterConfig->FilterIndex) << 16; //16bit + hfdcan->Instance->ACFMODE |= 1 << sFilterConfig->FilterIndex; //mask Ч + break; + } + + + __HAL_FDCAN_EXIT_RESET_STATE(hfdcan); + + hfdcan->Instance->ACFCR.b.AE |= 1 << sFilterConfig->FilterIndex; + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_EnableLoopBackInternal(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param (IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + if(HAL_FDCAN_GetBusStatus(hfdcan) & FDCAN_BUS_TACTIVE) + return HAL_BUSY; + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_LBMI); + + return HAL_OK; +} + +/* FDCAN should be re-initisized after calling HAL_FDCAN_DisLoopBackInternal */ +HAL_StatusTypeDef HAL_FDCAN_DisLoopBackInternal(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param (IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_RESET); + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_EnableLoopBackExternal(FDCAN_HandleTypeDef *hfdcan, bool sack) +{ + assert_param (IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + if(HAL_FDCAN_GetBusStatus(hfdcan) & FDCAN_BUS_TACTIVE) + return HAL_BUSY; + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_LBME); + if(sack) + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_SACK); + else + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_SACK); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_DisableLoopBackExternal(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param (IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_LBME); + + return HAL_OK; +} +/****************************************************************************** +*@brief : Transmission single shot mode configuration for PTB +* +*@param : hfdcan: a pointer of FDCAN_HandleTypeDef structure which contains +* the configuration information for the specified FDCAN. +*@param : state: Mode new state. This parameter can be: ENABLE or DISABLE. +*@note : If state is ENABLE, The transmission for PTB is configed in single shot mode, + otherwise it is in auto-retransmission mode. + The configuration will reset to default mode(auto-retransmission mode) + by module local reset. +*@return: None +******************************************************************************/ +void HAL_FDCAN_PTBTranmistSingleShot(FDCAN_HandleTypeDef *hfdcan, FunctionalState state) +{ + assert_param (IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param (IS_FUNCTIONAL_STATE(state)); + + if(state == ENABLE) + { + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TPSS); + } + else + { + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_TPSS); + } +} + +/****************************************************************************** +*@brief : Transmission single shot mode configuration for STB +* +*@param : hfdcan: a pointer of FDCAN_HandleTypeDef structure which contains +* the configuration information for the specified FDCAN. +*@param : state: Mode new state. This parameter can be: ENABLE or DISABLE. +*@note : If state is ENABLE, The transmission for PTB is configed in single shot mode, + otherwise it is in auto-retransmission mode. + The configuration will reset to default mode(auto-retransmission mode) + by module local reset. +*@return: None +******************************************************************************/ +void HAL_FDCAN_STBTranmistSingleShot(FDCAN_HandleTypeDef *hfdcan, FunctionalState state) +{ + assert_param (IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param (IS_FUNCTIONAL_STATE(state)); + + if(state == ENABLE) + { + __HAL_FDCAN_ENABLE_IT(hfdcan, FDCAN_IE_BUS_ERROR | FDCAN_IE_ARBITRATION_LOST); + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSSS); + } + else + { + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_TSSS); + } +} + +HAL_StatusTypeDef HAL_FDCAN_ClearEntireSTB(FDCAN_HandleTypeDef *hfdcan) +{ + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSALL | FDCAN_CR_TSA); + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_AddMessageToPTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) +{ + uint8_t i; + + uint8_t data_len; + + uint32_t* ptmp; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + assert_param(IS_FDCAN_DLC(pTxHeader->FrameInfo.b.DLC)); + + if(READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TPE)) + { + hfdcan->ErrorCode = ERR_FDCAN_PTB_LOCKED; + return HAL_BUSY; + } + + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_TBSEL); + + ptmp = (uint32_t*)pTxHeader; + + hfdcan->Instance->TBUF[0] = *ptmp++; + hfdcan->Instance->TBUF[1] = *ptmp; + + data_len = __HAL_FDCAN_DLC2LEN(pTxHeader->FrameInfo.b.DLC); + + for(i = 0; i < (data_len + 3) / 4; i++) + { + hfdcan->Instance->TBUF[2 + i] = *(uint32_t*)pTxData; + pTxData += 4; + } + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_TransmitMessageByPTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) +{ + HAL_StatusTypeDef status; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_DLC(pTxHeader->FrameInfo.b.DLC)); + + status = HAL_FDCAN_AddMessageToPTB(hfdcan, pTxHeader, pTxData); + + if(status) + return status; + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TPE); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_AddMessageToSTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) +{ + uint8_t i; + + uint8_t data_len; + + uint32_t* ptmp; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + assert_param(IS_FDCAN_DLC(pTxHeader->FrameInfo.b.DLC)); + + if((hfdcan->Instance->CR & FDCAN_CR_TSSTAT) == (3 << FDCAN_CR_TSSTAT_Pos)) + { + hfdcan->ErrorCode |= ERR_FDCAN_TXBUF_FULL; + return HAL_BUSY; + } + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TBSEL); + + ptmp = (uint32_t*)pTxHeader; + + hfdcan->Instance->TBUF[0] = *ptmp++; + hfdcan->Instance->TBUF[1] = *ptmp; + + data_len = __HAL_FDCAN_DLC2LEN(pTxHeader->FrameInfo.b.DLC); + + for(i = 0; i < (data_len + 3) / 4; i++) + { + hfdcan->Instance->TBUF[2 + i] = *(uint32_t*)pTxData; + pTxData += 4; + } + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSNEXT); + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_EnableSTBPriorityMode(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSMODE); + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_DisableSTBPriorityMode(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_TSMODE); + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_TransmitMessageBySTB(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) +{ + HAL_StatusTypeDef status; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_DLC(pTxHeader->FrameInfo.b.DLC)); + + status = HAL_FDCAN_AddMessageToSTB(hfdcan, pTxHeader, pTxData); + + if(status) + return status; + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSALL); + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, TransmitType_enum type) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TRANSMIT_TYPE(type)); + + if(type == FDCAN_TRANSMIT_PTB) + { + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TPE); + } + else if(type == FDCAN_TRANSMIT_STB_ALL) + { + if(READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TSONE)) + { + hfdcan->ErrorCode = HAL_FDCAN_ERROR_PENDING; + return HAL_BUSY; + } + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSALL); + } + else + { + if(READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TSALL)) + { + hfdcan->ErrorCode = HAL_FDCAN_ERROR_PENDING; + return HAL_BUSY; + } + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSONE); + } + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, TransmitAbortType_enum type) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_ABORT_TYPE(type)); + + if(type == FDCAN_ABORT_PTB) + { + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TPA); + while(READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TPA)); + } + else + { + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TSA); + while(READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TSA)); + } + + return HAL_OK; +} + +//true: completed; false: not completed +bool HAL_FDCAN_GetTxReqCompleted(FDCAN_HandleTypeDef *hfdcan, TransmitType_enum type) +{ + bool tx_status = false; + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + if(type == FDCAN_TRANSMIT_PTB) + { + if(!READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TPE)) + tx_status = true; + } + else if(type == FDCAN_TRANSMIT_STB_ALL) + { + if(!READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TSALL)) + tx_status = true; + } + else if(type == FDCAN_TRANSMIT_STB_ONE) + { + if(!READ_BIT(hfdcan->Instance->CR, FDCAN_CR_TSONE)) + tx_status = true; + } + + return tx_status; +} + +uint32_t HAL_FDCAN_GetBusStatus(FDCAN_HandleTypeDef *hfdcan) +{ + return (hfdcan->Instance->CR & 0x7); +} + + +HAL_StatusTypeDef HAL_FDCAN_WaitTxCompleted(FDCAN_HandleTypeDef *hfdcan, TransmitType_enum type, uint32_t timeout) +{ + uint32_t tickstart = 0; + + TransmitAbortType_enum abort_cmd; + + abort_cmd = (type == FDCAN_TRANSMIT_PTB)? FDCAN_ABORT_PTB : FDCAN_ABORT_STB; + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!HAL_FDCAN_GetTxReqCompleted(hfdcan, type)) + { + if((HAL_GetTick() - tickstart) > timeout) + { + /* Update error code */ + //hfdcan->ErrorCode |= ERR_FDCAN_TIMEOUT; + + HAL_FDCAN_AbortTxRequest(hfdcan, abort_cmd); + + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/* make sure the pRxData buffer size is aligned of uint32_t */ +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) +{ + + uint8_t idx = 0; + uint8_t i; + uint8_t data_len; + + uint32_t* ptmp;// = (uint32_t*)pRxData; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + assert_param(pRxHeader); + assert_param(pRxData); + + if((hfdcan->Instance->CR & FDCAN_CR_RSTAT) == 0) + { + hfdcan->ErrorCode |= ERR_FDCAN_RXBUF_EMPTY; + return HAL_ERROR; + } + + ptmp = (uint32_t*)pRxHeader; + + *ptmp = hfdcan->Instance->RBUF[idx++]; + ptmp++; + *ptmp = hfdcan->Instance->RBUF[idx++]; + ptmp++; + + data_len = __HAL_FDCAN_DLC2LEN(pRxHeader->FrameInfo.b.DLC); + + for(i = 0; i < (data_len + 3) / 4; i++) + { + *(uint32_t*)pRxData = hfdcan->Instance->RBUF[idx++]; + pRxData += 4; + } + + + *ptmp = hfdcan->Instance->RBUF[18]; + ptmp++; + *ptmp = hfdcan->Instance->RBUF[19]; + + /* RELease buffer slot */ + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_RREL); + + return HAL_OK; +} + +FDCAN_RXBUF_FILL_STATE_enum HAL_FDCAN_GetRxBufFillState(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t FillLevel; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + FillLevel = (hfdcan->Instance->CR & FDCAN_CR_RSTAT) >> FDCAN_CR_RSTAT_Pos; + + if((FillLevel == FDCAN_RXBUF_FULL) && READ_BIT(hfdcan->Instance->CR, FDCAN_CR_ROV)) + FillLevel = FDCAN_RXBUF_OV; + + return (FDCAN_RXBUF_FILL_STATE_enum)FillLevel; +} + + +FDCAN_TXBUF_FILL_STATE_enum HAL_FDCAN_GetTxBufFillState(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t FreeLevel; + + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + FreeLevel = (hfdcan->Instance->CR & FDCAN_CR_TSSTAT) >> FDCAN_CR_TSSTAT_Pos; + + /* Return Tx BUF free level */ + return (FDCAN_TXBUF_FILL_STATE_enum)FreeLevel; +} + + +HAL_StatusTypeDef HAL_FDCAN_ConfigRxBufWarnningLimit(FDCAN_HandleTypeDef *hfdcan, uint8_t afwl) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_AFWL(afwl)); + + MODIFY_REG(hfdcan->Instance->LIMIT, FDCAN_LIMIT_AFWL_Msk, afwl << FDCAN_LIMIT_AFWL_Pos); + + return HAL_OK; +} + + +uint8_t HAL_FDCAN_GetRxBufWarnningLimit(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + return ((hfdcan->Instance->LIMIT & FDCAN_LIMIT_AFWL_Msk) >> FDCAN_LIMIT_AFWL_Pos); +} + + +HAL_StatusTypeDef HAL_FDCAN_ConfigErrCntWarnningLimit(FDCAN_HandleTypeDef *hfdcan, uint8_t ecnt) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + MODIFY_REG(hfdcan->Instance->LIMIT, FDCAN_LIMIT_EWL_Msk, ecnt << FDCAN_LIMIT_EWL_Pos); + + return HAL_OK; +} + +uint8_t HAL_FDCAN_GetErrCntWarnningLimit(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + return ((hfdcan->Instance->LIMIT & FDCAN_LIMIT_EWL_Msk) >> FDCAN_LIMIT_EWL_Pos); + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_ConfigRxBufOverwriteMode(FDCAN_HandleTypeDef *hfdcan, uint32_t OverwriteMode) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + assert_param(IS_FDCAN_RX_BUF_MODE(OverwriteMode)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if(hfdcan->Init.RxBufOverFlowMode == FDCAN_RX_BUF_BLOCKING) + { + /* 1 - The new message will not be stored */ + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_ROM); + } + else + { + /* 0 - The oldest message will be overwritten */ + CLEAR_BIT(hfdcan->Instance->CR, FDCAN_CR_ROM); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +HAL_StatusTypeDef HAL_FDCAN_TransceiverEnterSTBY(FDCAN_HandleTypeDef *hfdcan) +{ + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_STBY); + return HAL_OK; +} + + +__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspInit could be implemented in the user file + */ +} + +HAL_StatusTypeDef HAL_FDCAN_GetErrorInfo(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorInfo_u *errinfo) +{ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + if(!errinfo) + return HAL_ERROR; + + errinfo->w = hfdcan->Instance->ECC.w; + + return HAL_OK; +} + + +__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_RxBufferAFCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_RxBufferFullCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_RxBufferOVCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_TXPTBCompletedCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_TXSTBCompletedCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_TxAbortCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + + +__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_BusErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_ErrorPassiveCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +__weak void HAL_FDCAN_ArbitrationLostCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} +/* ====================================================================================== */ + +__weak void HAL_FDCAN_TT_TimerTriggerCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +HAL_StatusTypeDef HAL_FDCAN_TT_Config(FDCAN_HandleTypeDef *hfdcan, uint32_t TT_Presc) +{ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TPRESC(TT_Presc)); + + CLEAR_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_TTEN); + + MODIFY_REG(hfdcan->Instance->TTCFG, FDCAN_TTCFG_T_PRESC, TT_Presc << FDCAN_TTCFG_T_PRESC_Pos); + + /* clear 'trigger error' interrupt flag */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_TEIF); + + /* clear 'time trigger' interrupt flag */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_TTIF); + + /* clear 'watch trigger' interrupt flag */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TTCFG_WTIF); + + /* Time Trigger Interrupt Enable */ + SET_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_TTIE); + + /* Watch Trigger Interrupt Flag */ + CLEAR_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_WTIE); + + SET_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_TTEN); + + SET_BIT(hfdcan->Instance->CR, FDCAN_CR_TTTBM); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure TTCAN reference message +* +*@param : hfdcan: FDCAN_HandleTypeDef handler +*@param : IdType: can be FDCAN_STANDARD_ID or FDCAN_EXTENDED_ID +*@param : Identifier : frame ID +*@param : Payload: not used +* +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_ID_TYPE(IdType)); + + if (IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU)); + } + else /* IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU)); + } + + hfdcan->Instance->TTREFMSG.b.REF_ID = Identifier; + + hfdcan->Instance->TTREFMSG.b.REF_IDE = (IdType == FDCAN_EXTENDED_ID) ? 1 : 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig) +{ + hfdcan->Instance->TTTRIGCFG.w = sTriggerConfig->TriggerType << 8 | sTriggerConfig->TTPtr | sTriggerConfig->TxEnWindow << 12; + + hfdcan->Instance->TTTRIG = sTriggerConfig->TimeMark & 0xFFFF; + + if(hfdcan->Instance->TTTRIG != sTriggerConfig->TimeMark) + return HAL_ERROR; + + return HAL_OK; +} + +void HAL_FDCAN_TT_ImmediateTrigger(FDCAN_HandleTypeDef *hfdcan, uint8_t TTPtr) +{ + /* Select TBUF slot for the trigger */ + hfdcan->Instance->TTTRIGCFG.b.TTPTR = TTPtr; + + /* configure the trigger type and transmit enable window */ + hfdcan->Instance->TTTRIGCFG.b.TTYPE = FDCAN_TT_TX_IMMEDIATE_TRIGGER; + + hfdcan->Instance->TTTRIG = 1; + + return; +} + + +HAL_StatusTypeDef HAL_FDCAN_TT_AddMessageByTBPtr(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint8_t TBPtr) +{ + uint8_t i; + uint8_t data_len; + uint32_t* ptmp; + + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_DLC(pTxHeader->FrameInfo.b.DLC)); + + MODIFY_REG(hfdcan->Instance->TTCFG, FDCAN_TTCFG_TBPTR_Msk, TBPtr << FDCAN_TTCFG_TBPTR_Pos); + + ptmp = (uint32_t*)pTxHeader; + + hfdcan->Instance->TBUF[0] = *ptmp++; + hfdcan->Instance->TBUF[1] = *ptmp; + + data_len = __HAL_FDCAN_DLC2LEN(pTxHeader->FrameInfo.b.DLC); + + for(i = 0; i < (data_len + 3) / 4; i++) + { + hfdcan->Instance->TBUF[2 + i] = *(uint32_t*)pTxData; + pTxData += 4; + } + + SET_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_TBF); + while(!READ_BIT(hfdcan->Instance->IR, FDCAN_IR_TSFF)); + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_TT_EnableWatchTrigger(FDCAN_HandleTypeDef *hfdcan, uint32_t cycle_time) +{ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + hfdcan->Instance->TTWTRIGR.w = (cycle_time & 0xFFFF); + SET_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_WTIE); + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_TT_DisableWatchTrigger(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + CLEAR_BIT(hfdcan->Instance->TTCFG, FDCAN_TTCFG_WTIE); + return HAL_OK; +} + + + +HAL_StatusTypeDef HAL_FDCAN_EnableTimestamp(FDCAN_HandleTypeDef *hfdcan, uint32_t ts_position) +{ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TIMESTAMP_POSITION(ts_position)); + + hfdcan->Instance->TIMECFG = FDCAN_TIMCFG_TIMEEN | (ts_position << FDCAN_TIMCFG_TIMEPOS_Pos); + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_FDCAN_DisableTimestamp(FDCAN_HandleTypeDef *hfdcan) +{ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + CLEAR_BIT(hfdcan->Instance->TIMECFG, FDCAN_TIMCFG_TIMEEN); + return HAL_OK; +} + +void HAL_FDCAN_GetTTS(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTSTypeDef *tts) +{ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + tts->tts_h = hfdcan->Instance->TTSH; + tts->tts_l = hfdcan->Instance->TTSL; +} + +#endif /* HAL_FDCAN_MODULE_ENABLED */ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_fmc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_fmc.c new file mode 100644 index 0000000000000000000000000000000000000000..53c7f194e3212482a530aa53f71921446b4e3ab0 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_fmc.c @@ -0,0 +1,623 @@ +/****************************************************************************** +* @file : HAL_FMC.c +* @version : 1.0 +* @date : 2022.10.25 +* @brief : FMC HAL module driver +* +* @history : +* 2022.10.25 lwq create +* +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_FMC_MODULE_ENABLED + +/****************************************************************************** +* @brief : Initialize the FMC NORSRAM MSP. +* @param : none. +* @return: none +******************************************************************************/ +__weak void HAL_FMC_NORSRAM_MspInit(void) +{ + + /* Prevent unused argument(s) compilation warning */ + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FMC_NORSRAM_MspInit could be implemented in the user file + */ +} + + +/****************************************************************************** +* @brief : Initialize the FMC NORSRAM peripheral. +* @param : hfmc: Pointer to a FMC_NORSRAMInitTypeDef structure that contains +* the configuration information for the specified FMC module. +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NORSRAM_Init(FMC_NORSRAMInitTypeDef *hfmc) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_BANK(hfmc->NSBank)); + assert_param(IS_FMC_MUX(hfmc->DataAddressMux)); + assert_param(IS_FMC_MEMORY(hfmc->MemoryType)); + assert_param(IS_FMC_MEMORY_WIDTH(hfmc->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(hfmc->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(hfmc->WaitSignalPolarity)); + assert_param(IS_FMC_WRAP_MODE(hfmc->WrapMode)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(hfmc->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(hfmc->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(hfmc->WaitSignal)); + assert_param(IS_FMC_ASYNWAIT(hfmc->AsynchronousWait)); + assert_param(IS_FMC_CRAMPPAGE_SIZE(hfmc->CRAMPageSize)); + assert_param(IS_FMC_WRITE_MODE(hfmc->WriteMode)); + + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /* Initialize the low level hardware (MSP) */ + HAL_FMC_NORSRAM_MspInit(); + + /*---------------------------- FMC SNCTL Configuration -----------------*/ + /* Clear NRBKEN, NRMUX, NRTP, NRW, NREN, SBRSTEN, NRWTPOL, WRAPEN, NRWTCFG, WREN, + NWAITEN, EXTMODEN, ASYNCWAIT, CPS and SYNCWR bits */ + FMC_NORSRAM->SNCTLCFG[hfmc->NSBank] &= ((uint32_t)~( FMC_SNCTLX_NRBKEN_Msk | FMC_SNCTLX_NRMUX_Msk | FMC_SNCTLX_NRTP_Msk | \ + FMC_SNCTLX_NRW_Msk | FMC_SNCTLX_NREN_Msk | FMC_SNCTLX_SBRSTEN_Msk | \ + FMC_SNCTLX_NRWTPOL_Msk | FMC_SNCTLX_WRAPEN_Msk | FMC_SNCTLX_NRWTCFG_Msk | \ + FMC_SNCTLX_WREN_Msk | FMC_SNCTLX_NRWTEN_Msk | FMC_SNCTLX_EXMODEN_Msk | \ + FMC_SNCTLX_ASYNCWAIT_Msk | FMC_SNCTLX_CPS_Msk | FMC_SNCTLX_SYNCWR_Msk)); + + /* Bank1 NOR/SRAM control register configuration */ + FMC_NORSRAM->SNCTLCFG[hfmc->NSBank] |= (uint32_t)(hfmc->DataAddressMux | \ + hfmc->MemoryType | \ + hfmc->MemoryDataWidth | \ + hfmc->BurstAccessMode | \ + hfmc->WaitSignalPolarity | \ + hfmc->WrapMode | \ + hfmc->WaitSignalActive | \ + hfmc->WriteOperation | \ + hfmc->WaitSignal | \ + hfmc->ExtendedMode | \ + hfmc->AsynchronousWait | \ + hfmc->CRAMPageSize | \ + hfmc->WriteMode); + + + + if(hfmc->MemoryType == FMC_MEMORY_TYPE_NOR) + { + FMC_NORSRAM->SNCTLCFG[hfmc->NSBank] |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + + FMC_NORSRAM->SNCTLCFG[hfmc->NSBank] |= FMC_SNCTLX_NRBKEN; + + return HAL_OK; +} + + +/****************************************************************************** +* @brief : DeInitialize the FMC_NORSRAM peripheral +* @param : hfmc: Pointer to a FMC_NORSRAMInitTypeDef structure that contains +* the configuration information for the specified FMC module. +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NORSRAM_DeInit(FMC_NORSRAMInitTypeDef *hfmc) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_BANK(hfmc->NSBank)); + + /* De-initialize the FMC_NORSRAM device */ + FMC_NORSRAM->SNCTLCFG[hfmc->NSBank] = 0x000030DAU; + + FMC_NORSRAM->SNCTLCFG[hfmc->NSBank+1] = 0x0FFFFFFFU; + + FMC_NORSRAM->SNWTCFG[hfmc->NSBank] = 0x0FFFFFFFU; + + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Initialize the FMC_NORSRAM Timing according to the specified +* parameters in the FMC_NORSRAM_TimingTypeDef +* @param : Timing Pointer to NORSRAM Timing structure +* @param : Bank NORSRAM bank number +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NORSRAM_Timing_Init(FMC_NORSRAMTimingInitTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /*---------------------------- FMC SNTCFG Configuration -----------------*/ + /* Clear ASET, AHLD, DSET, BUSLAT, CKDIV, DLAT and ASYNCMO bits */ + FMC_NORSRAM->SNCTLCFG[Bank+1] &= ((uint32_t)~(FMC_SNTCFGX_ASET_Msk | FMC_SNTCFGX_AHLD_Msk | FMC_SNTCFGX_DSET_Msk | \ + FMC_SNTCFGX_BUSLAT_Msk | FMC_SNTCFGX_CKDIV_Msk | FMC_SNTCFGX_DLAT_Msk | \ + FMC_SNTCFGX_ASYNCMOD_Msk)); + + /* Bank1 NOR/SRAM timing register configuration */ + FMC_NORSRAM->SNCTLCFG[Bank+1] |= (uint32_t)Timing->AddressSetupTime | \ + (Timing->AddressHoldTime << FMC_SNTCFGX_AHLD_Pos) | \ + (Timing->DataSetupTime << FMC_SNTCFGX_DSET_Pos) | \ + (Timing->BusTurnAroundDuration << FMC_SNTCFGX_BUSLAT_Pos) | \ + (Timing->CLKDivision << FMC_SNTCFGX_CKDIV_Pos) | \ + (Timing->DataLatency << FMC_SNTCFGX_DLAT_Pos) | \ + Timing->AccessMode; + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Initialize the FMC_NORSRAM Extended mode Timing according to the specified +* parameters in the FMC_NORSRAM_TimingTypeDef +* @param : Timing Pointer to NORSRAM Timing structure +* @param : Bank NORSRAM bank number +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAMTimingInitTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + /*---------------------------- FMC SNWTCFG Configuration -----------------*/ + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + + /* Clear WASET, WAHLD, WDSET, WBUSLAT, DLAT, and WASYNCMOD bits */ + FMC_NORSRAM->SNWTCFG[Bank] &= ((uint32_t)~(FMC_SNWTCFGX_WASET_Msk | FMC_SNWTCFGX_WAHLD_Msk | FMC_SNWTCFGX_WDSET_Msk | \ + FMC_SNWTCFGX_WBUSLAT_Msk | FMC_SNWTCFGX_DLAT_Msk | FMC_SNWTCFGX_WASYNCMOD_Msk)); + + FMC_NORSRAM->SNWTCFG[Bank] |= (uint32_t)Timing->AddressSetupTime | + (Timing->AddressHoldTime << FMC_SNWTCFGX_WAHLD_Pos )| + (Timing->DataSetupTime << FMC_SNWTCFGX_WDSET_Pos) | + (Timing->BusTurnAroundDuration << FMC_SNWTCFGX_WBUSLAT_Pos) | + (Timing->DataLatency << FMC_SNWTCFGX_DLAT_Pos) | + Timing->AccessMode; + + } + else + { + FMC_NORSRAM->SNWTCFG[Bank] = 0x0FFFFFFF; + } + return HAL_OK; +} + +/****************************************************************************** +* @brief : Initialize the FMC SDRAM MSP. +* @param : none. +* @return: none +******************************************************************************/ +__weak void HAL_FMC_SDRAM_MspInit(void) +{ + + /* Prevent unused argument(s) compilation warning */ + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_FMC_SDRAM_MspInit could be implemented in the user file + */ +} + +/****************************************************************************** +* @brief : Initializes the FMC_SDRAM device according to the specified +* control parameters in the FMC_SDRAMInitTypeDef +* @param : Init: Pointer to SDRAM Initialization structure +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_SDRAM_Init(FMC_SDRAMInitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /* Initialize the low level hardware (MSP) */ + HAL_FMC_SDRAM_MspInit(); + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank != FMC_SDRAM_BANK2) + { + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + FMC_SDRAM->SDRCR[FMC_SDRAM_BANK1] &= ((uint32_t)~(FMC_SDRCR_NCA_Msk | FMC_SDRCR_NRA_Msk | FMC_SDRCR_MWID_Msk | \ + FMC_SDRCR_NB_Msk | FMC_SDRCR_CAS_Msk | FMC_SDRCR_WP_Msk | \ + FMC_SDRCR_CLKDIV_Msk | FMC_SDRCR_RBURST_Msk | FMC_SDRCR_RPIPE_Msk)); + + FMC_SDRAM->SDRCR[FMC_SDRAM_BANK1] |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection |\ + Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay + ); + } + else /* FMC_Bank2_SDRAM */ + { + /* Clear SDCLK, RBURST, and RPIPE bits */ + FMC_SDRAM->SDRCR[FMC_SDRAM_BANK1] &= ((uint32_t)~(FMC_SDRCR_CLKDIV_Msk | FMC_SDRCR_RBURST_Msk | FMC_SDRCR_RPIPE_Msk)); + + FMC_SDRAM->SDRCR[FMC_SDRAM_BANK1] |= (uint32_t)(Init->SDClockPeriod |\ + Init->ReadBurst |\ + Init->ReadPipeDelay); + + /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ + FMC_SDRAM->SDRCR[FMC_SDRAM_BANK2] &= ((uint32_t)~(FMC_SDRCR_NCA_Msk | FMC_SDRCR_NRA_Msk | FMC_SDRCR_MWID_Msk | \ + FMC_SDRCR_NB_Msk | FMC_SDRCR_CAS_Msk | FMC_SDRCR_WP_Msk | \ + FMC_SDRCR_CLKDIV_Msk | FMC_SDRCR_RBURST_Msk | FMC_SDRCR_RPIPE_Msk)); + + FMC_SDRAM->SDRCR[FMC_SDRAM_BANK2] |= (uint32_t)(Init->ColumnBitsNumber |\ + Init->RowBitsNumber |\ + Init->MemoryDataWidth |\ + Init->InternalBankNumber |\ + Init->CASLatency |\ + Init->WriteProtection); + } + + return HAL_OK; +} + + + +/****************************************************************************** +* @brief : Initializes the FMC_SDRAM device timing according to the specified +* parameters in the FMC_SDRAMTimingInitTypeDef +* @param : Timing: Pointer to SDRAM Timing structure +* @param : Bank: SDRAM bank number +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_SDRAM_Timing_Init(FMC_SDRAMTimingInitTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank != FMC_SDRAM_BANK2) + { + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + FMC_SDRAM->SDRTR[FMC_SDRAM_BANK1] &= ((uint32_t)~(FMC_SDRTR_TMRD_Msk | FMC_SDRTR_TXSR_Msk | FMC_SDRTR_TRAS_Msk | \ + FMC_SDRTR_TRC_Msk | FMC_SDRTR_TWR_Msk | FMC_SDRTR_TRP_Msk | \ + FMC_SDRTR_TRCD_Msk)); + + FMC_SDRAM->SDRTR[FMC_SDRAM_BANK1] |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RPDelay)-1) << 20) |\ + (((Timing->RCDDelay)-1) << 24)); + } + else /* FMC_Bank2_SDRAM */ + { + /* Clear TRC and TRP bits */ + FMC_SDRAM->SDRTR[FMC_SDRAM_BANK1] &= ((uint32_t)~(FMC_SDRTR_TRC_Msk | FMC_SDRTR_TRP_Msk)); + + FMC_SDRAM->SDRTR[FMC_SDRAM_BANK1] |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ + (((Timing->RPDelay)-1) << 20)); + + /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ + FMC_SDRAM->SDRTR[FMC_SDRAM_BANK2] &= ((uint32_t)~(FMC_SDRTR_TMRD_Msk | FMC_SDRTR_TXSR_Msk | FMC_SDRTR_TRAS_Msk | \ + FMC_SDRTR_TRC_Msk | FMC_SDRTR_TWR_Msk | FMC_SDRTR_TRP_Msk | \ + FMC_SDRTR_TRCD_Msk)); + + FMC_SDRAM->SDRTR[FMC_SDRAM_BANK2] |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ + (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ + (((Timing->SelfRefreshTime)-1) << 8) |\ + (((Timing->WriteRecoveryTime)-1) <<16) |\ + (((Timing->RCDDelay)-1) << 24)); + } + + return HAL_OK; +} + +/****************************************************************************** +* @brief : DeInitializes the FMC_SDRAM peripheral +* @param : Bank: SDRAM bank number +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_SDRAM_DeInit(uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + FMC_SDRAM->SDRCR[Bank] = 0x000002D0; + FMC_SDRAM->SDRTR[Bank] = 0x0FFFFFFF; + FMC_SDRAM->SDRCMD = 0x00000000; + FMC_SDRAM->SDRART = 0x00000000; + FMC_SDRAM->SDRSR = 0x00000000; + + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Send Command to the FMC SDRAM bank +* @param : Command: Pointer to SDRAM command structure +* @param : Timing: Pointer to SDRAM Timing structure +* @param : Timeout: Timeout wait value +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_SDRAM_SendCommand(FMC_SDRAMCommandTypeDef *Command, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + + /* Check the parameters */ + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Clear CMD, CTD2, CTD1, NARF, MRD bits */ + FMC_SDRAM->SDRCMD &= ((uint32_t)~(FMC_SDRCMD_CMD_Msk | FMC_SDRCMD_CTD2_Msk | FMC_SDRCMD_CTD1_Msk | \ + FMC_SDRCMD_NARF_Msk | FMC_SDRCMD_MRD_Msk)); + /* Set command register */ + FMC_SDRAM->SDRCMD = (uint32_t)(Command->CommandMode |\ + (Command->CommandTarget) |\ + (((Command->AutoRefreshNumber)-1) << FMC_SDRCMD_NARF_Pos) |\ + ((Command->ModeRegisterDefinition) << FMC_SDRCMD_MRD_Pos) + ); + + uiTimeout = Timeout; + + /* wait until command is send */ + while(HAL_IS_BIT_SET(FMC_SDRAM->SDRSR, FMC_SDRSR_BUSY)) + { + /* Check for the Timeout */ + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Program the SDRAM Memory Refresh rate. +* @param : RefreshRate: The SDRAM refresh rate value. +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_SDRAM_ProgramRefreshRate(uint32_t RefreshRate) +{ + /* Check the parameters */ + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Clear COUNT bits */ + FMC_SDRAM->SDRART &= (uint32_t)~(FMC_SDRART_COUNT_Msk); + /* Set the refresh rate in command register */ + FMC_SDRAM->SDRART |= (RefreshRate << FMC_SDRART_COUNT_Pos); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Set the Number of consecutive SDRAM Memory auto Refresh commands. +* @param : AutoRefreshNumber: Specifies the auto Refresh number. +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_SDRAM_SetAutoRefreshNumber(uint32_t AutoRefreshNumber) +{ + /* Check the parameters */ + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Clear NARF bits */ + FMC_SDRAM->SDRCMD &= (uint32_t)~(FMC_SDRCMD_NARF_Msk); + /* Set the Auto-refresh number in command register */ + FMC_SDRAM->SDRCMD |= (AutoRefreshNumber << FMC_SDRCMD_NARF_Pos); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Returns the indicated FMC SDRAM bank mode status. +* @param : Bank: Defines the FMC SDRAM bank. This parameter can be +* FMC_SDRAM_BANK1 or FMC_SDRAM_BANK2. +* @return: The FMC SDRAM bank mode status, could be on of the following values: +* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or +* FMC_SDRAM_POWER_DOWN_MODE. +******************************************************************************/ +uint32_t HAL_FMC_SDRAM_GetBankModeStatus(uint32_t Bank) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if(Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)((FMC_SDRAM->SDRSR & FMC_SDRSR_STA1_Msk) >> FMC_SDRSR_STA1_Pos); + } + else + { + tmpreg = ((uint32_t)(FMC_SDRAM->SDRSR & FMC_SDRSR_STA2_Msk) >> FMC_SDRSR_STA2_Pos); + } + + /* Return the mode status */ + return tmpreg; +} + +/****************************************************************************** +* @brief : Returns the indicated FMC SDRAM status. +* @param : None. +* @return: The FMC SDRAM status. +******************************************************************************/ +uint32_t HAL_FMC_SDRAM_GetStatus(void) +{ + /* Return the mode status */ + return (FMC_SDRAM->SDRSR); +} + +/****************************************************************************** +* @brief : Set Burst read FIFO length. +* @param : FifoLen: fifo length. +* @param : Bank: Defines the FMC SDRAM bank. This parameter can be +* FMC_SDRAM_BANK1 or FMC_SDRAM_BANK2. +* @return: None. +******************************************************************************/ +void HAL_FMC_SDRAM_BurstReadFifoLength(uint32_t FifoLen, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_BURST_READ_FIFO_LEN(FifoLen)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + if(FifoLen == FMC_SDRAM_BURST_READ_FIFO_LEN_0) + { + FMC_SDRAM->SDRCR[Bank] &= ~(FMC_SDRCR_RBURST); + } + else + { + FMC_SDRAM->SDRCR[Bank] |= (FMC_SDRCR_RBURST); + FMC_SDRAM->SDRCR[Bank] &= ~(FMC_SDRCR_BDEPTH_Msk); + FMC_SDRAM->SDRCR[Bank] |= FifoLen; + } +} + +/****************************************************************************** +* @brief : Set write to read continuous operation with SDCLK delay. +* @param : W2RDelay: Number of delayed SDCLK.This parameter can be +* FMC_SDRAM_W2R_DELAY_0 or FMC_SDRAM_W2R_DELAY_HALF_SDCLK. +* @param : Bank: Defines the FMC SDRAM bank. This parameter can be +* FMC_SDRAM_BANK1 or FMC_SDRAM_BANK2. +* @return: None. +******************************************************************************/ +void HAL_FMC_SDRAM_W2RDelay(uint32_t W2RDelay, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_W2R_DELAY(W2RDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + FMC_SDRAM->SDRCR[Bank] &= ~(FMC_SDRCR_W2RDLY_Msk); + FMC_SDRAM->SDRCR[Bank] |= W2RDelay; +} + +/****************************************************************************** +* @brief : Enable or disable the SDRAM device refresh error interrupt. +* @param : NewState: new state of the specified SDRAM interrupts. +* This parameter can be: ENABLE or DISABLE. +* @return: None. +******************************************************************************/ +void HAL_FMC_SDRAM_ITConfig(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the refresh error interrupt */ + FMC_SDRAM->SDRART |= FMC_SDRART_RFEIE ; + } + else + { + /* Disable the refresh error interrupt */ + FMC_SDRAM->SDRART &= (~FMC_SDRART_RFEIE); + } +} + +/****************************************************************************** +* @brief: Checks whether the specified SDRAM interrupt has occurred or not. +* @param: None. +* @return: SET or RESET. +******************************************************************************/ +FlagStatus HAL_FMC_SDRAM_GetITStatus(void) +{ + FlagStatus bitstatus = RESET; + + /* Return the status of the flag */ + if (((FMC_SDRAM->SDRART & FMC_SDRART_RFEIE) != (uint32_t)RESET) && ((FMC_SDRAM->SDRSR & FMC_SDRSR_RFE) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/****************************************************************************** +* @brief: Clears the SDRAM's interrupt pending bits. +* @param: None. +* @return: None +******************************************************************************/ +void HAL_FMC_SDRAM_ClearITPendingBit(void) +{ + if((FMC_SDRAM->SDRART & FMC_SDRART_RFEIE) != (uint32_t)RESET) + { + /* Clear the interrupt pending bits in the SDRART register */ + FMC_SDRAM->SDRART |= FMC_SDRART_CRFE; + } +} + + +/****************************************************************************** +* @brief: SDRAM Refresh error callback. +* @param: None. +* @return: None +******************************************************************************/ +__weak void HAL_SDRAM_RefreshErrorCallback(void) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(NULL); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file + */ +} + +/****************************************************************************** +* @brief: This function handles SDRAM refresh error interrupt request. +* @param: None. +* @return: None +******************************************************************************/ +__weak void HAL_SDRAM_IRQHandler(void) +{ + /* Check SDRAM interrupt Rising edge flag */ + if (SET == HAL_FMC_SDRAM_GetITStatus()) + { + /* SDRAM refresh error interrupt callback */ + HAL_SDRAM_RefreshErrorCallback(); + /* Clear SDRAM refresh error interrupt pending bit */ + HAL_FMC_SDRAM_ClearITPendingBit(); + } +} + + +#endif + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_gpio.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..1b26bee9aa943853a335dac9c8cb19486eefbd1a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_gpio.c @@ -0,0 +1,328 @@ +/****************************************************************************** +*@file : hal_gpio.c +*@brief : GPIO HAL module driver. +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_GPIO_MODULE_ENABLED + +/****************************************************************************** +*@brief : Initializes the GPIOx peripheral according to the specified parameters +* in the GPIO_Init. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +*@param : GPIO_Init: pointer to an GPIO_InitTypeDef structure that contains +* the configuration information for the specified GPIO peripheral. +*@return: None +******************************************************************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position; + uint32_t currentPin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_ALL_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIOx, GPIO_Init->Mode)); + + /* Configure Select pins */ + position = 0; + while ((GPIO_Init->Pin) >> position != 0) + { + /* Get current pin position */ + currentPin = (GPIO_Init->Pin) & (1UL << position); + + if (currentPin) + { + if (currentPin & (GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)) + { + if (GPIOx == GPIOC) + { + __HAL_RCC_PMU_CLK_ENABLE(); + if (currentPin & GPIO_PIN_13) + PMU->IOSEL &= ~PMU_IOSEL_PC13VALUE; + else if (currentPin & GPIO_PIN_14) + PMU->IOSEL &= ~PMU_IOSEL_PC14VALUE; + else if (currentPin & GPIO_PIN_15) + PMU->IOSEL &= ~PMU_IOSEL_PC15VALUE; + } + } + + /*--------------------- GPIO Mode Configuration ------------------------*/ + if ((GPIO_Init->Mode == GPIO_MODE_ANALOG_SWITCH_OFF) || (GPIO_Init->Mode == GPIO_MODE_ANALOG_SWITCH_ON)) + { + if (position < 8U) + { + GPIOx->AF0 &= ~(0xFUL << (position << 2)); + GPIOx->DS0 &= ~(0xFUL << (position << 2)); + } + else + { + GPIOx->AF1 &= ~(0xFUL << ((position - 8) << 2)); + GPIOx->DS1 &= ~(0xFUL << ((position - 8) << 2)); + } + GPIOx->OTYP &= ~(1UL << position); + GPIOx->PUPD &= ~(0x3UL << (position << 1)); + GPIOx->SMIT &= ~(0x01UL << position); + + if (GPIO_Init->Mode == GPIO_MODE_ANALOG_SWITCH_OFF) + GPIOx->AIEN &= ~(0x01UL << position); + else + GPIOx->AIEN |= 0x01UL << position; + } + else + { + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + GPIOx->AIEN &= ~(0x01UL << position); + + /* Alternate Function */ + if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_FUNCTION(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + if (position < 8U) + { + GPIOx->AF0 = (GPIOx->AF0 & ~(0xFUL << (position << 2))) | (GPIO_Init->Alternate << (position << 2)); + } + else + { + GPIOx->AF1 = (GPIOx->AF1 & ~(0xFUL << ((position - 8) << 2))) | (GPIO_Init->Alternate << ((position - 8) << 2)); + } + } + /* In case of Output or Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the drive parameter */ + assert_param(IS_GPIO_DRIVE(GPIO_Init->Drive)); + + /* Configure the IO drive capability */ + if (position < 8) + { + GPIOx->DS0 = (GPIOx->DS0 & ~(0xFUL << (position << 2))) | (GPIO_Init->Drive << (position << 2)); + } + else + { + GPIOx->DS1 = (GPIOx->DS1 & ~(0xFUL << ((position - 8) << 2))) | (GPIO_Init->Drive << ((position - 8) << 2)); + } + + /* Configure the IO Output Type */ + GPIOx->OTYP = (GPIOx->OTYP & ~(1UL << position)) | (((GPIO_Init->Mode & GPIO_MODE_GPIO_OUTPUT_TYPE_MASK) >> 4) << position); + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + GPIOx->PUPD = (GPIOx->PUPD & ~(0x3UL << (position << 1))) | ((GPIO_Init->Pull) << (position << 1)); + + /* Configure schmitt input */ + GPIOx->SMIT |= 0x01UL << position; + + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + GPIOx->MD = (GPIOx->MD & ~(0x3UL << (position << 1))) | ((GPIO_Init->Mode & GPIO_MODE_GPIO_MASK) << (position << 1)); + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if (GPIO_Init->Mode & GPIO_MODE_EXTI_MASK) + { + /* Clear EXTI interrupt flag */ + HAL_EXTI_ClearPending(position); + + /* Configure the EXTI for the current IO */ + if (HAL_EXTI_SetConfigLine(GPIOx, position, GPIO_Init->Mode) != HAL_OK) + return; + } + else + { + + /* Check whether the current IO is configured as EXTI */ + if (HAL_EXTI_IsConfigLine(GPIOx, position) != DISABLE) + { + /* Deactivate the EXTI configuration of the current IO */ + HAL_EXTI_ClearConfigLine(position); + + /* Clear EXTI interrupt flag */ + HAL_EXTI_ClearPending(position); + } + } + } + position++; + } +} + +/****************************************************************************** +*@brief : De-initializes the GPIOx peripheral registers to their default reset values. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +*@param : GPIO_Pin: specifies the port bit to be written. +*@return: None +******************************************************************************/ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0; + uint32_t currentPin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_ALL_PIN(GPIO_Pin)); + + /* Configure Select pins */ + while (GPIO_Pin >> position != 0U) + { + /* Get current pin position */ + currentPin = GPIO_Pin & (1UL << position); + + if (currentPin) + { + /* SET GPIO Function */ + if (position < 8U) + { + GPIOx->AF0 &= ~(0xFU << (position << 2U)); + GPIOx->DS0 &= ~(0xFU << (position << 2U)); + } + else + { + GPIOx->AF1 &= ~(0xFU << ((position - 8U) << 2U)); + GPIOx->DS1 &= ~(0xFU << ((position - 8U) << 2U)); + } + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPD &= ~(0x3U << (position << 1U)); + + /* Configure the default value for output type */ + GPIOx->OTYP &= ~currentPin; + + /* Configure the default value for schmitt input */ + GPIOx->SMIT &= ~currentPin; + + GPIOx->AIEN &= ~currentPin; + + /* Configure IO Direction mode to Analog*/ + GPIOx->MD |= ((0x03U) << (position << 1U)); + + /* Check whether the current IO is configured as EXTI */ + if (HAL_EXTI_IsConfigLine(GPIOx, position) != DISABLE) + { + /* Deactivate the EXTI configuration of the current IO */ + HAL_EXTI_ClearConfigLine(position); + + /* Clear EXTI interrupt flag */ + HAL_EXTI_ClearPending(position); + } + } + position++; + } +} + +/****************************************************************************** +*@brief : Set or clear the selected data port bit. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +*@param : GPIO_Pin: specifies the port bit to be written. +*@param : PinState: specifies the value to be written to the selected bit. +* This parameter must be a value of @ref GPIO_PinState. +* @arg GPIO_PIN_RESET: clear the port pin. +* @arg GPIO_PIN_SET: set the port pin. +*@return: None +******************************************************************************/ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_ALL_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (GPIO_PIN_RESET == PinState) + { + GPIOx->BSC = GPIO_Pin << 16U; + } + else + { + GPIOx->BSC = GPIO_Pin; + } +} + +/****************************************************************************** +*@brief : Read the specified input port pin. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +*@param : GPIO_Pin: specifies the port bit to be written. +*@return: The input port pin value. +******************************************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + if (GPIOx->IDATA & GPIO_Pin) + { + return GPIO_PIN_SET; + } + else + { + return GPIO_PIN_RESET; + } +} + +/****************************************************************************** +*@brief : Toggle the specified GPIO pin. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +*@param : GPIO_Pin: specifies the port bit to be written. +*@return: None. +******************************************************************************/ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_ALL_PIN(GPIO_Pin)); + + if (GPIOx->ODATA & GPIO_Pin) + { + GPIOx->BSC = GPIO_Pin << 16; + } + else + { + GPIOx->BSC = GPIO_Pin; + } +} + +/****************************************************************************** +*@brief : Lock GPIO Pins configuration registers. +*@param : GPIOx: where x can be (A..F) to select the GPIO peripheral. +*@param : GPIO_Pin: specifies the port bit to be written. +*@return: HAL Status. +******************************************************************************/ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + __IO uint32_t temp = GPIO_LOCK_LOCK_KEY; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_ALL_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + temp |= GPIO_Pin; + + /* Set LOCKx bit(s): LOCKK='1' + LOCK[15-0] */ + GPIOx->LOCK = temp; + + /* Reset LOCKx bit(s): LOCKK='0' + LOCK[15-0] */ + GPIOx->LOCK = GPIO_Pin; + + /* Set LOCKx bit(s): LOCKK='1' + LOCK[15-0] */ + GPIOx->LOCK = temp; + + /* Read LOCK register. This read is mandatory to complete key lock sequence */ + temp = GPIOx->LOCK; + + /* read again in order to confirm lock is active */ + if (GPIOx->LOCK & GPIO_LOCK_LOCK_KEY) + return HAL_OK; + else + return HAL_ERROR; +} + + +#endif /* HAL_GPIO_MODULE_ENABLED */ + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_hrng_20230712.lib b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_hrng_20230712.lib new file mode 100644 index 0000000000000000000000000000000000000000..e437c8fa1184c47ba8ad20742e2bf20c65c7172d Binary files /dev/null and b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_hrng_20230712.lib differ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_i2c.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..93da5a3f2398400a57dc787cf750747f3aa211e4 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_i2c.c @@ -0,0 +1,1405 @@ +/****************************************************************************** +*@file : hal_i2c.c +*@brief : This file provides firmware functions to manage the I2C HAL module +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ + +#include "hal_i2c.h" + + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private functions for I2C */ +static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed); +static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); + + +/****************************************************************************** +*@brief : I2C interrupt handler +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@return: None +******************************************************************************/ +__weak void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->Init.I2C_Mode == I2C_MODE_SLAVE) + { + /* Slave ADDR1 Interrupt */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1)) + { + /* Clear ADDR1 Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN ); + + /* Slave Transmit */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + hi2c->state = I2C_STATE_TX_DATA; + } + else + { + hi2c->state = I2C_STATE_RX_DATA; + } + } + + if(hi2c->state == I2C_STATE_TX_DATA) + { + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + if(hi2c->Tx_Count == hi2c->Tx_Size) + { + ;//while(1); + } + else + { + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + } + } + } + else if(hi2c->state == I2C_STATE_RX_DATA) + { + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + } + } + + } + else + { + + + + + /* master */ + if(hi2c->state == I2C_STATE_TX_DATA) + { + + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + if(hi2c->Tx_Count > hi2c->Tx_Size) + { + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + } + } + } + else{ + + if((hi2c->state == I2C_STATE_RX_DATA) /*|| (hi2c->state == I2C_STATE_REQ_ADDR)*/) + { + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + + if(hi2c->Rx_Size - hi2c->Rx_Count == 1) + { + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + } + } + +// if(READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) +// { +// //clear MTF +// hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); +// +// if(hi2c->state == I2C_STATE_REQ_ADDR) +// { +// hi2c->state = I2C_STATE_RX_DATA; +// hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); +// +// } +// } + } + else if(hi2c->state == I2C_STATE_REQ_ADDR) + { + if(READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG)) + { + hi2c->state = I2C_STATE_RX_DATA; + hi2c->Instance->SR = I2C_SR_TX_RX_FLAG;//READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + if(hi2c->Rx_Size == 1) + { + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + } + } + } + } + + if(READ_BIT(hi2c->Instance->SR, I2C_SR_NACKF)) + { + //clear MTF + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_NACKF); + +// if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + } + + } + } + + /* STOP Flag Interrupt */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF)) + { + /* Clear STOPF Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF); + + /* Clear STOPF */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN); + + if(hi2c->state == I2C_STATE_RX_DATA) + { + if(hi2c->Init.I2C_Mode == I2C_MODE_MASTER) + { + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_STOP); + } + } + + if (hi2c->I2C_STOPF_Callback != NULL) + { + hi2c->I2C_STOPF_Callback(hi2c); + } + + hi2c->state = I2C_STATE_IDLE; + + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TXE_INT_EN | I2C_CR_MTF_INT_EN | I2C_CR_STOPF_INTEN | I2C_CR_RXNE_INT_EN | I2C_CR_NACKF_INTEN | I2C_CR_TX_RX_FLAG_INTEN); + + } +} + +/****************************************************************************** +*@brief : Init low level of I2C module: GPIO, CLK, NVIC +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@return: None +******************************************************************************/ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* I2C1 */ + if (hi2c->Instance == I2C1) + { + /* Enable Clock */ + __HAL_RCC_I2C1_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /* I2C1 SDA PB7 */ + /* I2C1 SCL PB6 */ + GPIO_Handle.Pin = GPIO_PIN_6 | GPIO_PIN_7; + GPIO_Handle.Mode = GPIO_MODE_AF_PP; + GPIO_Handle.Pull = GPIO_PULLUP; + GPIO_Handle.Drive = GPIO_DRIVE_LEVEL3; + GPIO_Handle.Alternate = GPIO_FUNCTION_5; + HAL_GPIO_Init(GPIOB, &GPIO_Handle); + + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2C1_IRQn); + + /* Enable External Interrupt */ + NVIC_EnableIRQ(I2C1_IRQn); + } + +} + +/****************************************************************************** +*@brief : DeInit low level of I2C module: GPIO, CLK, NVIC +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@return: None +******************************************************************************/ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* + NOTE : This function should be modified by the user. + */ + + /* For Example */ + GPIO_InitTypeDef GPIO_Handle; + + /* I2C1 */ + if (hi2c->Instance == I2C1) + { + /* Disable Clock */ + __HAL_RCC_I2C1_CLK_DISABLE(); + + /* I2C1 SDA PortB Pin7 */ + /* I2C1 SCL PortB Pin6 */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6 | GPIO_PIN_7); + /* Clear Pending Interrupt */ + NVIC_ClearPendingIRQ(I2C1_IRQn); + + /* Disable External Interrupt */ + NVIC_DisableIRQ(I2C1_IRQn); + } + +} + +/****************************************************************************** +*@brief : Initialize the I2c module with parameters +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param (IS_I2C_ALL_MODE(hi2c->Init.I2C_Mode)); + + if(hi2c->Init.I2C_Mode == I2C_MODE_MASTER) + assert_param (IS_I2C_CLOCK_SPEED(hi2c->Init.Clock_Speed)); + else + { + assert_param (IS_I2C_TX_AUTO_EN(hi2c->Init.Tx_Auto_En)); + assert_param (IS_I2C_STRETCH_EN(hi2c->Init.Stretch_Mode)); + } + + /* Disable the selected I2C peripheral */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_MEN); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_I2C_MspInit(hi2c); + + switch (hi2c->Init.I2C_Mode) + { + /* Master Mode */ + case I2C_MODE_MASTER: + { + /* Set Master Mode */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MASTER); + + /* Set Clock Speed */ + I2C_Set_Clock_Speed(hi2c, hi2c->Init.Clock_Speed); + + if (FILTER_ALGO_ENABLE == hi2c->Init.filter_enable) + { + hi2c->Instance->FILTER = 0x303; //config as PCLK + } + /* Set SDA auto change the direction */ + if (hi2c->Init.Tx_Auto_En == TX_AUTO_ENABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + + /* Enable the selected I2C peripheral */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MEN); + }break; + + /* Slave Mode */ + case I2C_MODE_SLAVE: + { + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + if (FILTER_ALGO_ENABLE == hi2c->Init.filter_enable) + { + hi2c->Instance->FILTER = 0x303; //config as PCLK + } + /* Set SDA auto change the direction */ + if (hi2c->Init.Tx_Auto_En == TX_AUTO_ENABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN); + + /* Set Clock Stretch Mode */ + if (hi2c->Init.Stretch_Mode == STRETCH_MODE_DISABLE) + SET_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH); + else + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH); + + /* Set Address 1 */ + hi2c->Instance->SLAVE_ADDR1 = hi2c->Init.Own_Address; + + /* Enable the selected I2C peripheral */ + SET_BIT(hi2c->Instance->CR, I2C_CR_MEN); + }break; + + default: break; + } + + hi2c->state = I2C_STATE_IDLE; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : De-Initialize the I2c module +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->state = I2C_STATE_IDLE; + + HAL_I2C_MspDeInit(hi2c); + + hi2c->Tx_Size = 0; + hi2c->Rx_Size = 0; + hi2c->Tx_Count = 0; + hi2c->Rx_Count = 0; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : send an amount of data in master mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress: I2C slave device address. +*@param : pData: Pointer to a data buffer. +*@param : Size: Total size of data to send. +*@param : Timeout: Timeout value. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress, 0) == HAL_OK) + { + for (i = 0; i < hi2c->Tx_Size; i++) + { + /* Wait TXE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Send Data */ + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in master mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress: I2C slave device address. +*@param : pData: Pointer to a data buffer to store data. +*@param : Size: Total size of data to receive . +*@param : Timeout: Timeout value. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + if (1 == hi2c->Rx_Size) + { + __set_PRIMASK(1); + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + // disable interrupt + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) + { + __set_PRIMASK(0); // enable interrupt + + return HAL_ERROR; + } + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) + { + __set_PRIMASK(0); // enable interrupt + + return HAL_ERROR; + } + + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) + { + __set_PRIMASK(0); // enable interrupt + + return HAL_ERROR; + } + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) + { + __set_PRIMASK(0); // enable interrupt + + return HAL_ERROR; + } + + /* Generate ACK by default*/ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + __set_PRIMASK(0); // enable interrupt + + return HAL_OK; + + } + else + { + __set_PRIMASK(0); + + return HAL_ERROR; + } + } + + + /* Send Read Access Request */ + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + /* Wait Master Transition receiving state */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + for (i = 0; i < hi2c->Rx_Size - 1; i++) + { + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + } + + __set_PRIMASK(1); + + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + __set_PRIMASK(0); + + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : send an amount of data in slave mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a data buffer. +*@param : Size: Total size of data to send . +*@param : Timeout: Timeout value. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i = 0; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + hi2c->Instance->DR = hi2c->Tx_Buffer[i++]; + + hi2c->Tx_Count++; + + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* Match the Address 1 */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Transmit */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) + { + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + } + + if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE)) + { + if (i < hi2c->Tx_Size || hi2c->Tx_Size == 0) + { + hi2c->Instance->DR = hi2c->Tx_Buffer[i++]; + hi2c->Tx_Count++; + } + } + } + hi2c->Instance->SR = READ_REG(hi2c->Instance->SR); + } + else + { + return HAL_ERROR; + } + + + return HAL_OK; +} + +/****************************************************************************** +*@brief : send an amount of data in Master mode using IT mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a buffer to send data. +*@param : Size: Total size of data to send . +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + /* Tx machine is running */ + if (hi2c->state != I2C_STATE_IDLE) + return HAL_ERROR; + + /* Set I2C machine is sending */ + hi2c->state = I2C_STATE_TX_DATA; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_INT_EN /*| I2C_CR_MTF_INT_EN */| I2C_CR_STOPF_INTEN | I2C_CR_NACKF_INTEN ); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress & 0xFE; + + + return HAL_OK; +} + +/****************************************************************************** +*@brief : receivd an amount of data in Master mode using IT mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a buffer to store data. +*@param : Size: Total size of data to receive . +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + uint32_t i; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + hi2c->state = I2C_STATE_REQ_ADDR; + + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + + SET_BIT(hi2c->Instance->CR, I2C_CR_RXNE_INT_EN | I2C_CR_TX_RX_FLAG_INTEN | I2C_CR_STOPF_INTEN | I2C_CR_NACKF_INTEN); + +// SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress | 0x01; + + if(hi2c->Rx_Size == 1) + { + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : send an amount of data in slave mode using IT mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a buffer to send data. +*@param : Size: Total size of data to send . +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + /* Rx machine is running */ + if (hi2c->state != I2C_STATE_IDLE) + return HAL_ERROR; + + /* Set Slave machine is sending */ + hi2c->state = I2C_STATE_TX_DATA; + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + + hi2c->Instance->DR = hi2c->Tx_Buffer[0]; + + hi2c->Tx_Count++; + + /* Clear RX ADDR1 Flag */ + SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN | I2C_CR_TXE_INT_EN | I2C_CR_STOPF_INTEN); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : receivd an amount of data in slave mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a buffer to store data. +*@param : Size: Total size of data to receive . +*@param : Timeout: Timeout value. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i = 0; + HAL_StatusTypeDef Status; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Match the Address 1 */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear RX_ADDR1 Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + + /* Slave Receive */ + if (!READ_BIT(hi2c->Instance->SR, I2C_SR_SRW)) + { + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* BUS BUSY */ + while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + { + /* Receive Data */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE)) + { + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + if (hi2c->Rx_Size != 0) + { + if (hi2c->Rx_Count >= hi2c->Rx_Size) + { + break; + } + } + } + } + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + hi2c->Instance->SR = READ_REG(hi2c->Instance->SR); + } + /* Slave Transmit */ + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : receivd an amount of data in slave mode using IT mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a buffer to store data. +*@param : Size: Total size of data to receive . +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + /* Rx machine is running */ + if (hi2c->state != I2C_STATE_IDLE) + return HAL_ERROR; + + /* Set Slave machine is receiving */ + hi2c->state = I2C_STATE_RX_DATA; + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Clear RX ADDR1 Flag */ + SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1); + /* RX ADDR1, RXNE, STOPF Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN | I2C_CR_RXNE_INT_EN | I2C_CR_STOPF_INTEN); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : receive an amount of data in slave mode using DMA mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a buffer to store data. +*@param : Size: Total size of data to receive . +*@return: HAL_StatusTypeDef +******************************************************************************/ +#ifdef HAL_DMA_MODULE_ENABLED +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = Size; + + /* DMA Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN); + + /* Clear STOPF Interrupt Flag */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF); + /* STOPF Interrupt Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN); + + HAL_DMA_Start(hi2c->HDMA_Rx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->Rx_Buffer, hi2c->Rx_Size); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : send an amount of data in slave mode using DMA mode. +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : pData: Pointer to a data buffer. +*@param : Size: Total size of data to send . +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size) +{ + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = Size; + + /* Must Set TXE_SEL In DMA Mode !!! */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL); + /* DMA Enable */ + SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN); + + HAL_DMA_Start_IT(hi2c->HDMA_Tx, (uint32_t)hi2c->Tx_Buffer, (uint32_t)&hi2c->Instance->DR, hi2c->Tx_Size); + + return HAL_OK; +} +#endif +/****************************************************************************** +*@brief : Write an amount of data in blocking mode to a specific memory address +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress : Target device address +*@param : MemAddress : MemAddress Internal memory address +*@param : MemAddSize : MemAddSize Size of internal memory address +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Timeout value +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Tx_Buffer = pData; + hi2c->Tx_Size = Size; + hi2c->Tx_Count = 0; + + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK) + { + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send Memory Address MSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + /* Send Memory Address LSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + for (i = 0; i < hi2c->Tx_Size; i++) + { + /* Wait TXE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout)!= HAL_OK) return HAL_ERROR; + + /* Send Data */ + hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++]; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + return HAL_ERROR; + } + } + + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + /* Check Device Ready */ + while(I2C_Check_Device_Ready(hi2c, DevAddress, Timeout) != HAL_OK); + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Read an amount of data in blocking mode to a specific memory address +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress : Target device address +*@param : MemAddress : MemAddress Internal memory address +*@param : MemAddSize : MemAddSize Size of internal memory address +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to read +*@param : Timeout : Timeout value +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t i; + + /* Check I2C Parameter */ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->Rx_Buffer = pData; + hi2c->Rx_Size = Size; + hi2c->Rx_Count = 0; + + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Send Write Access Request */ + if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK) + { + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send Memory Address MSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + /* Send Memory Address LSB*/ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + /* Send Write Read Request */ + if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK) + { + /* Wait Master Transition receiving state */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear TX_RX_FLAG */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG); + + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + + for (i = 0; i < hi2c->Rx_Size - 1; i++) + { + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + } + + /* Prepare for Generate NACK */ + SET_BIT(hi2c->Instance->CR, I2C_CR_TACK); + /* Prepare for Generate STOP */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait RXNE Flag */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Read Data */ + hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR; + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + /* Generate ACK */ + CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK); + } + else + { + /* Get NACK */ + return HAL_ERROR; + } + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Get Slave Rx State +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +* +*@return: Slave State +******************************************************************************/ +uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->state; +} + +/****************************************************************************** +*@brief : Get Slave Tx State +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +* +*@return: Slave State +******************************************************************************/ +uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c) +{ + return hi2c->state; +} + +/****************************************************************************** +*@brief : Set I2C Clock Speed +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : ClockSpeed: I2C Clock Speed +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed) +{ + uint32_t APB_Clock; + + APB_Clock = HAL_RCC_GetPCLK1Freq(); + + hi2c->Instance->CLK_DIV = APB_Clock / (4 * ClockSpeed) - 1; + + return HAL_OK; +} + +/****************************************************************************** +*@brief This function handles I2C Communication Timeout. +*@param hi2c Pointer to a I2C_HandleTypeDef structure that contains +* the configuration information for I2C module +*@param Flag specifies the I2C flag to check. +*@param Status The new Flag status (SET or RESET). +*@param Timeout Timeout duration +*@param Tickstart Tick start value +*@retval HAL status +******************************************************************************/ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + __IO uint32_t lu32_Timeout; + /* have no timeout */ + if (Timeout == 0) + { + while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status); + } + else + { + lu32_Timeout = Timeout * 0xFF; + + while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status) + { + if (lu32_Timeout-- == 0) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/****************************************************************************** +*@brief : I2C Write Access Request +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress: Device address +*@param : Timeout: Timeout value +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_STARTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress & 0xFE; + + /* Wait for transmission End*/ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + return HAL_OK; + } +} + +/****************************************************************************** +*@brief : I2C Read Access Request +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress: Device address +*@param : Timeout: Timeout value +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + assert_param (IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_STARTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + + /* Clear MTF, To Prevent Errors */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress | 0x01; + + /* Wait for transmission End */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + return HAL_OK; + } +} + +/****************************************************************************** +*@brief : Check Device Ready +* +*@param : hi2c: a pointer of I2C_HandleTypeDef structure which contains +* the configuration information for the specified I2C. +*@param : DevAddress: Device address +*@param : Timeout: Timeout value +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout) +{ + /* Bus Busy */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) + return HAL_ERROR; + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR, I2C_CR_START); + + /* Send Device Address */ + hi2c->Instance->DR = DevAddress; + + /* Wait for transmission End */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR; + /* Clear MTF */ + hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF); + + /* Get NACK */ + if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK)) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_ERROR; + } + /* Get ACK */ + else + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR, I2C_CR_STOP); + + /* Wait for the bus to idle */ + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR; + + return HAL_OK; + } +} + +#endif //HAL_I2C_MODULE_ENABLED diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_i2s.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..f6d36d5aa46b2702c7ffa510e50ea5a5e7b1e54a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_i2s.c @@ -0,0 +1,1552 @@ + +/****************************************************************************** +*@file : hal_i2s.c +*@brief : I2S HAL module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_I2S_MODULE_ENABLED + +static void HAL_I2S_InitParamter(I2S_HandleTypeDef *hi2s); + +/****************************************************************************** +*@brief : This function handles I2S interrupt request. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_IRQHander(I2S_HandleTypeDef *hi2s) +{ + uint32_t flag; + uint32_t source; + + flag = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_MASK); + source = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_MASK); + + if ((source & I2S_IT_TXE) && (flag & I2S_FLAG_TXE)) + { + /* Tx buffer empty callback function */ + HAL_I2S_TxEmptyCallback(hi2s); + } + + if ((source & I2S_IT_RXNE) && (flag & I2S_FLAG_RXNE)) + { + /* Rx buffer non empty callback function */ + HAL_I2S_RxNonEmptyCallback(hi2s); + } + + if ((source & I2S_IT_MSUSP) && (flag & I2S_FLAG_MSUSP)) + { + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MSUSP); + /* Tx complete callback function */ + HAL_I2S_MsuspCallback(hi2s); + } + + if ((source & I2S_IT_SVTC) && (flag & I2S_FLAG_SVTC)) + { + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_SVTC); + /* Tx complete callback function */ + HAL_I2S_SvtcCallback(hi2s); + } + + flag &= I2S_FLAG_FE | I2S_FLAG_UDR | I2S_FLAG_OVR; + if ((source & I2S_IT_ERR) && (flag)) + { + hi2s->Error |= flag; + __HAL_I2S_CLEAR_FLAG(hi2s, flag); + HAL_I2S_ErrorCallback(hi2s); + } +} + +/****************************************************************************** +*@brief : Tx buffer empty callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_TxEmptyCallback(I2S_HandleTypeDef *hi2s) +{ + uint32_t over; + + /* Continue sending */ + if (hi2s->TxCount) + { + if (hi2s->pTxBuf) + __HAL_I2S_WRITE_DATA(hi2s, *hi2s->pTxBuf++); + else + __HAL_I2S_WRITE_DATA(hi2s, 0); + if (--hi2s->TxCount == 0) + { + over = 1; + if (hi2s->TxEmptyCallback) + { + over = hi2s->TxEmptyCallback(hi2s); + } + if (over) + { + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_TXE); + } + } + } +} + +/****************************************************************************** +*@brief : Tx buffer empty callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_MsuspCallback(I2S_HandleTypeDef *hi2s) +{ + uint32_t over; + + over = 1; + if (hi2s->MsuspCallback) + { + over = hi2s->MsuspCallback(hi2s); + } + if (over != 0) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + hi2s->State = I2S_STATE_READY; + } +} + +/****************************************************************************** +*@brief : Tx buffer empty callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_SvtcCallback(I2S_HandleTypeDef *hi2s) +{ + uint32_t over; + + over = 1; + if (hi2s->SvtcCallback) + { + over = hi2s->SvtcCallback(hi2s); + } + if (over != 0) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + hi2s->State = I2S_STATE_READY; + } +} + +/****************************************************************************** +*@brief : Rx buffer non empty callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_RxNonEmptyCallback(I2S_HandleTypeDef *hi2s) +{ + uint32_t over; + volatile uint32_t temp; + + if (hi2s->RxCount--) + { + if (hi2s->pRxBuf) + *hi2s->pRxBuf++ = __HAL_I2S_READ_DATA(hi2s); + else + temp = __HAL_I2S_READ_DATA(hi2s); + + } + + if (hi2s->RxCount == 0) + { + over = 1; + if (hi2s->RxCpltCallback) + { + over = hi2s->RxCpltCallback(hi2s); + } + + if (over != 0) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + hi2s->State = I2S_STATE_READY; + } + } +} + +/****************************************************************************** +*@brief : Tx Error callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) +{ + if (hi2s->ErrorCallback) + { + hi2s->ErrorCallback(hi2s); + } +} + +/****************************************************************************** +*@brief : Tx DMA transfer complete callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_DMATxCpltCallback(DMA_HandleTypeDef *hdmac) +{ + I2S_HandleTypeDef *hi2s; + + hi2s = hdmac->Parent; + + /* Take the number of unsent data */ + hi2s->TxCount = __HAL_DMA_GET_TRANSFER_SIZE(hi2s->hdmactx); + + if (hi2s->DMATxCpltCallback) + { + hi2s->DMATxCpltCallback(hi2s); + } +} + +/****************************************************************************** +*@brief : Tx DMA half transfer complete callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_DMATxHalfCpltCallback(DMA_HandleTypeDef *hdmac) +{ + I2S_HandleTypeDef *hi2s; + + hi2s = hdmac->Parent; + + /* Take the number of unsent data */ + hi2s->TxCount = __HAL_DMA_GET_TRANSFER_SIZE(hi2s->hdmactx); + + if (hi2s->DMATxHalfCpltCallback) + { + hi2s->DMATxHalfCpltCallback(hi2s); + } +} + +/****************************************************************************** +*@brief : Rx DMA transfer complete callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_DMARxCpltCallback(DMA_HandleTypeDef *hdmac) +{ + uint32_t over; + I2S_HandleTypeDef *hi2s; + + hi2s = hdmac->Parent; + + over = 1; + if (hi2s->DMARxCpltCallback) + { + over = hi2s->DMARxCpltCallback(hi2s); + } + + if (over != 0) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + hi2s->State = I2S_STATE_READY; + } +} + +/****************************************************************************** +*@brief : Rx DMA hlaf transfer complete callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_DMARxHalfCpltCallback(DMA_HandleTypeDef *hdmac) +{ + I2S_HandleTypeDef *hi2s; + + hi2s = hdmac->Parent; + + /* Take the number of data not received */ + hi2s->RxCount = __HAL_DMA_GET_TRANSFER_SIZE(hi2s->hdmacrx); + + if (hi2s->DMARxHalfCpltCallback) + { + hi2s->DMARxHalfCpltCallback(hi2s); + } +} + +/****************************************************************************** +*@brief : Rx DMA transfer error callback function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +__attribute__((weak)) void HAL_I2S_DMAErrorCallback(DMA_HandleTypeDef *hdmac) +{ + uint32_t over; + I2S_HandleTypeDef *hi2s; + + hi2s = hdmac->Parent; + + over = 1; + if (hi2s->ErrorCallback) + { + over = hi2s->ErrorCallback(hi2s); + } + + if (over) + { + /* abort rx dma transfer */ + HAL_DMA_Abort(hdmac); + + /* disable I2S Tx Rx DMA */ + __HAL_I2S_TX_RX_DMA_DISABLE(hi2s); + + __HAL_I2S_TX_RX_DISABLE(hi2s); + + /* Disable the error interrupt */ + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_ERR); + + /* set the dma transfer error */ + hi2s->Error |= I2S_DMA_ERROR; + + /* End of reception */ + hi2s->State = I2S_STATE_READY; + } +} + +/****************************************************************************** +*@brief : Initialize the I2S according to the specified. +* parameters in the I2S_InitTypeDef and create the associated handle. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) +{ + double Freq; + uint32_t div; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_MODE(hi2s->Init.Mode)); + assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); + assert_param(IS_I2S_DATAFORMAT(hi2s->Init.DataFormat)); + assert_param(IS_I2S_MCLKOUTPUT(hi2s->Init.MCLKOutput)); + assert_param(IS_I2S_CLOCKPOLARITY(hi2s->Init.ClockPolarity)); + assert_param(IS_I2S_IOSWITCH(hi2s->Init.IOSwitch)); + + assert_param(hi2s->Init.AudioFreq != 0u); + + Freq = (double)HAL_RCC_GetHCLKFreq(); + if (hi2s->Init.MCLKOutput == I2S_MCLKOUT_DISABLE) + { + if (hi2s->Init.DataFormat == I2S_DATA_FORMAT_16B_EXTENDED_TO_16B) + Freq = Freq / 32; + else + Freq = Freq / 64; + } + else + { + Freq = Freq / 256; + } + assert_param(Freq >= (double)hi2s->Init.AudioFreq); + Freq = Freq / (double)hi2s->Init.AudioFreq; + Freq += 0.5; + div = (uint32_t)Freq; + if (div & 1u) + { + div = (div - 1) >> 1; + assert_param(div <= 0x1FFU); + div += I2S_PR_OF; + } + else + { + div = div >> 1; + assert_param(div <= 0x1FFU); + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + + /* Disable I2S */ + __HAL_I2S_DISABLE(hi2s); + + /* Init the internal parameter */ + HAL_I2S_InitParamter(hi2s); + + hi2s->Instance->CR = hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | \ + hi2s->Init.ClockPolarity | hi2s->Init.IOSwitch; + + hi2s->Instance->PR = hi2s->Init.MCLKOutput | div; + + __HAL_I2S_ENABLE(hi2s); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DeInitialize the I2S peripheral. +* Before Deinitialization, the sending or receiving process needs to be aborted. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) +{ + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + + __HAL_I2S_DISABLE(hi2s); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_I2S_MspDeInit(hi2s); + + /* Init the internal parameter */ + HAL_I2S_InitParamter(hi2s); + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Initialize the I2S MSP. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None +******************************************************************************/ +__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) +{ + UNUSED(hi2s); +} + +/****************************************************************************** +*@brief : DeInitialize the I2S MSP. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None +******************************************************************************/ +__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) +{ + UNUSED(hi2s); +} + +/****************************************************************************** +*@brief : Register a User I2S Callback. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@note The registered callback function must be after initialization. +*@param : id: ID of the callback to be registered +* This parameter can be a combination of @ref I2S_CallbackID. +* @arg I2S_CALLBACKID_TXCPLT : transfer complete callback function. +* @arg I2S_CALLBACKID_TXHALFCPLT : transfer half complete callback function. +* @arg I2S_CALLBACKID_TXERROR : transfer error callback function. +* @arg I2S_CALLBACKID_RXCPLT : recevice completion callback function. +* @arg I2S_CALLBACKID_RXHALFCPLT : recevice half completion callback function. +* @arg I2S_CALLBACKID_RXERROR : receive error callback function. +*@param : pCallback: pointer to the Callback function. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, uint32_t id, pI2S_CallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_CALLBACKID(id)); + assert_param(pCallback != NULL); + + switch (id) + { + case I2S_CALLBACKID_TX_EMPTY: + + hi2s->TxEmptyCallback = pCallback; + break; + + case I2S_CALLBACKID_MSUSP: + + hi2s->MsuspCallback = pCallback; + break; + + case I2S_CALLBACKID_SVTC: + + hi2s->SvtcCallback = pCallback; + break; + + case I2S_CALLBACKID_TX_CPLT: + + hi2s->TxCpltCallback = pCallback; + break; + + case I2S_CALLBACKID_RX_CPLT: + + hi2s->RxCpltCallback = pCallback; + break; + + case I2S_CALLBACKID_DMA_TX_CPLT: + + hi2s->DMATxCpltCallback = pCallback; + break; + + case I2S_CALLBACKID_DMA_TX_HALF_CPLT: + + hi2s->DMATxHalfCpltCallback = pCallback; + break; + + case I2S_CALLBACKID_DMA_RX_CPLT: + + hi2s->DMARxCpltCallback = pCallback; + break; + + case I2S_CALLBACKID_DMA_RX_HALF_CPLT: + + hi2s->DMARxHalfCpltCallback = pCallback; + break; + + case I2S_CALLBACKID_ERROR: + + hi2s->ErrorCallback = pCallback; + break; + + default: + return HAL_ERROR; + } + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Unregister a User I2S Callback. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : id: ID of the callback to be registered +* This parameter can be a combination of @ref I2S_CallbackID. +* @arg I2S_CALLBACKID_TXCPLT : transfer complete callback function. +* @arg I2S_CALLBACKID_TXHALFCPLT : transfer half complete callback function. +* @arg I2S_CALLBACKID_TXERROR : transfer error callback function. +* @arg I2S_CALLBACKID_RXCPLT : recevice completion callback function. +* @arg I2S_CALLBACKID_RXHALFCPLT : recevice half completion callback function. +* @arg I2S_CALLBACKID_RXERROR : receive error callback function. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, uint32_t id) +{ + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(IS_I2S_CALLBACKID(id)); + + switch (id) + { + case I2S_CALLBACKID_TX_EMPTY: + + hi2s->TxEmptyCallback = NULL; + break; + + case I2S_CALLBACKID_MSUSP: + + hi2s->MsuspCallback = NULL; + break; + + case I2S_CALLBACKID_SVTC: + + hi2s->SvtcCallback = NULL; + break; + + case I2S_CALLBACKID_TX_CPLT: + + hi2s->TxCpltCallback = NULL; + break; + + case I2S_CALLBACKID_RX_CPLT: + + hi2s->RxCpltCallback = NULL; + break; + + case I2S_CALLBACKID_DMA_TX_CPLT: + + hi2s->DMATxCpltCallback = NULL; + break; + + case I2S_CALLBACKID_DMA_TX_HALF_CPLT: + + hi2s->DMATxHalfCpltCallback = NULL; + break; + + case I2S_CALLBACKID_DMA_RX_CPLT: + + hi2s->DMARxCpltCallback = NULL; + break; + + case I2S_CALLBACKID_DMA_RX_HALF_CPLT: + + hi2s->DMARxHalfCpltCallback = NULL; + break; + + case I2S_CALLBACKID_ERROR: + + hi2s->ErrorCallback = NULL; + break; + + default: + return HAL_ERROR; + } + return HAL_OK; +} + +HAL_StatusTypeDef HAL_I2S_TxData(I2S_HandleTypeDef *hi2s, uint32_t Data) +{ + hi2s->Instance->TXDR = Data; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_I2S_RxData(I2S_HandleTypeDef *hi2s, uint32_t *pdata) +{ + *pdata = hi2s->Instance->RXDR; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send an amount of data in blocking mode. +*@note In blocking mode, the user cannot enable interrupt. +*@note Users can add or ignore error handling in TxErrorCallback(). +* Error codes are stored in hi2s->TxError. +*@note The last word was being sent when the function exited. +* The application also needs to call the HAL_I2S_GetBusyStatus() function +* to detect the end of sending. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be sent. +*@param : timeout: Timeout duration. +* The minimum value of this parameter is 1. +* If the value of this parameter is 0xFFFFFFFF, it will be sent until all data are sent. +* @node The timeout should be greater than the time of all data transfers. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size, uint32_t timeout) +{ + volatile uint32_t temp; + uint32_t startTick; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + assert_param(timeout != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + + hi2s->pTxBuf = pdata; + hi2s->TxCount = size; + hi2s->Error = 0U; + + __HAL_I2S_TX_ENABLE(hi2s); + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_START_ENABLE(hi2s); + } + + startTick = HAL_GetTick(); + while (1) + { + /* Whether sending is aborted */ + if (hi2s->Abort != DISABLE) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN); + hi2s->State = I2S_STATE_READY; + return (HAL_ERROR); + } + + /* Check for errors */ + hi2s->Error = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_FE | I2S_FLAG_UDR); + if (hi2s->Error) + { + __HAL_I2S_CLEAR_FLAG(hi2s, hi2s->Error); + + if (hi2s->ErrorCallback) + { + if (hi2s->ErrorCallback(hi2s)) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN); + hi2s->State = I2S_STATE_READY; + return (HAL_ERROR); + } + } + } + + if (hi2s->TxCount) + { + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE)) + { + __HAL_I2S_WRITE_DATA(hi2s, *pdata++); + hi2s->TxCount--; + } + } + else if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_MSUSP)) + { + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MSUSP); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN); + hi2s->State = I2S_STATE_READY; + return HAL_OK; + } + } + else + { + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_SVTC)) + { + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_SVTC); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN); + hi2s->State = I2S_STATE_READY; + return HAL_OK; + } + } + + if (timeout != 0xFFFFFFFFU) + { + /* Whether the sending time has expired */ + if ((HAL_GetTick() - startTick) >= timeout) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN); + hi2s->State = I2S_STATE_READY; + return (HAL_TIMEOUT); + } + } + } +} + +/****************************************************************************** +*@brief : Receive an amount of data in blocking mode. +*@note In blocking mode, the user cannot enable interrupt. +*@note Users can add or ignore error handling in RxErrorCallback(). +* Error codes are stored in hi2s->RxError. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@param : timeout: Timeout duration. +* If the value of this parameter is 0, the received data will be detected only once and will not wait. +* If the value of this parameter is 0xFFFFFFFF, it will be received until all data are received. +* @node The timeout should be greater than the time of all data transfers. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size, uint32_t timeout) +{ + volatile uint32_t temp; + uint32_t startTick; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If I2S is receiving, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking reception can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + hi2s->pRxBuf = pdata; + hi2s->RxCount = size; + hi2s->Error = 0U; + + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_START_ENABLE(hi2s); + } + else + { + hi2s->Instance->RSIZE = size; + } + __HAL_I2S_RX_ENABLE(hi2s); + + startTick = HAL_GetTick(); + while (1) + { + /* Whether reception is aborted */ + if (hi2s->Abort != DISABLE) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_ERROR); + } + + /* Whether there are errors */ + hi2s->Error = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_FE | I2S_FLAG_OVR); + if (hi2s->Error) + { + if (hi2s->Error & I2S_FLAG_OVR) + { + temp = __HAL_I2S_READ_DATA(hi2s); + } + __HAL_I2S_CLEAR_FLAG(hi2s, hi2s->Error); + + if (hi2s->ErrorCallback) + { + if (hi2s->ErrorCallback(hi2s)) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_ERROR); + } + } + } + + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE)) + { + /* receive data */ + *pdata++ = (uint32_t)(__HAL_I2S_READ_DATA(hi2s)); + hi2s->RxCount--; + + if (hi2s->RxCount == 1) + { + } + if (hi2s->RxCount == 0) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_OK); + } + } + + /* Whether the receiving time has expired */ + if (timeout != 0xFFFFFFFFU) + { + if ((HAL_GetTick() - startTick) >= timeout) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_TIMEOUT); + } + } + } +} + +/****************************************************************************** +*@brief : Send an amount of data in blocking mode. +*@note In blocking mode, the user cannot enable interrupt. +*@note Users can add or ignore error handling in TxErrorCallback(). +* Error codes are stored in hi2s->TxError. +*@note The last word was being sent when the function exited. +* The application also needs to call the HAL_I2S_GetBusyStatus() function +* to detect the end of sending. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be sent. +*@param : timeout: Timeout duration. +* The minimum value of this parameter is 1. +* If the value of this parameter is 0xFFFFFFFF, it will be sent until all data are sent. +* @node The timeout should be greater than the time of all data transfers. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_Receive(I2S_HandleTypeDef *hi2s, uint32_t *prxdata, uint32_t *ptxdata, uint32_t size, uint32_t timeout) +{ + volatile uint32_t temp; + uint32_t startTick; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param((prxdata != 0U) || (ptxdata != 0U)); + assert_param(size != 0U); + assert_param(timeout != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + hi2s->pTxBuf = ptxdata; + hi2s->pRxBuf = prxdata; + hi2s->TxCount = size; + hi2s->RxCount = size; + hi2s->Error = 0U; + + __HAL_I2S_TX_RX_ENABLE(hi2s); + + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_START_ENABLE(hi2s); + } + + startTick = HAL_GetTick(); + while (1) + { + /* Whether sending is aborted */ + if (hi2s->Abort != DISABLE) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_ERROR); + } + + /* Check for errors */ + hi2s->Error = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_FE | I2S_FLAG_OVR | I2S_FLAG_UDR); + if (hi2s->Error) + { + if (hi2s->Error & I2S_FLAG_OVR) + { + temp = __HAL_I2S_READ_DATA(hi2s); + } + __HAL_I2S_CLEAR_FLAG(hi2s, hi2s->Error); + + if (hi2s->ErrorCallback) + { + if (hi2s->ErrorCallback(hi2s)) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_ERROR); + } + } + } + + if (hi2s->TxCount) + { + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE)) + { + if (ptxdata) + { + __HAL_I2S_WRITE_DATA(hi2s, *ptxdata++); + } + else + { + __HAL_I2S_WRITE_DATA(hi2s, 0); + } + hi2s->TxCount--; + } + } + + if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE)) + { + /* receive data */ + if (prxdata) + { + *prxdata++ = (uint32_t)(__HAL_I2S_READ_DATA(hi2s)); + } + else + { + temp = (uint32_t)(__HAL_I2S_READ_DATA(hi2s)); + } + hi2s->RxCount--; + + if (hi2s->RxCount == 0) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_OK); + } + } + + if (timeout != 0xFFFFFFFF) + { + /* Whether the sending time has expired */ + if ((HAL_GetTick() - startTick) >= timeout) + { + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + hi2s->State = I2S_STATE_READY; + return (HAL_TIMEOUT); + } + } + } +} + +/****************************************************************************** +*@brief : Send an amount of data in interrupt mode. +*@note In interrupt mode, the transmission related interrupts (TXE/ERR) are forced enabled. +*@note Users can add or ignore error handling in ErrorCallback(). +* Error codes are stored in hi2s->TxError. +*@note When the callback function TxCpltCallback() is called, the last word is being sent. +* The application also needs to call the HAL_I2S_GetBusyStatus() function +* to detect the end of sending. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size) +{ + volatile uint32_t temp; + uint32_t tempCR; + uint32_t tempPR; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(pdata); + assert_param(size != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY_IT; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + hi2s->pTxBuf = pdata; + hi2s->TxCount = size; + hi2s->Error = 0U; + + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_TXE | I2S_IT_MSUSP | I2S_IT_ERR); + __HAL_I2S_TX_ENABLE(hi2s); + __HAL_I2S_START_ENABLE(hi2s); + } + else + { + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_TXE | I2S_IT_SVTC | I2S_IT_ERR); + __HAL_I2S_TX_ENABLE(hi2s); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in interrupt mode. +*@note In interrupt mode, receiving completion interrupt (RXNE/ERR) are forced enabled. +* If an error occurs in the reception, the reception stops automatically. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint32_t size) +{ + volatile uint32_t temp; + uint32_t tempCR; + uint32_t tempPR; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(pdata); + assert_param(size != 0U); + + /* If I2S is receiving, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking reception can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY_IT; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + hi2s->pRxBuf = pdata; + hi2s->RxCount = size; + hi2s->Error = 0U; + + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_RXNE | I2S_IT_ERR); + + __HAL_I2S_RX_ENABLE(hi2s); + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + hi2s->Instance->RSIZE = size; + __HAL_I2S_START_ENABLE(hi2s); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send an amount of data in interrupt mode. +*@note In interrupt mode, the transmission related interrupts (TXE/ERR) are forced enabled. +*@note Users can add or ignore error handling in ErrorCallback(). +* Error codes are stored in hi2s->TxError. +*@note When the callback function TxCpltCallback() is called, the last word is being sent. +* The application also needs to call the HAL_I2S_GetBusyStatus() function +* to detect the end of sending. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *prxdata, uint32_t *ptxdata, uint32_t size) +{ + volatile uint32_t temp; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param((prxdata != 0U) || (ptxdata != 0U)); + assert_param(size != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY_IT; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + hi2s->pTxBuf = ptxdata; + hi2s->TxCount = size; + hi2s->pRxBuf = prxdata; + hi2s->RxCount = size; + hi2s->Error = 0U; + + /* enable interrupt (TXE/RXNE/ERR) */ + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR); + + __HAL_I2S_TX_RX_ENABLE(hi2s); + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_START_ENABLE(hi2s); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send an amount of data in DMA mode. +*@note In DMA mode, the tx buffer empty interrupt (TXE) is forced to disabled. +* the error interrupt (ERR) is forced to enabled. +* the DMA transmission related interrupt (ITC/HFTC/IE) is forced to enabled. +* If an DMA transfer error occurs in the transmission, +* the transmission stops automatically. +*@note When the callback function TxCpltCallback() is called, the last word is being sent. +* The application also needs to call the HAL_I2S_GetBusyStatus() function +* to detect the end of sending. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint16_t size) +{ + volatile uint32_t temp; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY_DMA; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + /* set dmac callback function */ + hi2s->hdmactx->XferCpltCallback = HAL_I2S_DMATxCpltCallback; + if (hi2s->DMATxHalfCpltCallback) + hi2s->hdmactx->XferHalfCpltCallback = HAL_I2S_DMATxHalfCpltCallback; + else + hi2s->hdmactx->XferHalfCpltCallback = NULL; + hi2s->hdmactx->XferErrorCallback = HAL_I2S_DMAErrorCallback; + + hi2s->pTxBuf = pdata; + hi2s->TxCount = size; + hi2s->Error = 0U; + + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_ERR); + __HAL_I2S_TX_ENABLE(hi2s); + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_MSUSP); + __HAL_I2S_START_ENABLE(hi2s); + } + else + { + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_SVTC); + } + + /* Start DMA interrupt transfer */ + if (HAL_DMA_Start_IT(hi2s->hdmactx, (uint32_t)pdata, (uint32_t)&hi2s->Instance->TXDR, size) != HAL_OK) + { + /* DMA sending failed */ + HAL_DMA_Abort(hi2s->hdmactx); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_ERR); + hi2s->Error = I2S_DMA_TX_ERROR; + hi2s->State = I2S_STATE_READY; + return HAL_ERROR; + } + + __HAL_I2S_TX_DMA_ENABLE(hi2s); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in DMA mode. +*@note In DMA mode, rx buffer non empty interrupt (RXNE) is forced disable. +* the error interrupt (ERR) is forced enabled. +* the DMA transmission related interrupt (ITC/HFTC/IE) is forced to enabled. +* If an DMA transfer error occurs in the reception, +* the reception stops automatically. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *pdata, uint16_t size) +{ + volatile uint32_t temp; + uint32_t tempCR; + uint32_t tempPR; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY_DMA; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + /* set dma callback function */ + hi2s->hdmacrx->XferCpltCallback = HAL_I2S_DMARxCpltCallback; + hi2s->hdmacrx->XferErrorCallback = HAL_I2S_DMAErrorCallback; + if (hi2s->DMARxHalfCpltCallback) + hi2s->hdmacrx->XferHalfCpltCallback = HAL_I2S_DMARxHalfCpltCallback; + else + hi2s->hdmacrx->XferHalfCpltCallback = NULL; + + hi2s->pRxBuf = pdata; + hi2s->RxCount = size; + hi2s->Error = 0U; + + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_ERR); + __HAL_I2S_RX_ENABLE(hi2s); + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + hi2s->Instance->RSIZE = size; + __HAL_I2S_START_ENABLE(hi2s); + } + /* Start DMA interrupt transfer */ + if (HAL_DMA_Start_IT(hi2s->hdmacrx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)pdata, size) != HAL_OK) + { + /* Set error code to DMA */ + HAL_DMA_Abort(hi2s->hdmacrx); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_REN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_ERR); + hi2s->Error = I2S_DMA_RX_ERROR; + hi2s->State = I2S_STATE_READY; + return HAL_ERROR; + } + + __HAL_I2S_RX_DMA_ENABLE(hi2s); + + return HAL_OK; +} +/****************************************************************************** +*@brief : Send an amount of data in DMA mode. +*@note In DMA mode, the tx buffer empty interrupt (TXE) is forced to disabled. +* the error interrupt (ERR) is forced to enabled. +* the DMA transmission related interrupt (ITC/HFTC/IE) is forced to enabled. +* If an DMA transfer error occurs in the transmission, +* the transmission stops automatically. +*@note When the callback function TxCpltCallback() is called, the last word is being sent. +* The application also needs to call the HAL_I2S_GetBusyStatus() function +* to detect the end of sending. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Transmit_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *prxdata, uint32_t *ptxdata, uint16_t size) +{ + volatile uint32_t temp; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + assert_param(size != 0U); + + /* If I2S is sending, an error is returned */ + if (hi2s->State != I2S_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hi2s->Abort = DISABLE; + + /* state: busy */ + hi2s->State = I2S_STATE_BUSY_DMA; + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_STOP | I2S_CR_TEN | I2S_CR_REN | I2S_CR_TXDMAEN | I2S_CR_RXDMAEN); + + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_MASK); + temp = __HAL_I2S_READ_DATA(hi2s); + __HAL_I2S_CLEAR_FLAG(hi2s, I2S_FLAG_MASK); + + /* set dmac callback function */ + hi2s->hdmactx->XferCpltCallback = HAL_I2S_DMATxCpltCallback; + if (hi2s->DMATxHalfCpltCallback) + hi2s->hdmactx->XferHalfCpltCallback = HAL_I2S_DMATxHalfCpltCallback; + else + hi2s->hdmactx->XferHalfCpltCallback = NULL; + hi2s->hdmactx->XferErrorCallback = HAL_I2S_DMAErrorCallback; + + /* set dma callback function */ + hi2s->hdmacrx->XferCpltCallback = HAL_I2S_DMARxCpltCallback; + hi2s->hdmacrx->XferErrorCallback = HAL_I2S_DMAErrorCallback; + if (hi2s->DMARxHalfCpltCallback) + hi2s->hdmacrx->XferHalfCpltCallback = HAL_I2S_DMARxHalfCpltCallback; + else + hi2s->hdmacrx->XferHalfCpltCallback = NULL; + + hi2s->pTxBuf = ptxdata; + hi2s->TxCount = size; + hi2s->pRxBuf = prxdata; + hi2s->RxCount = size; + hi2s->Error = 0U; + + + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_ERR); + __HAL_I2S_TX_RX_ENABLE(hi2s); + if (hi2s->Init.Mode != I2S_MODE_SLAVE) + { + __HAL_I2S_START_ENABLE(hi2s); + } + + /* Start DMA interrupt transfer */ + if (HAL_DMA_Start_IT(hi2s->hdmactx, (uint32_t)ptxdata, (uint32_t)&hi2s->Instance->TXDR, size) != HAL_OK) + { + /* DMA sending failed */ + HAL_DMA_Abort(hi2s->hdmactx); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_ERR); + hi2s->Error = I2S_DMA_TX_ERROR; + hi2s->State = I2S_STATE_READY; + return HAL_ERROR; + } + + /* Start DMA interrupt transfer */ + if (HAL_DMA_Start_IT(hi2s->hdmacrx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)prxdata, size) != HAL_OK) + { + /* Set error code to DMA */ + HAL_DMA_Abort(hi2s->hdmactx); + HAL_DMA_Abort(hi2s->hdmacrx); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_ERR); + hi2s->Error = I2S_DMA_RX_ERROR; + hi2s->State = I2S_STATE_READY; + return HAL_ERROR; + } + + __HAL_I2S_TX_RX_DMA_ENABLE(hi2s); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Abort ongoing transmit transfer(block mode/interrupt mode/dma mode). +* In blocking mode, check TxState to exit the abort function. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_I2S_Abort(I2S_HandleTypeDef *hi2s) +{ + volatile uint32_t temp; + + /* Check the parameters */ + assert_param(IS_I2S_HANDLE(hi2s)); + assert_param(IS_I2S_INSTANCE(hi2s->Instance)); + + /* If I2S is not sent, return directly */ + if (hi2s->State == I2S_STATE_READY) + return HAL_OK; + + if (hi2s->State == I2S_STATE_BUSY) + { + /* Abort ongoing transmit transfer(in block mode) */ + + /* enable tx abort flag */ + hi2s->Abort = ENABLE; + return HAL_OK; + } + + if (hi2s->State == I2S_STATE_BUSY_IT) + { + /* Abort ongoing transmit transfer(interrupt mode) */ + + /* disable interrupt (TXE/ERR) */ + __HAL_I2S_IT_ENABLE(hi2s, I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_MSUSP | I2S_IT_ERR); + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + + /* end of sending */ + hi2s->State = I2S_STATE_READY; + return HAL_OK; + } + + if (hi2s->State == I2S_STATE_BUSY_DMA) + { + /* Abort ongoing transmit transfer(dma mode) */ + + /* disable interrupt (ERR) */ + __HAL_I2S_IT_DISABLE(hi2s, I2S_IT_ERR); + + /* abort dma transfer */ + HAL_DMA_Abort(hi2s->hdmactx); + + hi2s->Instance->CR &= ~(I2S_CR_START | I2S_CR_TEN | I2S_CR_REN); + + /* disable I2S Tx DMA */ + __HAL_I2S_TX_RX_DMA_DISABLE(hi2s); + + /* end of sending */ + hi2s->State = I2S_STATE_READY; + return HAL_OK; + } + + return HAL_ERROR; +} + +/****************************************************************************** +*@brief : Get sending status. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: sending status. +* The return value can be @ ref I2S_State value +* @arg I2S_STATE_READY: I2S not sent. +* @arg I2S_STATE_BUSY: I2S sending(block mode). +* @arg I2S_STATE_BUSY_IT: I2S sending(interrupt mode). +* @arg I2S_STATE_BUSY_DMA: I2S sending(dma mode). +******************************************************************************/ +uint32_t HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +{ + assert_param(IS_I2S_HANDLE(hi2s)); + + return (hi2s->State); +} + + + +/****************************************************************************** +*@brief : Init the internal parameter. +*@param : hi2s: pointer to a I2S_HandleTypeDef structure that contains +* the configuration information for I2S module. +*@return: None. +******************************************************************************/ +static void HAL_I2S_InitParamter(I2S_HandleTypeDef *hi2s) +{ + hi2s->State = 0U; + hi2s->Abort = 0U; + hi2s->pTxBuf = 0U; + hi2s->TxCount = 0U; + hi2s->pRxBuf = 0U; + hi2s->RxCount = 0U; + + hi2s->MsuspCallback = NULL; + hi2s->TxCpltCallback = NULL; + hi2s->RxCpltCallback = NULL; + hi2s->DMATxCpltCallback = NULL; + hi2s->DMATxHalfCpltCallback = NULL; + hi2s->DMARxCpltCallback = NULL; + hi2s->DMARxHalfCpltCallback = NULL; + hi2s->ErrorCallback = NULL; +} + +#endif /* HAL_I2S_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT AISINOCHIP *****END OF FILE****/ + + + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_iwdt.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_iwdt.c new file mode 100644 index 0000000000000000000000000000000000000000..b4085712463584fbc42fa7d5e958d9a7c4a4b265 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_iwdt.c @@ -0,0 +1,245 @@ + +/****************************************************************************** +*@file : hal_iwdt.c +*@brief : IWDT HAL module driver. +******************************************************************************/ + +#include "hal.h" + + +#ifdef HAL_IWDT_MODULE_ENABLED + + +static HAL_StatusTypeDef HAL_IWDT_WaitOnFlagToResetUntilTimeout(IWDT_HandleTypeDef *hiwdt, \ + uint32_t flags, int32_t startTick, uint32_t timeout); + +/****************************************************************************** +*@brief : IWDT interrupt request. +*@param : hiwdt: pointer to a IWDT_HandleTypeDef structure that contains +* the configuration information for the specified IWDT module. +*@return: None +******************************************************************************/ +void HAL_IWDT_IRQHandler(IWDT_HandleTypeDef *hiwdt) +{ + /* Check the parameters */ + assert_param(IS_IWDT_ALL_INSTANCE(hiwdt->Instance)); + + if (SET == HAL_IWDT_GetPending()) + { + HAL_IWDT_Callback(hiwdt); + + /* Clear interrupt pending bit of the IWDT. */ + HAL_IWDT_ClearPending(); + } +} + + +/****************************************************************************** +*@brief : IWDT interrupt callback. +*@param : hiwdt: pointer to a IWDT_HandleTypeDef structure that contains +* the configuration information for the specified IWDT module. +*@return: None +******************************************************************************/ +__weak void HAL_IWDT_Callback(IWDT_HandleTypeDef *hiwdt) +{ + UNUSED(hiwdt); +} + +/****************************************************************************** +*@brief : Initialize the IWDT according to the specified parameters in the +* IWDT_InitTypeDef and start watchdog. Before exiting function, +* watchdog is refreshed in order to have correct time base. +*@param : hiwdt: pointer to a IWDT_HandleTypeDef structure that contains +* the configuration information for the specified IWDT module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hiwdt) +{ + uint32_t startTime; + + /* Check the parameters */ + assert_param(IS_IWDT_HANDLE(hiwdt)); + assert_param(IS_IWDT_ALL_INSTANCE(hiwdt->Instance)); + assert_param(IS_IWDT_PRESCALER(hiwdt->Init.Prescaler)); + assert_param(IS_IWDT_RELOAD(hiwdt->Init.Reload)); + assert_param(IS_IWDT_WINDOW(hiwdt->Init.Window)); + assert_param(IS_IWDT_WAKEUP(hiwdt->Init.Wakeup)); + + HAL_IWDT_MspInit(hiwdt); + + + /* Enable IWDT. RC32K is turned on automatically */ + hiwdt->Instance->CMDR = IWDT_CMD_ENABLE; + + /* Enable write access to IWDT_PR */ + hiwdt->Instance->CMDR = IWDT_CMD_WRITE_ENABLE; + + /* Check flag IWDT_FLAG_PVU */ + startTime = HAL_GetTick(); + if (HAL_IWDT_WaitOnFlagToResetUntilTimeout(hiwdt, IWDT_FLAG_PVU, startTime, IWDT_PVU_TIMEOUT) != HAL_OK) + return HAL_ERROR; + + /* Write to IWDT registers the Prescaler to work with */ + hiwdt->Instance->PR = hiwdt->Init.Prescaler; + + /* Check flag IWDT_FLAG_RVU */ + startTime = HAL_GetTick(); + if (HAL_IWDT_WaitOnFlagToResetUntilTimeout(hiwdt, IWDT_FLAG_RVU, startTime, IWDT_RVU_TIMEOUT) != HAL_OK) + return HAL_ERROR; + + /* Write to IWDT registers the Reload values to work with */ + hiwdt->Instance->RLR = hiwdt->Init.Reload; + + /* Check flag IWDT_FLAG_WTU */ + startTime = HAL_GetTick(); + if (HAL_IWDT_WaitOnFlagToResetUntilTimeout(hiwdt, IWDT_FLAG_WTU, startTime, IWDT_WTU_TIMEOUT) != HAL_OK) + return HAL_ERROR; + + /* Write to IWDT registers the Wakeup values to work with */ + if (hiwdt->Init.Reload > hiwdt->Init.Wakeup) + { + /* Check the parameters */ + assert_param(IS_IWDT_WAKEUPMODE(hiwdt->Init.WakeupMode)); + + hiwdt->Instance->WUTR = hiwdt->Init.Wakeup; + + /* Clear interrupt pending bit of the IWDT. */ + HAL_EXTI_ClearPending(IWDT_EXTI_LINE); + + /* set wakeup mode. */ + HAL_EXTI_SetConfigLine(NULL, IWDT_EXTI_LINE, hiwdt->Init.WakeupMode); + + } + else + { + /* wakeup disable */ + hiwdt->Instance->WUTR = IWDT_RELOAD_MAX_VALUE; + + /* Clear wakeup mode. */ + HAL_EXTI_ClearConfigLine(IWDT_EXTI_LINE); + + /* Clear interrupt pending bit of the IWDT. */ + HAL_EXTI_ClearPending(IWDT_EXTI_LINE); + } + + /* Check flag IWDT_FLAG_WVU */ + startTime = HAL_GetTick(); + if (HAL_IWDT_WaitOnFlagToResetUntilTimeout(hiwdt, IWDT_FLAG_WVU, startTime, IWDT_WVU_TIMEOUT) != HAL_OK) + return HAL_ERROR; + + /* Write to IWDT registers the window values to work with */ + if (hiwdt->Init.Reload <= hiwdt->Init.Window) + hiwdt->Instance->WINR = IWDT_RELOAD_MAX_VALUE; + + /* Check all flags */ + startTime = HAL_GetTick(); + if (HAL_IWDT_WaitOnFlagToResetUntilTimeout(hiwdt, IWDT_FLAG_PVU | IWDT_FLAG_RVU | IWDT_FLAG_WVU | IWDT_FLAG_WTU | \ + IWDT_FLAG_RLF, startTime, IWDT_RLF_TIMEOUT) != HAL_OK) + { + return HAL_ERROR; + } + + if (hiwdt->Init.Reload > hiwdt->Init.Wakeup) + { + /* wakeup enable */ + hiwdt->Instance->CMDR = IWDT_CMD_WAKEUP_ENABLE; + } + + if (hiwdt->Init.Reload > hiwdt->Init.Window) + { + /* Write to IWDT registers the window values to work with */ + hiwdt->Instance->WINR = hiwdt->Init.Window; + } + else + { + hiwdt->Instance->CMDR = IWDT_CMD_RELOAD; + } + + /* Check all flags */ + startTime = HAL_GetTick(); + if (HAL_IWDT_WaitOnFlagToResetUntilTimeout(hiwdt, IWDT_FLAG_PVU | IWDT_FLAG_RVU | IWDT_FLAG_WVU | IWDT_FLAG_WTU | \ + IWDT_FLAG_RLF, startTime, IWDT_RLF_TIMEOUT) != HAL_OK) + return HAL_ERROR; + + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the IWDT MSP. +*@param : hiwdt: pointer to a IWDT_HandleTypeDef structure that contains +* the configuration information for the specified IWDT module. +*@return: None +******************************************************************************/ +__weak void HAL_IWDT_MspInit(IWDT_HandleTypeDef * hiwdt) +{ + UNUSED(hiwdt); +} + +/****************************************************************************** +*@brief : Refresh the IWDT. +*@param : hiwdt: pointer to a IWDT_HandleTypeDef structure that contains +* the configuration information for the specified IWDT module. +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_IWDT_Refresh(IWDT_HandleTypeDef *hiwdt) +{ + /* Check the parameters */ + assert_param(IS_IWDT_HANDLE(hiwdt)); + + hiwdt->Instance->CMDR = IWDT_CMD_RELOAD; + + while (hiwdt->Instance->SR & IWDT_FLAG_RLF); + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Get interrupt pending bit of the IWDT. +*@return: None +******************************************************************************/ +FlagStatus HAL_IWDT_GetPending(void) +{ + return (HAL_EXTI_GetPending(IWDT_EXTI_LINE)); +} + +/****************************************************************************** +*@brief : Clear interrupt pending bit of the IWDT. +*@return: None. +******************************************************************************/ +void HAL_IWDT_ClearPending(void) +{ + HAL_EXTI_ClearPending(IWDT_EXTI_LINE); +} + +/****************************************************************************** +*@brief : Handle IWDT Timeout. +*@param : hiwdt: pointer to a IWDT_HandleTypeDef structure that contains +* the configuration information for the specified IWDT module. +*@param : flags: Specifies the IWDT flag to check. +* This parameter can be a combination of @ref IWDT_Flag. +* @arg IWDT_FLAG_PVU: IWDT timer prescaler value update. +* @arg IWDT_FLAG_RVU: IWDT timer reload value update. +* @arg IWDT_FLAG_WVU: IWDT timer window value update. +* @arg IWDT_FLAG_WTU: IWDT timer wake-up value update. +* @arg IWDT_FLAG_RLF: IWDT timer feeding dog completed. +*@param : startTick: Tick start value. +*@param : timeout: Timeout duration. +*@return: None. +******************************************************************************/ +static HAL_StatusTypeDef HAL_IWDT_WaitOnFlagToResetUntilTimeout(IWDT_HandleTypeDef *hiwdt, \ + uint32_t flags, int32_t startTick, uint32_t timeout) +{ + while ((hiwdt->Instance->SR & flags) == flags) + { + if ((HAL_GetTick() - startTick) >= timeout) + return (HAL_TIMEOUT); + } + return (HAL_OK); +} + +#endif /* HAL_IWDT_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT AISINOCHIP *****END OF FILE****/ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_lptim.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_lptim.c new file mode 100644 index 0000000000000000000000000000000000000000..e4d7974eef25ff4970b862ec3980f1b686bea1e1 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_lptim.c @@ -0,0 +1,1244 @@ + +/****************************************************************************** +*@file : hal_lptim.c +*@brief : LPTIM HAL module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_LPTIM_MODULE_ENABLED + + +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); +static HAL_StatusTypeDef HAL_LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); + +/****************************************************************************** +*@brief : Handle LPTIM interrupt request. +*@param : hlptim: LPTIM handle. +*@return: None +******************************************************************************/ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) +{ + /* Compare match interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM)) + { + /* Clear Compare match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); + + if (hlptim->CompareMatchCallback) + { + hlptim->CompareMatchCallback(hlptim); + } + return; + } + } + + /* Autoreload match interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM)) + { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); + + if (hlptim->AutoReloadMatchCallback) + { + hlptim->AutoReloadMatchCallback(hlptim); + } + return; + } + } + + /* Repetition Counter update event interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPUE)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPUE)) + { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPUE); + + if (hlptim->RepetitionUpdateCallback) + { + hlptim->RepetitionUpdateCallback(hlptim); + } + return; + } + } + + /* Direction counter changed from Down to Up interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP)) + { + /* Clear Direction counter changed from Down to Up flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); + + if (hlptim->DirectionUpCallback) + { + hlptim->DirectionUpCallback(hlptim); + } + return; + } + } + + /* Direction counter changed from Up to Down interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN)) + { + /* Clear Direction counter changed from Up to Down flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); + + if (hlptim->DirectionDownCallback) + { + hlptim->DirectionDownCallback(hlptim); + } + return; + } + } + + /* Trigger detected interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG)) + { + /* Clear Trigger detected flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); + + if (hlptim->TriggerCallback) + { + hlptim->TriggerCallback(hlptim); + } + return; + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK)) + { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + if (hlptim->CompareWriteCallback) + { + hlptim->CompareWriteCallback(hlptim); + } + return; + } + } + + /* Autoreload write interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK)) + { + /* Clear Autoreload write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + if (hlptim->AutoReloadWriteCallback) + { + hlptim->AutoReloadWriteCallback(hlptim); + } + return; + } + } + + /* Repetition Counter write interrupt */ + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK)) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK)) + { + /* Clear Autoreload write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + if (hlptim->RepetitionWriteCallback) + { + hlptim->RepetitionWriteCallback(hlptim); + } + return; + } + } + +} + +/****************************************************************************** +*@brief : Initialize the LPTIM according to the specified parameters in the +* LPTIM_InitTypeDef and initialize the associated handle. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t temp; + + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.ClockSource)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.ClockPrescaler)); + assert_param(IS_LPTIM_TRIG_SOURCE(hlptim->Init.TriggerSource));; + assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); + assert_param(IS_LPTIM_WAVEFORM_POLARITY(hlptim->Init.WaveformPolarity)); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_LPTIM_MspInit(hlptim); + + /* LPTIM Reset */ + { + if (hlptim->Instance == LPTIM1) + { + __HAL_RCC_LPTIM1_RESET(); + } + else if(hlptim->Instance == LPTIM2) + { + __HAL_RCC_LPTIM2_RESET(); + } + else if(hlptim->Instance == LPTIM3) + { + __HAL_RCC_LPTIM3_RESET(); + } + else if(hlptim->Instance == LPTIM4) + { + __HAL_RCC_LPTIM4_RESET(); + } + else if(hlptim->Instance == LPTIM5) + { + __HAL_RCC_LPTIM5_RESET(); + } + else if(hlptim->Instance == LPTIM6) + { + __HAL_RCC_LPTIM6_RESET(); + } + } + + + /* Set initialization parameters */ + temp = hlptim->Init.ClockPrescaler | hlptim->Init.WaveformPolarity | hlptim->Init.UpdateMode; + + if (hlptim->Init.TriggerSource != LPTIM_TRIGSOURCE_SOFTWARE) + temp |= hlptim->Init.TriggerSource; + + /* Configure internal clock source, counter source */ + if (hlptim->Init.ClockSource != LPTIM_CLOCKSOURCE_EXTERNAL_INPUT1) + { + assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); + + /* Configure LPTIM internal clock sources */ + { + if (hlptim->Instance == LPTIM1) + { + if (HAL_RCC_LPTIM1ClockSourceConfig(hlptim->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM2) + { + if (HAL_RCC_LPTIM2ClockSourceConfig(hlptim->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM3) + { + if (HAL_RCC_LPTIM3ClockSourceConfig(hlptim->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM4) + { + if (HAL_RCC_LPTIM4ClockSourceConfig(hlptim->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM5) + { + if (HAL_RCC_LPTIM5ClockSourceConfig(hlptim->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM6) + { + if (HAL_RCC_LPTIM6ClockSourceConfig(hlptim->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + } + } + + /* Configure counter source */ + temp |= hlptim->Init.CounterSource; + + /* Configure counter polarity and counter filtering, if external counter source is selected */ + if (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL) + { + assert_param(IS_LPTIM_COUNTER_POLARITY(hlptim->Init.CounterPolarity)); + assert_param(IS_LPTIM_COUNTER_FILTER(hlptim->Init.CounterFilter)); + + temp |= hlptim->Init.CounterPolarity | hlptim->Init.CounterFilter; + + /* Configure LPTIM input1 sources */ +// if (hlptim->Instance == LPTIM1) +// { + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Init.Input1Source)); + + /* Configure LPTIM Input1 sources */ + hlptim->Instance->CFGR2 |= hlptim->Init.Input1Source; +// } + } + + /* Configure trigger polarity and trigger filtering, if external trigger source is selected */ + if (hlptim->Init.TriggerSource != LPTIM_TRIGSOURCE_SOFTWARE) + { + assert_param(IS_LPTIM_TRIG_POLARITY(hlptim->Init.TriggerPolarity)); + assert_param(IS_LPTIM_TRIG_FILTER(hlptim->Init.TriggerFilter)); + + temp |= hlptim->Init.TriggerPolarity | hlptim->Init.TriggerFilter; + } + } + else + { + assert_param((hlptim->Init.CounterPolarity == LPTIM_COUNTERPOLARITY_RISING) || \ + (hlptim->Init.CounterPolarity == LPTIM_COUNTERPOLARITY_FALLING)); + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Init.Input1Source)); + + /* Configure external clock source and counter polarity */ +// temp |= hlptim->Init.ClockSource | hlptim->Init.CounterPolarity; + temp |= LPTIM_CFGR1_CKSEL | hlptim->Init.CounterPolarity; + + /* Configure trigger polarity and trigger filtering, if external trigger source is selected */ + if (hlptim->Init.TriggerSource != LPTIM_TRIGSOURCE_SOFTWARE) + { + assert_param(IS_LPTIM_TRIG_POLARITY(hlptim->Init.TriggerPolarity)); + + temp |= hlptim->Init.TriggerPolarity; + } + + /* Configure LPTIM input sources */ +// if (hlptim->Instance == LPTIM1) +// { + /* Configure LPTIM Input1 sources */ + hlptim->Instance->CFGR2 |= hlptim->Init.Input1Source; +// } + } + + hlptim->RepetitionCounter = 0U; + hlptim->AutoReload = 1U; + hlptim->Compare = 0U; + + /* Write to LPTIMx CFGR1 */ + hlptim->Instance->CFGR1 = temp; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : DeInitialize the LPTIM peripheral. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* LPTIM Reset */ + if (hlptim->Instance == LPTIM1) + { + __HAL_RCC_LPTIM1_RESET(); + } + else if(hlptim->Instance == LPTIM2) + { + __HAL_RCC_LPTIM2_RESET(); + } + else if(hlptim->Instance == LPTIM3) + { + __HAL_RCC_LPTIM3_RESET(); + } + else if(hlptim->Instance == LPTIM4) + { + __HAL_RCC_LPTIM4_RESET(); + } + else if(hlptim->Instance == LPTIM5) + { + __HAL_RCC_LPTIM5_RESET(); + } + else if(hlptim->Instance == LPTIM6) + { + __HAL_RCC_LPTIM6_RESET(); + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_LPTIM_MspDeInit(hlptim); + + hlptim->RepetitionCounter = 0U; + hlptim->AutoReload = 1U; + hlptim->Compare = 0U; + + hlptim->CompareMatchCallback = NULL; + hlptim->AutoReloadMatchCallback = NULL; + hlptim->TriggerCallback = NULL; + hlptim->CompareWriteCallback = NULL; + hlptim->AutoReloadWriteCallback = NULL; + hlptim->DirectionUpCallback = NULL; + hlptim->DirectionDownCallback = NULL; + hlptim->RepetitionUpdateCallback = NULL; + hlptim->RepetitionWriteCallback = NULL; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the LPTIM MSP. +*@param : hlpuart: pointer to a LPTIM_HandleTypeDef structure that contains +* the configuration information for LPTIM module. +*@return: None +******************************************************************************/ +__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) +{ + UNUSED(hlptim); +} + +/****************************************************************************** +*@brief : DeInitialize the LPTIM MSP. +*@param : hlpuart: pointer to a LPTIM_HandleTypeDef structure that contains +* the configuration information for LPTIM module. +*@return: None +******************************************************************************/ +__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) +{ + UNUSED(hlptim); +} + +/****************************************************************************** +*@brief : Configure Count Value. +*@param : hlptim: LPTIM handle. +*@param : RepetitionCounter: Specifies the Repetition counter value. +* This parameter must be a value between 0x00 and 0xFF. +*@param : Period: Specifies the Autoreload value. +* This parameter must be a value between 0x0000 and 0xFFFF. +*@param : PulseOrTimeout: Specifies the compare value. +* This parameter must be a value between 0x0000 and 0xFFFF. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_ConfigCountValue(LPTIM_HandleTypeDef *hlptim, uint8_t RepetitionCounter, \ + uint16_t Period, uint16_t PulseOrTimeout) +{ + /* Check the LPTIM handle allocation */ + if ((hlptim == NULL) || (PulseOrTimeout >= Period)) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_REPETITION_COUNTER(RepetitionCounter)); + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(PulseOrTimeout)); + + hlptim->RepetitionCounter = RepetitionCounter; + hlptim->AutoReload = Period; + hlptim->Compare = PulseOrTimeout; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Enable interrupt. +*@param : hlptim: LPTIM handle. +*@param : IT: interrupt. +* This parameter can be a combination of @ref LPTIM_IT. +* @arg LPTIM_IT_REPOK: Repetition counter write complete interrupt. +* @arg LPTIM_IT_REPUE: Repetition counter update event interrupt +* @arg LPTIM_IT_ARROK: Autoreload write complete interrupt +* @arg LPTIM_IT_ARRM: Autoreload match interrupt +* @arg LPTIM_IT_CMPOK: Compare write complete interrupt +* @arg LPTIM_IT_CMPM: Compare match interrupt +* @arg LPTIM_IT_EXTTRIG:External trigger interrupt +* @arg LPTIM_IT_DOWN: "switch to down direction" interrupt +* @arg LPTIM_IT_UP: "switch to up direction" interrupt +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_EnableIT(LPTIM_HandleTypeDef *hlptim, uint32_t IT) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_IT(IT)); + + __HAL_LPTIM_ENABLE_IT(hlptim, IT); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Disable interrupt. +*@param : hlptim: LPTIM handle. +*@param : IT: interrupt. +* This parameter can be a combination of @ref LPTIM_IT. +* @arg LPTIM_IT_REPOK: Repetition counter write complete interrupt. +* @arg LPTIM_IT_REPUE: Repetition counter update event interrupt +* @arg LPTIM_IT_ARROK: Autoreload write complete interrupt +* @arg LPTIM_IT_ARRM: Autoreload match interrupt +* @arg LPTIM_IT_CMPOK: Compare write complete interrupt +* @arg LPTIM_IT_CMPM: Compare match interrupt +* @arg LPTIM_IT_EXTTRIG:External trigger interrupt +* @arg LPTIM_IT_DOWN: "switch to down direction" interrupt +* @arg LPTIM_IT_UP: "switch to up direction" interrupt +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_DisableIT(LPTIM_HandleTypeDef *hlptim, uint32_t IT) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_IT(IT)); + + __HAL_LPTIM_DISABLE_IT(hlptim, IT); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the LPTIM PWM generation. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_REPETITION_COUNTER(hlptim->RepetitionCounter)); + assert_param(IS_LPTIM_PERIOD(hlptim->AutoReload)); + assert_param(IS_LPTIM_PULSE(hlptim->Compare)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR1 &= ~LPTIM_CFGR1_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the LPTIM PWM generation. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the LPTIM One pulse generation. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_REPETITION_COUNTER(hlptim->RepetitionCounter)); + assert_param(IS_LPTIM_PERIOD(hlptim->AutoReload)); + assert_param(IS_LPTIM_PULSE(hlptim->Compare)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR1 &= ~LPTIM_CFGR1_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the LPTIM One pulse generation. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the LPTIM in Set once mode. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_REPETITION_COUNTER(hlptim->RepetitionCounter)); + assert_param(IS_LPTIM_PERIOD(hlptim->AutoReload)); + assert_param(IS_LPTIM_PULSE(hlptim->Compare)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR1 |= LPTIM_CFGR1_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the LPTIM Set once mode. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the Encoder interface. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t temp; + + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(hlptim->AutoReload)); + assert_param(hlptim->Init.ClockSource != LPTIM_CLOCKSOURCE_EXTERNAL_INPUT1); + assert_param(hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL); + assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Init.Input2Source)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Get the LPTIMx CFGR2 value */ + temp = hlptim->Instance->CFGR2; + + /* Clear CKPOL bits */ + temp &= (uint32_t)(~LPTIM_CFGR2_IN2SEL_Msk); + + /* Set Input polarity */ + temp |= hlptim->Init.Input2Source; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR2 = temp; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR1 |= LPTIM_CFGR1_ENC; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the Encoder interface. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR1 &= ~LPTIM_CFGR1_ENC; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the Timeout function. +* @note The first trigger event will start the timer, any successive +* trigger event will reset the counter and the timer restarts. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Timeout_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(hlptim->AutoReload)); + assert_param(IS_LPTIM_PULSE(hlptim->Compare)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR1 |= LPTIM_CFGR1_TIMEOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the Timeout function. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Timeout_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR1 &= ~LPTIM_CFGR1_TIMEOUT; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Start the Counter mode. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(hlptim->AutoReload)); + assert_param(IS_LPTIM_PULSE(hlptim->Compare)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the Counter mode. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Disable LPTIM */ + if (HAL_LPTIM_Disable(hlptim) != HAL_OK) + return HAL_ERROR; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +*@brief : Register a User LPTIM callback to be used instead of the weak predefined callback +*@param : hlptim: LPTIM handle. +*@param : CallbackID: ID of the callback to be registered +* This parameter can be a combination of @ref LPTIM_CallbackID. +* @arg @ref LPTIM_CALLBACKID_COMPARE_MATCH : Compare match Callback ID +* @arg @ref LPTIM_CALLBACKID_AUTORELOAD_MATCH : Auto-reload match Callback ID +* @arg @ref LPTIM_CALLBACKID_TRIGGER : External trigger event detection Callback ID +* @arg @ref LPTIM_CALLBACKID_COMPARE_WRITE : Compare register write complete Callback ID +* @arg @ref LPTIM_CALLBACKID_AUTORELOAD_WRITE : Auto-reload register write complete Callback ID +* @arg @ref LPTIM_CALLBACKID_DIRECTION_UP : Up-counting direction change Callback ID +* @arg @ref LPTIM_CALLBACKID_DIRECTION_DOWN : Down-counting direction change Callback ID +* @arg @ref LPTIM_CALLBACKID_REPETITION_UPDATE : Repetition counter update event Callback ID +* @arg @ref LPTIM_CALLBACKID_REPETITION_WRITE : Repetition counter write complete Callback ID +*@param : pCallback pointer to the callback function +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + uint32_t CallbackID, + pLPTIM_CallbackTypeDef pCallback) +{ + if ((hlptim == NULL) || (pCallback == NULL)) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + switch (CallbackID) + { + case LPTIM_CALLBACKID_COMPARE_MATCH : + + hlptim->CompareMatchCallback = pCallback; + break; + + case LPTIM_CALLBACKID_AUTORELOAD_MATCH : + + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case LPTIM_CALLBACKID_TRIGGER : + + hlptim->TriggerCallback = pCallback; + break; + + case LPTIM_CALLBACKID_COMPARE_WRITE : + + hlptim->CompareWriteCallback = pCallback; + break; + + case LPTIM_CALLBACKID_AUTORELOAD_WRITE : + + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case LPTIM_CALLBACKID_DIRECTION_UP : + + hlptim->DirectionUpCallback = pCallback; + break; + + case LPTIM_CALLBACKID_DIRECTION_DOWN : + + hlptim->DirectionDownCallback = pCallback; + break; + + case LPTIM_CALLBACKID_REPETITION_UPDATE : + + hlptim->RepetitionUpdateCallback = pCallback; + break; + + case LPTIM_CALLBACKID_REPETITION_WRITE : + + hlptim->RepetitionWriteCallback = pCallback; + break; + + default : + + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Unregister a LPTIM callback +*@param : hlptim: LPTIM handle. +*@param : CallbackID: ID of the callback to be registered +* This parameter can be a combination of @ref LPTIM_CallbackID. +* @arg @ref LPTIM_CALLBACKID_COMPARE_MATCH : Compare match Callback ID +* @arg @ref LPTIM_CALLBACKID_AUTORELOAD_MATCH : Auto-reload match Callback ID +* @arg @ref LPTIM_CALLBACKID_TRIGGER : External trigger event detection Callback ID +* @arg @ref LPTIM_CALLBACKID_COMPARE_WRITE : Compare register write complete Callback ID +* @arg @ref LPTIM_CALLBACKID_AUTORELOAD_WRITE : Auto-reload register write complete Callback ID +* @arg @ref LPTIM_CALLBACKID_DIRECTION_UP : Up-counting direction change Callback ID +* @arg @ref LPTIM_CALLBACKID_DIRECTION_DOWN : Down-counting direction change Callback ID +* @arg @ref LPTIM_CALLBACKID_REPETITION_UPDATE : Repetition counter update event Callback ID +* @arg @ref LPTIM_CALLBACKID_REPETITION_WRITE : Repetition counter write complete Callback ID +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + uint32_t CallbackID) +{ + if (hlptim == NULL) + return HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + switch (CallbackID) + { + case LPTIM_CALLBACKID_COMPARE_MATCH : + + hlptim->CompareMatchCallback = NULL; + break; + + case LPTIM_CALLBACKID_AUTORELOAD_MATCH : + + hlptim->AutoReloadMatchCallback = NULL; + break; + + case LPTIM_CALLBACKID_TRIGGER : + + hlptim->TriggerCallback = NULL; + break; + + case LPTIM_CALLBACKID_COMPARE_WRITE : + + hlptim->CompareWriteCallback = NULL; + break; + + case LPTIM_CALLBACKID_AUTORELOAD_WRITE : + + hlptim->AutoReloadWriteCallback = NULL; + break; + + case LPTIM_CALLBACKID_DIRECTION_UP : + + hlptim->DirectionUpCallback = NULL; + break; + + case LPTIM_CALLBACKID_DIRECTION_DOWN : + + hlptim->DirectionDownCallback = NULL; + break; + + case LPTIM_CALLBACKID_REPETITION_UPDATE : + + hlptim->RepetitionUpdateCallback = NULL; + break; + + case LPTIM_CALLBACKID_REPETITION_WRITE : + + hlptim->RepetitionWriteCallback = NULL; + break; + + default : + + return HAL_ERROR; + } + return HAL_OK; +} + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ + +/****************************************************************************** +*@brief : LPTimer Wait for flag set +*@param : hlptim: LPTIM handle. +*@param : flag: The lptim flag. +*@return: HAL status +******************************************************************************/ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + uint32_t count = 120000000U; + + while (count--) + { + if (__HAL_LPTIM_GET_FLAG(hlptim, flag)) + return HAL_OK; + } + + return HAL_TIMEOUT; +} + +/****************************************************************************** +*@brief : Disable LPTIM HW instance. +*@param : hlptim: LPTIM handle. +*@return: HAL status +******************************************************************************/ +static HAL_StatusTypeDef HAL_LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpclksource = 0; + uint32_t tmpIER; + uint32_t tmpCFGR1; + uint32_t tmpCFGR2; + +// __disable_irq(); + + /* Save LPTIM source clock */ + { + if (hlptim->Instance == LPTIM1) + { + if (HAL_RCC_GetLPTIM1ClockSource(&tmpclksource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM2) + { + if (HAL_RCC_GetLPTIM2ClockSource(&tmpclksource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM6) + { + if (HAL_RCC_GetLPTIM6ClockSource(&tmpclksource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM3) + { + if (HAL_RCC_GetLPTIM3ClockSource(&tmpclksource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM4) + { + if (HAL_RCC_GetLPTIM4ClockSource(&tmpclksource) != HAL_OK) + return HAL_ERROR; + } + else if(hlptim->Instance == LPTIM5) + { + if (HAL_RCC_GetLPTIM5ClockSource(&tmpclksource) != HAL_OK) + return HAL_ERROR; + } + else + { + return HAL_ERROR; + } + } + + + /* Save LPTIM configuration registers */ + tmpIER = hlptim->Instance->IER; + tmpCFGR1 = hlptim->Instance->CFGR1; + tmpCFGR2 = hlptim->Instance->CFGR2; + + /*********** Reset LPTIM ***********/ + /* LPTIM Reset */ + { + if (hlptim->Instance == LPTIM1) + { + __HAL_RCC_LPTIM1_RESET(); + } + else if(hlptim->Instance == LPTIM2) + { + __HAL_RCC_LPTIM2_RESET(); + } + else if(hlptim->Instance == LPTIM3) + { + __HAL_RCC_LPTIM3_RESET(); + } + else if(hlptim->Instance == LPTIM4) + { + __HAL_RCC_LPTIM4_RESET(); + } + else if(hlptim->Instance == LPTIM5) + { + __HAL_RCC_LPTIM5_RESET(); + } + else if(hlptim->Instance == LPTIM6) + { + __HAL_RCC_LPTIM6_RESET(); + } + } + /*********** Restore LPTIM Config ***********/ + + if ((hlptim->RepetitionCounter != 0UL) || (hlptim->AutoReload != 1UL) || (hlptim->Compare != 0U)) + { + /* Force LPTIM source kernel clock from PCLK */ + if (hlptim->Instance == LPTIM1) + { + HAL_RCC_LPTIM1ClockSourceConfig(LPTIM_CLOCKSOURCE_INTERNAL_PCLK); + } + else if(hlptim->Instance == LPTIM2) + { + HAL_RCC_LPTIM2ClockSourceConfig(LPTIM_CLOCKSOURCE_INTERNAL_PCLK); + } + else if(hlptim->Instance == LPTIM3) + { + HAL_RCC_LPTIM3ClockSourceConfig(LPTIM_CLOCKSOURCE_INTERNAL_PCLK); + } + else if(hlptim->Instance == LPTIM4) + { + HAL_RCC_LPTIM4ClockSourceConfig(LPTIM_CLOCKSOURCE_INTERNAL_PCLK); + } + else if(hlptim->Instance == LPTIM5) + { + HAL_RCC_LPTIM5ClockSourceConfig(LPTIM_CLOCKSOURCE_INTERNAL_PCLK); + } + else if(hlptim->Instance == LPTIM6) + { + HAL_RCC_LPTIM6ClockSourceConfig(LPTIM_CLOCKSOURCE_INTERNAL_PCLK); + } + + + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + + if (hlptim->RepetitionCounter != 0UL) + { + hlptim->Instance->RCR = hlptim->RepetitionCounter; + + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) != HAL_OK) + return HAL_TIMEOUT; + + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + } + + if (hlptim->AutoReload != 0UL) + { + hlptim->Instance->ARR = hlptim->AutoReload; + + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) != HAL_OK) + return HAL_TIMEOUT; + + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + } + + if (hlptim->Compare != 0UL) + { + hlptim->Instance->CMP = hlptim->Compare; + + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) != HAL_OK) + return HAL_TIMEOUT; + + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + } + + hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + + /* Restore LPTIM source kernel clock */ + if (hlptim->Instance == LPTIM1) + { + HAL_RCC_LPTIM1ClockSourceConfig(tmpclksource); + } + else if(hlptim->Instance == LPTIM2) + { + HAL_RCC_LPTIM2ClockSourceConfig(tmpclksource); + } + else if(hlptim->Instance == LPTIM3) + { + HAL_RCC_LPTIM5ClockSourceConfig(tmpclksource); + } + else if(hlptim->Instance == LPTIM4) + { + HAL_RCC_LPTIM4ClockSourceConfig(tmpclksource); + } + else if(hlptim->Instance == LPTIM5) + { + HAL_RCC_LPTIM5ClockSourceConfig(tmpclksource); + } + else if(hlptim->Instance == LPTIM6) + { + HAL_RCC_LPTIM6ClockSourceConfig(tmpclksource); + } + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + hlptim->Instance->CFGR2 = tmpCFGR2; + hlptim->Instance->CFGR1 = tmpCFGR1; + hlptim->Instance->IER = tmpIER; + +// __enable_irq(); + + return HAL_OK; +} + +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT AISINOCHIP *****END OF FILE****/ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_lpuart.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_lpuart.c new file mode 100644 index 0000000000000000000000000000000000000000..f51b72daac4ccd9bfc5c4f993a6fbe45ef40f50a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_lpuart.c @@ -0,0 +1,1392 @@ + +/****************************************************************************** +*@file : hal_lpuart.c +*@brief : LPUART HAL module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_LPUART_MODULE_ENABLED + +static void HAL_LPUART_InitParamter(LPUART_HandleTypeDef *hlpuart); + +/****************************************************************************** +*@brief : This function handles LPUART interrupt request. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None +******************************************************************************/ +void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart) +{ + uint32_t Flag; + uint32_t ITSource; + uint32_t RxError; + uint32_t Wakeup; + + /* Check for errors */ + Flag = __HAL_LPUART_GET_FLAG(hlpuart, LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | \ + LPUART_FLAG_PEIF | LPUART_FLAG_RXIF | \ + LPUART_FLAG_TCIF | LPUART_FLAG_TXEIF | \ + LPUART_FLAG_STARTIF | LPUART_FLAG_MATCHIF | \ + LPUART_FLAG_IDLEIF | LPUART_FLAG_BCNTIF); + + ITSource = __HAL_LPUART_GET_IT_SOURCE(hlpuart, LPUART_IT_RXOV | LPUART_IT_FE | \ + LPUART_IT_PE | LPUART_IT_RX | \ + LPUART_IT_TC | LPUART_IT_TXE | \ + LPUART_IT_START | LPUART_IT_MATCH |\ + LPUART_IT_IDLE | LPUART_IT_BCNT); + + if ((Flag & (LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | LPUART_FLAG_PEIF)) == 0U) + { + /* No error occurred */ + + /* Receive completion interrupt */ + if ((Flag & LPUART_FLAG_RXIF) && (ITSource & LPUART_IT_RX)) + { + /* Clear the receive completion interrupt flag */ + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_RXIF); + + /* Receive completion (RXIF) callback function */ + HAL_LPUART_RxCompleteCallback(hlpuart); + } + } + else + { + hlpuart->RxError = 0; + + /* some errors occurred */ + + /* Over-Run interrupt occurred */ + if ((Flag & LPUART_FLAG_RXOVIF) && (ITSource & LPUART_IT_RXOV)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_RXOVIF); + hlpuart->RxError |= LPUART_FLAG_RXOVIF; + } + + /* frame error interrupt occurred */ + if ((Flag & LPUART_FLAG_FEIF) && (ITSource & LPUART_IT_FE)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_FEIF); + hlpuart->RxError |= LPUART_FLAG_FEIF; + } + + /* parity error interrupt occurred */ + if ((Flag & LPUART_FLAG_PEIF) && (ITSource & LPUART_IT_PE)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_PEIF); + hlpuart->RxError |= LPUART_FLAG_PEIF; + } + + if (Flag & (LPUART_FLAG_FEIF | LPUART_FLAG_PEIF)) + { + /* receive completion interrupt */ + if (ITSource & LPUART_IT_RX) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_RXIF); + + /* receive complete (RXIF) callback function */ + HAL_LPUART_RxCompleteCallback(hlpuart); + } + } + else + { + /* Receive completion (RXIF) interrupt */ + if ((Flag & LPUART_FLAG_RXIF) && (ITSource & LPUART_IT_RX)) + { + /* Clear the receive completion interrupt flag */ + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_RXIF); + + /* Receive completion (RXIF) callback function */ + HAL_LPUART_RxCompleteCallback(hlpuart); + } + } + + if (hlpuart->RxError) + { + /* Error callback function */ + if (hlpuart->RxErrorCallback) + { + hlpuart->RxErrorCallback(hlpuart); + } + } + } + + /* transmit buffer empty interrupt */ + if ((Flag & LPUART_FLAG_TXEIF) && (ITSource & LPUART_IT_TXE)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_TXEIF); + + /* transmit empty (TXEIF) callback function */ + HAL_LPUART_TxEmptyCallback(hlpuart); + } + + /* transmit complete interrupt */ + if ((Flag & LPUART_FLAG_TCIF) && (ITSource & LPUART_IT_TC)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_TCIF); + + /* transmit complete (TCIF) callback function */ + HAL_LPUART_TxCompleteCallback(hlpuart); + } + + /* Bit counting interrupt */ + if ((Flag & LPUART_FLAG_BCNTIF) && (ITSource & LPUART_IT_BCNT)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_BCNTIF); + + /* Bit counting callback function */ + HAL_LPUART_BcntCallback(hlpuart); + } + + /* Idle interrupt */ + if ((Flag & LPUART_FLAG_IDLEIF) && (ITSource & LPUART_IT_IDLE)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_IDLEIF); + + /* Idle callback function */ + HAL_LPUART_IdleCallback(hlpuart); + } + + /* wakeup from Stop mode interrupt occurred */ + Wakeup = 0U; + if ((Flag & LPUART_FLAG_STARTIF) && (ITSource & LPUART_IT_START)) + { + /* Start bit wakeup */ + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_STARTIF); + Wakeup = 1U; + } + + if ((Flag & LPUART_FLAG_MATCHIF) && (ITSource & LPUART_IT_MATCH)) + { + /* address matching wakeup */ + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_MATCHIF); + Wakeup = 1U; + } + + /* wakeup callback function */ + if (Wakeup) + { + HAL_LPUART_WakeupCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Initialize the LPUART according to the specified. +* parameters in the LPUART_InitTypeDef and create the associated handle. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(IS_LPUART_WORDLENGTH(hlpuart->Init.WordLength)); + assert_param(IS_LPUART_STOPBITS(hlpuart->Init.StopBits)); + assert_param(IS_LPUART_PARITY(hlpuart->Init.Parity)); + assert_param(IS_LPUART_MODE(hlpuart->Init.Mode)); + assert_param(IS_LPUART_WAKEUPMODE(hlpuart->Init.WakeupMode)); + assert_param(IS_LPUART_CLOCKSOURCE(hlpuart->Init.ClockSource)); + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_LPUART_MspInit(hlpuart); + + /* Init the internal parameter */ + HAL_LPUART_InitParamter(hlpuart); + + /* set the clock source */ + if (HAL_RCC_LPUART1ClockSourceConfig(hlpuart->Init.ClockSource) != HAL_OK) + return HAL_ERROR; + + /* Set baud rate */ + HAL_LPUART_SetBaudRate(hlpuart, hlpuart->Init.BaudRate); + + /* Set the communication parameters */ + hlpuart->Instance->LCR = hlpuart->Init.WordLength | \ + hlpuart->Init.StopBits | \ + hlpuart->Init.Parity | \ + hlpuart->Init.WakeupMode; + + /* Set the address matching for wakeup */ + if ((hlpuart->Init.WakeupMode == LPUART_WAKEUPMODE_ADDRNOCHECK) || \ + (hlpuart->Init.WakeupMode == LPUART_WAKEUPMODE_ADDRCHECK)) + { + /* Check the parameters */ + assert_param(IS_LPUART_WAKEUPADDR(hlpuart->Init.WakeupAddr)); + + hlpuart->Instance->ADDR = hlpuart->Init.WakeupAddr; + } + + /* enable tx rx */ + hlpuart->Instance->CR = hlpuart->Init.Mode; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DeInitialize the LPUART peripheral. +* Before Deinitialization, the sending or receiving process needs to be aborted. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + + /* Disable tx */ + __HAL_LPUART_DISABLE_TX(hlpuart); + + /* Disable rx */ + __HAL_LPUART_DISABLE_RX(hlpuart); + + /* DeInit the low level hardware */ + HAL_LPUART_MspDeInit(hlpuart); + + /* Init the internal parameter */ + HAL_LPUART_InitParamter(hlpuart); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the LPUART MSP. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None +******************************************************************************/ +__weak void HAL_LPUART_MspInit(LPUART_HandleTypeDef *hlpuart) +{ + UNUSED(hlpuart); +} + +/****************************************************************************** +*@brief : DeInitialize the LPUART MSP. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None +******************************************************************************/ +__weak void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart) +{ + UNUSED(hlpuart); +} + +/****************************************************************************** +*@brief : set baud rate. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : baudRate: This member configures the UART communication baud rate +* The integer value of LPUART clock frequency divided by +* baud rate is 2-254. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_SetBaudRate(LPUART_HandleTypeDef *hlpuart, uint32_t baudRate) +{ + uint32_t temp; + float tempFloat; + uint32_t bits; + uint32_t ClockNum; + uint32_t iBaudRate; + + const uint16_t fBaudRate[4][13] = + { +// 0 1 2 3 4 5 6 7 8 9 10 11 12 + {0x0000, 0x0010, 0x0044, 0x0092, 0x00AA, 0x0155, 0x01B6, 0x01DD, 0x01EF, 0x01FF, 0x0000, 0x0000, 0x0000},//start+7bit+end + {0x0000, 0x0020, 0x0084, 0x0124, 0x014A, 0x02AA, 0x02B5, 0x036D, 0x03DE, 0x03DF, 0x03FF, 0x0000, 0x0000}, + {0x0000, 0x0020, 0x0088, 0x0124, 0x0252, 0x02AA, 0x0355, 0x0575, 0x0776, 0x0777, 0x07DF, 0x07FF, 0x0000}, + {0x0000, 0x0040, 0x0108, 0x0248, 0x02A4, 0x0554, 0x0AAA, 0x0AEA, 0x0DB6, 0x0EEE, 0x0F7B, 0x0FDF, 0x0FFF},//start+8bit+pol+2end + }; + + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + + /* Calculate the baud rate division factor */ + tempFloat = (float)HAL_RCC_GetLPUART1ClockFreq();//(float)HAL_RCC_GetLPUART1CLKFreq(); + + tempFloat = tempFloat / hlpuart->Init.BaudRate; + iBaudRate = (uint32_t)tempFloat; + tempFloat = tempFloat - iBaudRate; + iBaudRate--; + assert_param(IS_LPUART_BAUDRATE(iBaudRate)); + + bits = 10; + if (hlpuart->Init.WordLength != LPUART_WORDLENGTH_8B) + bits--; + if (hlpuart->Init.Parity != LPUART_PARITY_NONE) + bits++; + if (hlpuart->Init.StopBits != LPUART_STOPBITS_1B) + bits++; + + tempFloat = tempFloat * bits; + ClockNum = (uint32_t)tempFloat; + tempFloat = tempFloat - ClockNum; + if (tempFloat >= 0.5) + ClockNum++; + + hlpuart->Instance->IBAUD = iBaudRate + ((iBaudRate >> 1) << LPUART_IBAUD_RXSAM_Pos); + hlpuart->Instance->FBAUD = fBaudRate[bits - 9][ClockNum]; + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Register a User LPUART Callback. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : id: ID of the callback to be registered +* This parameter can be a combination of @ref LPUART_CallbackID. +* @arg LPUART_CALLBACKID_TXCPLT : transfer completion callback function. +* @arg LPUART_CALLBACKID_TXHALFCPLT : transfer half completion callback function. +* @arg LPUART_CALLBACKID_TXERROR : transfer error callback function. +* @arg LPUART_CALLBACKID_RXCPLT : receive completion callback function. +* @arg LPUART_CALLBACKID_RXHALFCPLT : receive half completion callback function. +* @arg LPUART_CALLBACKID_RXERROR : receive error callback function. +* @arg LPUART_CALLBACKID_WAKEUP : wakeup callback function. +* @arg LPUART_CALLBACKID_BCNT : bit count callback function. +* @arg LPUART_CALLBACKID_IDLE : idle callback function. +*@param : pCallback: pointer to the Callback function. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_RegisterCallback(LPUART_HandleTypeDef *hlpuart, uint32_t id, pLPUART_CallbackTypeDef pCallback) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(IS_LPUART_CALLBACKID(id)); + + switch (id) + { + case LPUART_CALLBACKID_TXCPLT: + + hlpuart->TxCpltCallback = pCallback; + break; + + case LPUART_CALLBACKID_TXHALFCPLT: + + hlpuart->TxHalfCpltCallback = pCallback; + break; + + case LPUART_CALLBACKID_TXERROR: + + hlpuart->TxErrorCallback = pCallback; + break; + + case LPUART_CALLBACKID_RXCPLT: + + hlpuart->RxCpltCallback = pCallback; + break; + + case LPUART_CALLBACKID_RXHALFCPLT: + + hlpuart->RxHalfCpltCallback = pCallback; + break; + + case LPUART_CALLBACKID_RXERROR: + + hlpuart->RxErrorCallback = pCallback; + break; + + case LPUART_CALLBACKID_WAKEUP: + + hlpuart->WakeupCallback = pCallback; + break; + case LPUART_CALLBACKID_BCNT: + + hlpuart->BcntCallback = pCallback; + break; + case LPUART_CALLBACKID_IDLE: + + hlpuart->IdleCallback = pCallback; + break; + + default: + return HAL_ERROR; + } + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Unregister a User LPUART Callback. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : id: ID of the callback to be registered +* This parameter can be a combination of @ref LPUART_CallbackID. +* @arg LPUART_CALLBACKID_TXCPLT : transfer completion callback function. +* @arg LPUART_CALLBACKID_TXHALFCPLT : transfer half completion callback function. +* @arg LPUART_CALLBACKID_TXERROR : transfer error callback function. +* @arg LPUART_CALLBACKID_RXCPLT : receive completion callback function. +* @arg LPUART_CALLBACKID_RXHALFCPLT : receive half completion callback function. +* @arg LPUART_CALLBACKID_RXERROR : receive error callback function. +* @arg LPUART_CALLBACKID_WAKEUP : wakeup callback function. +* @arg LPUART_CALLBACKID_BCNT : bit count callback function. +* @arg LPUART_CALLBACKID_IDLE : idle callback function. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_UnRegisterCallback(LPUART_HandleTypeDef *hlpuart, uint32_t id) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(IS_LPUART_CALLBACKID(id)); + + switch (id) + { + case LPUART_CALLBACKID_TXCPLT: + + hlpuart->TxCpltCallback = NULL; + break; + + case LPUART_CALLBACKID_TXHALFCPLT: + + hlpuart->TxHalfCpltCallback = NULL; + break; + + case LPUART_CALLBACKID_TXERROR: + + hlpuart->TxErrorCallback = NULL; + break; + + case LPUART_CALLBACKID_RXCPLT: + + hlpuart->RxCpltCallback = NULL; + break; + + case LPUART_CALLBACKID_RXHALFCPLT: + + hlpuart->RxHalfCpltCallback = NULL; + break; + + case LPUART_CALLBACKID_RXERROR: + + hlpuart->RxErrorCallback = NULL; + break; + + case LPUART_CALLBACKID_WAKEUP: + + hlpuart->WakeupCallback = NULL; + break; + case LPUART_CALLBACKID_BCNT: + + hlpuart->BcntCallback = NULL; + break; + case LPUART_CALLBACKID_IDLE: + + hlpuart->IdleCallback = NULL; + break; + default: + return HAL_ERROR; + } + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send an amount of data in blocking mode. +*@note In blocking mode, the user cannot enable interrupt. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be sent. +*@param : timeout: Timeout duration. +* The minimum value of this parameter is 1. +* If the value of this parameter is 0xFFFFFFFF, it will be sent until all data are sent. +* @node The timeout should be greater than the time of all data transfers. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Transmit(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size, uint32_t timeout) +{ + uint32_t startTick; + + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + assert_param(timeout != 0U); + + /* If LPUART is sending, an error is returned */ + if (hlpuart->TxState != LPUART_STATE_READY) + return HAL_ERROR; + + /* Blocking transmission can be aborted. Clear the abort flag bit */ + hlpuart->TxAbort = DISABLE; + + /* tx state: busy */ + hlpuart->TxState = LPUART_STATE_BUSY; + + hlpuart->pTxBuf = pdata; + hlpuart->TxCount = size; + + startTick = HAL_GetTick(); + while (1) + { + if (hlpuart->TxCount) + { + /* Whether tx buffer is empty */ + if (__HAL_LPUART_GET_FLAG(hlpuart, LPUART_FLAG_TXE)) + { + /* send byte */ + hlpuart->Instance->TXDR = *pdata++; + hlpuart->TxCount--; + } + } + else + { + /* Whether sending has ended */ + if (__HAL_LPUART_GET_FLAG(hlpuart, LPUART_FLAG_TCIF)) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_TCIF); + + hlpuart->TxState = LPUART_STATE_READY; + return HAL_OK; + } + } + + /* Whether sending is aborted */ + if (hlpuart->TxAbort != DISABLE) + { + if (hlpuart->Instance->CR & LPUART_CR_TX_EN) + { + __HAL_LPUART_DISABLE_TX(hlpuart); + __HAL_LPUART_ENABLE_TX(hlpuart); + } + hlpuart->TxState = LPUART_STATE_READY; + return (HAL_ERROR); + } + + /* Whether the sending time has expired */ + if (timeout != 0xFFFFFFFF) + { + if ((HAL_GetTick() - startTick) >= timeout) + { + if (hlpuart->Instance->CR & LPUART_CR_TX_EN) + { + __HAL_LPUART_DISABLE_TX(hlpuart); + __HAL_LPUART_ENABLE_TX(hlpuart); + } + hlpuart->TxState = LPUART_STATE_READY; + return (HAL_TIMEOUT); + } + } + } +} + +/****************************************************************************** +*@brief : Receive an amount of data in blocking mode. +*@note In blocking mode, the user cannot enable interrupt. +*@note Users can add or ignore error handling in RxErrorCallback(). +* Error codes are stored in hlpuart->RxError. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@param : timeout: Timeout duration. +* If the value of this parameter is 0, the received data will be detected only once and will not wait. +* If the value of this parameter is 0xFFFFFFFF, it will be received until all data are received. +* @node The timeout should be greater than the time of all data transfers. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Receive(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size, uint32_t timeout) +{ + uint32_t startTick; + + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If LPUART is receiving, an error is returned */ + if (hlpuart->RxState != LPUART_STATE_READY) + return HAL_ERROR; + + /* Blocking reception can be aborted. Clear the abort flag bit */ + hlpuart->RxAbort = DISABLE; + + /* rx state: busy */ + hlpuart->RxState = LPUART_STATE_BUSY; + + hlpuart->pRxBuf = pdata; + hlpuart->RxCount = size; + + startTick = HAL_GetTick(); + while (1) + { + /* Whether there are errors */ + hlpuart->RxError = __HAL_LPUART_GET_FLAG(hlpuart, LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | LPUART_FLAG_PEIF); + if (hlpuart->RxError) + { + __HAL_LPUART_CLEAR_FLAG(hlpuart, hlpuart->RxError & (LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | LPUART_FLAG_PEIF)); + if (hlpuart->RxErrorCallback) + { + hlpuart->RxErrorCallback(hlpuart); + } + } + + /* Whether reception is completed */ + if (__HAL_LPUART_GET_FLAG(hlpuart, LPUART_FLAG_RXF)) + { + /* receive data */ + *pdata++ = hlpuart->Instance->RXDR; + hlpuart->RxCount--; + + /* receive complete */ + if (hlpuart->RxCount == 0) + { + hlpuart->RxState = LPUART_STATE_READY; + return HAL_OK; + } + } + + /* Whether reception is aborted */ + if (hlpuart->RxAbort != DISABLE) + { + hlpuart->RxState = LPUART_STATE_READY; + return (HAL_ERROR); + } + + if (timeout != 0xFFFFFFFF) + { + /* Whether the receiving time has expired */ + if ((HAL_GetTick() - startTick) >= timeout) + { + hlpuart->TxState = LPUART_STATE_READY; + return (HAL_TIMEOUT); + } + } + } +} +/****************************************************************************** +*@brief : Receive an amount of data to Idle line or BCNT time. +* +*@param : hlpuart: lpuart handle with LPUART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@param : rece_mode: by idle line, or by bit value count reached +*@param : timeout: BCNT value(relative to LPUART baudrate), when LPUART BaudRate = 115200, + then set timeout = 115200,it is approximately 1 second. MAX BCNT value can be 0xFFFF. +* Only used when 'rece_mode' = LPUART_RECEIVE_TOBCNT +* when 'rece_mode' = LPUART_RECEIVE_TOIDLE, it is meaningless. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Receive_To_IDLEorBCNT(LPUART_HandleTypeDef *hlpuart, uint8_t *buf, uint32_t size, + LPUART_Receive_Mode_Enum rece_mode, uint32_t timeout) +{ + + assert_param (IS_LPUART_INSTANCE(hlpuart->Instance)); + + if ((buf == NULL) || (size == 0U)) + { + return HAL_ERROR; + } + + hlpuart->RxCount = 0; + hlpuart->pRxBuf = buf; + + if(rece_mode == LPUART_RECEIVE_TOBCNT) + { + MODIFY_REG(hlpuart->Instance->LCR, LPUART_LCR_BCNT_VALUE, timeout<Instance->LCR, LPUART_LCR_AUTO_START_EN); + + } + + while (size--) + { + while(!(hlpuart->Instance->SR & LPUART_SR_RXF)) + { + if(rece_mode == RECEIVE_TOBCNT) + { + if(READ_BIT(hlpuart->Instance->SR, LPUART_SR_BCNTIF)) + { + CLEAR_BIT(hlpuart->Instance->LCR, LPUART_LCR_AUTO_START_EN); + CLEAR_STATUS(hlpuart->Instance->SR, LPUART_SR_BCNTIF); + return HAL_TIMEOUT; + } + } + else + { + if(READ_BIT(hlpuart->Instance->SR, LPUART_SR_IDLEIF)) + { + CLEAR_STATUS(hlpuart->Instance->SR, LPUART_SR_IDLEIF); + while(READ_BIT(hlpuart->Instance->SR, LPUART_SR_IDLEIF)) + { + CLEAR_STATUS(hlpuart->Instance->SR, 0); + CLEAR_STATUS(hlpuart->Instance->SR, LPUART_SR_IDLEIF); + } + return HAL_TIMEOUT; + } + } + } + + + hlpuart->pRxBuf[hlpuart->RxCount++] = (uint8_t)hlpuart->Instance->RXDR; + + } + + CLEAR_BIT(hlpuart->Instance->LCR, LPUART_LCR_AUTO_START_EN); + + return HAL_OK; +} +/****************************************************************************** +*@brief : Send an amount of data in interrupt mode. +*@note In interrupt mode, sending related interrupts (TXE/TC) is forced to enable. +*@note Users can add or ignore error handling in ErrorCallback(). +*@note The user can add the processing of sending completion in TxCpltCallback(). +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Transmit_IT(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If LPUART is sending, an error is returned */ + if (hlpuart->TxState != LPUART_STATE_READY) + return HAL_ERROR; + + /* tx state: busy */ + hlpuart->TxState = LPUART_STATE_BUSY_IT; + + hlpuart->pTxBuf = pdata; + hlpuart->TxCount = size; + + /* enable interrupt (TC) */ + __HAL_LPUART_ENABLE_IT(hlpuart, LPUART_IT_TXE); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in interrupt mode. +*@note In interrupt mode, receiving completion interrupt (RX) and error +* interrupt (RXOVFEPE) are forced enabled. +* If an error occurs in the reception, the reception stops automatically. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Receive_IT(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If LPUART is receiving, an error is returned */ + if (hlpuart->RxState != LPUART_STATE_READY) + return HAL_ERROR; + + /* rx state: busy */ + hlpuart->RxState = LPUART_STATE_BUSY_IT; + + hlpuart->pRxBuf = pdata; + hlpuart->RxCount = size; + hlpuart->RxError = 0; + + /* enable interrupt (RXPEFERXOV) */ + __HAL_LPUART_ENABLE_IT(hlpuart, LPUART_IT_RXOV | LPUART_IT_FE | LPUART_IT_PE | LPUART_IT_RX); + + return HAL_OK; +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Send an amount of data in DMA mode. +*@note In DMA mode, the transmission related interrupt (TC/TXE) is forced to disabled. +* the DMA transmission related interrupt (ITC/HFTC/IE) is forced to enabled. +* If an DMA transfer error occurs in the transmission, +* the transmission stops automatically. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Transmit_DMA(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If LPUART is sending, an error is returned */ + if (hlpuart->TxState != LPUART_STATE_READY) + return HAL_ERROR; + + /* tx state: busy */ + hlpuart->TxState = LPUART_STATE_BUSY_DMA; + + /* set dma callback function */ + hlpuart->hdmatx->XferCpltCallback = HAL_LPUART_DMATxCpltCallback; + hlpuart->hdmatx->XferErrorCallback = HAL_LPUART_DMATxErrorCallback; + if (hlpuart->TxHalfCpltCallback) + hlpuart->hdmatx->XferHalfCpltCallback = HAL_LPUART_DMATxHalfCpltCallback; + else + hlpuart->hdmatx->XferHalfCpltCallback = NULL; + + hlpuart->pTxBuf = pdata; + hlpuart->TxCount = size; + hlpuart->TxError = 0U; + + /* Start DMA interrupt transfer */ + if (HAL_DMA_Start_IT(hlpuart->hdmatx, (uint32_t)pdata, (uint32_t)&hlpuart->Instance->TXDR, size) != HAL_OK) + { + /* Set error code to DMA */ + hlpuart->TxError = LPUART_DMA_TX_ERROR; + hlpuart->TxState = LPUART_STATE_READY; + return HAL_ERROR; + } + + /* enable LPUART DMA */ + __HAL_LPUART_ENABLE_DMA(hlpuart); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in DMA mode. +*@note In DMA mode, receiving completion interrupt (RX) is forced disable. +* the error interrupt (RXOVFEPE) are forced enabled. +* the DMA transmission related interrupt (ITC/HFTC/IE) is forced to enabled. +* If an error occurs in the reception, the reception stops automatically. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@param : pdata: Pointer to data buffer. +*@param : size: Amount of data elements to be received. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_Receive_DMA(LPUART_HandleTypeDef *hlpuart, uint8_t *pdata, uint32_t size) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + assert_param(pdata != NULL); + assert_param(size != 0U); + + /* If LPUART is receiving, an error is returned */ + if (hlpuart->RxState != LPUART_STATE_READY) + return HAL_ERROR; + + /* rx state: busy */ + hlpuart->RxState = LPUART_STATE_BUSY_DMA; + + /* set dma callback function */ + hlpuart->hdmarx->XferCpltCallback = HAL_LPUART_DMARxCpltCallback; + if (hlpuart->RxHalfCpltCallback) + hlpuart->hdmarx->XferHalfCpltCallback = HAL_LPUART_DMARxHalfCpltCallback; + else + hlpuart->hdmarx->XferHalfCpltCallback = NULL; + hlpuart->hdmarx->XferErrorCallback = HAL_LPUART_DMARxErrorCallback; + + hlpuart->pRxBuf = pdata; + hlpuart->RxCount = size; + hlpuart->RxError = 0U; + + /* Start DMA interrupt transfer */ + if (HAL_DMA_Start_IT(hlpuart->hdmarx, (uint32_t)&hlpuart->Instance->RXDR, (uint32_t)pdata, size) != HAL_OK) + { + /* Set error code to DMA */ + hlpuart->RxError = LPUART_DMA_RX_ERROR; + hlpuart->RxState = LPUART_STATE_READY; + return HAL_ERROR; + } + + /* enable interrupt (PEFERXOV) */ + if (hlpuart->RxErrorCallback) + { + __HAL_LPUART_ENABLE_IT(hlpuart, LPUART_IT_RXOV | LPUART_IT_FE | LPUART_IT_PE); + } + + /* enable LPUART DMA */ + __HAL_LPUART_ENABLE_DMA(hlpuart); + + return HAL_OK; +} +#endif + +/****************************************************************************** +*@brief : Abort ongoing transmit transfer(block mode/interrupt mode/dma mode). +* In blocking mode, check TxState to exit the abort function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_AbortTransmit(LPUART_HandleTypeDef *hlpuart) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + + /* If LPUART is not sent, return directly */ + if (hlpuart->TxState == LPUART_STATE_READY) + return HAL_OK; + + if (hlpuart->TxState == LPUART_STATE_BUSY) + { + /* Abort ongoing transmit transfer(block mode) */ + + /* enable tx abort flag */ + hlpuart->TxAbort = ENABLE; + } + else if (hlpuart->TxState == LPUART_STATE_BUSY_IT) + { + /* Abort ongoing transmit transfer(interrupt mode) */ + + /* disable interrupt (TXE/TC) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_TXE | LPUART_IT_TC); + + if (hlpuart->Instance->CR & LPUART_CR_TX_EN) + { + __HAL_LPUART_DISABLE_TX(hlpuart); + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_TCIF); + __HAL_LPUART_ENABLE_TX(hlpuart); + } + + /* end of sending */ + hlpuart->TxState = LPUART_STATE_READY; + } +#ifdef HAL_DMA_MODULE_ENABLED + else if (hlpuart->TxState == LPUART_STATE_BUSY_DMA) + { + /* Abort ongoing transmit transfer(dma mode) */ + + /* abort dma transfer */ + HAL_DMA_Abort(hlpuart->hdmatx); + + /* Take the number of unsent data */ + hlpuart->TxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmatx); + + if (hlpuart->Instance->CR & LPUART_CR_TX_EN) + { + __HAL_LPUART_DISABLE_TX(hlpuart); + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_TCIF); + __HAL_LPUART_ENABLE_TX(hlpuart); + } + + /* end of sending */ + hlpuart->TxState = LPUART_STATE_READY; + } +#endif + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Abort ongoing reception transfer(block mode/interrupt mode/dma mode). +* In blocking mode, check TxState to exit the abort function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_LPUART_AbortReceive(LPUART_HandleTypeDef *hlpuart) +{ + /* Check the parameters */ + assert_param(IS_LPUART_HANDLE(hlpuart)); + assert_param(IS_LPUART_INSTANCE(hlpuart->Instance)); + + /* If LPUART is not receving, return directly */ + if (hlpuart->RxState == LPUART_STATE_READY) + return HAL_OK; + + if (hlpuart->RxState == LPUART_STATE_BUSY) + { + /* Abort ongoing transmit transfer(block mode) */ + + /* enable rx abort flag */ + hlpuart->RxAbort = ENABLE; + } + else if (hlpuart->RxState == LPUART_STATE_BUSY_IT) + { + /* Abort ongoing transmit transfer(interrupt mode) */ + + /* disable interrupt (RXOV/FE/PE/RX) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_RXOV | LPUART_IT_FE | \ + LPUART_IT_PE | LPUART_IT_RX); + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | \ + LPUART_FLAG_PEIF | LPUART_FLAG_RXIF); + + /* End of reception */ + hlpuart->RxState = LPUART_STATE_READY; + } +#ifdef HAL_DMA_MODULE_ENABLED + else if (hlpuart->RxState == LPUART_STATE_BUSY_DMA) + { + /* Abort ongoing transmit transfer(dma mode) */ + + /* disable interrupt (RXOV/FE/PE) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_RXOV | LPUART_IT_FE | LPUART_IT_PE); + + /* abort dma transfer */ + HAL_DMA_Abort(hlpuart->hdmarx); + + /* Take the number of unsent data */ + hlpuart->RxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmarx); + + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_RXOVIF | LPUART_FLAG_FEIF | \ + LPUART_FLAG_PEIF | LPUART_FLAG_RXIF); + + /* End of reception */ + hlpuart->RxState = LPUART_STATE_READY; + } +#endif + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Get sending status. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: sending status. +* The return value can be @ ref LPUART_State value +* @arg LPUART_STATE_READY: LPUART not sent. +* @arg LPUART_STATE_BUSY: LPUART sending(block mode). +* @arg LPUART_STATE_BUSY_IT: LPUART sending(interrupt mode). +* @arg LPUART_STATE_BUSY_DMA: LPUART sending(dma mode). +******************************************************************************/ +uint32_t HAL_LPUART_GetTxState(LPUART_HandleTypeDef *hlpuart) +{ + assert_param(IS_LPUART_HANDLE(hlpuart)); + return (hlpuart->TxState); +} + +/****************************************************************************** +*@brief : Get the receiving status. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: receiving status. +* The return value can be @ ref LPUART_State value +* @arg LPUART_STATE_READY: LPUART did not receive. +* @arg LPUART_STATE_BUSY: LPUART is receiving(block mode). +* @arg LPUART_STATE_BUSY_IT: LPUART is receiving(interrupt mode). +* @arg LPUART_STATE_BUSY_DMA: LPUART is receiving(dma mode). +******************************************************************************/ +uint32_t HAL_LPUART_GetRxState(LPUART_HandleTypeDef *hlpuart) +{ + assert_param(IS_LPUART_HANDLE(hlpuart)); + return (hlpuart->RxState); +} + +/****************************************************************************** +*@brief : bit counting callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_BcntCallback(LPUART_HandleTypeDef *hlpuart) +{ + if (hlpuart->BcntCallback) + { + hlpuart->BcntCallback(hlpuart); + } +} +/****************************************************************************** +*@brief : Idle callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_IdleCallback(LPUART_HandleTypeDef *hlpuart) +{ + if (hlpuart->IdleCallback) + { + hlpuart->IdleCallback(hlpuart); + } +} +/****************************************************************************** +*@brief : Tx buffer empty callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_TxEmptyCallback(LPUART_HandleTypeDef *hlpuart) +{ + if (hlpuart->TxCount) + { + /* Continue sending */ + hlpuart->Instance->TXDR = *hlpuart->pTxBuf++; + hlpuart->TxCount--; + } + else + { + /* disable interrupt (TXE) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_TXE); + + /* enable interrupt (TC) */ + __HAL_LPUART_ENABLE_IT(hlpuart, LPUART_IT_TC); + } +} + +/****************************************************************************** +*@brief : Tx transfer complete callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_TxCompleteCallback(LPUART_HandleTypeDef *hlpuart) +{ + /* disable interrupt (TC) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_TC); + + hlpuart->TxState = LPUART_STATE_READY; + + if (hlpuart->TxCpltCallback) + { + hlpuart->TxCpltCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Rx transfer complete callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_RxCompleteCallback(LPUART_HandleTypeDef *hlpuart) +{ + /* The received data is put into the buffer */ + *hlpuart->pRxBuf++ = hlpuart->Instance->RXDR; + hlpuart->RxCount--; + + if (hlpuart->RxCount == 0U) + { + /* Receiving completed */ + + /* disable interrupt (RX/RXOV/FE/PE) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_RX | LPUART_IT_RXOV | \ + LPUART_IT_FE | LPUART_IT_PE); + + /* receive complete */ + hlpuart->RxState = LPUART_STATE_READY; + + if (hlpuart->RxCpltCallback) + { + hlpuart->RxCpltCallback(hlpuart); + } + } +} + +/****************************************************************************** +*@brief : Wakeup callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_WakeupCallback(LPUART_HandleTypeDef *hlpuart) +{ + if (hlpuart->WakeupCallback) + { + hlpuart->WakeupCallback(hlpuart); + } +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Tx DMA transfer complete callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_DMATxCpltCallback(DMA_HandleTypeDef *hdma) +{ + LPUART_HandleTypeDef *hlpuart; + + hlpuart = hdma->Parent; + + /* clear flag (TCIF) */ + __HAL_LPUART_CLEAR_FLAG(hlpuart, LPUART_FLAG_TCIF); + + /* Take the number of unsent data */ + hlpuart->TxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmatx); + + /* tx DMA transfer complete */ + hlpuart->TxState = LPUART_STATE_READY; + + if (hlpuart->TxCpltCallback) + { + hlpuart->TxCpltCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Tx DMA half transfer complete callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_DMATxHalfCpltCallback(DMA_HandleTypeDef *hdma) +{ + LPUART_HandleTypeDef *hlpuart; + + hlpuart = hdma->Parent; + + /* Take the number of unsent data */ + hlpuart->TxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmatx); + + if (hlpuart->TxHalfCpltCallback) + { + hlpuart->TxHalfCpltCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Tx DMA transfer error callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_DMATxErrorCallback(DMA_HandleTypeDef *hdma) +{ + LPUART_HandleTypeDef *hlpuart; + + hlpuart = hdma->Parent; + + /* abort tx dma transfer */ + HAL_DMA_Abort(hdma); + + /* set the dma transfer error */ + hlpuart->TxError |= LPUART_DMA_TX_ERROR; + + /* Take the number of unsent data */ + hlpuart->TxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmatx); + + /* end of sending */ + hlpuart->TxState = LPUART_STATE_READY; + + if (hlpuart->TxErrorCallback) + { + hlpuart->TxErrorCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Rx DMA transfer complete callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_DMARxCpltCallback(DMA_HandleTypeDef *hdma) +{ + LPUART_HandleTypeDef *hlpuart; + + hlpuart = hdma->Parent; + + /* if no error occurs in reception, disable interrupt (RXOV/FE/PE) */ + __HAL_LPUART_DISABLE_IT(hlpuart, LPUART_IT_RXOV | LPUART_IT_FE | LPUART_IT_PE); + + /* Take the number of data not received */ + hlpuart->RxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmarx); + + /* End of reception */ + hlpuart->RxState = LPUART_STATE_READY; + + if (hlpuart->RxCpltCallback) + { + hlpuart->RxCpltCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Rx DMA hlaf transfer complete callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_DMARxHalfCpltCallback(DMA_HandleTypeDef *hdma) +{ + LPUART_HandleTypeDef *hlpuart; + + hlpuart = hdma->Parent; + + /* Take the number of data not received */ + hlpuart->RxCount = __HAL_DMA_GET_TRANSFER_SIZE(hlpuart->hdmarx); + + if (hlpuart->RxHalfCpltCallback) + { + hlpuart->RxHalfCpltCallback(hlpuart); + } +} + +/****************************************************************************** +*@brief : Rx DMA transfer error callback function. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +__weak void HAL_LPUART_DMARxErrorCallback(DMA_HandleTypeDef *hdma) +{ + LPUART_HandleTypeDef *hlpuart; + + hlpuart = hdma->Parent; + + /* abort rx dma transfer */ + HAL_DMA_Abort(hdma); + + /* set the dma transfer error */ + hlpuart->RxError = LPUART_DMA_RX_ERROR; + + /* End of reception */ + hlpuart->RxState = LPUART_STATE_READY; + + if (hlpuart->RxErrorCallback) + { + hlpuart->RxErrorCallback(hlpuart); + } +} +#endif + +/****************************************************************************** +*@brief : Init the internal parameter. +*@param : hlpuart: pointer to a LPUART_HandleTypeDef structure that contains +* the configuration information for LPUART module. +*@return: None. +******************************************************************************/ +static void HAL_LPUART_InitParamter(LPUART_HandleTypeDef *hlpuart) +{ + hlpuart->TxState = 0U; + hlpuart->TxError = 0U; + hlpuart->pTxBuf = 0U; + hlpuart->TxCount = 0U; + hlpuart->TxAbort = 0U; + + hlpuart->RxState = 0U; + hlpuart->RxError = 0U; + hlpuart->pRxBuf = 0U; + hlpuart->RxCount = 0U; + hlpuart->RxAbort = 0U; + + hlpuart->TxCpltCallback = NULL; + hlpuart->TxHalfCpltCallback = NULL; + hlpuart->TxErrorCallback = NULL; + hlpuart->RxCpltCallback = NULL; + hlpuart->RxHalfCpltCallback = NULL; + hlpuart->RxErrorCallback = NULL; + hlpuart->WakeupCallback = NULL; +} + +#endif /* HAL_LPUART_MODULE_ENABLED */ + +/************************ (C) COPYRIGHT AISINOCHIP *****END OF FILE****/ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_ltdc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_ltdc.c new file mode 100644 index 0000000000000000000000000000000000000000..78b530d16a85d9d74a37006371515a274ab2677b --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_ltdc.c @@ -0,0 +1,1812 @@ +/****************************************************************************** +*@file : hal_ltdc.c +*@brief : GPIO HAL module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_LTDC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + + +HAL_StatusTypeDef HAL_LTDC_Clk_Div(uint8_t PLL2Q, uint8_t DckCfg) +{ + __ISB(); + while(0==(RCC->PLL2CR&RCC_PLL2CR_PLL2FREERUN)); + + //PLL2 Qclk output Q div value set + RCC->PLL2CFR = ((RCC->PLL2CFR & (~(0x0F<PLL2CR |= RCC_PLL2CR_PLL2UPDATEEN; + __ISB(); + while(0==(RCC->PLL2CR&RCC_PLL2CR_PLL2FREERUN)); + + //LTDC pixle clk divider set + HAL_RCC_LCDPiexlClockDivConfig(DckCfg); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp = 0, tmp1 = 0; + + /* Check the LTDC peripheral state */ + if(hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + + if(hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } + + __HAL_RCC_LTDC_CLK_ENABLE(); + __HAL_RCC_LTDC_RESET(); + + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + hltdc->Instance->GCR |= LTDC_GCR_AHB_LOCK; + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); +// __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU|LTDC_IT_LI|LTDC_IT_RR); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); + + while(0 == (LTDC->CDSR&(1<<2))); //disable ltdc while vsync is invalid to avoid screen blink + __HAL_LTDC_DISABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + /* Transfer Error Interrupt management ***************************************/ + if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_TE) != RESET) + { + if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_TE) != RESET) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ + HAL_LTDC_ErrorCallback(hltdc); + } + } + /* FIFO underrun Interrupt management ***************************************/ + if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_FU) != RESET) + { + if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_FU) != RESET) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ + HAL_LTDC_ErrorCallback(hltdc); + } + } + /* Line Interrupt management ************************************************/ + if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_LI) != RESET) + { + if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_LI) != RESET) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ + HAL_LTDC_LineEventCallback(hltdc); + } + } + /* Register reload Interrupt management ***************************************/ + if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET) + { + if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Register reload interrupt Callback */ + HAL_LTDC_ReloadEventCallback(hltdc); + } + } +} + + +void HAL_LTDC_ERR_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); +} + + + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t counter = 0; + uint32_t pcounter = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for(counter = 0; (counter < CLUTSize); counter++) + { + if(hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + 16*counter) << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + } + else + { + tmp = ((counter << 24) | ((uint32_t)(*pCLUT) & 0xFF) | ((uint32_t)(*pCLUT) & 0xFF00) | ((uint32_t)(*pCLUT) & 0xFF0000)); + } + pcounter = (uint32_t)pCLUT + sizeof(*pCLUT); + pCLUT = (uint32_t *)pcounter; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx, uint32_t ReloadType) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is + * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we + * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels + * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch + * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t pitchUpdate = 0; + uint32_t pixelFormat = 0; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Do not set the Immediate Reload */ + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. +* @retval LTDC Error Code +*/ +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Configures the LTDC peripheral + * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp = 0; + uint32_t tmp1 = 0; + uint32_t tmp2 = 0; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16)) << 16); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16); + tmp2 = (pLayerCfg->Alpha0 << 24); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + + if(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3; + } + else if((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2; + } + else + { + tmp = 1; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3)); + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_mdac.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_mdac.c new file mode 100644 index 0000000000000000000000000000000000000000..809acb6b7a1b42270c591d36ab290b6f25cf9828 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_mdac.c @@ -0,0 +1,323 @@ +/****************************************************************************** +* @file : hal_mdac.c +* @version : 1.0 +* @date : 2023.10.16 +* @brief : MDAC HAL module driver +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_MDAC_MODULE_ENABLED + +/****************************************************************************** +* @brief : Initialize the MDAC MSP. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @return: none +******************************************************************************/ +__weak void HAL_MDAC_MspInit(MDAC_HandleTypeDef *hmdac) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MDAC_MspInit can be implemented in the user file + */ + UNUSED(hmdac); +} + +/****************************************************************************** +* @brief : MDAC MSP De-Initialization. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @return: none +******************************************************************************/ +__weak void HAL_MDAC_MspDeInit(MDAC_HandleTypeDef* hmdac) +{ + /* + NOTE : This function should be modified by the user. + the HAL_MDAC_MspDeInit can be implemented in the user file. + */ + UNUSED(hmdac); + +} + +/****************************************************************************** +* @brief : Initializes the MDAC peripheral according to the specified parameters in the MDAC_HandleTypeDef. +* @param : hdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_Init(MDAC_HandleTypeDef *hmdac) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + + __HAL_RCC_MDAC_RESET(); + + __HAL_RCC_MDAC_CLK_ENABLE(); + + HAL_MDAC_MspInit(hmdac); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Deinitialize the MDAC peripheral registers to their default reset values. +* @param : hdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_DeInit(MDAC_HandleTypeDef *hmdac) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + + HAL_MDAC_MspDeInit(hmdac); + + __HAL_RCC_MDAC_CLK_DISABLE(); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Configures the selected MDAC voltage channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Config : MDAC voltage channel configuration structure +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_ConfigVoltageChannel(MDAC_HandleTypeDef* hmdac, uint32_t Channel, VDAC_ChannelConfigTypeDef* Config) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_VDAC_CHANNEL_NUM(Channel)); + assert_param(IS_VDAC_BUFFER_MODE(Config->BufferMode)); + + if(Config->SampleEn) + { + hmdac->Instance->VDACx_CTRL[Channel] |= MDAC_VDACX_CR_SAMPLE_EN; + } + else + { + hmdac->Instance->VDACx_CTRL[Channel] &= ~MDAC_VDACX_CR_SAMPLE_EN; + } + + /* config the Voltage DAC buffer mode. Note; config buffer mode before setting VDACx_CTRL.EN */ + MODIFY_REG(hmdac->Instance->VDACx_CTRL[Channel], MDAC_VDACX_CR_MODE_Msk, Config->BufferMode << MDAC_VDACX_CR_MODE_Pos); + + if(Config->SelfCalibrateEn) + { + HAL_MDAC_VoltageSelfcalibrate(hmdac, Channel); + } + else + { + /* factory trimming in NVR,read to DAC_CCR */ + uint8_t trim_val; + HAL_StatusTypeDef ret; + ret = HAL_EFUSE_ReadByte(EFUSE1, 0x7A + Channel, &trim_val, 100000); + + if(ret == HAL_OK) + MODIFY_REG(hmdac->Instance->VDACx_CTRL[Channel], MDAC_VDACX_CR_OTRIM_Msk, trim_val << MDAC_VDACX_CR_OTRIM_Pos); + } + + SET_BIT(hmdac->Instance->VDACx_CTRL[Channel], MDAC_VDACX_CR_EN); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Configures the selected MDAC current channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Config : MDAC current channel configuration structure +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_ConfigCurrentChannel(MDAC_HandleTypeDef* hmdac, uint32_t Channel, IDAC_ChannelConfigTypeDef* Config) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_IDAC_ITURN(Config->ITurn)); + assert_param(IS_IDAC_CHANNEL_NUM(Channel)); + + if(Config->ITurn == ITURN_FACTORY) + { + uint8_t iturn_val; + HAL_StatusTypeDef ret; + ret = HAL_EFUSE_ReadByte(EFUSE1, 0x86 + Channel, &iturn_val, 100000); + + if(ret == HAL_OK) + MODIFY_REG(hmdac->Instance->IDACx_CTRL[Channel], MDAC_IDACX_CR_ITURE_Msk, iturn_val << MDAC_IDACX_CR_ITURE_Pos); + } + else + { + MODIFY_REG(hmdac->Instance->IDACx_CTRL[Channel], MDAC_IDACX_CR_ITURE_Msk, Config->ITurn << MDAC_IDACX_CR_ITURE_Pos); + } + + SET_BIT(hmdac->Instance->IDACx_CTRL[Channel], MDAC_IDACX_CR_EN); + + return HAL_OK; +} + + +/****************************************************************************** +* @brief : Set the specified value for MDAC voltage channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : MDAC voltage channel index. +* @param : Data: The destination peripheral data. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_SetVoltageValue(MDAC_HandleTypeDef *hmdac, uint32_t Channel, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_VDAC_CHANNEL_NUM(Channel)); + + hmdac->Instance->DACx_DOR[Channel] = Data; + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Returns the last data output value of the selected MDAC voltage channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : MDAC voltage channel index. +* @return: The selected MDAC voltage channel data output value +******************************************************************************/ +uint32_t HAL_MDAC_GetVoltageValue(MDAC_HandleTypeDef* hmdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_VDAC_CHANNEL_NUM(Channel)); + + return hmdac->Instance->DACx_DOR[Channel]; + +} + +/****************************************************************************** +* @brief : Set the specified value for MDAC current channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : MDAC current channel index. +* @param : Data: The destination peripheral data. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_SetCurrentValue(MDAC_HandleTypeDef *hmdac, uint32_t Channel, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_IDAC_CHANNEL_NUM(Channel)); + + hmdac->Instance->DACx_DOR[12 + Channel] = Data; + + /* Return function status */ + return HAL_OK; +} + +/****************************************************************************** +* @brief : Returns the last data output value of the selected MDAC current channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : MDAC current channel index. +* @return: The selected MDAC current channel data output value +******************************************************************************/ +uint32_t HAL_MDAC_GetCurrentValue(MDAC_HandleTypeDef* hmdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_IDAC_CHANNEL_NUM(Channel)); + + return hmdac->Instance->DACx_DOR[12 + Channel]; + +} + +/****************************************************************************** +* @brief : Run the self calibration of one voltage DAC channel. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : The selected MDAC voltage channel. +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_VoltageSelfcalibrate(MDAC_HandleTypeDef *hmdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_VDAC_CHANNEL_NUM(Channel)); + + uint32_t TrimVal; + uint32_t ChannelEn; + + ChannelEn = READ_BIT((hmdac->Instance->VDACx_CTRL[Channel]), MDAC_VDACX_CR_EN); + + if(!ChannelEn) + SET_BIT((hmdac->Instance->VDACx_CTRL[Channel]), MDAC_VDACX_CR_EN); + + SET_BIT((hmdac->Instance->VDACx_CTRL[Channel]), MDAC_VDACX_CR_CEN); + + for(TrimVal = 0; TrimVal < 32; TrimVal++) + { + /* Set candidate trimming */ + MODIFY_REG(hmdac->Instance->VDACx_CTRL[Channel], MDAC_VDACX_CR_OTRIM_Msk, TrimVal << MDAC_VDACX_CR_OTRIM_Pos); + + HAL_SimpleDelay(50000); + + if(READ_BIT((hmdac->Instance->VDACx_CTRL[Channel]), MDAC_VDACX_CR_CAL_FLAG)) + break; + } + + CLEAR_BIT((hmdac->Instance->VDACx_CTRL[Channel]), MDAC_VDACX_CR_CEN); + + if(!ChannelEn) + CLEAR_BIT((hmdac->Instance->VDACx_CTRL[Channel]), MDAC_VDACX_CR_EN); + + if(TrimVal > 31) + { + /* Restore the original TrimVal */ + + return HAL_ERROR; + } + + return HAL_OK; +} + + + +/****************************************************************************** +* @brief : Set the trimming mode and trimming value (user trimming mode applied). +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : The selected MDAC voltage channel. +* @param : TrimVal: VDAC trim value +* @return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_MDAC_SetVoltageTrim(MDAC_HandleTypeDef *hmdac, uint32_t Channel, uint32_t TrimVal) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_VDAC_CHANNEL_NUM(Channel)); + assert_param(IS_VDAC_TRIM_VALUE(TrimVal)); + + MODIFY_REG(hmdac->Instance->VDACx_CTRL[Channel], MDAC_VDACX_CR_OTRIM_Msk, TrimVal << MDAC_VDACX_CR_OTRIM_Pos); + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Return the MDAC voltage trim value. +* @param : hmdac : pointer to a MDAC_HandleTypeDef structure that contains +* the configuration information for MDAC module. +* @param : Channel : The selected MDAC voltage channel. +* @return: The trim value of selected voltage channel. +******************************************************************************/ +uint32_t HAL_MDAC_GetVoltageTrimValue(MDAC_HandleTypeDef *hmdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_MDAC_INSTANCE(hmdac->Instance)); + assert_param(IS_VDAC_CHANNEL_NUM(Channel)); + + /* Retrieve trimming */ + return ((hmdac->Instance->VDACx_CTRL[Channel] & MDAC_VDACX_CR_OTRIM_Msk) >> MDAC_VDACX_CR_OTRIM_Pos); +} + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_nand.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_nand.c new file mode 100644 index 0000000000000000000000000000000000000000..2675ff1c5b64baa6a0922c3385315041ddaca147 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_nand.c @@ -0,0 +1,467 @@ +/* + ****************************************************************************** + * @file hal_nand.c + * @author AisinoChip Firmware Team + * @version V1.0.0 + * @date 2020 + * @brief Nand HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * @ Initialization and de-initialization functions + * @ IO operation functions + * @ Peripheral Control functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2020 AisinoChip. + * All rights reserved. + ****************************************************************************** +*/ +#include "hal.h" + +#ifdef HAL_NAND_MODULE_ENABLED + +volatile uint8_t flag_nand_int = 0; +void WaitFlashReady(void); +/****************************************************************************** +*@brief : FMC callback. +*@ret : None +******************************************************************************/ +__weak void HAL_FMC_NAND_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FMC_NAND_Callback could be implemented in the user file + */ +} + +/****************************************************************************** +*@brief : BCH callback. +*@ret : None +******************************************************************************/ +__weak void HAL_BCH_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_BCH_Callback could be implemented in the user file + */ +} + + +void FMC_NAND_IRQHandler(void) +{ + HAL_FMC_NAND_Callback(); +} + +void BCH_IRQHandler(void) +{ + HAL_BCH_Callback(); +} + + +/****************************************************************************** +*@brief : Initialize nand according to the specified parameters in hnand. +* +*@param : hnand: handle with nand parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Init(FMC_NAND_HandleTypeDef *hnand) +{ + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + assert_param (IS_FMC_NAND_EDO_EN(hnand->Init.EDO_EN)); + assert_param (IS_FMC_NAND_ENDIAN_EN(hnand->Init.ENDIAN)); + assert_param (IS_FMC_NAND_FCE_EN(hnand->Init.FCE)); + + __HAL_RCC_FMC_CLK_ENABLE(); + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_FMC_NAND_MspInit(hnand); + + hnand->Instance->CTRL = hnand->Init.EDO_EN | hnand->Init.RBN_INTEN | hnand->Init.ENDIAN | hnand->Init.FWP | hnand->Init.FCE; + hnand->Instance->WST = hnand->Init.TADL | hnand->Init.TRHW | hnand->Init.TWHR | hnand->Init.TREH | hnand->Init.TRP | hnand->Init.TWH | hnand->Init.TWP; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the nand MSP: CLK, GPIO, NVIC +* +*@param : hnand: handle with nand parameters. +*@return: None +******************************************************************************/ +__weak void HAL_FMC_NAND_MspInit(FMC_NAND_HandleTypeDef *hnand) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + GPIO_InitTypeDef GPIO_InitStructure; + + /* ʹnandصGPIOʱ */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*-- GPIO -----------------------------------------------------*/ + + /* ͨ GPIO */ + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;//Ϊù + GPIO_InitStructure.Pull = GPIO_PULLUP; + GPIO_InitStructure.Alternate = GPIO_FUNCTION_10;//AF10 + GPIO_InitStructure.Drive = GPIO_DRIVE_LEVEL7; + + /*D[0:7]ź */ + GPIO_InitStructure.Pin = FMC_NAND_D0_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D0_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D1_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D1_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D2_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D2_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D3_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D3_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D4_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D4_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D5_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D5_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D6_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D6_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_D7_GPIO_PIN; + HAL_GPIO_Init(FMC_NAND_D7_GPIO_PORT, &GPIO_InitStructure); + + /*ź*/ + GPIO_InitStructure.Pin = FMC_NAND_CEN_GPIO_PIN; //Ƭѡź + HAL_GPIO_Init(FMC_NAND_CEN_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_WEN_GPIO_PIN; //WEN + HAL_GPIO_Init(FMC_NAND_WEN_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_REN_GPIO_PIN; //REN + HAL_GPIO_Init(FMC_NAND_REN_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_CLE_GPIO_PIN; //CLE + HAL_GPIO_Init(FMC_NAND_CLE_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_ALE_GPIO_PIN; //ALE + HAL_GPIO_Init(FMC_NAND_ALE_GPIO_PORT, &GPIO_InitStructure); + + + GPIO_InitStructure.Alternate = GPIO_FUNCTION_11; //AF11 + + + GPIO_InitStructure.Pin = FMC_NAND_CEN_GPIO_PIN; //Ƭѡź + HAL_GPIO_Init(FMC_NAND_CEN_GPIO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = FMC_NAND_RBN_GPIO_PIN; //RBN + HAL_GPIO_Init(FMC_NAND_RBN_GPIO_PORT, &GPIO_InitStructure); + +} + +/****************************************************************************** +*@brief : Wait for Flash RBN rising event +* +*@param : hnand: handle with nand parameters. +*@return: None +******************************************************************************/ +static HAL_StatusTypeDef HAL_FMC_NAND_WaitFlashReady(FMC_NAND_HandleTypeDef *hnand) +{ + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + + /* wait nand not busy*/ + while(READ_BIT(hnand->Instance->STATUS, FMC_NAND_STATUS_POS_RBN_0) == 0){;} + SET_BIT(hnand->Instance->STATUS, FMC_NAND_STATUS_POS_RBN_0); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Reset Nand Flash +* +*@param : hnand: handle with nand parameters. +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashReset(FMC_NAND_HandleTypeDef *nand) +{ + assert_param (IS_FMC_NAND_ALL_INSTANCE(nand->Instance)); + + /* clear CE0 */ + CLEAR_BIT(nand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + /* write RESET CMD */ + nand->Instance->CMD = FMC_NAND_CMD_RESET; + HAL_FMC_NAND_WaitFlashReady(nand); + + /* release CE0 */ + SET_BIT(nand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + return HAL_OK; +} + +/****************************************************************************** +*@brief : Read ID from Nand Flash +* +*@param : hnand: handle with nand parameters. +*@param : rdata: start address to store ID +*@param : lenth: ID length +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashGetID(FMC_NAND_HandleTypeDef *hnand, uint8_t rdata[], uint8_t lenth) +{ + uint8_t i; + + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + + /* clear CE0 */ + CLEAR_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + /* write READ ID CMD */ + hnand->Instance->CMD = FMC_NAND_CMD_ID; + /* write address 00 */ + hnand->Instance->ADDR = 0x00; + + for(i = 0; i < lenth; i++) + { + *rdata++ = FMC_NAND->FMC_NAND_NECCDATA.FMC_NAND_NECCDATA_CH8; + } + + /* release CE0 */ + SET_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Erase a block +* +*@param : hnand: handle with nand parameters. +*@param : BlockAddr: start address of the block to erase +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashErase(FMC_NAND_HandleTypeDef *hnand, uint32_t BlockAddr) +{ + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + + /* clear CE0 */ + CLEAR_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + hnand->Instance->CMD = FMC_NAND_CMD_ERASE1; + hnand->Instance->ADDR = BlockAddr & 0xff; + hnand->Instance->ADDR = (BlockAddr >> 8) & 0xff; + hnand->Instance->ADDR = (BlockAddr >> 16) & 0xff; + + hnand->Instance->CMD = FMC_NAND_CMD_ERASE2; + HAL_FMC_NAND_WaitFlashReady(hnand); + + /* release CE0 */ + SET_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Program one sector(512 bytes) +* +*@param : hnand: handle with nand parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : wdata: start address of data to program +*@param : ecc_en:select the mode of program + BCH_ECC_MODE_EN : program with ecc mode + BCH_ECC_MODE_DIS: progran with no ecc mode +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Flash_Program(FMC_NAND_HandleTypeDef *hnand, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t wdata[], uint8_t ecc_en) +{ + uint32_t i; + uint32_t temp; + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + + /* clear CE0 */ + CLEAR_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + hnand->Instance->CMD = FMC_NAND_CMD_PROGRAM1; + + hnand->Instance->ADDR = (uint8_t)ColumnAddr; // Column address + hnand->Instance->ADDR = (uint8_t)(ColumnAddr >> 8); // Column address + hnand->Instance->ADDR = (uint8_t)RowAddr; // Page address + hnand->Instance->ADDR = (uint8_t)(RowAddr >> 8); // Page address + hnand->Instance->ADDR = (uint8_t)(RowAddr >> 16); // Page address + + /* ECC Channel */ + if(BCH_ECC_MODE_EN == ecc_en) + { + /* BCH encode mode */ + CLEAR_BIT(hnand->Instance->BCH_CTRL, FMC_NAND_BCH_CTRL_MODE); + + /* Reset Encode Channel */ //reset encode channel + SET_BIT(hnand->Instance->BCH_STATUS, FMC_NAND_BCH_STATUS_ENCODE_CLR); + + for(i = 0; i < (BCH_SECTOR_SIZE + BCH_INF_SIZE); i++) + { + hnand->Instance->FMC_NAND_ECCDATA.FMC_NAND_ECCDATA_CH8 = wdata[i]; + } + + /* Reset BCH Code PTR */ + hnand->Instance->BCH_CODEPTR = 0; + for(i = 0; i < BCH_ECC_SIZE; i++) + { + hnand->Instance->FMC_NAND_ECCDATA.FMC_NAND_ECCDATA_CH8 = FMC_NAND->BCH_CODE.FMC_NAND_BCHCODE_CH8; + } + } + else + { + for(i = 0; i < BCH_SECTOR_SIZE; i++) + { + hnand->Instance->FMC_NAND_NECCDATA.FMC_NAND_NECCDATA_CH8 = wdata[i]; ;//no ecc channel + } + } + hnand->Instance->CMD = FMC_NAND_CMD_PROGRAM2; + HAL_FMC_NAND_WaitFlashReady(hnand); + + /* release CE0 */ + SET_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Program one sector(512 bytes) using necc channel and ecc data +* +*@param : hnand: handle with nand parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : wdata: start address of data to program +*@param : pEccByte: input ecc data +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Flash_Program_NECC_with_ECC_CODE(FMC_NAND_HandleTypeDef *hnand, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t wdata[], uint8_t pEccByte[]) +{ + uint32_t i; + uint32_t temp; + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + + /* clear CE0 */ + CLEAR_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + hnand->Instance->CMD = FMC_NAND_CMD_PROGRAM1; + + hnand->Instance->ADDR = (uint8_t)ColumnAddr; // Column address + hnand->Instance->ADDR = (uint8_t)(ColumnAddr >> 8); // Column address + hnand->Instance->ADDR = (uint8_t)RowAddr; // Page address + hnand->Instance->ADDR = (uint8_t)(RowAddr >> 8); // Page address + hnand->Instance->ADDR = (uint8_t)(RowAddr >> 16); // Page address + + + for(i = 0; i < (BCH_SECTOR_SIZE + BCH_INF_SIZE); i++) + { + hnand->Instance->FMC_NAND_NECCDATA.FMC_NAND_NECCDATA_CH8 = wdata[i]; ;//write data using no ecc channel + } + for(i = 0; i < BCH_ECC_SIZE; i++) + { + hnand->Instance->FMC_NAND_NECCDATA.FMC_NAND_NECCDATA_CH8 = pEccByte[i]; ;//write ecc data + } + + hnand->Instance->CMD = FMC_NAND_CMD_PROGRAM2; + HAL_FMC_NAND_WaitFlashReady(hnand); + + /* release CE0 */ + SET_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Read one sector(512 bytes) +* +*@param : hnand: handle with nand parameters. +*@param : RowAddr: row start address +*@param : ColumnAddr: column start address +*@param : rdata: start address of read data +*@param : ecc_en:select the mode of read + BCH_ECC_MODE_EN : read with ecc mode + BCH_ECC_MODE_DIS: read with no ecc mode +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_FlashRead(FMC_NAND_HandleTypeDef *hnand, uint32_t RowAddr, uint16_t ColumnAddr, uint8_t rdata[], uint8_t auto_sel) +{ + int i; + + assert_param (IS_FMC_NAND_ALL_INSTANCE(hnand->Instance)); + + /* clear CE0 */ + CLEAR_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + hnand->Instance->CMD = FMC_NAND_CMD_READ1; + hnand->Instance->ADDR = (uint8_t)ColumnAddr; // Column address + hnand->Instance->ADDR = (uint8_t)(ColumnAddr >> 8); // Column address + hnand->Instance->ADDR = (uint8_t)RowAddr; // Page address + hnand->Instance->ADDR = (uint8_t)(RowAddr >> 8); // Page address + hnand->Instance->ADDR = (uint8_t)(RowAddr >> 16); // Page address + + hnand->Instance->CMD = FMC_NAND_CMD_READ2; + + HAL_FMC_NAND_WaitFlashReady(hnand); + + if(BCH_ECC_MODE_EN == auto_sel) + { + /* BCH decode mode */ + SET_BIT(hnand->Instance->BCH_CTRL, FMC_NAND_BCH_CTRL_MODE); + + /* Auto Correct */ + SET_BIT(hnand->Instance->BCH_CTRL, FMC_NAND_BCH_CTRL_AUTO_CORRECT); + + /* SRAM Base */ + hnand->Instance->BCH_BASEADDR = (uint32_t)rdata; + + /* ECC Channel */ + for(i = 0; i < (BCH_SECTOR_SIZE + BCH_INF_SIZE + BCH_ECC_SIZE); i++) + { + rdata[i] = hnand->Instance->FMC_NAND_ECCDATA.FMC_NAND_ECCDATA_CH8; + } + + /* Wait Correct Done */ + while(READ_BIT(hnand->Instance->BCH_STATUS, FMC_NAND_BCH_STATUS_CORRECT_DONE) == 0){;} + /* Clear Flag */ + SET_BIT(hnand->Instance->BCH_STATUS, FMC_NAND_BCH_STATUS_CORRECT_DONE); + + if(READ_BIT(hnand->Instance->BCH_STATUS, FMC_NAND_BCH_STATUS_BCH_FAIL)) + { + /* Clear Error Flag */ + SET_BIT(hnand->Instance->BCH_STATUS, FMC_NAND_BCH_STATUS_BCH_FAIL); + /* release CE0 */ + SET_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + + return HAL_ERROR; + } + } + else + { + for(i = 0; i < BCH_SECTOR_SIZE; i++) // + { + rdata[i] = FMC_NAND->FMC_NAND_NECCDATA.FMC_NAND_NECCDATA_CH8;//REG_NFM_NECC_CH8; + } + + } + + /* release CE0 */ + SET_BIT(hnand->Instance->CTRL, FMC_NAND_CTRL_FCE_0); + return HAL_OK; +} + +/****************************************************************************** +*@brief : Reset ECC Channel +* +*@return: None +******************************************************************************/ +HAL_StatusTypeDef HAL_FMC_NAND_Reset_ECC_Channel(FMC_NAND_HandleTypeDef *hnand) +{ + /* Reset Channel */ + SET_BIT(hnand->Instance->BCH_CTRL, FMC_NAND_BCH_CTRL_RESET_CHANNEL); + return HAL_OK; +} + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_norflash.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_norflash.c new file mode 100644 index 0000000000000000000000000000000000000000..f1d153543c629e30a174879066afbf41bb2f58a2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_norflash.c @@ -0,0 +1,728 @@ +/***************************************************************** +Copyright(C) 2008 - 2021, Shanghai AisinoChip Co.,Ltd. +@ļ: hal_norflash.c +@: norflashģ麯 +@Ա: bobzhang +@: 2023.1.18 +@ǰ汾: 1.0 +@޸ļ¼: +޸ ޸ ޸˵ + +******************************************************************/ + +/***************************************************************** +ע⣺ʹ HAL_NORFLASH_ModifyData Ҫջ6KBϡ +Ϊ HAL_NORFLASH_ModifyData ڲʹ4KBջռ䣬ݡ +******************************************************************/ + +#include "hal_norflash.h" + +#ifdef HAL_NORFLASH_MODULE_ENABLED + +static uint8_t HAL_NORFLASH_EraseSector(uint32_t addr); +static uint8_t HAL_NORFLASH_EraseBlock32K(uint32_t addr); +static uint8_t HAL_NORFLASH_EraseBlock64K(uint32_t addr); +static uint8_t HAL_NORFLASH_ProgramPage(uint32_t addr, uint8_t *buff, uint32_t len); + + + +//NORFLASH_ParamTypeDef NORFLASH_param = {0x200000, READ_DATA, 0, PAGE_PROGARM}; +NORFLASH_ParamTypeDef NORFLASH_param = {0x200000, QUAD_IO_FAST_READ, 0x02, QUAD_PAGE_PROGRAM}; + +uint32_t HAL_NORFLASH_EnterCritical(void) +{ + uint32_t sr; + sr = __get_PRIMASK(); + __set_PRIMASK(1); + SCB->ICSR = BIT25; // clear systick pending bit + return sr; +} + +void HAL_NORFLASH_ExitCritical(uint32_t sr) +{ + __set_PRIMASK(sr&0x01); +} + + + +/***************************************************************** +@ NORFLASHʼ +@ +@ HAL_OK-ɹ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_Init(void) +{ +// uint32_t sr; +// uint8_t paramBuff[32],ret; +// SPI_Flash_Parameter spiflashParam; +// +// spiflashParam.Command = READ_DATA; +// spiflashParam.Delay = NORFLASH_OPRA_DELAY; +// spiflashParam.Cont_MID = 0; +// spiflashParam.Dummy_bytes = 0; +// spiflashParam.Addr = 0; +// spiflashParam.Addr_Length = 24; +// spiflashParam.Operation_length = 32; +// spiflashParam.Output_data = paramBuff; +// sr = HAL_NORFLASH_EnterCritical(); +// ret = SPI_Nor_Get_Parameter(&spiflashParam); +// HAL_NORFLASH_ExitCritical(sr); +// if(ret) +// { +// return HAL_ERROR; +// } +// +// NORFLASH_param.chipSize = (paramBuff[4] | (paramBuff[5] << 8) | (paramBuff[6] << 16) | (paramBuff[7] << 24)); +// if(paramBuff[10]!=0) +// { +// NORFLASH_param.readCmd = paramBuff[10]; +// NORFLASH_param.readDummyBytes = paramBuff[11]; +// } +// else if(paramBuff[12]!=0) +// { +// NORFLASH_param.readCmd = paramBuff[12]; +// NORFLASH_param.readDummyBytes = paramBuff[13]; +// } +// else if(paramBuff[14]!=0) +// { +// NORFLASH_param.readCmd = paramBuff[14]; +// NORFLASH_param.readDummyBytes = paramBuff[15]; +// } +// else if(paramBuff[16]!=0) +// { +// NORFLASH_param.readCmd = paramBuff[16]; +// NORFLASH_param.readDummyBytes = paramBuff[17]; +// } +// else +// { +// NORFLASH_param.readCmd = READ_DATA; +// NORFLASH_param.readDummyBytes = 0; +// } +// +// if(paramBuff[23]!=0) +// { +// NORFLASH_param.programCmd = paramBuff[23]; +// } +// else if(paramBuff[22]!=0) +// { +// NORFLASH_param.programCmd = paramBuff[22]; +// } +// else +// { +// NORFLASH_param.programCmd = PAGE_PROGARM; +// } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : read Unique ID. +*@param : buff: save Unique ID. +*@param : len: len of Unique ID. +*@return: HAL_OK,HAL_ERROR +******************************************************************************/ +//9FH +uint8_t HAL_NORFLASH_ReadUniqueID(uint8_t *buff,uint32_t len) +{ + uint32_t sr; + uint8_t ret; + SPI_Flash_Parameter spiflashParam; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_READ_UNIQUE_ID; + spiflashParam.Delay = 0xFF; + spiflashParam.Operation_length = len; + spiflashParam.Output_data_Addr = (uint32_t)buff; + spiflashParam.Dummy_clks = 8; + + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_Read_Unique_ID(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + + +/****************************************************************************** +*@brief : read Manufacture ID , Device ID. +*@param : buff: save Manufacture ID , Device ID.length is 2. +*@return: HAL_OK,HAL_ERROR +******************************************************************************/ +// 9FH 3 byte +uint8_t HAL_NORFLASH_ReadID(uint8_t *buff) +{ + uint32_t sr; + uint8_t ret; + SPI_Flash_Parameter spiflashParam; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_READ_ID_1S0S1S; + spiflashParam.Delay = 0xFF; + spiflashParam.Dummy_clks = 0; + spiflashParam.Operation_length = 3; + spiflashParam.Output_data_Addr = (uint32_t)buff; + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_Read_MID_DID(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/***************************************************************** +@ õ͹ģʽ +@ mode + BIT0=1: spi flash enter power down mode + BIT1=1: mcu enter deep sleep + BIT2=1: mcu enter standby mode + BIT3=1: wakeup spi flash +@ HAL_OK-ɹ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_SetLowPowerMode(uint8_t mode) +{ +// uint32_t sr; +// uint8_t ret; +// SPI_Flash_Parameter spiflashParam; +// +// spiflashParam.Command = mode; +// spiflashParam.Delay = NORFLASH_OPRA_DELAY; +// spiflashParam.Cont_MID = 0; +// +// sr = HAL_NORFLASH_EnterCritical(); +// ret = SPI_Nor_Low_Power_Mode(&spiflashParam); +// HAL_NORFLASH_ExitCritical(sr); +// +// if(ret) +// { +// return HAL_ERROR; +// } + return HAL_OK; +} + +/***************************************************************** +@ λMCUλϵͳROMиֱ־жϣУ飬ͨתAPPʧͣBOOTģʽ +@ +@ +******************************************************************/ +void HAL_NORFLASH_ResetMcu(void) +{ +// uint32_t sr; +// uint8_t ret; +// SPI_Flash_Parameter spiflashParam; +// +// spiflashParam.Command = 0; +// spiflashParam.Delay = NORFLASH_OPRA_DELAY; +// spiflashParam.Cont_MID = 0; +// spiflashParam.Operation_length = 0; +// spiflashParam.Dummy_bytes = 0; +// +// sr = HAL_NORFLASH_EnterCritical(); +// ret = SPI_Nor_Flash_Reset_SOC(&spiflashParam); +// HAL_NORFLASH_ExitCritical(sr); +} + + +/***************************************************************** +@ flashֽڶ +@ addr - ʼַ +@ buf-ݻ棬ֽڵַ +@ len-ȡֽ +@ HAL_OK-ɹ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_Read(uint32_t addr, uint8_t *buff, uint32_t len) +{ + uint32_t sr; + uint8_t ret; + SPI_Flash_Parameter spiflashParam; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_READ_DATA_1S1S1S_24; + spiflashParam.Delay = 0xFFU; + spiflashParam.Cont_MID = 0; + spiflashParam.Dummy_clks = 0; + spiflashParam.Addr = addr; + spiflashParam.Operation_length = len; + spiflashParam.Output_data_Addr = (uint32_t)buff; + + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_Read(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + + + + +/***************************************************************** +@ ݣֿ֧ +@ addr - ʼַ +@ len - +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_Erase(uint32_t addr, uint32_t len) +{ + uint8_t ret; + uint32_t eraseAddr; + + eraseAddr = addr & (~NORFLASH_SECTOR_SIZE_MASK);//׵ַ + len += (addr & NORFLASH_SECTOR_SIZE_MASK); + while(len) + { + if(((eraseAddr&NORFLASH_BLOCK_64K_SIZE_MASK)==0) && (len>=NORFLASH_BLOCK_64K_SIZE)) + { + ret=HAL_NORFLASH_EraseBlock64K(eraseAddr); + if(ret) + { + return HAL_ERROR; + } + if(len > NORFLASH_BLOCK_64K_SIZE) + { + len -= NORFLASH_BLOCK_64K_SIZE; + } + else + { + len = 0; + } + eraseAddr += NORFLASH_BLOCK_64K_SIZE; + } + else if(((eraseAddr&NORFLASH_BLOCK_32K_SIZE_MASK)==0) && (len>=NORFLASH_BLOCK_32K_SIZE)) + { + ret=HAL_NORFLASH_EraseBlock32K(eraseAddr); + if(ret) + { + return HAL_ERROR; + } + + if(len > NORFLASH_BLOCK_32K_SIZE) + { + len -= NORFLASH_BLOCK_32K_SIZE; + } + else + { + len = 0; + } + eraseAddr += NORFLASH_BLOCK_32K_SIZE; + } + else + { + ret=HAL_NORFLASH_EraseSector(eraseAddr); + if(ret) + { + return HAL_ERROR; + } + + if(len > NORFLASH_SECTOR_SIZE) + { + len -= NORFLASH_SECTOR_SIZE; + } + else + { + len = 0; + } + eraseAddr += NORFLASH_SECTOR_SIZE; + } + } + return HAL_OK; +} + +/***************************************************************** +@ eflashݡñǰȲFLASHݣ +@ addr - ʼַ +@ buff-ݻ棬ֽڵַ +@ len-дֽ +@ HAL_OK-ɹ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_Program(uint32_t addr, uint8_t *buff, uint32_t len) +{ + uint8_t ret; + uint32_t offset,writeLen,writeAddr; + + offset = addr & NORFLASH_PAGE_SIZE_MASK; + writeAddr = addr; + + while(len) + { + if((offset+len) < NORFLASH_PAGE_SIZE) + { + writeLen = len; + } + else + { + writeLen = NORFLASH_PAGE_SIZE-offset; + } + + ret = HAL_NORFLASH_ProgramPage(writeAddr,buff,writeLen); + if(ret != HAL_OK) + return HAL_ERROR; + writeAddr += writeLen; + buff += writeLen; + len -= writeLen; + offset = 0; + } + return HAL_OK; +} + +/***************************************************************** +@ eflashдֽݡԶд룬ֿ֧ҳдڲʹ4KBջռ䣬ݡ +@ addr - ʼַ +@ buff-ݻ棬ֽڵַ +@ len-дֽ +@ HAL_OK-ɹ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_ModifyData(uint32_t addr, uint8_t *buff, uint32_t len) +{ + uint16_t offset; + uint16_t writeLen; + uint32_t writeAddr; + uint8_t *writePtr; + uint8_t flash_buff[NORFLASH_SECTOR_SIZE]; + + offset = (addr & NORFLASH_SECTOR_SIZE_MASK); //ƫ + writeAddr = addr - offset; //ʼַ + + while(len>0) + { + //д볤 + if(len <= (NORFLASH_SECTOR_SIZE - offset))//дݲʣռ䣬ûгΧ + { + writeLen = len; + } + else + { + writeLen = NORFLASH_SECTOR_SIZE - offset; + } + + if(writeLen != NORFLASH_SECTOR_SIZE)//д + { + HAL_NORFLASH_Read(writeAddr, flash_buff, NORFLASH_SECTOR_SIZE);// + memcpy(flash_buff+offset,buff,writeLen); + + writePtr = flash_buff; + } + else//ҳд + { + writePtr = buff; + } + + //Ȳд1 + + if(HAL_NORFLASH_EraseSector(writeAddr)!=HAL_OK) + { + return HAL_ERROR; + } + + if(HAL_NORFLASH_Program(writeAddr,writePtr,NORFLASH_SECTOR_SIZE)!= HAL_OK) + { + return HAL_ERROR; + } + + offset = 0; //ƫλΪ0 + writeAddr += NORFLASH_SECTOR_SIZE; //дַƫ + buff += writeLen; //ָƫ + len -= writeLen; //ֽݼ + } + return HAL_OK; +} + + +/***************************************************************** +@ BOOT־ +@ +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_EraseBootFlag(void) +{ + uint8_t ret; + uint8_t val[4] = {0xFF, 0xFF, 0xFF, 0xFF}; + HAL_NORFLASH_ModifyData(0x1018, val, 4); + + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + + +void otfdec_key_reverse(uint8_t *data_in, uint32_t *data_out) +{ + uint32_t i; + + i = 0; + + for(i = 0; i < 4; i++) + { + data_out[i] = (data_in[15-4*i] << 24) + (data_in[14-i*4] << 16) + (data_in[13-i*4] << 8) + (data_in[12-i*4] << 0); + } +} + + +// input value: pointer to 16 bytes key +// return value: 1 means valid, other value means invalid +uint8_t HAL_NORFLASH_SetEncryptionKey(uint8_t * key_input) +{ + uint32_t sr; + uint8_t ret; + uint32_t key_reverse[8]; + SPI_Flash_Parameter spiflashParam; + + otfdec_key_reverse( (uint8_t *)key_input, key_reverse); + key_reverse[7] = 0xFE01; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_CMD_ID_NOT_CARE; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = 0; + spiflashParam.Delay = 0xFFU; + spiflashParam.Operation_length = 0; + spiflashParam.Input_data_Addr = (uint32_t)key_reverse; + spiflashParam.Dummy_clks = 0; + + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_SetEncrytionKey(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/***************************************************************** +@ ֹ̡ܱҳ߽磨256ֽڶ룩̡ +@ addr - ʼַ0x08000000Ļַһҳʱ128ֽڶ +@ buff-ݻ棬ַ4ֽڶ롣 +@ wordLen-дWORDȣһҳʱΪ32ֳ128ֽڣ64ֳ256ֽڣ +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_EncryptProgram(uint32_t addr, uint32_t *data_in, uint32_t len, uint32_t *data_out) +{ + SPI_Flash_Parameter spiflashParam; + uint8_t ret; + uint32_t sr; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_PROG_DATA_1S1S1S_24; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = addr; + spiflashParam.Delay = 0xFFU; + spiflashParam.Operation_length = len; + spiflashParam.Input_data_Addr = (uint32_t)data_in; + spiflashParam.Output_data_Addr = (uint32_t)data_out; + spiflashParam.Dummy_clks = 0; + + sr = HAL_NORFLASH_EnterCritical(); + ret = ( SPI_Nor_Encrypt_Data)(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; + +} + +/***************************************************************** +@ ޸SPIĴ +@ write_addr - SPI Ĵַ +@ p_value-ݡ +@ len-ֵij +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_ModifySPIControllerParam(uint32_t write_addr, uint32_t * p_value, uint32_t len) +{ + SPI_Flash_Parameter spiflashParam; + uint8_t ret; + uint32_t sr; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_CMD_ID_NOT_CARE; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = write_addr; + spiflashParam.Delay = 0xFFU; + spiflashParam.Operation_length = len; + spiflashParam.Input_data_Addr = (uint32_t)p_value; + + sr = HAL_NORFLASH_EnterCritical(); + ret = (SPI_Nor_ModifyValue)(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + + +/***************************************************************** +@ Modify baud rate of SPI +@ div: spi baud configuration, can set to 2, 4, 6, 8... +@ shift_clk- SPI_SHIFT_ZERO, SPI_SHIFT_1HCLK, ... +@ 0-ɹ , others-ʧ +******************************************************************/ +uint8_t HAL_NORFLASH_ModifyDivShift(uint32_t div, uint32_t shift_clk) +{ + uint32_t reg_addr; + uint32_t spi_data_write[4] = {0,}; + uint8_t ret; + + spi_data_write[0] = div; + spi_data_write[1] = SPI7->CTL; + spi_data_write[2] = SPI7->TX_CTL; + + if (shift_clk < SPI_SHIFT_2P5HCLK) + { + spi_data_write[3] = (SPI7->RX_CTL & ~((0x3 << 8) | BIT24) ) | (shift_clk << 8); + } + else if(shift_clk == SPI_SHIFT_2P5HCLK) + { + spi_data_write[3] = (SPI7->RX_CTL & ~((0x3 << 8) | BIT24) ) | (0x1 << 24); + } + else if(shift_clk == SPI_SHIFT_3HCLK) + { + spi_data_write[3] = (SPI7->RX_CTL & ~((0x3 << 8) | BIT24) ) | (0x1 << 24) | (1 << 8); + } + else + { + return 1; + } + + reg_addr = (uint32_t)(&(SPI7->BAUD)); + + ret = HAL_NORFLASH_ModifySPIControllerParam(reg_addr, spi_data_write, 4); + + return ret; +} + + + +/***************************************************************** +@ +@ addr - ʼַ +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +static uint8_t HAL_NORFLASH_EraseSector(uint32_t addr) +{ + uint32_t sr; + uint8_t ret; + SPI_Flash_Parameter spiflashParam; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_ERASE_SECTOR_1S1S_24; + spiflashParam.Delay = 0xFFU; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = addr; + + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_Erase(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/***************************************************************** +@ 32K +@ addr - ʼַ +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +static uint8_t HAL_NORFLASH_EraseBlock32K(uint32_t addr) +{ + uint32_t sr; + uint8_t ret; + SPI_Flash_Parameter spiflashParam; + uint32_t offset; + + offset = addr & 0x00FFFFFFU; + + if (offset < 64 * 1024) + { + return HAL_ERROR; + } + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_ERASE_BLOCK1_1S1S_24; + spiflashParam.Delay = 0xFFU; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = addr; + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_Erase(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/***************************************************************** +@ 64K +@ addr - ʼַ +@ HAL_OK-ɹ ,HAL_ERROR-ʧ +******************************************************************/ +static uint8_t HAL_NORFLASH_EraseBlock64K(uint32_t addr) +{ + uint32_t sr; + uint8_t ret; + uint32_t offset; + SPI_Flash_Parameter spiflashParam; + + offset = addr & 0x00FFFFFFU; + + if (offset < 64 * 1024) + { + return HAL_ERROR; + } + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_ERASE_BLOCK2_1S1S_24; + spiflashParam.Delay = 0xFFU; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = addr; + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_Erase(&spiflashParam); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + +static uint8_t HAL_NORFLASH_ProgramPage(uint32_t addr, uint8_t *buff, uint32_t len) +{ + uint32_t sr; + uint8_t ret; + SPI_Flash_Parameter spiflashParam; + + spiflashParam.SPI_Instance = (uint32_t)SPI7; + spiflashParam.Command = SPI_PROG_DATA_1S1S1S_24; + spiflashParam.Cont_MID = 0; + spiflashParam.Addr = addr; + spiflashParam.Delay = 0xFFU; + spiflashParam.Operation_length = len; + spiflashParam.Input_data_Addr = (uint32_t)buff; + spiflashParam.Dummy_clks = 0; + + sr = HAL_NORFLASH_EnterCritical(); + ret=SPI_Nor_PageProgram(&spiflashParam); + //System_InvalidateIAccelerate(); + HAL_NORFLASH_ExitCritical(sr); + if(ret) + { + return HAL_ERROR; + } + return HAL_OK; +} + +#endif /* HAL_NORFLASH_MODULE_ENABLED */ \ No newline at end of file diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_ospi.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_ospi.c new file mode 100644 index 0000000000000000000000000000000000000000..f07dd3b3c47c731624d97eaed18fc9f01ffd0ec7 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_ospi.c @@ -0,0 +1,1996 @@ +/****************************************************************************** +*@file : hal_ospi.c +*@brief : This file provides firmware functions to manage the OSPI HAL module +*@ver : 1.0.0 +*@date : 2023.06.16 +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_OSPI_MODULE_ENABLED + +/****************************************************************************** +*@brief : OSPI interrupt handler +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: None +******************************************************************************/ +__weak void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) +{ + if ( (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_NOT_EMPTY) && ((hospi->Instance->IE) & SPI_IE_RX_FIFO_NOT_EMPTY_EN) ) + { + do{ + if (hospi->Rx_Count < hospi->Rx_Size) + { + hospi->Rx_Buffer[hospi->Rx_Count++] = hospi->Instance->DAT; + } + else break; + }while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_NOT_EMPTY); + } + + if ( (hospi->Instance->STATUS & SPI_STATUS_TX_FIFO_HALF_EMPTY) && ((hospi->Instance->IE) & SPI_IE_TX_FIFO_HALF_EMPTY_EN) ) + { + while (!(hospi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + if(hospi->Tx_Count < hospi->Tx_Size) + { + hospi->Instance->DAT = hospi->Tx_Buffer[hospi->Tx_Count++]; + } + else + { + /* Disable TxFIFO half empty interrupt */ + CLEAR_BIT(hospi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN); + break; + } + } + } + + if ((hospi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE) && ((hospi->Instance->IE) & SPI_IE_TX_BATCH_DONE_EN) ) + { + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + /* Disable TX Batch Done Interrupt, Tx FIFO half empty Interrupt */ + CLEAR_BIT(hospi->Instance->IE, SPI_IE_TX_BATCH_DONE_EN | SPI_IE_TX_FIFO_HALF_EMPTY_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + /* Tx Disable */ + CLEAR_BIT(hospi->Instance->TX_CTL, SPI_TX_CTL_EN); + CLEAR_BIT(hospi->Instance->TX_CTL, SPI_TX_CTL_DMA_REQ_EN); + + hospi->TxState = OSPI_TX_STATE_IDLE; + } + + if ( (hospi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE) && ((hospi->Instance->IE) & SPI_STATUS_RX_BATCH_DONE) ) + { + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE); + + /* Disable RX Batch Done Interrupt, RXFIFO not Empty interrupt */ + CLEAR_BIT(hospi->Instance->IE, SPI_IE_RX_BATCH_DONE_EN | SPI_IE_RX_FIFO_NOT_EMPTY_EN); + + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_NOT_EMPTY) + { + if (hospi->Rx_Count < hospi->Rx_Size) + { + hospi->Rx_Buffer[hospi->Rx_Count++] = hospi->Instance->DAT; + } + else break; + } + ///////////// + + /* Receive End */ + HAL_OSPI_CS_Release(hospi); + + /* Rx Disable */ + CLEAR_BIT(hospi->Instance->RX_CTL, SPI_RX_CTL_DMA_REQ_EN); + CLEAR_BIT(hospi->Instance->RX_CTL, SPI_RX_CTL_EN); + + hospi->RxState = OSPI_RX_STATE_IDLE; + } +} + +/****************************************************************************** +*@brief : Init low level of OSPI module: GPIO, CLK, NVIC +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: None +******************************************************************************/ +__weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); +} + +/****************************************************************************** +*@brief : OSPI De-Initialize the OSPI clock, GPIO, IRQ. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: None +******************************************************************************/ +__weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hospi); +} + +/****************************************************************************** +*@brief : Initialize the OSPI module with parameters +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi) +{ + /* Check OSPI Parameter */ + assert_param(IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_WORK_MODE(hospi->Init.WorkMode)); + assert_param(IS_OSPI_X_MODE(hospi->Init.XMode)); + assert_param(IS_OSPI_FIRST_BIT(hospi->Init.FirstBit)); + assert_param(IS_OSPI_BAUDRATE_PRESCALER(hospi->Init.BaudRatePrescaler)); + assert_param(IS_OSPI_SAMPLE_SHIFT(hospi->Init.SampleShifting)); + assert_param(IS_OSPI_FIFO_MODE(hospi->Init.FWMode)); + assert_param(IS_OSPI_FIFO_MODE(hospi->Init.FRMode)); + assert_param(IS_OSPI_CS_SEL(hospi->CSx)); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_OSPI_MspInit(hospi); + + /* Clear Mst_ModeCHPACPOLLSB_firstX_ModeIO_MODEFW_MODE bit */ + hospi->Instance->CTL &= (~(OSPI_CTL_MST_MODE | SPI_CTL_CPHA | SPI_CTL_CPOL | SPI_CTL_LSB_FIRST | \ + SPI_CTL_X_MODE | OSPI_CTL_IO_MODE | OSPI_CTL_FW_MODE | OSPI_CTL_MEM_MODE)); + + /* Set OSPI Master ModeWorkModeFirstBitXModeAutomatic change directionFIFO wirte mode*/ + hospi->Instance->CTL |= (OSPI_CTL_MST_MODE | (hospi->Init.WorkMode) | (hospi->Init.FirstBit) | \ + (hospi->Init.XMode) | OSPI_CTL_IO_MODE | (hospi->Init.FWMode << OSPI_CTL_FW_MODE_Pos) | (hospi->Init.FRMode << OSPI_CTL_FR_MODE_Pos)); + + /* Set OSPI BaudRate Prescaler */ + hospi->Instance->BAUD = ((hospi->Instance->BAUD) & (~(SPI_BAUD_DIV1 | SPI_BAUD_DIV2))) | (hospi->Init.BaudRatePrescaler); + + /* Clear SSHIFT bit */ + hospi->Instance->RX_CTL &= ~(OSPI_RX_CTL_SSHIFT); + /* Set Master Sample shift*/ + hospi->Instance->RX_CTL |= ((hospi->Init.SampleShifting) << OSPI_RX_CTL_SSHIFT_Pos); + + /* CLEAR SPI_CS BIT*/ + hospi->Instance->CS &= (~OSPI_CS_CS); + + /* Disable All Interrupt */ + hospi->Instance->IE = 0x00000000; + + + return HAL_OK; +} + +/****************************************************************************** +*@brief : e-Initialize the OSPI peripheral +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) +{ + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + return HAL_ERROR; + } + + /* Check OSPI Instance parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + hospi->RxState = OSPI_RX_STATE_IDLE; + hospi->TxState = OSPI_TX_STATE_IDLE; + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_OSPI_MspDeInit(hospi); + + hospi->Rx_Size = 0; + hospi->Tx_Size = 0; + hospi->Rx_Count = 0; + hospi->Tx_Count = 0; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the OSPI module Octal communication +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : Octal: a pointer of OSPI_OctalInitTypeDef structure which contains +* the configuration information for the specified OSPI Octal communication. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_OctalInit(OSPI_HandleTypeDef *hospi, OSPI_OctalInitTypeDef *Octal) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_DTRM(Octal->DTRMode)); + assert_param(IS_OSPI_DQSOE(Octal->DQSMode)); + assert_param(IS_OSPI_MEMORY_TYPE(Octal->MemoryType)); + assert_param(IS_OSPI_DQS_SAMPLE(Octal->DQSSample)); + + + /* Clear DTRMMem_Mode bit */ + hospi->Instance->CTL &= (~(OSPI_CTL_DTRM | OSPI_CTL_MEM_MODE | OSPI_CTL_DQSOE)); + + /* Set DTRMDM_ENDMCTRLMem_ModeAPMD_CLK */ + hospi->Instance->CTL |= ((Octal->DTRMode) | (Octal->MemoryType) | (Octal->DQSMode)); + + /* Set DQS_SAMP_EN */ + hospi->Instance->RX_CTL = ((hospi->Instance->RX_CTL & (~OSPI_RX_CTL_DQS_SAMP_EN)) | (Octal->DQSSample)); + + if(Octal->DTRMode == OSPI_DTRM_DTR) + { + /* Check OSPI Parameter */ + assert_param (IS_OSPI_TX_OUT_DELAY(Octal->OutDelay)); + /* set DTR TX out delay */ + hospi->Instance->TX_CTL = ((hospi->Instance->TX_CTL) & (~(OSPI_TX_CTL_OUTDLY))) | (Octal->OutDelay); + } + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : OSPI module memory mode initialization +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : Memory: a pointer of OSPI_MemoryInitTypeDef structure which contains +* the configuration information for the specified OSPI memory mode. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_MemoryInit(OSPI_HandleTypeDef *hospi, OSPI_MemoryInitTypeDef *Memory) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_BURST_TYPE(Memory->HyperBurstType)); + assert_param(IS_OSPI_DATA_MODE(Memory->DataMode)); + assert_param(IS_OSPI_ALTER_BYTE_MODE(Memory->AlterByteMode)); + assert_param(IS_OSPI_ADDR_MODE(Memory->AddrMode)); + assert_param(IS_OSPI_INSRT_MODE(Memory->InstrMode)); + assert_param(IS_OSPI_ADDR_WIDTH(Memory->AddrWidth)); + assert_param(IS_OSPI_DUMMY_CYCLE(Memory->DummyCycleSize)); + assert_param(IS_OSPI_READ_DUMMY_STATE(Memory->ReadDummyByteEnable)); + assert_param(IS_OSPI_WRITE_DUMMY_STATE(Memory->WriteummyByteEnable)); + assert_param(IS_OSPI_ALTER_BYTE_SIZE(Memory->AlterByteSize)); + assert_param(IS_OSPI_READ_ALTER_STATE(Memory->ReadAlterByteEnable)); + assert_param(IS_OSPI_WRITE_ALTER_STATE(Memory->WriteAlterByteEnable)); + assert_param(IS_OSPI_CMD_SEND_STATE(Memory->SendInstrOnce)); + assert_param(IS_OSPI_CONTINUOUS_STATE(Memory->ContinuousModeEnable)); + assert_param(IS_OSPI_CS_TIMEOUT_STATE(Memory->CsTimeoutEnable)); + assert_param(IS_OSPI_WRAP_SIZE(Memory->WrapSize)); + assert_param(IS_OSPI_BURST_LEN(Memory->BurstLen)); + assert_param(IS_OSPI_LATENCY1_CYCLE(Memory->HyperXspiLC1)); + assert_param(IS_OSPI_LATENCY0_CYCLE(Memory->HyperXspiLc0)); + assert_param(IS_OSPI_CS_TIMEOUT_VAL(Memory->CsTimeoutVal)); + + if(Memory->CsTimeoutEnable == MEMOACC1_CS_TIMEOUT_ENABLE) + { + hospi->Instance->CS_TIMEOUT_VAL = Memory->CsTimeoutVal; + } + /* Set Wr_Cmd/Rd_Cmd bits of CMD register */ + hospi->Instance->CMD= ((Memory->ReadCmd) | (Memory->WriteCmd << 8)); + + /* Set Alter_Byte bit of ALTER_BYTE register */ + hospi->Instance->ALTER_BYTE = Memory->AlterByte; + + /* Set WRPS/BL/Hxspi_LC1/Hxspi_LC0 bits of MEMO_ACC2 register */ + hospi->Instance->MEMO_ACC2 = ((Memory->WrapSize) | \ + (Memory->BurstLen) | \ + (Memory->HyperXspiLC1 << OSPI_MEMO_ACC2_HXLC1_Pos) | \ + (Memory->HyperXspiLc0 << OSPI_MEMO_ACC2_HXLC0_Pos)); + + /* Disable Memory mode and clear 0*/ + hospi->Instance->MEMO_ACC1 = MEMOACC1_MEMORY_DISABLE; + + /* Set Hyper_BT/Data_Mode/Alter_Byte_Mode/Addr_Mode/Instr_Mode/Addr_width/Dummy_Cycle_Size + Rd_Db_EN/Wr_Db_EN/Alter_Byte_Size/Rd_Ab_EN/Wr_Ab_EN/disable_CMD/Con_Mode_EN/CS_Tout_EN + bits of MEMO_ACC1 register */ + hospi->Instance->MEMO_ACC1 = ((Memory->HyperBurstType) | \ + (Memory->DataMode) | \ + (Memory->AlterByteMode) | \ + (Memory->AddrMode) | \ + (Memory->InstrMode) | \ + (Memory->AddrWidth) | \ + (Memory->DummyCycleSize << OSPI_MEMO_ACC1_DUMMY_CYCLE_SIZE_Pos) | \ + (Memory->ReadDummyByteEnable) | \ + (Memory->WriteummyByteEnable) | \ + (Memory->AlterByteSize) | \ + (Memory->ReadAlterByteEnable) | \ + (Memory->WriteAlterByteEnable) | \ + (Memory->SendInstrOnce) | \ + (Memory->ContinuousModeEnable) | \ + (Memory->CsTimeoutEnable)); + + /* Enable Memory mode */ + hospi->Instance->MEMO_ACC1 |= MEMOACC1_MEMORY_ENABLE; + return HAL_OK; +} + +/****************************************************************************** +*@brief : CS Select +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: None +******************************************************************************/ +void HAL_OSPI_CS_Select(OSPI_HandleTypeDef *hospi) +{ + uint32_t tempreg = 0; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + /* Get MULTCS_EN value */ + tempreg = hospi->Instance->CS & OSPI_CS_CSMAP_EN_Msk; + /* Set bit0~2 */ + tempreg |= hospi->CSx; + /* Set OSPI_CS */ + hospi->Instance->CS = tempreg; +} + + +/****************************************************************************** +*@brief : CS Release +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: None +******************************************************************************/ +void HAL_OSPI_CS_Release(OSPI_HandleTypeDef *hospi) +{ + uint32_t tempreg = 0; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + /* Get MULTCS_EN value */ + tempreg = hospi->Instance->CS & OSPI_CS_CSMAP_EN_Msk; + /* Set OSPI_CS */ + hospi->Instance->CS = tempreg; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by loop mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* RX Disable */ + hospi->Instance->RX_CTL &= ~OSPI_RX_CTL_RX_EN; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size > 0) + { + /* Wait Tx FIFO Not Full */ + while (hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + hospi->Instance->DAT = *pData++; + Size--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + Status = HAL_OK; + + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + + return Status; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by loop mode and retain CS. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_TransmitKeepCS(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* RX Disable */ + hospi->Instance->RX_CTL &= ~OSPI_RX_CTL_RX_EN; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size > 0) + { + /* Wait Tx FIFO Not Full */ + while (hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + hospi->Instance->DAT = *pData++; + Size--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + Status = HAL_OK; + + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + ///* Transmit End */ + //HAL_OSPI_CS_Release(hospi); + + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* Tx Disable */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Receive Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size) + { + /* have no timeout */ + if (uiTimeout == 0) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY); + } + else + { + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY) + { + if (uiTimeout-- == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pData++ = hospi->Instance->DAT; + Size--; + uiTimeout = Timeout; + } + + Status = HAL_OK; + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Receive End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode and retain CS. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_ReceiveKeepCS(OSPI_HandleTypeDef *hospi, uint8_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* Tx Disable */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Receive Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size) + { + /* have no timeout */ + if (uiTimeout == 0) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY); + } + else + { + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY) + { + if (uiTimeout-- == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pData++ = hospi->Instance->DAT; + Size--; + uiTimeout = Timeout; + } + + Status = HAL_OK; + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + ///* Receive End */ + //HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by IT mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + /* Tx machine is running */ + if (hospi->TxState != OSPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + + hospi->Tx_Size = Size; + hospi->Tx_Buffer = pData; + hospi->Tx_Count = 0; + + /* Set machine is Sending */ + hospi->TxState = OSPI_TX_STATE_SENDING; + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear Tx FIFO half empty Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_FIFO_HALF_EMPTY); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* Rx Disable */ + hospi->Instance->RX_CTL &= ~OSPI_RX_CTL_RX_EN; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + + while (hospi->Tx_Count < hospi->Tx_Size) + { + if (!(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL)) + { + hospi->Instance->DAT = hospi->Tx_Buffer[hospi->Tx_Count++]; + } + else + { + break; + } + } + + /* Enable Tx FIFO half empty Interrupt and Tx batch done Interrupt*/ + SET_BIT(hospi->Instance->IE, (OSPI_IE_TX_FIFO_HALF_EMPTY_EN | OSPI_IE_TX_BATCH_DONE_EN)); + + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data by IT mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + /* Rx machine is running */ + if (hospi->RxState != OSPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + + /* Set Slave machine is receiving */ + hospi->RxState = OSPI_RX_STATE_RECEIVING; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* TX Disable */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Receive Start */ + HAL_OSPI_CS_Select(hospi); + + hospi->Rx_Size = Size; + hospi->Rx_Buffer = pData; + hospi->Rx_Count = 0; + + /* Enable Rx FIFO Not Empty Interrupt */ + SET_BIT(hospi->Instance->IE, OSPI_STATUS_RX_FIFO_NOT_EMPTY | OSPI_IE_RX_BATCH_DONE_EN); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by DMA mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + /* Rx machine is running */ + if (hospi->TxState != OSPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + /* Set machine is Sending */ + hospi->TxState = OSPI_TX_STATE_SENDING; + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Enable Tx Batch Done Interrupt */ + SET_BIT(hospi->Instance->IE, OSPI_STATUS_TX_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* Tx DMA FIFO */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_DMA_LEVEL; + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_DMA_LEVEL_0; + + /* Rx Disable */ + hospi->Instance->RX_CTL &= ~OSPI_RX_CTL_RX_EN; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + + HAL_DMA_Start(hospi->HDMA_Tx, (uint32_t)pData, (uint32_t)&hospi->Instance->DAT, Size); + + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_DMA_REQ_EN; + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data by DMA mode. +* +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Size) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + /* Rx machine is running */ + if (hospi->RxState != OSPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + /* Set Slave machine is receiving */ + hospi->RxState = OSPI_RX_STATE_RECEIVING; + + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Enable Rx Batch Done Interrupt */ + SET_BIT(hospi->Instance->IE, OSPI_STATUS_RX_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = Size; + + /* Rx FIFO */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_DMA_LEVEL_0; + + /* TX Disable */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Receive Start */ + HAL_OSPI_CS_Select(hospi); + + + HAL_DMA_Start(hospi->HDMA_Rx, (uint32_t)&hospi->Instance->DAT, (uint32_t)pData, Size); + + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_DMA_REQ_EN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Simultaneously transmits and recieve an amount of data in loop mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pTxData : Pointer to transmit data buffer +*@param : pRxData : Pointer to recieve data buffer +*@param : Size : Amount of data to be sent and receive +*@param : Timeout : sent and receive timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_SimultTransmitReceive(OSPI_HandleTypeDef *hospi, uint8_t *pTxData, \ + uint8_t *pRxData, uint32_t Size, uint32_t Timeout) +{ + __IO uint32_t TxFlag = 1U, uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + hospi->Tx_Count = 0; + hospi->Rx_Count = 0; + hospi->Tx_Buffer = pTxData; + hospi->Rx_Buffer = pRxData; + hospi->Tx_Size = Size; + hospi->Rx_Size = Size; + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = hospi->Tx_Size; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + TxFlag = 1; + + + while((hospi->Tx_Size>0) || (hospi->Rx_Size>0)) + { + /* Wait Tx FIFO Not Full */ + if((!(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL)) && (hospi->Tx_Size>0) && (TxFlag == 1U)) + { + hospi->Instance->DAT = hospi->Tx_Buffer[hospi->Tx_Count++]; + hospi->Tx_Size--; + TxFlag = 0; + } + + /* Wait Rx FIFO Not Empty */ + if((!(hospi->Instance->STATUS & OSPI_STATUS_RX_FIFO_EMPTY)) && (hospi->Rx_Size>0)) + { + hospi->Rx_Buffer[hospi->Rx_Count++] = hospi->Instance->DAT; + hospi->Rx_Size--; + TxFlag = 1U; + } + + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + + Status = HAL_OK; + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + + +/****************************************************************************** +*@brief : Transmit data through FIFO Half Word mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_TransmitByHalfWord(OSPI_HandleTypeDef *hospi, uint16_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = (Size * 2); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= ~OSPI_RX_CTL_RX_EN; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size > 0) + { + /* Wait Tx FIFO Not Full */ + while(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + hospi->Instance->DAT = *pData++; + Size--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + Status = HAL_OK; + + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + + return Status; +} + +/****************************************************************************** +*@brief : Transmit data through FIFO Word mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_TransmitByWord(OSPI_HandleTypeDef *hospi, uint32_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = (Size * 4); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= ~OSPI_RX_CTL_RX_EN; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size > 0) + { + /* Wait Tx FIFO Not Full */ + while(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + hospi->Instance->DAT = *pData++; + Size--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + Status = HAL_OK; + + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + + return Status; +} + + +/****************************************************************************** +*@brief : Receive an amount of data through FIFO HalfWord mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_ReceiveByHalfWord(OSPI_HandleTypeDef *hospi, uint16_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = (Size * 2); + + /* TX Disable */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Receive Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size) + { + /* have no timeout */ + if (uiTimeout == 0) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY); + } + else + { + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY) + { + if (uiTimeout-- == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pData++ = hospi->Instance->DAT; + Size--; + uiTimeout = Timeout; + } + + Status = HAL_OK; + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Receive End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data through FIFO Word mode. +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_ReceiveByWord(OSPI_HandleTypeDef *hospi, uint32_t *pData, \ + uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status = HAL_OK; + __IO uint32_t uiTimeout; + + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if (pData == NULL) return HAL_ERROR; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + hospi->Instance->BATCH = (Size * 4); + + /* TX Disable */ + hospi->Instance->TX_CTL &= ~OSPI_TX_CTL_TX_EN; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* Receive Start */ + HAL_OSPI_CS_Select(hospi); + + while(Size) + { + /* have no timeout */ + if (uiTimeout == 0) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY); + } + else + { + while (hospi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY) + { + if (uiTimeout-- == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pData++ = hospi->Instance->DAT; + Size--; + uiTimeout = Timeout; + } + + Status = HAL_OK; + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Receive End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : transmits an amount of data in FIFO Half Word mode before receiving an amount of data through FIFO Byte +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pTxData : Pointer to transmit data buffer +*@param : pRxData : Pointer to recieve data buffer +*@param : TxSize : Amount of data to be sent +*@param : RxSize : Amount of data to be receive +*@param : Timeout : sent and receive timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Transmit_Recieve_ByByte(OSPI_HandleTypeDef *hospi, uint8_t *pTxData, uint32_t TXSize, \ + uint8_t *pRxData, uint32_t RXSize, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Clear RX FIFO */ + SET_BIT(hospi->Instance->RX_CTL, OSPI_RX_CTL_RX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->RX_CTL, OSPI_RX_CTL_RX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = TXSize; + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + uiTimeout = Timeout; + + while(TXSize) + { + /* Wait Tx FIFO Not Full */ + while(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + Status = HAL_TIMEOUT; + return Status; + } + } + } + hospi->Instance->DAT = *pTxData++; + TXSize--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Set Data Size */ + hospi->Instance->BATCH = RXSize; + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* recv reStart */ + HAL_OSPI_CS_Select(hospi); + + uiTimeout = Timeout; + + while(RXSize) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & OSPI_STATUS_RX_FIFO_EMPTY) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pRxData++ = hospi->Instance->DAT; + RXSize--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : transmits an amount of data in FIFO Half Word mode before receiving an amount of data through FIFO Half Word +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pTxData : Pointer to transmit data buffer +*@param : pRxData : Pointer to recieve data buffer +*@param : TxSize : Amount of data to be sent +*@param : RxSize : Amount of data to be receive +*@param : Timeout : sent and receive timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Transmit_Recieve_ByHalfWord(OSPI_HandleTypeDef *hospi, uint16_t *pTxData, \ + uint32_t TXSize, uint16_t *pRxData, uint32_t RXSize, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Clear RX FIFO */ + SET_BIT(hospi->Instance->RX_CTL, OSPI_RX_CTL_RX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->RX_CTL, OSPI_RX_CTL_RX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = (TXSize * 2); + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + uiTimeout = Timeout; + + while(TXSize) + { + /* Wait Tx FIFO Not Full */ + while(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + Status = HAL_TIMEOUT; + return Status; + } + } + } + hospi->Instance->DAT = *pTxData++; + TXSize--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Set Data Size */ + hospi->Instance->BATCH = (RXSize * 2); + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* recv reStart */ + HAL_OSPI_CS_Select(hospi); + + uiTimeout = Timeout; + + while(RXSize) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & OSPI_STATUS_RX_FIFO_EMPTY) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pRxData++ = hospi->Instance->DAT; + RXSize--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : transmits an amount of data in FIFO Word mode before receiving an amount of data through FIFO Word +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : pTxData : Pointer to transmit data buffer +*@param : pRxData : Pointer to recieve data buffer +*@param : TxSize : Amount of data to be sent +*@param : RxSize : Amount of data to be receive +*@param : Timeout : sent and receive timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_Transmit_Recieve_ByWord(OSPI_HandleTypeDef *hospi, uint32_t *pTxData, uint32_t TXSize, \ + uint32_t *pRxData, uint32_t RXSize, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Clear TX FIFO */ + SET_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->TX_CTL, OSPI_TX_CTL_TX_FIFO_RESET); + + /* Clear RX FIFO */ + SET_BIT(hospi->Instance->RX_CTL, OSPI_RX_CTL_RX_FIFO_RESET); + CLEAR_BIT(hospi->Instance->RX_CTL, OSPI_RX_CTL_RX_FIFO_RESET); + + /* Set Data Size */ + hospi->Instance->BATCH = (TXSize * 4); + + /* Tx Enable */ + hospi->Instance->TX_CTL |= OSPI_TX_CTL_TX_EN; + + /* Transmit Start */ + HAL_OSPI_CS_Select(hospi); + + uiTimeout = Timeout; + + while(TXSize) + { + /* Wait Tx FIFO Not Full */ + while(hospi->Instance->STATUS & OSPI_STATUS_TX_FIFO_FULL) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_TX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + Status = HAL_TIMEOUT; + return Status; + } + } + } + hospi->Instance->DAT = *pTxData++; + TXSize--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_TX_BATCH_DONE)); + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + /* Tx Disable */ + hospi->Instance->TX_CTL &= (~OSPI_TX_CTL_TX_EN); + + /* Set Data Size */ + hospi->Instance->BATCH = (RXSize * 4); + + /* Rx Enable */ + hospi->Instance->RX_CTL |= OSPI_RX_CTL_RX_EN; + + /* recv reStart */ + HAL_OSPI_CS_Select(hospi); + + uiTimeout = Timeout; + + while(RXSize) + { + /* Wait Rx FIFO Not Empty */ + while (hospi->Instance->STATUS & OSPI_STATUS_RX_FIFO_EMPTY) + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + *pRxData++ = hospi->Instance->DAT; + RXSize--; + uiTimeout = Timeout; + } + + /* Wait Transmit Done */ + while (!(hospi->Instance->STATUS & OSPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_RX_BATCH_DONE); + SET_BIT(hospi->Instance->STATUS, OSPI_STATUS_BATCH_DONE); + /* Rx Disable */ + hospi->Instance->RX_CTL &= (~OSPI_RX_CTL_RX_EN); + + /* Transmit End */ + HAL_OSPI_CS_Release(hospi); + + return Status; +} + +/****************************************************************************** +*@brief : Get Tx state. +* +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: OSPI Tx State +******************************************************************************/ +uint8_t HAL_OSPI_GetTxState(OSPI_HandleTypeDef *hospi) +{ + return hospi->TxState; +} + +/****************************************************************************** +*@brief : Get Rx state. +* +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: OSPI Rx State +******************************************************************************/ +uint8_t HAL_OSPI_GetRxState(OSPI_HandleTypeDef *hospi) +{ + return hospi->RxState; +} + +/****************************************************************************** +*@brief : OSPI Wire Config +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : X_Mode : 1x/2x/4x/8x Mode, see@ref X_MODE +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_WireConfig(OSPI_HandleTypeDef *hospi, uint32_t X_Mode) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_X_MODE(X_Mode)); + + /* Set OSPI X_Mode */ + hospi->Instance->CTL = ((hospi->Instance->CTL) & (~SPI_CTL_X_MODE_Msk)) | X_Mode; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : OSPI Transmission rate mode +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : mode : OSPI_DTRM_STR or OSPI_DTRM_DTR, see@ref OSPI_DTR_STR +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_TransmitRateMode(OSPI_HandleTypeDef *hospi, uint32_t mode) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_DTRM(mode)); + + /* Set OSPI DTRM */ + hospi->Instance->CTL = ((hospi->Instance->CTL) & (~OSPI_CTL_DTRM_Msk)) | mode; + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : OSPI FIFO Write mode +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : mode : Byte/Halfword/Word Mode, see@ref OSPI_FIFO_Mode +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_FifoWriteMode(OSPI_HandleTypeDef *hospi, uint32_t mode) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_FIFO_MODE(mode)); + + /* Set OSPI FIFO Write Mode */ + hospi->Instance->CTL = ((hospi->Instance->CTL) & (~OSPI_CTL_FW_MODE_Msk)) | (mode << OSPI_CTL_FW_MODE_Pos); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : OSPI FIFO Read mode +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : mode : Byte/Halfword/Word Mode, see@ref OSPI_FIFO_Mode +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_FifoReadMode(OSPI_HandleTypeDef *hospi, uint32_t mode) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_FIFO_MODE(mode)); + + /* Set OSPI FIFO Write Mode */ + hospi->Instance->CTL = ((hospi->Instance->CTL) & (~OSPI_CTL_FR_MODE_Msk)) | (mode << OSPI_CTL_FR_MODE_Pos); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : set APM OPI Memory Dummy Clock +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : APMClock : see@ref OSPI_APM_Dummy_Clock +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_APMDummyClock(OSPI_HandleTypeDef *hospi, uint32_t APMClock) +{ + assert_param(IS_OSPI_APM_DUMMY_CLOCK(APMClock)); + /* Clear APMD_CLK bit */ + hospi->Instance->CTL &= (~OSPI_CTL_APMD_CLK_Msk ); + /* Set APMD_CLK */ + hospi->Instance->CTL |= APMClock; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send output delay +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : Outdelay : see@ref OSPI_TX_OUT_Delay +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_TxOutDelay(OSPI_HandleTypeDef *hospi, uint32_t Outdelay) +{ + assert_param(IS_OSPI_TX_OUT_DELAY(Outdelay)); + /* Clear OUTDLY bit */ + hospi->Instance->TX_CTL &= (~(OSPI_TX_CTL_OUTDLY_Msk)); + /* Set OUTDLY */ + hospi->Instance->TX_CTL |= (Outdelay); + + return HAL_OK; + +} + +/****************************************************************************** +*@brief : Receive sampling delay +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : Outdelay : see@ref OSPI_TX_OUT_Delay +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_RxSampleDelay(OSPI_HandleTypeDef *hospi, uint32_t Sampledelay) +{ + assert_param(IS_OSPI_SAMPLE_SHIFT(Sampledelay)); + /* Clear SSHIFT bit */ + hospi->Instance->RX_CTL &= ~(OSPI_RX_CTL_SSHIFT_Msk); + /* Set SSHIFT */ + hospi->Instance->RX_CTL |= (Sampledelay << OSPI_RX_CTL_SSHIFT_Pos); + + return HAL_OK; + +} + + +/****************************************************************************** +*@brief : Memory mode enabled or disabled +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : state : see@ref OSPI_Memory_State +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_MemoryEnableDisable(OSPI_HandleTypeDef *hospi, uint32_t state) +{ + assert_param(IS_OSPI_MEMORY_STATE(state)); + + if(state == MEMOACC1_MEMORY_DISABLE) + { + hospi->Instance->MEMO_ACC1 &= ~MEMOACC1_MEMORY_ENABLE; + } + else + { + hospi->Instance->MEMO_ACC1 |= MEMOACC1_MEMORY_ENABLE; + } + + return HAL_OK; + +} + + +/****************************************************************************** +*@brief : DQS output enable or disable +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : state : see@ref OSPI_DQS_Output +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_DQSOutputEnableDisable(OSPI_HandleTypeDef *hospi, uint32_t state) +{ + assert_param(IS_OSPI_DQSOE(state)); + + if(state == OSPI_DQSOE_DISABLE) + { + hospi->Instance->CTL &= ~OSPI_DQSOE_ENABLE; + } + else + { + hospi->Instance->CTL |= OSPI_DQSOE_ENABLE; + } + + return HAL_OK; + +} + + +/****************************************************************************** +*@brief : DQS Sample enable or disable +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : Outdelay : see@ref OSPI_DQS_Smaple +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_DQSSampleEnableDisable(OSPI_HandleTypeDef *hospi, uint32_t state) +{ + assert_param(IS_OSPI_DQS_SAMPLE(state)); + + if(state == OSPI_DQS_SAMPLE_DISABLE) + { + hospi->Instance->RX_CTL &= ~OSPI_DQS_SAMPLE_ENABLE; + } + else + { + hospi->Instance->RX_CTL |= OSPI_DQS_SAMPLE_ENABLE; + } + + return HAL_OK; + +} + + +/****************************************************************************** +*@brief : Initialize the OSPI module Octal communication +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@param : DataMaskMode: see@ref OSPI_Data_Mask_Mode. +*@param : DataMaskCtrl: see@ref OSPI_DataMask_Ctrl. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_OSPI_DataMaskConfig(OSPI_HandleTypeDef *hospi, uint32_t DataMaskMode, uint32_t DataMaskCtrl) +{ + /* Check OSPI Parameter */ + assert_param (IS_OSPI_ALL_INSTANCE(hospi->Instance)); + assert_param(IS_OSPI_DM(DataMaskMode)); + assert_param(IS_OSPI_DMCTRL_ADDR(DataMaskCtrl)); + + /* Clear DTRMDM_ENDMCTRLMem_Mode bit */ + hospi->Instance->CTL &= (~(OSPI_CTL_DM_EN | OSPI_CTL_DMCTRL)); + + /* Set DM_ENDMCTRL */ + hospi->Instance->CTL |= ((DataMaskMode) | (DataMaskCtrl)); + + + return HAL_OK; +} + + + + + +#endif //HAL_OSPI_MODULE_ENABLED + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_pmu.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_pmu.c new file mode 100644 index 0000000000000000000000000000000000000000..c4bc7d3122a0a6f0bf2293f87aeb879bb3697b1b --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_pmu.c @@ -0,0 +1,533 @@ + +/****************************************************************************** +*@file : hal_pmu.c +*@brief : PMU HAL module driver. +******************************************************************************/ +#include "hal.h" + + +#ifdef HAL_PMU_MODULE_ENABLED + +/****************************************************************************** +* @brief : PMU Initiation. +* @param : none +* @return: none +******************************************************************************/ +void HAL_PMU_Init(void) +{ + //PMU CLK Enable + __HAL_RCC_PMU_CLK_ENABLE(); + + HAL_SimpleDelay(10); +} + +/****************************************************************************** +* @brief : enter sleep mode. +* @param : mode: Event wake-up or interrupt wake-up +* @return: none +******************************************************************************/ +void HAL_PMU_EnterSleep(uint32_t mode) +{ + /* clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + if(mode == WAIT_FOR_INT) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + /*Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + +} + +/****************************************************************************** +* @brief : enter stop mode. +* @param : mode: Event wake-up or interrupt wake-up +* @return: none +******************************************************************************/ +void HAL_PMU_EnterStop(uint32_t mode) +{ + HAL_PMU_ClearWakeupStatus(ALL_WANKEUP_STATUS); + + MODIFY_REG(PMU->CTRL0, PMU_CTRL0_LPMS_Msk, PMU_CTRL0_LPMS_STOP); + + HAL_SimpleDelay(1000);//Waiting for PMU area clock synchronization + + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); // Set SLEEPDEEP bit of Cortex System Control Register + + if(mode == WAIT_FOR_INT) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + /* Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/****************************************************************************** +* @brief : enter standby mode. +* @param : mode: Event wake-up or interrupt wake-up +* @return: none +******************************************************************************/ +void HAL_PMU_EnterStandbyMode(uint32_t mode) +{ + HAL_PMU_ClearWakeupStatus(ALL_WANKEUP_STATUS); + + MODIFY_REG(PMU->CTRL0, PMU_CTRL0_LPMS_Msk, PMU_CTRL0_LPMS_STANDBY);//Standby Mode + + HAL_SimpleDelay(1000);//Waiting for PMU area clock synchronization + + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); // Set SLEEPDEEP bit of Cortex System Control Register + + if(mode == WAIT_FOR_INT) + { + /* Wait For Interrupt */ + __WFI(); + } + else + { + /* Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/****************************************************************************** +*@brief : Initialize the WakeupIO MSP: CLK, GPIO +*@param : none. +*@return: none +******************************************************************************/ +__weak void HAL_PMU_WakeupIO_MspInit(PMU_WakeUpIo_t wakeup_io) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(NULL); +} + +/****************************************************************************** +* @brief : wakeup source select. +* @param : wakeup_io: wakeup source select(PMU_WAKEUP1 PMU_WAKEUP2 ...) +* @param : polarity: 0(high level), 1(low level). +* @return: none +******************************************************************************/ +void HAL_PMU_WakeupIOInit(PMU_WakeUpIo_t wakeup_io, PMU_WakeUpPolarity_t polarity) +{ + switch (wakeup_io) + { + case PMU_WAKEUP1: + case PMU_WAKEUP2: + case PMU_WAKEUP3: + case PMU_WAKEUP4: + case PMU_WAKEUP5: + { + HAL_PMU_WakeupIO_MspInit(wakeup_io); + /* Wakeup IO Filter Enable */ + __HAL_RCC_RTC_CLK_ENABLE(); + PMU->CTRL2 |= wakeup_io << PMU_CTRL2_WUXFILEN_Pos; + + /* Wakeup IO Enable */ + PMU->CTRL2 |= wakeup_io; + + if (polarity) + { + PMU->CTRL3 |= wakeup_io;//low level + } + else + { + PMU->CTRL3 &= (~wakeup_io);//high level + } + + } + break; + + default: break; + } +} + +/****************************************************************************** +* @brief : DeInitialize the Wakeup IO. +* @param : wakeup_io: wakeup source select(PMU_WAKEUP1 PMU_WAKEUP2 ...) +* @return: none +******************************************************************************/ +void HAL_PMU_WakeupIODeInit(PMU_WakeUpIo_t wakeup_io) +{ + /* Wakeup IO Filter Disable */ + PMU->CTRL2 &= ~(wakeup_io << PMU_CTRL2_WUXFILEN_Pos); + + /* Wakeup IO Disable */ + PMU->CTRL2 &= (~wakeup_io); +} + +/****************************************************************************** +* @brief : wakeup source select. +* @param : Wakeup_rtc: wakeup source select(RTC_WAKEUP_DATE...) +* @return: none +******************************************************************************/ +void HAL_PMU_StandbyWakeupRTCConfig(PMU_WakeUpRtc_t wakeup_rtc) +{ + switch (wakeup_rtc) + { + case STANDBY_WAKEUP_WUTIE: + case STANDBY_WAKEUP_STAMP2: + case STANDBY_WAKEUP_STAMP1: + case STANDBY_WAKEUP_32S: + case STANDBY_WAKEUP_ALARM: + case STANDBY_WAKEUP_1KHZ: + case STANDBY_WAKEUP_256HZ: + case STANDBY_WAKEUP_64HZ: + case STANDBY_WAKEUP_16HZ: + case STANDBY_WAKEUP_8HZ: + case STANDBY_WAKEUP_4HZ: + case STANDBY_WAKEUP_2HZ: + case STANDBY_WAKEUP_SEC: + case STANDBY_WAKEUP_MIN: + case STANDBY_WAKEUP_HOUR: + case STANDBY_WAKEUP_DATE: + { + //Enable RTC CLK + __HAL_RCC_RTC_CLK_ENABLE(); + + //Clear flags + SET_BIT(PMU->STCLR, (PMU_STCLR_CRTCWUF_Msk | PMU_STCLR_CSBF_Msk)); + + /* RTC domain write enable */ + SET_BIT(PMU->CTRL0,PMU_CTRL0_RTCWE); + RTC->SR = wakeup_rtc; + RTC->IE |= wakeup_rtc; + + }break; + + default: break; + } +} + +/****************************************************************************** +* @brief : Release the selected RTC wakeup source. +* @param : wakeup_rtc: wakeup source select(RTC_WAKEUP_DATE...) +* @return: none +******************************************************************************/ +void HAL_PMU_StandbyWakeupRTCRelease(PMU_WakeUpRtc_t wakeup_rtc) +{ + switch (wakeup_rtc) + { + case STANDBY_WAKEUP_WUTIE: + case STANDBY_WAKEUP_STAMP2: + case STANDBY_WAKEUP_STAMP1: + case STANDBY_WAKEUP_32S: + case STANDBY_WAKEUP_ALARM: + case STANDBY_WAKEUP_1KHZ: + case STANDBY_WAKEUP_256HZ: + case STANDBY_WAKEUP_64HZ: + case STANDBY_WAKEUP_16HZ: + case STANDBY_WAKEUP_8HZ: + case STANDBY_WAKEUP_4HZ: + case STANDBY_WAKEUP_2HZ: + case STANDBY_WAKEUP_SEC: + case STANDBY_WAKEUP_MIN: + case STANDBY_WAKEUP_HOUR: + case STANDBY_WAKEUP_DATE: + { + //Enable RTC CLK + __HAL_RCC_RTC_CLK_ENABLE(); + /* RTC domain write enable */ + SET_BIT(PMU->CTRL0,PMU_CTRL0_RTCWE); + + RTC->SR = wakeup_rtc; + RTC->IE &= (~wakeup_rtc); + + }break; + + default: break; + } +} + +/********************************************************************************* +* @brief : Check MCU have entered standby mode +* @param : none +* @return: 0: Not Enter Standby Mode,1: Entered Standby Mode +**********************************************************************************/ +bool HAL_PMU_CheckStandbyStatus(void) +{ + if (PMU->SR & PMU_SR_SBF_Msk) + { + return true; + } + else + { + return false; + } +} + +/****************************************************************************** +* @brief : Get MCU Wakeup Source. +* @param : none +* @return: Wakeup Source(PMU_SR_WUPFX_WKUP1PMU_SR_WUPFX_WKUP2 ...) +******************************************************************************/ +uint32_t HAL_PMU_GetWakeupSource(void) +{ + return PMU->SR; +} + +/****************************************************************************** +* @brief : Clear MCU Wakeup Status. +* @param : status:Wakeup Source(PMU_SR_WUPFX_WKUP1PMU_SR_WUPFX_WKUP2 ...) +* @return: none +******************************************************************************/ +void HAL_PMU_ClearWakeupStatus(uint32_t status) +{ + PMU->STCLR = status; +} + +/****************************************************************************** +* @brief : LVD Enable. +* @param : voltage: LVD threshold voltage selection (PMU_CTRL1_LVD_SEL_171~PMU_CTRL1_LVD_SEL_290) +* @param : filter: LVD filter time (PMU_CTRL1_FLT_TIME_1~PMU_CTRL1_FLT_TIME_4095) +* @param : filter_en: Digital filter enable (PMU_CTRL1_LVD_FLTEN) +* @return: none +******************************************************************************/ +void HAL_PMU_LvdEnable(uint32_t voltage, uint32_t filter, uint32_t filter_en) +{ + assert_param(IS_PMU_LVD_VOLTAGE(voltage)); + assert_param(IS_PMU_LVD_FILTER(filter)); + PMU->CTRL1 = ((voltage) | (PMU_CTRL1_LVDEN) | (filter) | (filter_en)); + HAL_SimpleDelay(100); +} + +/****************************************************************************** +* @brief : LVD disable. +* @param : none +* @return: none +******************************************************************************/ +void HAL_PMU_LvdDisable(void) +{ + PMU->CTRL1 &= (~PMU_CTRL1_LVDEN); +} + +/****************************************************************************** +* @brief : BOR Reset Enable. +* @param : voltage: BOR voltage selection (PMU_CTRL2_BOR_CFG_2V0~PMU_CTRL2_BOR_CFG_2V77) +* @return: none +******************************************************************************/ +void HAL_PMU_BorResetEnable(uint32_t voltage) +{ + assert_param(IS_PMU_BOR_VOLTAGE(voltage)); + + PMU->CTRL2 = (PMU->CTRL2 & (~(PMU_CTRL2_BORCFG))) | ((voltage) | (PMU_CTRL2_BOREN) | (PMU_CTRL2_BORRSTEN)); + HAL_SimpleDelay(100); +} + +/****************************************************************************** +* @brief : BOR Reset Disable. +* @param : none +* @return: none +******************************************************************************/ +void HAL_PMU_BorResetDisable(void) +{ + PMU->CTRL2 &= (~((PMU_CTRL2_BOREN) | (PMU_CTRL2_BORRSTEN))); + HAL_SimpleDelay(100); +} + +/****************************************************************************** +* @brief : Set the wake-up waiting time of Stop mode. +* @param : stopWaitTime: STOP wake-up waiting time +* @return: none +******************************************************************************/ +void HAL_PMU_StopWaitTime(uint32_t stopWaitTime) +{ + assert_param(IS_PMU_STOP_WAKE_WAIT(stopWaitTime)); + PMU->CTRL0 &= (~PMU_CTRL0_STOPWPT_Msk); + PMU->CTRL0 |= stopWaitTime << PMU_CTRL0_STOPWPT_Pos; +} + +/****************************************************************************** +* @brief : Set the wake-up waiting time of standby mode. +* @param : standbyWaitTime: standby wake-up waiting time +* @return: none +******************************************************************************/ +void HAL_PMU_StandbypWaitTime(uint32_t standbyWaitTime) +{ + assert_param(IS_PMU_STANDBY_WAKE_WAIT(standbyWaitTime)); + PMU->CTRL2 &= (~PMU_CTRL2_STDBYWPT_Msk); + PMU->CTRL2 |= standbyWaitTime << PMU_CTRL2_STDBYWPT_Pos; +} + +/****************************************************************************** +* @brief: STANDBY domain IO function selection. +* @param: PMU_Pin: specifies the STANDBY domain IO Pin. +* @param: PMU_Func: Specify the IO pin function of STANDBY domain. +* @return: None +******************************************************************************/ +void HAL_PMU_StandbyDomainPinConfig(uint32_t PMU_Pin, uint32_t PMU_Func) +{ + /* Check the parameters */ + assert_param(IS_PMU_PIN(PMU_Pin)); + assert_param(IS_PMU_PIN_FUNCTION(PMU_Func)); + + /* PC13 pin function selection */ + if(PMU_Pin == PMU_PIN_PC13) + { + /* Clear PC13_SEL bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC13SEL_Msk); + + /* Set PC13_SEL bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_Func << PMU_IOSEL_PC13SEL_Pos); + } + /* PC14 pin function selection */ + else if(PMU_Pin == PMU_PIN_PC14) + { + /* Clear PC14_SEL bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC14SEL_Msk); + + /* Set PC14_SEL bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_Func << PMU_IOSEL_PC14SEL_Pos); + } + /* PC15 pin function selection */ + else if(PMU_Pin == PMU_PIN_PC15) + { + /* Clear PC15_SEL bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC15SEL_Msk); + + /* Set PC15_SEL bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_Func << PMU_IOSEL_PC15SEL_Pos); + } + /* PI8 pin function selection */ + else + { + /* Clear PI8_SEL bits */ + PMU->IOSEL &= (~PMU_IOSEL_PI8SEL_Msk); + + /* Set PI8_SEL bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_Func << PMU_IOSEL_PI8SEL_Pos); + + } +} + +/****************************************************************************** +* @brief: Set STANDBY domain IO value. +* @param: PMU_Pin: specifies the STANDBY domain IO Pin. +* @param: PMU_PinValue: specifies the STANDBY domain Pin Value. +* @return: None +******************************************************************************/ +void HAL_PMU_SetStandbyDomainPinValue(uint32_t PMU_Pin, uint32_t PMU_PinValue) +{ + /* Check the parameters */ + assert_param(IS_PMU_PIN(PMU_Pin)); + assert_param(IS_PMU_PIN_VALUE(PMU_PinValue)); + + /* PC13 pin function selection */ + if(PMU_Pin == PMU_PIN_PC13) + { + /* Clear PC13_Value bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC13VALUE_Msk); + + /* Set PC13_Value bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_PinValue << PMU_IOSEL_PC13VALUE_Pos); + } + /* PC14 pin function selection */ + else if(PMU_Pin == PMU_PIN_PC14) + { + /* Clear PC14_Value bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC14VALUE_Msk); + + /* Set PC14_Value bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_PinValue << PMU_IOSEL_PC14VALUE_Pos); + } + /* PC15 pin function selection */ + else if(PMU_Pin == PMU_PIN_PC15) + { + /* Clear PC15_Value bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC15VALUE_Msk); + + /* Set PC15_Value bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_PinValue << PMU_IOSEL_PC15VALUE_Pos); + } + /* PI8 pin function selection */ + else + { + /* Clear PI8_Value bits */ + PMU->IOSEL &= (~PMU_IOSEL_PI8VALUE_Msk); + + /* Set PI8_Value bits according to PMU_Func value */ + PMU->IOSEL |= (PMU_PinValue << PMU_IOSEL_PI8VALUE_Pos); + } +} + +/****************************************************************************** +* @brief: Get STANDBY domain IO value. +* @param: PMU_Pin: specifies the STANDBY domain IO Pin. +* @return: Pin Value +******************************************************************************/ +uint32_t HAL_PMU_GetStandbyDomainPinValue(uint32_t PMU_Pin) +{ + uint32_t tmp_value = 0; + /* Check the parameters */ + assert_param(IS_PMU_PIN(PMU_Pin)); + + /* get PC13 pin value */ + if(PMU_Pin == PMU_PIN_PC13) + { + tmp_value = ((PMU->IOSEL & PMU_IOSEL_PC13VALUE_Msk) >> PMU_IOSEL_PC13VALUE_Pos); + } + /* get PC14 pin value */ + else if(PMU_Pin == PMU_PIN_PC14) + { + tmp_value = ((PMU->IOSEL & PMU_IOSEL_PC14VALUE_Msk) >> PMU_IOSEL_PC14VALUE_Pos); + } + /* get PC15 pin value */ + else if(PMU_Pin == PMU_PIN_PC15) + { + tmp_value = ((PMU->IOSEL & PMU_IOSEL_PC15VALUE_Msk) >> PMU_IOSEL_PC15VALUE_Pos); + } + /* get PI8 pin value */ + else + { + tmp_value = ((PMU->IOSEL & PMU_IOSEL_PI8VALUE_Msk) >> PMU_IOSEL_PI8VALUE_Pos); + } + return tmp_value; +} + + +/****************************************************************************** +*@brief : PMU domain pin PC13 output type. +*@param : type: output type. +*@return: None +******************************************************************************/ +void HAL_PMU_StandbyDomainPinPC13OutputType(uint32_t type) +{ + /* Check the parameters */ + assert_param(IS_PMU_PIN_PC13_OUTPUT(type)); + + /* Clear PC13_Value bits */ + PMU->IOSEL &= (~PMU_IOSEL_PC13VALUE_Msk); + + /* Set PC13_Value bits according to type value */ + PMU->IOSEL |= (type << PMU_IOSEL_PC13VALUE_Pos); +} + +#endif + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_rcc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_rcc.c new file mode 100644 index 0000000000000000000000000000000000000000..572ce43d9e2d88bd78c3010a37188fc3c69b7f09 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_rcc.c @@ -0,0 +1,3087 @@ +/****************************************************************************** +*@file : hal_rcc.c +*@brief : RCC HAL module driver. +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_RCC_MODULE_ENABLED + +__attribute__((weak)) void HAL_RCC_ReadyIRQHandler(void) +{ + // RCH clock ready + if ((RCC->CIR & (RCC_CIR_RCHRDYIE | RCC_CIR_RCHRDYIF)) == (RCC_CIR_RCHRDYIE | RCC_CIR_RCHRDYIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_RCHRDYIC; + HAL_RCC_RCHReadyCallback(); + } + + // XTH clock ready + if ((RCC->CIR & (RCC_CIR_XTHRDYIE | RCC_CIR_XTHRDYIF)) == (RCC_CIR_XTHRDYIE | RCC_CIR_XTHRDYIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_XTHRDYIC; + HAL_RCC_XTHReadyCallback(); + } + + // PLL1 clock ready + if ((RCC->CIR & (RCC_CIR_PLL1LOCKIE | RCC_CIR_PLL1LOCKIF)) == (RCC_CIR_PLL1LOCKIE | RCC_CIR_PLL1LOCKIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_PLL1LOCKIC; + HAL_RCC_PLL1ReadyCallback(); + } + + // PLL2 clock ready + if ((RCC->CIR & (RCC_CIR_PLL2LOCKIE | RCC_CIR_PLL2LOCKIF)) == (RCC_CIR_PLL2LOCKIE | RCC_CIR_PLL2LOCKIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_PLL2LOCKIC; + HAL_RCC_PLL2ReadyCallback(); + } + + // PLL3 clock ready + if ((RCC->CIR & (RCC_CIR_PLL3LOCKIE | RCC_CIR_PLL3LOCKIF)) == (RCC_CIR_PLL3LOCKIE | RCC_CIR_PLL3LOCKIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_PLL3LOCKIC; + HAL_RCC_PLL3ReadyCallback(); + } + + // RCL clock ready + if ((RCC->CIR & (RCC_CIR_RCLRDYIE | RCC_CIR_RCLRDYIF)) == (RCC_CIR_RCLRDYIE | RCC_CIR_RCLRDYIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_RCLRDYIC; + HAL_RCC_RCLReadyCallback(); + } + + // XTL clock ready + if ((RCC->CIR & (RCC_CIR_XTLRDYIE | RCC_CIR_XTLRDYIF)) == (RCC_CIR_XTLRDYIE | RCC_CIR_XTLRDYIF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_XTLRDYIC; + HAL_RCC_XTLReadyCallback(); + } +} + +__attribute__((weak)) void HAL_RCC_XTHStopIRQHandler(void) +{ + // XTH stop + if ((RCC->CIR & (RCC_CIR_XTHSDIE | RCC_CIR_XTHSDF)) == (RCC_CIR_XTHSDIE | RCC_CIR_XTHSDF)) + { + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_XTHSDIC; + HAL_RCC_XTHStopCallback(); + } +} + +__attribute__((weak)) void HAL_RCC_XTLStopIRQHandler(void) +{ + // XTL stop + if ((RCC->CIR & (RCC_CIR_XTLSDIE | RCC_CIR_XTLSDF)) == (RCC_CIR_XTLSDIE | RCC_CIR_XTLSDF)) + { + RCC->STDBYCTRL &= ~RCC_STDBYCTRL_XTLSDEN; + RCC->STDBYCTRL &= ~RCC_STDBYCTRL_XTLEN; + RCC->CIR = (RCC->CIR & ~RCC_IT_CLEAR_FLAG_MASK) | RCC_CIR_XTLSDIC; + HAL_RCC_XTLStopCallback(); + } +} + +/****************************************************************************** +*@brief : RCH clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_RCHReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : RCL clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_RCLReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : XTH clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_XTHReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : XTL clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_XTLReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : PLL1 clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_PLL1ReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : PLL2 clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_PLL2ReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : PLL3 clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_PLL3ReadyCallback(void) +{ +} + +/****************************************************************************** +*@brief : PLL3 clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_XTHStopCallback(void) +{ +} + +/****************************************************************************** +*@brief : PLL3 clock stable interrupt callback. +*@param : None +*@return: None +******************************************************************************/ +__attribute__((weak)) void HAL_RCC_XTLStopCallback(void) +{ +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInit) +{ + /* Check the parameters */ + assert_param(IS_RCC_OSC_TYPE(RCC_OscInit->OscType)); + + /*------------------------------- RCH Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_RCH) + { + if (HAL_RCC_RCHConfig(RCC_OscInit->RCH, RCC_OscInit->RCHDiv16) != HAL_OK) + return HAL_ERROR; + } + + /*------------------------------- RCL Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_RCL) + { + if (HAL_RCC_RCLConfig(RCC_OscInit->RCL) != HAL_OK) + return HAL_ERROR; + } + + /*------------------------------- XTH Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_XTH) + { + if (HAL_RCC_XTHConfig(RCC_OscInit->XTH, RCC_OscInit->XTHBypass) != HAL_OK) + return HAL_ERROR; + } + + /*------------------------------- XTL Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_XTL) + { + if (HAL_RCC_XTLConfig(RCC_OscInit->XTL, RCC_OscInit->XTLBypass) != HAL_OK) + return HAL_ERROR; + } + + /*------------------------------- PLL1 Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_PLL1) + { + if (RCC_OscInit->PLL1.SSC == DISABLE) + { + if (HAL_RCC_PLL1Config(RCC_OscInit->PLL1.PLL, RCC_OscInit->PLL1.Source, RCC_OscInit->PLL1.PLLN, \ + RCC_OscInit->PLL1.PLLF, RCC_OscInit->PLL1.PLLP, RCC_OscInit->PLL1.PLLQ) != HAL_OK) + return HAL_ERROR; + } + else + { + if (HAL_RCC_PLL1SSCConfig(RCC_OscInit->PLL1.PLL, RCC_OscInit->PLL1.Source, RCC_OscInit->PLL1.PLLN, \ + RCC_OscInit->PLL1.PLLF, RCC_OscInit->PLL1.PLLP, RCC_OscInit->PLL1.PLLQ, \ + RCC_OscInit->PLL1.SSC, RCC_OscInit->PLL1.SSCMode, RCC_OscInit->PLL1.SSCSpectrum, \ + RCC_OscInit->PLL1.SSCStep) != HAL_OK) + return HAL_ERROR; + } + + if (HAL_RCC_PLL1PCLKConfig(RCC_OscInit->PLL1.PLLPCLK) != HAL_OK) + return HAL_ERROR; + + if (HAL_RCC_PLL1QCLKConfig(RCC_OscInit->PLL1.PLLQCLK) != HAL_OK) + return HAL_ERROR; + } + + /*------------------------------- PLL2 Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_PLL2) + { + if (RCC_OscInit->PLL1.SSC == DISABLE) + { + if (HAL_RCC_PLL2Config(RCC_OscInit->PLL2.PLL, RCC_OscInit->PLL2.Source, RCC_OscInit->PLL2.PLLN, \ + RCC_OscInit->PLL2.PLLF, RCC_OscInit->PLL2.PLLP, RCC_OscInit->PLL2.PLLQ) != HAL_OK) + return HAL_ERROR; + } + else + { + if (HAL_RCC_PLL2SSCConfig(RCC_OscInit->PLL2.PLL, RCC_OscInit->PLL2.Source, RCC_OscInit->PLL2.PLLN, \ + RCC_OscInit->PLL2.PLLF, RCC_OscInit->PLL2.PLLP, RCC_OscInit->PLL2.PLLQ, \ + RCC_OscInit->PLL1.SSC, RCC_OscInit->PLL1.SSCMode, RCC_OscInit->PLL1.SSCSpectrum, \ + RCC_OscInit->PLL1.SSCStep) != HAL_OK) + return HAL_ERROR; + } + + if (HAL_RCC_PLL2PCLKConfig(RCC_OscInit->PLL2.PLLPCLK) != HAL_OK) + return HAL_ERROR; + + if (HAL_RCC_PLL2QCLKConfig(RCC_OscInit->PLL2.PLLQCLK) != HAL_OK) + return HAL_ERROR; + } + + /*------------------------------- PLL3 Configuration ------------------------*/ + if (RCC_OscInit->OscType & RCC_OSC_TYPE_PLL3) + { + if (HAL_RCC_PLL3Config(RCC_OscInit->PLL3.PLL, RCC_OscInit->PLL3.Source, RCC_OscInit->PLL3.PLLN, \ + RCC_OscInit->PLL3.PLLF, RCC_OscInit->PLL3.PLLP, RCC_OscInit->PLL3.PLLQ) != HAL_OK) + return HAL_ERROR; + + if (HAL_RCC_PLL3PCLKConfig(RCC_OscInit->PLL3.PLLPCLK) != HAL_OK) + return HAL_ERROR; + + if (HAL_RCC_PLL3QCLKConfig(RCC_OscInit->PLL3.PLLQCLK) != HAL_OK) + return HAL_ERROR; + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_RCHConfig(FunctionalState RCH, FunctionalState Div16) +{ + uint32_t temp; + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(RCH)); + + if (RCH == DISABLE) + { + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL_1) == 0) + return (HAL_ERROR); + + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1SRCSEL)) == RCC_PLL1CR_PLL1EN) + return (HAL_ERROR); + + if ((RCC->PLL2CR & (RCC_PLL2CR_PLL2SLEEP | RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2SRCSEL)) == RCC_PLL2CR_PLL2EN) + return (HAL_ERROR); + + if ((RCC->PLL3CR & (RCC_PLL3CR_PLL3SLEEP | RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3SRCSEL)) == RCC_PLL3CR_PLL3EN) + return (HAL_ERROR); + + /* disable RCH */ + RCC->RCHCR &= ~(RCC_RCHCR_RCHEN | RCC_RCHCR_RCHDIV); + HAL_SimpleDelay(2); + timeout = RCC_RCHP_UNREADY_TIMEOUT; + while (RCC->RCHCR & RCC_RCHCR_RCHRDY) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + else + { + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Div16)); + + if (Div16 == DISABLE) + { + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1SRCSEL)) == RCC_PLL1CR_PLL1EN) + return (HAL_ERROR); + + if ((RCC->PLL2CR & (RCC_PLL2CR_PLL2SLEEP | RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2SRCSEL)) == RCC_PLL2CR_PLL2EN) + return (HAL_ERROR); + + if ((RCC->PLL3CR & (RCC_PLL3CR_PLL3SLEEP | RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3SRCSEL)) == RCC_PLL3CR_PLL3EN) + return (HAL_ERROR); + + RCC->RCHCR &= ~RCC_RCHCR_RCHDIV; + } + + RCC->RCHCR |= RCC_RCHCR_RCHEN; + + HAL_SimpleDelay(5); + + timeout = RCC_RCH_READY_TIMEOUT; + while ((RCC->RCHCR & RCC_RCHCR_RCHRDY) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + if (Div16) + RCC->RCHCR |= RCC_RCHCR_RCHDIV; + + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL) == RCC_SYSCLK_SOURCE_RCH) + { + temp = SystemCoreClock; + SystemCoreClock = HAL_RCC_GetSysCoreClockFreq(); + if (temp != SystemCoreClock) + { + HAL_InitTick(g_systickHandle.intPrio,g_systickHandle.msPeriod); + } + } + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_RCLConfig(FunctionalState RCL) +{ + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(RCL)); + + if (RCL == DISABLE) + { + if ((RCC->STDBYCTRL & (RCC_STDBYCTRL_RTCEN | RCC_STDBYCTRL_RTCSEL)) == RCC_STDBYCTRL_RTCEN) + return (HAL_ERROR); + + /* disable RCL */ + RCC->STDBYCTRL = (RCC->STDBYCTRL & ~(RCC_STDBYCTRL_RCLDIS | RCC_STDBYCTRL_RCLEN)) | \ + (0x0AUL << RCC_STDBYCTRL_RCLDIS_Pos); + + HAL_SimpleDelay(2); + timeout = RCC_RCL_UNREADY_TIMEOUT; + while (RCC->STDBYCTRL & RCC_STDBYCTRL_RCLRDY) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + else + { + /* enable RCL */ + RCC->STDBYCTRL |= RCC_STDBYCTRL_RCLEN; + HAL_SimpleDelay(5); + /* Wait till RCL is ready */ + timeout = RCC_RCL_READY_TIMEOUT; + while (!(RCC->STDBYCTRL & RCC_STDBYCTRL_RCLRDY)) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_XTHConfig(FunctionalState XTH, FunctionalState Bypass) +{ +// volatile uint32_t temp; + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(XTH)); + + if (DISABLE == XTH) + { + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL) == RCC_CCR1_SYSCLKSEL_1) + return (HAL_ERROR); + + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1SRCSEL)) == (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1SRCSEL)) + return (HAL_ERROR); + + if ((RCC->PLL2CR & (RCC_PLL2CR_PLL2SLEEP | RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2SRCSEL)) == (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1SRCSEL)) + return (HAL_ERROR); + + if ((RCC->PLL3CR & (RCC_PLL3CR_PLL3SLEEP | RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3SRCSEL)) == (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1SRCSEL)) + return (HAL_ERROR); + + /* disable XTH */ + RCC->XTHCR &= ~RCC_XTHCR_XTHEN; + HAL_SimpleDelay(2); + timeout = RCC_XTH_UNREADY_TIMEOUT; + while (RCC->XTHCR & RCC_XTHCR_XTHRDY) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + else + { + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Bypass)); + + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL) == RCC_CCR1_SYSCLKSEL_1) + { + if (Bypass) + { + if ((RCC->XTHCR & RCC_XTHCR_XTHBYP) == 0) + return (HAL_ERROR); + } + else + { + if (RCC->XTHCR & RCC_XTHCR_XTHBYP) + return (HAL_ERROR); + } + } + + if (Bypass) + RCC->XTHCR |= RCC_XTHCR_XTHRDYTIME | RCC_XTHCR_XTHBYP | RCC_XTHCR_XTHEN; + else + RCC->XTHCR = (RCC->XTHCR & ~RCC_XTHCR_XTHBYP) | RCC_XTHCR_XTHRDYTIME | RCC_XTHCR_XTHEN; + + HAL_SimpleDelay(5); + timeout = RCC_XTH_READY_TIMEOUT; + while (!(RCC->XTHCR & RCC_XTHCR_XTHRDY)) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_XTLConfig(FunctionalState XTL, FunctionalState Bypass) +{ + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(XTL)); + + if (DISABLE == XTL) + { + if ((RCC->STDBYCTRL & (RCC_STDBYCTRL_RTCEN | RCC_STDBYCTRL_RTCSEL)) == (RCC_STDBYCTRL_RTCEN | RCC_STDBYCTRL_RTCSEL)) + return (HAL_ERROR); + + /* disable XTL */ + RCC->STDBYCTRL &= ~RCC_STDBYCTRL_XTLEN; + HAL_SimpleDelay(5); + timeout = RCC_XTL_UNREADY_TIMEOUT; + while (RCC->STDBYCTRL & RCC_STDBYCTRL_XTLRDY) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + else + { + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(Bypass)); + + /* XTL oscillator bypass configuration */ + if (Bypass) + { + RCC->STDBYCTRL = (RCC->STDBYCTRL & ~RCC_STDBYCTRL_XTLDRV) | RCC_STDBYCTRL_XTLBYP | \ + RCC_STDBYCTRL_XTLDRV_1 | RCC_STDBYCTRL_XTLDRV_0 | RCC_STDBYCTRL_XTLEN; + } + else + { + RCC->STDBYCTRL = (RCC->STDBYCTRL & ~(RCC_STDBYCTRL_XTLBYP | RCC_STDBYCTRL_XTLDRV)) | \ + RCC_STDBYCTRL_XTLDRV_1 | RCC_STDBYCTRL_XTLDRV_0 | RCC_STDBYCTRL_XTLEN; + } + HAL_SimpleDelay(5); + timeout = RCC_XTL_READY_TIMEOUT; + while ((RCC->STDBYCTRL & RCC_STDBYCTRL_XTLRDY) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + RCC->STDBYCTRL |= RCC_STDBYCTRL_XTLDRV_2; + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PLL1Config(FunctionalState PLL1, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ) +{ + uint32_t lock; + uint32_t timeout; + #ifdef USE_FULL_ASSERT + double freq; + #endif + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(PLL1)); + + /* check whether the current configured clock is the system clock */ + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL) == (RCC_CCR1_SYSCLKSEL_0 | RCC_CCR1_SYSCLKSEL_1)) + return (HAL_ERROR); + + if (PLL1 == DISABLE) + { + /* disable PLL1 */ + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1EN; + /* enter sleep mode */ + RCC->PLL1CR |= RCC_PLL1CR_PLL1SLEEP; + HAL_SimpleDelay(15); + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL_CLOCK_SOURCE(ClockSource)); + assert_param(IS_RCC_PLL1_PLLN(PLLN)); + assert_param(IS_RCC_PLL1_PLLF(PLLF)); + assert_param(IS_RCC_PLL1_PLLP(PLLP)); + assert_param(IS_RCC_PLL1_PLLQ(PLLQ)); + + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + { + if ((RCC->RCHCR & (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != \ + (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return (HAL_ERROR); + lock = RCC_PLL1CR_PLL1FREERUN; + #ifdef USE_FULL_ASSERT + freq = (double)4000000; + #endif + } + else + { + if ((RCC->XTHCR & (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN)) != (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN)) + return (HAL_ERROR); + lock = RCC_PLL1CR_PLL1LOCK; + #ifdef USE_FULL_ASSERT + freq = (double)XTH_VALUE; + #endif + } + + // FCLK_VCO=FCLKIN*F/N; FCLK_P=FCLK_VCO /P; FCLK_Q=FCLK_VCO /Q + + #ifdef USE_FULL_ASSERT + assert_param((freq >= 1000000) && (freq <= 132000000)); + freq = freq / PLLN; + assert_param((freq >= 1000000) && (freq <= 2000000)); + freq = freq * PLLF; + assert_param((freq >= 100000000) && (freq <= 550000000)); + assert_param(((freq / PLLP) >= 30000000) && ((freq / PLLP) <= 220000000)); + assert_param(((freq / PLLQ) >= 16000000) && ((freq / PLLQ) <= 220000000)); + #endif + + RCC->PLL1CR |= RCC_PLL1CR_PLL1LOCKSEL; + RCC->PLL1CR &= ~(RCC_PLL1CR_PLL1PCLKEN | RCC_PLL1CR_PLL1QCLKEN); + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1SRCSEL; + else + RCC->PLL1CR |= RCC_PLL1CR_PLL1SRCSEL; + /* lock delay 400us */ + RCC->PLL1CR = (RCC->PLL1CR & ~RCC_PLL1CR_PLL1LOCKDLY) | \ + ((((uint32_t)(((double)400 * SystemCoreClock) / ((double)512 * 1000000))) \ + << RCC_PLL1CR_PLL1LOCKDLY_Pos) & RCC_PLL1CR_PLL1LOCKDLY); + /* enable PLL1 */ + RCC->PLL1CR |= RCC_PLL1CR_PLL1EN; + RCC->PLL1SCR = 0; + /* exit sleep mode */ + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1SLEEP; + + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL1_READY_TIMEOUT; + while ((RCC->PLL1CR & RCC_PLL1CR_PLL1FREERUN) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + RCC->PLL1CFR = (((PLLQ) << RCC_PLL1CFR_PLL1Q_Pos) & RCC_PLL1CFR_PLL1Q) | \ + (((((PLLP) >> 1) - 1) << RCC_PLL1CFR_PLL1P_Pos) & RCC_PLL1CFR_PLL1P) | \ + (((PLLN) << RCC_PLL1CFR_PLL1N_Pos) & RCC_PLL1CFR_PLL1N) | \ + (((PLLF) << RCC_PLL1CFR_PLL1F_Pos) & RCC_PLL1CFR_PLL1F); + + + if (ClockSource == RCC_PLL_SOURCE_XTH) + { + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1LOCKSEL; + } + /* update pll */ + RCC->PLL1CR |= RCC_PLL1CR_PLL1UPDATEEN; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL1_READY_TIMEOUT; + while ((RCC->PLL1CR & lock) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + + + RCC->PLL1CR |= RCC_PLL1CR_PLL1PCLKEN; + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PLL1SSCConfig(FunctionalState PLL1, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ, \ + FunctionalState SSC, uint32_t Mode, uint32_t Spectrum, uint32_t Step) +{ + uint32_t lock; + uint32_t timeout; + #ifdef USE_FULL_ASSERT + double freq; + #endif + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(PLL1)); + + /* check whether the current configured clock is the system clock */ + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL) == (RCC_CCR1_SYSCLKSEL_0 | RCC_CCR1_SYSCLKSEL_1)) + return (HAL_ERROR); + + if (PLL1 == DISABLE) + { + /* disable PLL1 */ + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1EN; + RCC->PLL1SCR = 0; + /* enter sleep mode */ + RCC->PLL1CR |= RCC_PLL1CR_PLL1SLEEP; + HAL_SimpleDelay(15); + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL_CLOCK_SOURCE(ClockSource)); + assert_param(IS_RCC_PLL1_PLLN(PLLN)); + assert_param(IS_RCC_PLL1_PLLF(PLLF)); + assert_param(IS_RCC_PLL1_PLLP(PLLP)); + assert_param(IS_RCC_PLL1_PLLQ(PLLQ)); + + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + { + if ((RCC->RCHCR & (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != \ + (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return (HAL_ERROR); + lock = RCC_PLL1CR_PLL1FREERUN; + #ifdef USE_FULL_ASSERT + freq = (double)4000000; + #endif + } + else + { + if ((RCC->XTHCR & (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN)) != (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN)) + return (HAL_ERROR); + lock = RCC_PLL1CR_PLL1LOCK; + #ifdef USE_FULL_ASSERT + freq = (double)XTH_VALUE; + #endif + } + + // FCLK_VCO=FCLKIN*F/N; FCLK_P=FCLK_VCO /P; FCLK_Q=FCLK_VCO /Q + + #ifdef USE_FULL_ASSERT + assert_param((freq >= 1000000) && (freq <= 132000000)); + freq = freq / PLLN; + assert_param((freq >= 1000000) && (freq <= 2000000)); + freq = freq * PLLF; + assert_param((freq >= 100000000) && (freq <= 550000000)); + assert_param(((freq / PLLP) >= 30000000) && ((freq / PLLP) <= 222000000)); + assert_param(((freq / PLLQ) >= 16000000) && ((freq / PLLQ) <= 222000000)); + #endif + + RCC->PLL1CR |= RCC_PLL1CR_PLL1LOCKSEL; + RCC->PLL1CR &= ~(RCC_PLL1CR_PLL1PCLKEN | RCC_PLL1CR_PLL1QCLKEN); + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1SRCSEL; + else + RCC->PLL1CR |= RCC_PLL1CR_PLL1SRCSEL; + /* lock delay 400us */ + RCC->PLL1CR = (RCC->PLL1CR & ~RCC_PLL1CR_PLL1LOCKDLY) | \ + ((((uint32_t)(((double)400 * SystemCoreClock) / ((double)512 * 1000000))) \ + << RCC_PLL1CR_PLL1LOCKDLY_Pos) & RCC_PLL1CR_PLL1LOCKDLY); + /* enable PLL1 */ + RCC->PLL1CR |= RCC_PLL1CR_PLL1EN; + + if (SSC == DISABLE) + { + RCC->PLL1SCR = 0; + } + else + { + RCC->PLL1SCR = ((Step << RCC_PLL1SCR_PLL1SSCSTP_Pos) & RCC_PLL1SCR_PLL1SSCSTP) | \ + ((Spectrum << RCC_PLL1SCR_PLL1SSCPER_Pos) & RCC_PLL1SCR_PLL1SSCPER) | \ + Mode | RCC_PLL1SCR_PLL1SSCEN; + } + + /* exit sleep mode */ + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1SLEEP; + + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL1_READY_TIMEOUT; + while ((RCC->PLL1CR & RCC_PLL1CR_PLL1FREERUN) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + RCC->PLL1CFR = (((PLLQ) << RCC_PLL1CFR_PLL1Q_Pos) & RCC_PLL1CFR_PLL1Q) | \ + (((((PLLP) >> 1) - 1) << RCC_PLL1CFR_PLL1P_Pos) & RCC_PLL1CFR_PLL1P) | \ + (((PLLN) << RCC_PLL1CFR_PLL1N_Pos) & RCC_PLL1CFR_PLL1N) | \ + (((PLLF) << RCC_PLL1CFR_PLL1F_Pos) & RCC_PLL1CFR_PLL1F); + + if (ClockSource == RCC_PLL_SOURCE_XTH) + { + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1LOCKSEL; + } + /* update pll */ + RCC->PLL1CR |= RCC_PLL1CR_PLL1UPDATEEN; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL1_READY_TIMEOUT; + while ((RCC->PLL1CR & lock) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + + return (HAL_OK); +} + +HAL_StatusTypeDef HAL_RCC_PLL1PCLKConfig(FunctionalState PLL1PCLK) +{ + /* check whether the current configured clock is the system clock */ + if ((RCC->CCR1 & RCC_CCR1_SYSCLKSEL) == (RCC_CCR1_SYSCLKSEL_1 | RCC_CCR1_SYSCLKSEL_0)) + return (HAL_ERROR); + + if (PLL1PCLK == DISABLE) + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1PCLKEN; + else + RCC->PLL1CR |= RCC_PLL1CR_PLL1PCLKEN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_RCC_PLL1QCLKConfig(FunctionalState PLL1QCLK) +{ + if (PLL1QCLK == DISABLE) + RCC->PLL1CR &= ~RCC_PLL1CR_PLL1QCLKEN; + else + RCC->PLL1CR |= RCC_PLL1CR_PLL1QCLKEN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PLL2Config(FunctionalState PLL2, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ) +{ + uint32_t lock; + uint32_t timeout; + #ifdef USE_FULL_ASSERT + double freq; + #endif + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(PLL2)); + + if (PLL2 == DISABLE) + { + /* disable PLL2 */ + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2EN; + /* enter sleep mode */ + RCC->PLL2CR |= RCC_PLL2CR_PLL2SLEEP; + HAL_SimpleDelay(15); + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL_CLOCK_SOURCE(ClockSource)); + assert_param(IS_RCC_PLL2_PLLN(PLLN)); + assert_param(IS_RCC_PLL2_PLLF(PLLF)); + assert_param(IS_RCC_PLL2_PLLP(PLLP)); + assert_param(IS_RCC_PLL2_PLLQ(PLLQ)); + + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + { + if ((RCC->RCHCR & (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != \ + (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return (HAL_ERROR); + lock = RCC_PLL2CR_PLL2FREERUN; + #ifdef USE_FULL_ASSERT + freq = (double)4000000; + #endif + } + else + { + if ((RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN) != (RCC->XTHCR & (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN))) + return (HAL_ERROR); + lock = RCC_PLL2CR_PLL2LOCK; + #ifdef USE_FULL_ASSERT + freq = (double)XTH_VALUE; + #endif + } + + // FCLK_VCO=FCLKIN*F/N; FCLK_P=FCLK_VCO /P; FCLK_Q=FCLK_VCO /Q + #ifdef USE_FULL_ASSERT + assert_param((freq >= 1000000) && (freq <= 132000000)); + freq = freq / PLLN; + assert_param((freq >= 1000000) && (freq <= 2000000)); + freq = freq * PLLF; + assert_param((freq >= 100000000) && (freq <= 550000000)); + assert_param(((freq / PLLP) >= 30000000) && ((freq / PLLP) <= 220000000)); + assert_param(((freq / PLLQ) >= 16000000) && ((freq / PLLQ) <= 220000000)); + #endif + + RCC->PLL2CR |= RCC_PLL2CR_PLL2LOCKSEL; + RCC->PLL2CR &= ~(RCC_PLL2CR_PLL2PCLKEN | RCC_PLL2CR_PLL2QCLKEN); + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2SRCSEL; + else + RCC->PLL2CR |= RCC_PLL2CR_PLL2SRCSEL; + /* lock delay 400us */ + RCC->PLL2CR = (RCC->PLL2CR & ~RCC_PLL2CR_PLL2LOCKDLY) | \ + ((((uint32_t)(((double)400 * SystemCoreClock) / ((double)512 * 1000000))) \ + << RCC_PLL2CR_PLL2LOCKDLY_Pos) & RCC_PLL2CR_PLL2LOCKDLY); + /* enable PLL2 */ + RCC->PLL2CR |= RCC_PLL2CR_PLL2EN; + RCC->PLL2SCR = 0; + /* exit sleep mode */ + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2SLEEP; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL2_READY_TIMEOUT; + while ((RCC->PLL2CR & RCC_PLL2CR_PLL2FREERUN) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + + RCC->PLL2CFR = (((PLLQ) << RCC_PLL2CFR_PLL2Q_Pos) & RCC_PLL2CFR_PLL2Q) | \ + (((((PLLP) >> 1) - 1) << RCC_PLL2CFR_PLL2P_Pos) & RCC_PLL2CFR_PLL2P) | \ + (((PLLN) << RCC_PLL2CFR_PLL2N_Pos) & RCC_PLL2CFR_PLL2N) | \ + (((PLLF) << RCC_PLL2CFR_PLL2F_Pos) & RCC_PLL2CFR_PLL2F); + + if (ClockSource == RCC_PLL_SOURCE_XTH) + { + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2LOCKSEL; + } + /* update pll */ + RCC->PLL2CR |= RCC_PLL2CR_PLL2UPDATEEN; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL2_READY_TIMEOUT; + while ((RCC->PLL2CR & lock) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PLL2SSCConfig(FunctionalState PLL2, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ, \ + FunctionalState SSC, uint32_t Mode, uint32_t Spectrum, uint32_t Step) +{ + uint32_t lock; + uint32_t timeout; + #ifdef USE_FULL_ASSERT + double freq; + #endif + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(PLL2)); + + if (PLL2 == DISABLE) + { + /* disable PLL2 */ + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2EN; + /* enter sleep mode */ + RCC->PLL2CR |= RCC_PLL2CR_PLL2SLEEP; + HAL_SimpleDelay(15); + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL_CLOCK_SOURCE(ClockSource)); + assert_param(IS_RCC_PLL2_PLLN(PLLN)); + assert_param(IS_RCC_PLL2_PLLF(PLLF)); + assert_param(IS_RCC_PLL2_PLLP(PLLP)); + assert_param(IS_RCC_PLL2_PLLQ(PLLQ)); + + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + { + if ((RCC->RCHCR & (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != \ + (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return (HAL_ERROR); + lock = RCC_PLL2CR_PLL2FREERUN; + #ifdef USE_FULL_ASSERT + freq = (double)4000000; + #endif + } + else + { + if ((RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN) != (RCC->XTHCR & (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN))) + return (HAL_ERROR); + lock = RCC_PLL2CR_PLL2LOCK; + #ifdef USE_FULL_ASSERT + freq = (double)XTH_VALUE; + #endif + } + + // FCLK_VCO=FCLKIN*F/N; FCLK_P=FCLK_VCO /P; FCLK_Q=FCLK_VCO /Q + #ifdef USE_FULL_ASSERT + assert_param((freq >= 1000000) && (freq <= 132000000)); + freq = freq / PLLN; + assert_param((freq >= 1000000) && (freq <= 2000000)); + freq = freq * PLLF; + assert_param((freq >= 100000000) && (freq <= 550000000)); + assert_param(((freq / PLLP) >= 30000000) && ((freq / PLLP) <= 220000000)); + assert_param(((freq / PLLQ) >= 16000000) && ((freq / PLLQ) <= 220000000)); + #endif + + RCC->PLL2CR |= RCC_PLL2CR_PLL2LOCKSEL; + RCC->PLL2CR &= ~(RCC_PLL2CR_PLL2PCLKEN | RCC_PLL2CR_PLL2QCLKEN); + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2SRCSEL; + else + RCC->PLL2CR |= RCC_PLL2CR_PLL2SRCSEL; + /* lock delay 400us */ + RCC->PLL2CR = (RCC->PLL2CR & ~RCC_PLL2CR_PLL2LOCKDLY) | \ + ((((uint32_t)(((double)400 * SystemCoreClock) / ((double)512 * 1000000))) \ + << RCC_PLL2CR_PLL2LOCKDLY_Pos) & RCC_PLL2CR_PLL2LOCKDLY); + /* enable PLL2 */ + RCC->PLL2CR |= RCC_PLL2CR_PLL2EN; + + if (SSC == DISABLE) + { + RCC->PLL2SCR = 0; + } + else + { + RCC->PLL2SCR = ((Step << RCC_PLL2SCR_PLL2SSCSTP_Pos) & RCC_PLL2SCR_PLL2SSCSTP) | \ + ((Spectrum << RCC_PLL2SCR_PLL2SSCPER_Pos) & RCC_PLL2SCR_PLL2SSCPER) | \ + Mode | RCC_PLL2SCR_PLL2SSCEN; + } + + /* exit sleep mode */ + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2SLEEP; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL2_READY_TIMEOUT; + while ((RCC->PLL2CR & RCC_PLL2CR_PLL2FREERUN) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + + RCC->PLL2CFR = (((PLLQ) << RCC_PLL2CFR_PLL2Q_Pos) & RCC_PLL2CFR_PLL2Q) | \ + (((((PLLP) >> 1) - 1) << RCC_PLL2CFR_PLL2P_Pos) & RCC_PLL2CFR_PLL2P) | \ + (((PLLN) << RCC_PLL2CFR_PLL2N_Pos) & RCC_PLL2CFR_PLL2N) | \ + (((PLLF) << RCC_PLL2CFR_PLL2F_Pos) & RCC_PLL2CFR_PLL2F); + + if (ClockSource == RCC_PLL_SOURCE_XTH) + { + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2LOCKSEL; + } + /* update pll */ + RCC->PLL2CR |= RCC_PLL2CR_PLL2UPDATEEN; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL2_READY_TIMEOUT; + while ((RCC->PLL2CR & lock) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + + return (HAL_OK); +} + +HAL_StatusTypeDef HAL_RCC_PLL2PCLKConfig(FunctionalState PLL2PCLK) +{ + if (PLL2PCLK == DISABLE) + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2PCLKEN; + else + RCC->PLL2CR |= RCC_PLL2CR_PLL2PCLKEN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_RCC_PLL2QCLKConfig(FunctionalState PLL2QCLK) +{ + if (DISABLE == PLL2QCLK) + RCC->PLL2CR &= ~RCC_PLL2CR_PLL2QCLKEN; + else + RCC->PLL2CR |= RCC_PLL2CR_PLL2QCLKEN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initializes the RCC Oscillators according to the specified parameters +* in the RCC_OscInitTypeDef. +*@param : RCC_OscInit: pointer to an RCC_OscInitTypeDef structure that contains +* the configuration information for the RCC Oscillators. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PLL3Config(FunctionalState PLL3, uint32_t ClockSource, \ + uint32_t PLLN, uint32_t PLLF, uint32_t PLLP, uint32_t PLLQ) +{ + uint32_t lock; + uint32_t timeout; + #ifdef USE_FULL_ASSERT + double freq; + #endif + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(PLL3)); + + if (DISABLE == PLL3) + { + /* disable PLL3 */ + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3EN; + /* enter sleep mode */ + RCC->PLL3CR |= RCC_PLL3CR_PLL3SLEEP; + } + else + { + /* Check the parameters */ + assert_param(IS_RCC_PLL_CLOCK_SOURCE(ClockSource)); + assert_param(IS_RCC_PLL3_PLLN(PLLN)); + assert_param(IS_RCC_PLL3_PLLF(PLLF)); + assert_param(IS_RCC_PLL3_PLLP(PLLP)); + assert_param(IS_RCC_PLL3_PLLQ(PLLQ)); + + if (RCC_PLL_SOURCE_RCH_DIV16 == ClockSource) + { + if ((RCC->RCHCR & (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != \ + (RCC_RCHCR_RCHDIV | RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return (HAL_ERROR); + lock = RCC_PLL3CR_PLL3FREERUN; + #ifdef USE_FULL_ASSERT + freq = (double)4000000; + #endif + } + else + { + if ((RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN) != (RCC->XTHCR & (RCC_XTHCR_XTHRDY | RCC_XTHCR_XTHEN))) + return (HAL_ERROR); + lock = RCC_PLL3CR_PLL3LOCK; + #ifdef USE_FULL_ASSERT + freq = (double)XTH_VALUE; + #endif + } + + // FCLK_VCO=FCLKIN*F/N; FCLK_P=FCLK_VCO /P; FCLK_Q=FCLK_VCO /Q + + #ifdef USE_FULL_ASSERT + assert_param((freq >= 1000000) && (freq <= 50000000)); + freq = freq / PLLN; + freq = freq * PLLF; + assert_param((freq >= 200000000) && (freq <= 500000000)); + assert_param(((freq / PLLP) >= 25000000) && ((freq / PLLP) <= 220000000)); + assert_param(((freq / PLLQ) >= 25000000) && ((freq / PLLQ) <= 220000000)); + #endif + + RCC->PLL3CR |= RCC_PLL3CR_PLL3LOCKSEL; + RCC->PLL3CR &= ~(RCC_PLL3CR_PLL3PCLKEN | RCC_PLL3CR_PLL3QCLKEN); + if (ClockSource == RCC_PLL_SOURCE_RCH_DIV16) + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3SRCSEL; + else + RCC->PLL3CR |= RCC_PLL3CR_PLL3SRCSEL; + /* lock delay 110us */ + RCC->PLL3CR = (RCC->PLL3CR & ~RCC_PLL3CR_PLL3LOCKDLY) | \ + ((((uint32_t)(((double)110 * SystemCoreClock) / ((double)512 * 1000000))) \ + << RCC_PLL3CR_PLL3LOCKDLY_Pos) & RCC_PLL3CR_PLL3LOCKDLY); + /* enable PLL2 */ + RCC->PLL3CR |= RCC_PLL3CR_PLL3EN; + /* exit sleep mode */ + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3SLEEP; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL3_READY_TIMEOUT; + while ((RCC->PLL3CR & RCC_PLL3CR_PLL3FREERUN) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + + RCC->PLL3CFR = ((((PLLQ) == 1 ? 0 : ((PLLQ) == 2 ? 1 : ((PLLQ) == 4 ? 2 : 3))) << RCC_PLL3CFR_PLL3Q_Pos) & RCC_PLL3CFR_PLL3Q) | \ + ((((PLLP) == 1 ? 0 : ((PLLP) == 2 ? 1 : ((PLLP) == 4 ? 2 : 3))) << RCC_PLL3CFR_PLL3P_Pos) & RCC_PLL3CFR_PLL3P) | \ + ((((PLLN) - 1) << RCC_PLL3CFR_PLL3N_Pos) & RCC_PLL3CFR_PLL3N) | \ + ((((PLLF) - 1) << RCC_PLL3CFR_PLL3F_Pos) & RCC_PLL3CFR_PLL3F); + + if (ClockSource == RCC_PLL_SOURCE_XTH) + { + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3LOCKSEL; + } + /* update pll */ + RCC->PLL3CR |= RCC_PLL3CR_PLL3UPDATEEN; + HAL_SimpleDelay(15); + /* Wait till PLL is ready */ + timeout = RCC_PLL3_READY_TIMEOUT; + while ((RCC->PLL3CR & lock) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + } + + return (HAL_OK); +} + +HAL_StatusTypeDef HAL_RCC_PLL3PCLKConfig(FunctionalState PLL3PCLK) +{ + if (PLL3PCLK == DISABLE) + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3PCLKEN; + else + RCC->PLL3CR |= RCC_PLL3CR_PLL3PCLKEN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_RCC_PLL3QCLKConfig(FunctionalState PLL3QCLK) +{ + if (PLL3QCLK == DISABLE) + RCC->PLL3CR &= ~RCC_PLL3CR_PLL3QCLKEN; + else + RCC->PLL3CR |= RCC_PLL3CR_PLL3QCLKEN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_RCC_ITConfig(uint32_t IT, FunctionalState NewStatus) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(IT)); + + if (NewStatus) + RCC->CIR |= ((IT & RCC_IT_READY_MASK) << 8) | ((IT & RCC_IT_STOP_MASK) >> 3); + else + RCC->CIR &= ~((((IT & RCC_IT_READY_MASK)) << 8) | ((IT & RCC_IT_STOP_MASK) >> 3)); + + return HAL_OK; +} + +uint32_t HAL_RCC_GetITFlag(uint32_t IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(IT)); + + if ((RCC->CIR & IT) == IT) + return true; + else + return false; +} + +HAL_StatusTypeDef HAL_RCC_ClearITFlag(uint32_t IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(IT)); + + RCC->CIR |= ((IT & RCC_IT_READY_MASK) << 16) | ( (IT & RCC_IT_STOP_MASK) >> 2); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initializes the CPU, AHB and APB buses clocks according to the +* specified parameters in the RCC_ClkInitTypeDef. +*@param : RCC_ClkInit: pointer to an RCC_ClkInitTypeDef structure that +* contains the configuration information for the RCC peripheral. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInit) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLOCK_TYPE(RCC_ClkInit->ClockType)); + + /* first level frequency division of system clock */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_SYSDIV0) + { + if (HAL_RCC_SYSCLKDiv0Config(RCC_ClkInit->SYSCLKDiv0) != HAL_OK) + return HAL_ERROR; + } + + /* second level frequency division of system clock */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_SYSDIV1) + { + if (HAL_RCC_SYSCLKDiv1Config(RCC_ClkInit->SYSCLKDiv1) != HAL_OK) + return HAL_ERROR; + } + + /* frequency division of PCLK1 clock */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_PCLK1) + { + if (HAL_RCC_PCLK1DivConfig(RCC_ClkInit->PCLK1Div) != HAL_OK) + return HAL_ERROR; + } + + /* frequency division of PCLK2 clock */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_PCLK2) + { + if (HAL_RCC_PCLK2DivConfig(RCC_ClkInit->PCLK2Div) != HAL_OK) + return HAL_ERROR; + } + + /* frequency division of PCLK3 clock */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_PCLK3) + { + if (HAL_RCC_PCLK3DivConfig(RCC_ClkInit->PCLK3Div) != HAL_OK) + return HAL_ERROR; + } + + /* frequency division of PCLK4 clock */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_PCLK4) + { + if (HAL_RCC_PCLK4DivConfig(RCC_ClkInit->PCLK4Div) != HAL_OK) + return HAL_ERROR; + } + + /* system clok source configuration */ + if (RCC_ClkInit->ClockType & RCC_CLOCK_TYPE_SYSCLK) + { + if (HAL_RCC_SYSCLKSourceConfig(RCC_ClkInit->SYSCLKSource) != HAL_OK) + return HAL_ERROR; + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Switch the system clock. +*@param : SYSCLKSource: SYSCLK clock source. +* This parameter must be a value of @ref RCC_Sysclk_Source. +* @arg RCC_SYSCLKSOURCE_RCH: RCH clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_RCL: RCL clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_XTH: XTH clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_XTL: XTL clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_PLL1PCLK: PLL1PCLK clock selected as SYSCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_SYSCLKSourceConfig(uint32_t ClockSource) +{ + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(ClockSource)); + + if (ClockSource == RCC_SYSCLK_SOURCE_RCH) + { + /* Check whether the RCH clock is turned on and running stably */ + if ((RCC->RCHCR & (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return HAL_ERROR; + + /* system clok source configuration */ + RCC->CCR1 = RCC->CCR1 & ~RCC_CCR1_SYSCLKSEL; + } + else if (RCC_SYSCLK_SOURCE_XTH == ClockSource) + { + /* Check whether the XTH clock is turned on and running stably */ + if ((RCC->XTHCR & (RCC_XTHCR_XTHEN | RCC_XTHCR_XTHRDY)) != (RCC_XTHCR_XTHEN | RCC_XTHCR_XTHRDY)) + return HAL_ERROR; + + /* system clok source configuration */ + RCC->CCR1 = (RCC->CCR1 & ~RCC_CCR1_SYSCLKSEL) | RCC_CCR1_SYSCLKSEL_1; + } + else + { + /* Check whether the PLL clock is turned on and running stably */ + if (RCC->PLL1CR & RCC_PLL1CR_PLL1SRCSEL) + { + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1PCLKEN | RCC_PLL1CR_PLL1LOCK)) != \ + (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1PCLKEN | RCC_PLL1CR_PLL1LOCK)) + return HAL_ERROR; + } + else + { + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1PCLKEN | RCC_PLL1CR_PLL1FREERUN)) != \ + (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1PCLKEN | RCC_PLL1CR_PLL1FREERUN)) + return HAL_ERROR; + } + + /* system clok source configuration */ + RCC->CCR1 = (RCC->CCR1 & ~RCC_CCR1_SYSCLKSEL) | RCC_CCR1_SYSCLKSEL_1 | RCC_CCR1_SYSCLKSEL_0; + } + + temp = SystemCoreClock; + SystemCoreClock = HAL_RCC_GetSysCoreClockFreq(); + if (temp != SystemCoreClock) + { + HAL_InitTick(g_systickHandle.intPrio,g_systickHandle.msPeriod); + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_SYSCLKDiv0Config(uint32_t Div) +{ + uint32_t temp; + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_DIV(Div)); + + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_SYSDIV0) | (((Div - 1) << RCC_CCR2_SYSDIV0_Pos) & RCC_CCR2_SYSDIV0); + HAL_SimpleDelay(5); + /* Wait till the update frequency division to complete */ + timeout = 256u; + while ((RCC->CCR2 & RCC_CCR2_DIVDONE) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + + temp = SystemCoreClock; + SystemCoreClock = HAL_RCC_GetSysCoreClockFreq(); + if (temp != SystemCoreClock) + { + HAL_InitTick(g_systickHandle.intPrio,g_systickHandle.msPeriod); + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_SYSCLKDiv1Config(uint32_t Div) +{ + uint32_t temp; + uint32_t timeout; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_DIV(Div)); + + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_SYSDIV1) | (((Div - 1) << RCC_CCR2_SYSDIV1_Pos) & RCC_CCR2_SYSDIV1); + + HAL_SimpleDelay(2); + + /* Wait till the update frequency division to complete */ + timeout = 256u; + while ((RCC->CCR2 & RCC_CCR2_DIVDONE) == 0) + { + if (timeout-- == 0) + return (HAL_TIMEOUT); + } + + temp = SystemCoreClock; + SystemCoreClock = HAL_RCC_GetSysCoreClockFreq(); + if (temp != SystemCoreClock) + { + HAL_InitTick(g_systickHandle.intPrio,g_systickHandle.msPeriod); + } + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PCLK1DivConfig(uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_RCC_PCLK_DIV(Div)); + + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_PCLK1DIV) | ((Div == 1 ? 0 : \ + (Div == 2 ? 4 : \ + (Div == 4 ? 5 : \ + (Div == 8 ? 6 : 7)))) << RCC_CCR2_PCLK1DIV_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PCLK2DivConfig(uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_RCC_PCLK_DIV(Div)); + + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_PCLK2DIV) | ((Div == 1 ? 0 : \ + (Div == 2 ? 4 : \ + (Div == 4 ? 5 : \ + (Div == 8 ? 6 : 7)))) << RCC_CCR2_PCLK2DIV_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PCLK3DivConfig(uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_RCC_PCLK_DIV(Div)); + + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_PCLK3DIV) | ((Div == 1 ? 0 : \ + (Div == 2 ? 4 : \ + (Div == 4 ? 5 : \ + (Div == 8 ? 6 : 7)))) << RCC_CCR2_PCLK3DIV_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_PCLK4DivConfig(uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_RCC_PCLK_DIV(Div)); + + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_PCLK4DIV) | ((Div == 1 ? 0 : \ + (Div == 2 ? 4 : \ + (Div == 4 ? 5 : \ + (Div == 8 ? 6 : 7)))) << RCC_CCR2_PCLK4DIV_Pos); + + return (HAL_OK); +} + + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_HRNGSClockDivConfig(uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_RCC_HRNGS_CLK_DIV(Div)); + + /* FLTCLK clok source configuration */ + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_HRNGSDIV) | (((Div - 1) << RCC_CCR2_HRNGSDIV_Pos) & RCC_CCR2_HRNGSDIV); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_FLTClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_FLT_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->CCR2 = (RCC->CCR2 & ~RCC_CCR2_FLTCLKSEL) | ((ClockSource << RCC_CCR2_FLTCLKSEL_Pos) & RCC_CCR2_FLTCLKSEL); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure LPUART1 clock source. +*@param : ClockSource: LPUART1 clock source. +* This parameter must be a value of @ref RCC_LPUART1_CLK_Source. +* @arg RCC_LPUART1_CLK_SOURCE_RCL : +* @arg RCC_LPUART1_CLK_SOURCE_XTL : +* @arg RCC_LPUART1_CLK_SOURCE_PCLK1_DIV4 : +* @arg RCC_LPUART1_CLK_SOURCE_PCLK1_DIV8 : +* @arg RCC_LPUART1_CLK_SOURCE_PCLK1_DIV16 : +* @arg RCC_LPUART1_CLK_SOURCE_PCLK1_DIV32 : +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPUART1ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPUART1_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + if (ClockSource <= RCC_LPUART1_CLK_SOURCE_XTL) + RCC->PERCFGR = (RCC->PERCFGR & ~(RCC_PERCFGR_LPUART1CKS | RCC_PERCFGR_LPUART1DIV)) | \ + (ClockSource << RCC_PERCFGR_LPUART1CKS_Pos); + else + RCC->PERCFGR = (RCC->PERCFGR & ~(RCC_PERCFGR_LPUART1CKS | RCC_PERCFGR_LPUART1DIV)) | \ + RCC_PERCFGR_LPUART1CKS_1 | ((ClockSource - 2) << RCC_PERCFGR_LPUART1DIV_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM1_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_RCH: RCH clock selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_XTL: XTL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPTIM1ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_LPTIM1CKS) | (ClockSource << RCC_PERCFGR_LPTIM1CKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM2_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_RCH: RCH clock selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_XTL: XTL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPTIM2ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_LPTIM2CKS) | (ClockSource << RCC_PERCFGR_LPTIM2CKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCH clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: XTL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPTIM3ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_LPTIM345CKS) | (ClockSource << RCC_PERCFGR_LPTIM345CKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCH clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: XTL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPTIM4ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM4_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_LPTIM345CKS) | (ClockSource << RCC_PERCFGR_LPTIM345CKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCH clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: XTL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPTIM5ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM5_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_LPTIM345CKS) | (ClockSource << RCC_PERCFGR_LPTIM345CKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM6_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_RCH: RCH clock selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_XTL: XTL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LPTIM6ClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIM6_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_LPTIM6CKS) | (ClockSource << RCC_PERCFGR_LPTIM6CKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_SDMMC_CLK_SOURCE_SYSCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_SDMMC_CLK_SOURCE_PLL2PCLK: PLL2P clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_SDMMCClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_SDMMC_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_SDMMCCKS) | (ClockSource << RCC_PERCFGR_SDMMCCKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_SDIO_CLK_SOURCE_SYSCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_SDIO_CLK_SOURCE_PLL2_P_CLK: PLL2P clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_SDMMCSampleClockSourceConfig(uint32_t SampleClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_SDMMC_SCLK_SOURCE(SampleClockSource)); + + /* FLTCLK clok source configuration */ + RCC->PERCFGR = (RCC->PERCFGR & ~RCC_PERCFGR_SDMMCSCKS) | (SampleClockSource << RCC_PERCFGR_SDMMCSCKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_SDIO_CLK_SOURCE_SYS_CLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_SDIO_CLK_SOURCE_PLL2_P_CLK: PLL2P clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_LCDPiexlClockDivConfig(uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_RCC_LCD_CLK_DIV(Div)); + + /* FLTCLK clok source configuration */ + RCC->DCKCFG = (RCC->DCKCFG & ~RCC_DCKCFG_LCDDIV) | ((Div == 2 ? 0 : \ + (Div == 4 ? 1 : \ + (Div == 8 ? 2 : 3))) << RCC_DCKCFG_LCDDIV_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_RTC_CLK_SOURCE_RCL: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_RTC_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_RTCClockSourceConfig(uint32_t ClockSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTC_CLK_SOURCE(ClockSource)); + + /* FLTCLK clok source configuration */ + RCC->STDBYCTRL = (RCC->STDBYCTRL & ~RCC_STDBYCTRL_RTCSEL) | (ClockSource << RCC_STDBYCTRL_RTCSEL_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Initializes the CPU, AHB and APB buses clocks according to the +* specified parameters in the RCC_ClkInitTypeDef. +*@param : RCC_ClkInit: pointer to an RCC_ClkInitTypeDef structure that +* contains the configuration information for the RCC peripheral. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetClock(RCC_ClkInitTypeDef *RCC_ClkInit) +{ + uint32_t temp; + + if (RCC_ClkInit == NULL) + return HAL_ERROR; + + HAL_RCC_GetSYSCLKSource(&RCC_ClkInit->SYSCLKSource); + + RCC_ClkInit->SYSCLKDiv0 = ((RCC->CCR2 & RCC_CCR2_SYSDIV0) >> RCC_CCR2_SYSDIV0_Pos) + 1; + RCC_ClkInit->SYSCLKDiv1 = ((RCC->CCR2 & RCC_CCR2_SYSDIV1) >> RCC_CCR2_SYSDIV1_Pos) + 1; + + temp = (RCC->CCR2 & RCC_CCR2_PCLK1DIV) >> RCC_CCR2_PCLK1DIV_Pos; + if (temp < 4) + temp = 1; + else + temp = 1 << (temp - 3); + RCC_ClkInit->PCLK1Div = temp; + + temp = (RCC->CCR2 & RCC_CCR2_PCLK2DIV) >> RCC_CCR2_PCLK2DIV_Pos; + if (temp < 4) + temp = 1; + else + temp = 1 << (temp - 3); + RCC_ClkInit->PCLK2Div = temp; + + temp = (RCC->CCR2 & RCC_CCR2_PCLK3DIV) >> RCC_CCR2_PCLK3DIV_Pos; + if (temp < 4) + temp = 1; + else + temp = 1 << (temp - 3); + RCC_ClkInit->PCLK3Div = temp; + + temp = (RCC->CCR2 & RCC_CCR2_PCLK4DIV) >> RCC_CCR2_PCLK4DIV_Pos; + if (temp < 4) + temp = 1; + else + temp = 1 << (temp - 3); + RCC_ClkInit->PCLK4Div = temp; + + RCC_ClkInit->ClockType = RCC_CLOCK_TYPE_SYSCLK | RCC_CLOCK_TYPE_SYSDIV0 | RCC_CLOCK_TYPE_SYSDIV1 | \ + RCC_CLOCK_TYPE_PCLK1 | RCC_CLOCK_TYPE_PCLK2 | RCC_CLOCK_TYPE_PCLK3 | RCC_CLOCK_TYPE_PCLK4; + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Switch the system clock. +*@param : SYSCLKSource: SYSCLK clock source. +* This parameter must be a value of @ref RCC_Sysclk_Source. +* @arg RCC_SYSCLKSOURCE_RCH: RCH clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_RCL: RCL clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_XTH: XTH clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_XTL: XTL clock selected as SYSCLK source +* @arg RCC_SYSCLKSOURCE_PLLCLK: PLL clock selected as SYSCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetSYSCLKSource(uint32_t *pClockSource) +{ + uint32_t source; + + if (pClockSource == NULL) + return HAL_ERROR; + + source = (RCC->CCR1 & RCC_CCR1_SYSCLKSEL) >> RCC_CCR1_SYSCLKSEL_Pos; + + if (source <= 1) + source = RCC_SYSCLK_SOURCE_RCH; + else if (source == 2) + source = RCC_SYSCLK_SOURCE_XTH; + else + source = RCC_SYSCLK_SOURCE_PLL1PCLK; + + *pClockSource = source; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetHRNGSlowClockDiv(uint32_t *pClockDiv) +{ + if (pClockDiv == NULL) + return HAL_ERROR; + + *pClockDiv = ((RCC->CCR2 & RCC_CCR2_HRNGSDIV) >> RCC_CCR2_HRNGSDIV_Pos) + 1; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetFLTClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->CCR2 & RCC_CCR2_FLTCLKSEL) >> RCC_CCR2_FLTCLKSEL_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPUART1_CLK_SOURCE_RCL: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPUART1_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +* @arg RCC_LPUART1_CLK_SOURCE_PCLK: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPUART1ClockSource(uint32_t *pClockSource) +{ + uint32_t source; + + if (pClockSource == NULL) + return HAL_ERROR; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPUART1CKS) >> RCC_PERCFGR_LPUART1CKS_Pos; + + if (source <= 1) + { + *pClockSource = source; + return HAL_OK; + } + + if (source == 2) + { + source = (RCC->PERCFGR & RCC_PERCFGR_LPUART1DIV) >> RCC_PERCFGR_LPUART1DIV_Pos; + *pClockSource = source + 2; + return HAL_OK; + } + + return HAL_ERROR; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM1_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPTIM1ClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_LPTIM1CKS) >> RCC_PERCFGR_LPTIM1CKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM2_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPTIM2ClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_LPTIM2CKS) >> RCC_PERCFGR_LPTIM2CKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPTIM3ClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_LPTIM345CKS) >> RCC_PERCFGR_LPTIM345CKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPTIM4ClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_LPTIM345CKS) >> RCC_PERCFGR_LPTIM345CKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPTIM5ClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_LPTIM345CKS) >> RCC_PERCFGR_LPTIM345CKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM6_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetLPTIM6ClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_LPTIM6CKS) >> RCC_PERCFGR_LPTIM6CKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_SDIO_CLK_SOURCE_SYS_CLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_SDIO_CLK_SOURCE_PLL2_P_CLK: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetSDMMCClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_SDMMCCKS) >> RCC_PERCFGR_SDMMCCKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_SDIO_CLK_SOURCE_SYS_CLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_SDIO_CLK_SOURCE_PLL2_P_CLK: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetSDMMCSampleClockSource(uint32_t *pClockSource) +{ + if (pClockSource == NULL) + return HAL_ERROR; + + *pClockSource = (RCC->PERCFGR & RCC_PERCFGR_SDMMCSCKS) >> RCC_PERCFGR_SDMMCSCKS_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_RTC_CLK_SOURCE_RCL: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_RTC_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RCC_GetRTCClockSource(uint32_t *pClockSource) +{ +// uint32_t source; + + if (pClockSource == NULL) + return HAL_ERROR; + + if (RCC->STDBYCTRL & RCC_STDBYCTRL_RTCSEL_1) + return HAL_ERROR; + + *pClockSource = (RCC->STDBYCTRL & RCC_STDBYCTRL_RTCSEL) >> RCC_STDBYCTRL_RTCSEL_Pos; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Returns RC64M infact value +*@return: RC64M val +******************************************************************************/ +uint32_t HAL_RCC_GetRCHTrimFreq(void) +{ + uint32_t freq; + + HAL_EFUSE_RpEnable(EFUSE1); + HAL_EFUSE_ReadBytes(EFUSE1, 0x1C, (uint8_t *)&freq, 4, 100000); + + if ((freq > 76800000) || (freq < 51200000)) + return 64000000; + else + return freq; +} + +/****************************************************************************** +*@brief : Returns RC32K infact value +*@return: RC32K val +******************************************************************************/ +uint32_t HAL_RCC_GetRCLTrimFreq(void) +{ + uint32_t freq; + + HAL_EFUSE_RpEnable(EFUSE1); + HAL_EFUSE_ReadBytes(EFUSE1, 0x20, (uint8_t *)&freq, 4, 100000); + + if ((freq > 39321) || (freq < 26214)) + return 32768; + else + return freq; +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetRCHFreq(void) +{ + uint32_t freq; + + if ((RCC->RCHCR & (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) != (RCC_RCHCR_RCHEN | RCC_RCHCR_RCHRDY)) + return (0); + + freq = HAL_RCC_GetRCHTrimFreq(); + + if (RCC->RCHCR & RCC_RCHCR_RCHDIV) + freq = freq >> 4; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCL infact value +*@return: RCL val +******************************************************************************/ +uint32_t HAL_RCC_GetRCLFreq(void) +{ + if ((RCC->STDBYCTRL & (RCC_STDBYCTRL_RCLEN | RCC_STDBYCTRL_RCLRDY)) != (RCC_STDBYCTRL_RCLEN | RCC_STDBYCTRL_RCLRDY)) + return (0); + + return (HAL_RCC_GetRCLTrimFreq()); +} + + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetXTHFreq(void) +{ + if ((RCC->XTHCR & (RCC_XTHCR_XTHEN | RCC_XTHCR_XTHRDY)) == (RCC_XTHCR_XTHEN | RCC_XTHCR_XTHRDY)) + return (XTH_VALUE); + else + return 0; +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetXTLFreq(void) +{ + if ((RCC->STDBYCTRL & (RCC_STDBYCTRL_XTLEN | RCC_STDBYCTRL_XTLRDY)) == (RCC_STDBYCTRL_XTLEN | RCC_STDBYCTRL_XTLRDY)) + return (32768U); + else + return (0); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL1Freq(void) +{ + uint32_t freq; + uint32_t plln; + uint32_t pllf; + + if (RCC->PLL1CR & RCC_PLL1CR_PLL1SRCSEL) + { + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1LOCK | RCC_PLL1CR_PLL1PCLKEN)) != \ + (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1LOCK | RCC_PLL1CR_PLL1PCLKEN)) + { + return (0); + } + freq = HAL_RCC_GetXTHFreq(); + } + else + { + if ((RCC->PLL1CR & (RCC_PLL1CR_PLL1SLEEP | RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1FREERUN | RCC_PLL1CR_PLL1PCLKEN)) != \ + (RCC_PLL1CR_PLL1EN | RCC_PLL1CR_PLL1FREERUN | RCC_PLL1CR_PLL1PCLKEN)) + { + return (0); + } + freq = HAL_RCC_GetRCHFreq(); + } + + if (freq == 0) + return (0); + + plln = (RCC->PLL1CFR & RCC_PLL1CFR_PLL1N_Msk) >> RCC_PLL1CFR_PLL1N_Pos; + if (plln == 0) + plln = 1; + + pllf = (RCC->PLL1CFR & RCC_PLL1CFR_PLL1F_Msk) >> RCC_PLL1CFR_PLL1F_Pos; + if (pllf < 50) + pllf = 50; + + freq = (uint32_t)((uint64_t)freq * pllf / plln); + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL1PFreq(void) +{ + uint32_t freq; + uint32_t pllp; + + freq = HAL_RCC_GetPLL1Freq(); + if (freq == 0) + return (0); + + pllp = (RCC->PLL1CFR & RCC_PLL1CFR_PLL1P_Msk) >> RCC_PLL1CFR_PLL1P_Pos; + pllp = (pllp + 1) << 1; + + freq = freq / pllp; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL2Freq(void) +{ + uint32_t freq; + uint32_t plln; + uint32_t pllf; + + if (RCC->PLL2CR & RCC_PLL2CR_PLL2SRCSEL) + { + if ((RCC->PLL2CR & (RCC_PLL2CR_PLL2SLEEP | RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2LOCK | RCC_PLL2CR_PLL2PCLKEN)) != \ + (RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2LOCK | RCC_PLL2CR_PLL2PCLKEN)) + { + return (0); + } + freq = HAL_RCC_GetXTHFreq(); + } + else + { + if ((RCC->PLL2CR & (RCC_PLL2CR_PLL2SLEEP | RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2FREERUN | RCC_PLL2CR_PLL2PCLKEN)) != \ + (RCC_PLL2CR_PLL2EN | RCC_PLL2CR_PLL2FREERUN | RCC_PLL2CR_PLL2PCLKEN)) + { + return (0); + } + freq = HAL_RCC_GetRCHFreq(); + } + + if (freq == 0) + return (0); + + plln = (RCC->PLL2CFR & RCC_PLL2CFR_PLL2N_Msk) >> RCC_PLL2CFR_PLL2N_Pos; + if (plln == 0) + plln = 1; + + pllf = (RCC->PLL2CFR & RCC_PLL2CFR_PLL2F_Msk) >> RCC_PLL2CFR_PLL2F_Pos; + if (pllf < 50) + pllf = 50; + + freq = (uint32_t)((uint64_t)freq * pllf / plln); + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL2QFreq(void) +{ + uint32_t freq; + uint32_t pllq; + + freq = HAL_RCC_GetPLL2Freq(); + if (freq == 0) + return (0); + + pllq = (RCC->PLL2CFR & RCC_PLL2CFR_PLL2Q_Msk) >> RCC_PLL2CFR_PLL2Q_Pos; + if (pllq == 0) + pllq = 1; + + freq = freq / pllq; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL2PFreq(void) +{ + uint32_t freq; + uint32_t pllp; + + freq = HAL_RCC_GetPLL2Freq(); + if (freq == 0) + return (0); + + pllp = (RCC->PLL2CFR & RCC_PLL2CFR_PLL2P_Msk) >> RCC_PLL2CFR_PLL2P_Pos; + pllp = (pllp + 1) << 1; + + freq = freq / pllp; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL3Freq(void) +{ + uint32_t freq; + uint32_t plln; + uint32_t pllf; + + if (RCC->PLL3CR & RCC_PLL3CR_PLL3SRCSEL) + { + if ((RCC->PLL3CR & (RCC_PLL3CR_PLL3SLEEP | RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3LOCK | RCC_PLL3CR_PLL3QCLKEN)) != \ + (RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3LOCK | RCC_PLL3CR_PLL3QCLKEN)) + { + return (0); + } + freq = HAL_RCC_GetXTHFreq(); + } + else + { + if ((RCC->PLL3CR & (RCC_PLL3CR_PLL3SLEEP | RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3FREERUN | RCC_PLL3CR_PLL3QCLKEN)) != \ + (RCC_PLL3CR_PLL3EN | RCC_PLL3CR_PLL3FREERUN | RCC_PLL3CR_PLL3QCLKEN)) + { + return (0); + } + freq = HAL_RCC_GetRCHFreq(); + } + + if (freq == 0) + return (0); + + plln = ((RCC->PLL3CFR & RCC_PLL3CFR_PLL3N_Msk) >> RCC_PLL3CFR_PLL3N_Pos) + 1; + + pllf = ((RCC->PLL3CFR & RCC_PLL3CFR_PLL3F_Msk) >> RCC_PLL3CFR_PLL3F_Pos) + 1; + + freq = (uint32_t)((uint64_t)freq * pllf / plln); + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL3QFreq(void) +{ + uint32_t freq; + uint32_t pllq; + + freq = HAL_RCC_GetPLL3Freq(); + if (freq == 0) + return (0); + + pllq = (RCC->PLL3CFR & RCC_PLL3CFR_PLL3Q_Msk) >> RCC_PLL3CFR_PLL3Q_Pos; + if (pllq == 0) + pllq = 1; + else if (pllq == 1) + pllq = 2; + else if (pllq == 2) + pllq = 4; + else + pllq = 8; + + freq = freq / pllq; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns RCH infact value +*@return: RCH val +******************************************************************************/ +uint32_t HAL_RCC_GetPLL3PFreq(void) +{ + uint32_t freq; + uint32_t pllp; + + freq = HAL_RCC_GetPLL3Freq(); + if (freq == 0) + return (0); + + pllp = (RCC->PLL3CFR & RCC_PLL3CFR_PLL3P_Msk) >> RCC_PLL3CFR_PLL3P_Pos; + if (pllp == 0) + pllp = 1; + else if (pllp == 1) + pllp = 2; + else if (pllp == 2) + pllp = 4; + else + pllp = 8; + + freq = freq / pllp; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns the SYSCLK frequency +*@return: SYSCLK frequency +******************************************************************************/ +uint32_t HAL_RCC_GetSYSCLKFreq(void) +{ + uint32_t source; + + source = (RCC->CCR1 & RCC_CCR1_SYSCLKSEL) >> RCC_CCR1_SYSCLKSEL_Pos; + + if (source < 1) + return HAL_RCC_GetRCHFreq(); + + if (source == 2) + return HAL_RCC_GetXTHFreq(); + + return HAL_RCC_GetPLL1PFreq(); +} + +/****************************************************************************** +*@brief : Returns the SysCoreClock frequency +*@return: SysCoreClock frequency +******************************************************************************/ +uint32_t HAL_RCC_GetSysCoreClockFreq(void) +{ + uint32_t div; + uint32_t freq = 0U; + + freq = HAL_RCC_GetSYSCLKFreq(); + + /* first level frequency division of system clock */ + div = ((RCC->CCR2 & RCC_CCR2_SYSDIV0) >> RCC_CCR2_SYSDIV0_Pos) + 1; + + freq = freq / div; + + /* second level frequency division of system clock */ + div = ((RCC->CCR2 & RCC_CCR2_SYSDIV1) >> RCC_CCR2_SYSDIV1_Pos) + 1; + + freq = freq / div; + + SystemCoreClock = freq; + + return (freq); +} + +/****************************************************************************** +*@brief : Returns the FCLK (Core) frequency +*@return: FCLK frequency +******************************************************************************/ +uint32_t HAL_RCC_GetFCLKFreq(void) +{ + return SystemCoreClock; +} + +/****************************************************************************** +*@brief : Returns the HCLK (AHB CLK) frequency +*@return: HCLK frequency +******************************************************************************/ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/****************************************************************************** +*@brief : Returns the PCLK1 (APB1 CLK) frequency +*@return: PCLK1 frequency +******************************************************************************/ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + if ((RCC->CCR2 & RCC_CCR2_PCLK1DIV_2) == 0) + return (SystemCoreClock); + + return (SystemCoreClock >> (((RCC->CCR2 & (RCC_CCR2_PCLK1DIV_0 | RCC_CCR2_PCLK1DIV_1)) >> RCC_CCR2_PCLK1DIV_Pos) + 1)); +} + +/****************************************************************************** +*@brief : Returns the PCLK2 (APB2 CLK) frequency +*@return: PCLK2 frequency +******************************************************************************/ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + if ((RCC->CCR2 & RCC_CCR2_PCLK2DIV_2) == 0) + return (SystemCoreClock); + + return (SystemCoreClock >> (((RCC->CCR2 & (RCC_CCR2_PCLK2DIV_0 | RCC_CCR2_PCLK2DIV_1)) >> RCC_CCR2_PCLK2DIV_Pos) + 1)); +} + +/****************************************************************************** +*@brief : Returns the PCLK2 (APB2 CLK) frequency +*@return: PCLK2 frequency +******************************************************************************/ +uint32_t HAL_RCC_GetPCLK3Freq(void) +{ + if ((RCC->CCR2 & RCC_CCR2_PCLK3DIV_2) == 0) + return (SystemCoreClock); + + return (SystemCoreClock >> (((RCC->CCR2 & (RCC_CCR2_PCLK3DIV_0 | RCC_CCR2_PCLK3DIV_1)) >> RCC_CCR2_PCLK3DIV_Pos) + 1)); +} + +/****************************************************************************** +*@brief : Returns the PCLK2 (APB2 CLK) frequency +*@return: PCLK2 frequency +******************************************************************************/ +uint32_t HAL_RCC_GetPCLK4Freq(void) +{ + if ((RCC->CCR2 & RCC_CCR2_PCLK4DIV_2) == 0) + return (SystemCoreClock); + + return (SystemCoreClock >> (((RCC->CCR2 & (RCC_CCR2_PCLK4DIV_0 | RCC_CCR2_PCLK4DIV_1)) >> RCC_CCR2_PCLK4DIV_Pos) + 1)); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetHRNGSClockFreq(void) +{ + return (SystemCoreClock / (((RCC->CCR2 & RCC_CCR2_HRNGSDIV) >> RCC_CCR2_HRNGSDIV_Pos) + 1)); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_FLT_CLK_SOURCE_PCLK_DIV32: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_FLT_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetFLTClockFreq(void) +{ + if ((RCC->CCR2 & RCC_CCR2_FLTCLKSEL) == 0) + return (HAL_RCC_GetPCLK1Freq() >> 5); + else + return (HAL_RCC_GetRCLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPUART1_CLK_SOURCE_RCL: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPUART1_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +* @arg RCC_LPUART1_CLK_SOURCE_PCLK: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPUART1ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPUART1CKS) >> RCC_PERCFGR_LPUART1CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetRCLFreq()); + + if (source == 1) + return (HAL_RCC_GetXTLFreq()); + + if (source == 2) + return (HAL_RCC_GetPCLK1Freq() >> (((RCC->PERCFGR & RCC_PERCFGR_LPUART1DIV) >> RCC_PERCFGR_LPUART1DIV_Pos) + 2)); + + return (0); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM1_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM1_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPTIM1ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPTIM1CKS) >> RCC_PERCFGR_LPTIM1CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetPCLK1Freq()); + + if (source == 1) + return (HAL_RCC_GetRCLFreq()); + + if (source == 2) + return (HAL_RCC_GetRCHFreq()); + + return (HAL_RCC_GetXTLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM2_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM2_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPTIM2ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPTIM2CKS) >> RCC_PERCFGR_LPTIM2CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetPCLK1Freq()); + + if (source == 1) + return (HAL_RCC_GetRCLFreq()); + + if (source == 2) + return (HAL_RCC_GetRCHFreq()); + + return (HAL_RCC_GetXTLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPTIM3ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPTIM345CKS) >> RCC_PERCFGR_LPTIM345CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetPCLK3Freq()); + + if (source == 1) + return (HAL_RCC_GetRCLFreq()); + + if (source == 2) + return (HAL_RCC_GetRCHFreq()); + + return (HAL_RCC_GetXTLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPTIM4ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPTIM345CKS) >> RCC_PERCFGR_LPTIM345CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetPCLK3Freq()); + + if (source == 1) + return (HAL_RCC_GetRCLFreq()); + + if (source == 2) + return (HAL_RCC_GetRCHFreq()); + + return (HAL_RCC_GetXTLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM345_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCL: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM345_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPTIM5ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPTIM345CKS) >> RCC_PERCFGR_LPTIM345CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetPCLK3Freq()); + + if (source == 1) + return (HAL_RCC_GetRCLFreq()); + + if (source == 2) + return (HAL_RCC_GetRCHFreq()); + + return (HAL_RCC_GetXTLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_LPTIM6_CLK_SOURCE_PCLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_RCL: RCL selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_RCH: RCL clock selected as FLTCLK source +* @arg RCC_LPTIM6_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLPTIM6ClockFreq(void) +{ + uint32_t source; + + source = (RCC->PERCFGR & RCC_PERCFGR_LPTIM6CKS) >> RCC_PERCFGR_LPTIM6CKS_Pos; + + if (source == 0) + return (HAL_RCC_GetPCLK3Freq()); + + if (source == 1) + return (HAL_RCC_GetRCLFreq()); + + if (source == 2) + return (HAL_RCC_GetRCHFreq()); + + return (HAL_RCC_GetXTLFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_SDMMC_CLK_SOURCE_SYS_CLK: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_SDMMC_CLK_SOURCE_PLL2_P_CLK: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetSDMMCClockFreq(void) +{ + if ((RCC->PERCFGR & RCC_PERCFGR_SDMMCCKS) == 0) + return (HAL_RCC_GetHCLKFreq()); + else + return (HAL_RCC_GetPLL2PFreq()); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_RTC_CLK_SOURCE_RCL: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_RTC_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetLCDPiexlClockFreq(void) +{ + return (HAL_RCC_GetPLL2QFreq() >> (((RCC->DCKCFG & RCC_DCKCFG_LCDDIV) >> RCC_DCKCFG_LCDDIV_Pos) + 1)); +} + +/****************************************************************************** +*@brief : Configure FLTCLK (LVD and COMP) clock source. +*@param : ClockSource: LVD and COMP clock source. +* This parameter must be a value of @ref RCC_FLT_CLK_Source. +* @arg RCC_RTC_CLK_SOURCE_RCL: clock after pclk 32 frequency division selected as FLTCLK source +* @arg RCC_RTC_CLK_SOURCE_XTL: RCL clock selected as FLTCLK source +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_GetRTCClockFreq(void) +{ + uint32_t source; + + if ((RCC->STDBYCTRL & RCC_STDBYCTRL_RTCEN) == 0) + return (0); + + source = (RCC->STDBYCTRL & RCC_STDBYCTRL_RTCSEL) >> RCC_STDBYCTRL_RTCSEL_Pos; + + if (source == 0) + return (HAL_RCC_GetRCLFreq()); + + if (source == 1) + return (HAL_RCC_GetXTLFreq()); + + return (0); +} + +/****************************************************************************** +*@brief : Configure MCO output. +*@param : MCO_Init: pointer to an RCC_MCOInitTypeDef structure that contains +* the configuration information for the MCO output. +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_MCOConfig(RCC_MCOInitTypeDef *MCO_InitStruct) +{ + volatile uint32_t temp; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(MCO_InitStruct->MCO)); + assert_param(IS_FUNCTIONAL_STATE(MCO_InitStruct->MCO1)); + assert_param(IS_FUNCTIONAL_STATE(MCO_InitStruct->MCO2)); + + temp = MCO_InitStruct->MCO; + + if (MCO_InitStruct->MCO1) + { + assert_param(IS_RCC_MCO1_DIV(MCO_InitStruct->MCO1Div)); + assert_param(IS_FUNCTIONAL_STATE(MCO_InitStruct->MCO1RevPol)); + + /* MCO1 clock polarity configuration */ + if (MCO_InitStruct->MCO1RevPol) + temp |= RCC_CLKOCR_MCO1POL; + + /* MCO1 division configuration */ + temp |= RCC_CLKOCR_MCO1SEL | RCC_CLKOCR_MCO1EN | ((MCO_InitStruct->MCO1Div - 1) << RCC_CLKOCR_MCO1DIV_Pos); + } + else + { + assert_param(IS_FUNCTIONAL_STATE(MCO_InitStruct->MCO1RevPol)); + + /* MCO1 clock polarity configuration */ + if (MCO_InitStruct->MCO1RevPol) + temp |= RCC_CLKOCR_MCO1POL; + } + + if (MCO_InitStruct->MCO2) + { + assert_param(IS_RCC_MCO2_DIV(MCO_InitStruct->MCO2Div)); + assert_param(IS_FUNCTIONAL_STATE(MCO_InitStruct->MCO2RevPol)); + + /* MCO1 clock polarity configuration */ + if (MCO_InitStruct->MCO2RevPol != DISABLE) + temp |= RCC_CLKOCR_MCO2POL; + + /* MCO1 division configuration */ + temp |= RCC_CLKOCR_MCO2EN | (((MCO_InitStruct->MCO2Div - 1) << RCC_CLKOCR_MCO2DIV_Pos) & RCC_CLKOCR_MCO2DIV); + } + else + { + assert_param(IS_FUNCTIONAL_STATE(MCO_InitStruct->MCO2RevPol)); + + /* MCO1 clock polarity configuration */ + if (MCO_InitStruct->MCO2RevPol != DISABLE) + temp |= RCC_CLKOCR_MCO2POL; + } + + RCC->CLKOCR = temp; + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure MCO1 output. +*@param : MCO_Init: pointer to an RCC_MCOInitTypeDef structure that contains +* the configuration information for the MCO output. +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_MCO1Config(uint32_t MCO, uint32_t NewStatus, uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewStatus)); + + if (NewStatus == DISABLE) + { + RCC->CLKOCR = (RCC->CLKOCR & ~RCC_CLKOCR_MCO1EN) | RCC_CLKOCR_MCO1SEL; + return HAL_OK; + } + + assert_param(IS_RCC_MCO(MCO)); + assert_param(IS_RCC_MCO1_DIV(Div)); + + RCC->CLKOCR = (RCC->CLKOCR & ~(RCC_CLKOCR_MCO1DIV | RCC_CLKOCR_MCOCLKS)) | \ + RCC_CLKOCR_MCO1EN | RCC_CLKOCR_MCO1SEL | \ + ((Div - 1) << RCC_CLKOCR_MCO1DIV_Pos) | \ + (MCO << RCC_CLKOCR_MCOCLKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Configure MCO1 output. +*@param : MCO_Init: pointer to an RCC_MCOInitTypeDef structure that contains +* the configuration information for the MCO output. +*@return: HAL status +******************************************************************************/ +uint32_t HAL_RCC_MCO2Config(uint32_t MCO, uint32_t NewStatus, uint32_t Div) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewStatus)); + + if (DISABLE == NewStatus) + { + RCC->CLKOCR = RCC->CLKOCR & ~RCC_CLKOCR_MCO2EN; + return HAL_OK; + } + + assert_param(IS_RCC_MCO(MCO)); + assert_param(IS_RCC_MCO2_DIV(Div)); + + RCC->CLKOCR = (RCC->CLKOCR & ~(RCC_CLKOCR_MCO2DIV | RCC_CLKOCR_MCOCLKS)) | RCC_CLKOCR_MCO2EN | \ + ((Div - 1) << RCC_CLKOCR_MCO2DIV_Pos) | (MCO << RCC_CLKOCR_MCOCLKS_Pos); + + return (HAL_OK); +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +void HAL_RCC_SoftwareReset(void) +{ + RCC->RCR &= ~RCC_RCR_SRST_MAP; +} + +/****************************************************************************** +*@brief : Standby software reset +*@return: None +******************************************************************************/ +void HAL_RCC_StandbyReset(void) +{ + /* check RTC clock source */ + RCC->STDBYCTRL &= ~RCC_STDBYCTRL_STDBYRST; +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +void HAL_RCC_LockupResetConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState) + RCC->RCR |= RCC_RCR_LOCKRST_EN; + else + RCC->RCR &= ~RCC_RCR_LOCKRST_EN; +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +void HAL_RCC_IWDTResetConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState) + RCC->RCR |= RCC_RCR_IWDTRST_EN; + else + RCC->RCR = (RCC->RCR & ~(RCC_RCR_IWDTRST_DIS | RCC_RCR_IWDTRST_EN)) | (0xB5UL << RCC_RCR_IWDTRST_DIS_Pos); +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +void HAL_RCC_WDTResetConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState) + RCC->RCR |= RCC_RCR_WDTRST_EN; + else + RCC->RCR &= ~RCC_RCR_WDTRST_EN; +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +void HAL_RCC_LVDResetConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState) + RCC->RCR |= RCC_RCR_LVDRST_EN; + else + RCC->RCR &= ~RCC_RCR_LVDRST_EN; +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +uint32_t HAL_RCC_GetResetSource(void) +{ + return (RCC->RSR & RCC_RESET_SOURCE_MASK); +} + +/****************************************************************************** +*@brief : Software reset +*@return: None +******************************************************************************/ +void HAL_RCC_ClearAllResetSource(void) +{ + RCC->RSR = RCC_RSR_RSTFLAGCLR; +} + +#endif /* HAL_RCC_MODULE_ENABLED */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_rtc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..3f0ae2056ba6c80974a914fe8c93eba542ab835a --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_rtc.c @@ -0,0 +1,549 @@ + +/****************************************************************************** +* @file : HAL_RTC.c +* @version : 1.0 +* @date : 2022.10.25 +* @brief : RTC HAL module driver +* +* @history : +* 2022.10.25 lwq create +* +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_RTC_MODULE_ENABLED + + + +/****************************************************************************** +* @brief : Initialize the RTC peripheral. +* @param : hrtc: Pointer to a RTC_ConfigTypeDef structure that contains +* the configuration information for the specified RTC module. +* @return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc) +{ + /* Check RTC Parameter */ + assert_param(IS_RTC_CLOCKSRC(hrtc->ClockSource)); + assert_param(IS_RTC_COMPENSATION(hrtc->Compensation)); + assert_param(IS_RTC_COMPENSATION_VALUE(hrtc->CompensationValue)); + + /* Enable PMU CLK */ + __HAL_RCC_PMU_CLK_ENABLE(); + /* Enable RTC Moudle CLK */ + __HAL_RCC_RTC_CLK_ENABLE(); + + /* Enable RTC CLK */ + SET_BIT(RCC->STDBYCTRL, RCC_STDBYCTRL_RTCEN); + /* RTC domain write enable */ + SET_BIT(PMU->CTRL0,PMU_CTRL0_RTCWE); + + switch (hrtc->ClockSource) + { + case RTC_CLOCK_RC32K: + { + //RC32K Enable + RCC->STDBYCTRL |= RCC_STDBYCTRL_RCLEN; + while(!(RCC->STDBYCTRL & RCC_STDBYCTRL_RCLRDY)); + //RTC SEL RC32K + RCC->STDBYCTRL &= ~RCC_STDBYCTRL_RTCSEL; + + }break; + + case RTC_CLOCK_XTL: + { + RCC->STDBYCTRL = (RCC->STDBYCTRL & ~RCC_STDBYCTRL_XTLDRV) | (RCC_STDBYCTRL_XTLDRV_1 | RCC_STDBYCTRL_XTLDRV_0); + + RCC->STDBYCTRL |= RCC_STDBYCTRL_XTLEN; + while(!(RCC->STDBYCTRL & RCC_STDBYCTRL_XTLRDY)); + + //RTC SEL XTL + RCC->STDBYCTRL |= RCC_STDBYCTRL_RTCSEL_0; + }break; + + default: break; + } + + RTC->ADJUST = hrtc->Compensation | hrtc->CompensationValue; + + + return HAL_OK; +} + +/****************************************************************************** +* @brief : Set RTC current time. +* @param : time: Pointer to RTC_TimeTypeDef structure +* @return: none +******************************************************************************/ +void HAL_RTC_SetTime(RTC_TimeTypeDef *time) +{ + /* Check RTC Parameter */ + assert_param(IS_RTC_HOUR(time->Hour)); + assert_param(IS_RTC_MINUTES(time->Minute)); + assert_param(IS_RTC_SECONDS(time->Second)); + + + /* Write-Protect Disable */ + RTC->WP = RTC_WRITE_PROTECT_DISABLE; + + RTC->HOUR = time->Hour; + RTC->MIN = time->Minute; + RTC->SEC = time->Second; + + + /* Write-Protect Enable */ + RTC->WP = RTC_WRITE_PROTECT_ENABLE; +} + +/****************************************************************************** +* @brief : Get RTC current time. +* @param : time: Pointer to RTC_TimeTypeDef structure +* @return: none +******************************************************************************/ +void HAL_RTC_GetTime(RTC_TimeTypeDef *time) +{ + time->Hour = RTC->HOUR; + time->Minute = RTC->MIN; + time->Second = RTC->SEC; +} + + +/****************************************************************************** +* @brief : Set RTC current Date. +* @param : date: Pointer to RTC_DateTypeDef structure +* @return: none +******************************************************************************/ +void HAL_RTC_SetDate(RTC_DateTypeDef *date) +{ + /* Check RTC Parameter */ + assert_param(IS_RTC_YEAR(date->Year)); + assert_param(IS_RTC_MONTH(date->Month)); + assert_param(IS_RTC_DAY(date->Date)); + assert_param(IS_RTC_WEEKDAY(date->WeekDay)); + + + /* Write-Protect Disable */ + RTC->WP = RTC_WRITE_PROTECT_DISABLE; + + RTC->YEAR = date->Year; + RTC->MONTH = date->Month; + RTC->DAY = date->Date; + RTC->WEEK = date->WeekDay; + + + /* Write-Protect Enable */ + RTC->WP = RTC_WRITE_PROTECT_ENABLE; +} + +/****************************************************************************** +* @brief : Get RTC current Date. +* @param : date: Pointer to RTC_DateTypeDef structure +* @return: none +******************************************************************************/ +void HAL_RTC_GetDate(RTC_DateTypeDef *date) +{ + date->Year = RTC->YEAR; + date->Month = RTC->MONTH; + date->Date = RTC->DAY; + date->WeekDay = RTC->WEEK; +} + +/****************************************************************************** +* @brief : Alarm Config. +* @param : alarm: Pointer to RTC_AlarmTypeDef structure. +* @return: none +******************************************************************************/ +void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *alarm) +{ + uint32_t lu32_WeekDay; + + /* Check RTC Parameter */ + assert_param(IS_RTC_ALARM_MODE(alarm->u32_AlarmMode)); + assert_param(IS_RTC_ALARM_INT(alarm->u32_AlarmInterrupt)); + assert_param(IS_RTC_ALARM_DAY_MASK(alarm->u32_DayMask)); + assert_param(IS_RTC_ALARM_HOUR_MASK(alarm->u32_HourMask)); + assert_param(IS_RTC_ALARM_MIN_MASK(alarm->u32_MinMask)); + assert_param(IS_RTC_HOUR(alarm->u32_Hours)); + assert_param(IS_RTC_MINUTES(alarm->u32_Minutes)); + assert_param(IS_RTC_SECONDS(alarm->u32_Seconds)); + + if (alarm->u32_AlarmMode == RTC_ALM_ALM_WDS_WEEK) + { + assert_param(IS_RTC_ALARM_WEEKDAY(alarm->u32_AlarmWeek)); + lu32_WeekDay = alarm->u32_AlarmWeek; + } + else + { + assert_param(IS_RTC_DAY(alarm->u32_AlarmDay)); + lu32_WeekDay = alarm->u32_AlarmDay << RTC_ALM_ALMWEEK_ALMDAY_Pos; + } + + /* Coinfig Week/DayHourMinSec */ + RTC->ALM = alarm->u32_AlarmMode | lu32_WeekDay | alarm->u32_Hours << RTC_ALM_ALMHOUR_Pos | alarm->u32_Minutes << RTC_ALM_ALMMIN_Pos | alarm->u32_Seconds; + + /* Interrupt Enable */ + if (RTC_ALARM_INT_ENABLE == alarm->u32_AlarmInterrupt) + { + RTC->IE |= RTC_IE_ALM_IE; + } + + MODIFY_REG(RTC->CR, RTC_CR_ALM_MSKD, alarm->u32_DayMask); + + MODIFY_REG(RTC->CR, RTC_CR_ALM_MSKH, alarm->u32_HourMask); + + MODIFY_REG(RTC->CR, RTC_CR_ALM_MSKM, alarm->u32_MinMask); +} + +/****************************************************************************** +* @brief : Alarm Enable. +* @param : none. +* @return: none +******************************************************************************/ +void HAL_RTC_AlarmEnable(void) +{ + RTC->CR |= RTC_CR_ALM_EN; +} + +/****************************************************************************** +* @brief : Alarm Disable. +* @param : none. +* @return: none +******************************************************************************/ +void HAL_RTC_AlarmDisable(void) +{ + RTC->CR &= ~RTC_CR_ALM_EN; +} + + +/****************************************************************************** +* @brief : RTC Tamper Config. +* @param : temperx: RTC_TEMPER_1 or RTC_TEMPER_2 +* @param : temper: Pointer to RTC_TemperTypeDef structure +* @return: none +******************************************************************************/ +void HAL_RTC_Tamper(RTC_Temper_t temperx, RTC_TemperTypeDef *temper) +{ + + /* Check RTC Parameter */ + assert_param(IS_RTC_TEMP_EDGE(temper->u32_TemperEdge)); + assert_param(IS_RTC_TEMP_INT(temper->u32_InterruptEN)); + assert_param(IS_RTC_TEMP_CLEAR_BACKUP(temper->u32_ClearBackup)); + assert_param(IS_RTC_TEMP_FILTER(temper->u32_Filter)); + assert_param(IS_RTC_TEMP_FILTER_CLK(temper->u32_FilterClk)); + assert_param(IS_FUNCTIONAL_STATE(temper->u32_FilterEn)); + switch (temperx) + { + case RTC_TEMPER_1: + { + /* RTC domain write enable */ + SET_BIT(PMU->CTRL0,PMU_CTRL0_RTCWE); + + /* Configure PC13 as tamper function */ + __HAL_PMU_PC13_SEL(PMU_IOSEL_PC13_SEL_RTC_TAMPER); + + /* Clear Config */ + RTC->CR &= ~(RTC_CR_TAMP1RCLR | RTC_CR_TAMP1FCLR | RTC_CR_TAMP1FLTEN | RTC_CR_TAMP1FLT_Msk | RTC_CR_TS1EDGE | RTC_CR_TAMPFLTCLK_Msk); + + if(temper->u32_FilterEn == ENABLE) + { + RTC->CR |= RTC_CR_TAMP1FLTEN; + } + else + { + RTC->CR &= ~RTC_CR_TAMP1FLTEN; + } + /* Edge select */ + RTC->CR |= temper->u32_TemperEdge ? RTC_CR_TS1EDGE : 0x00; + /* Auto clear backup register */ + if (temper->u32_ClearBackup) + { + RTC->CR |= temper->u32_TemperEdge ? RTC_CR_TAMP1FCLR : RTC_CR_TAMP1RCLR; + } + /* Temper filter clock*/ + RTC->CR |= temper->u32_FilterClk; + + /* Temper filter */ + RTC->CR |= temper->u32_Filter << RTC_CR_TAMP1FLT_Pos; + + RTC->CR |= RTC_CR_TAMP1EN; + + HAL_SimpleDelay(2000); + + RTC->SR = (RTC_SR_STP1FIF | RTC_SR_STP1RIF); + RTC->IE &= (~(RTC_IE_STP1FIE | RTC_IE_STP1RIE)); + + /* Put Temper Interrupt enable here !!!*/ + if (temper->u32_InterruptEN) + { + RTC->IE |= temper->u32_TemperEdge ? RTC_IE_STP1FIE : RTC_IE_STP1RIE; + } + + }break; + + case RTC_TEMPER_2: + { + /* RTC domain write enable */ + SET_BIT(PMU->CTRL0,PMU_CTRL0_RTCWE); + + /* Configure PI8 as tamper function */ + __HAL_PMU_PI8_SEL(PMU_IOSEL_PI8_SEL_RTC_TAMPER); + + /* Clear Config */ + RTC->CR &= ~(RTC_CR_TAMP2RCLR | RTC_CR_TAMP2FCLR | RTC_CR_TAMP2FLTEN | RTC_CR_TAMP2FLT_Msk | RTC_CR_TS2EDGE | RTC_CR_TAMPFLTCLK_Msk); + + if(temper->u32_FilterEn == ENABLE) + { + RTC->CR |= RTC_CR_TAMP2FLTEN; + } + else + { + RTC->CR &= ~RTC_CR_TAMP2FLTEN; + } + + /* Edge select */ + RTC->CR |= temper->u32_TemperEdge ? RTC_CR_TS2EDGE : 0x00; + /* Auto clear backup register */ + if (temper->u32_ClearBackup) + { + RTC->CR |= temper->u32_TemperEdge ? RTC_CR_TAMP2FCLR : RTC_CR_TAMP2RCLR; + } + + /* Temper filter clock*/ + RTC->CR |= temper->u32_FilterClk; + + /* Temper filter */ + RTC->CR |= temper->u32_Filter << 19; + + RTC->CR |= RTC_CR_TAMP2EN; + + HAL_SimpleDelay(2000); + + RTC->SR = (RTC_SR_STP2FIF|RTC_SR_STP2RIF); + RTC->IE &= (~(RTC_IE_STP2FIE|RTC_IE_STP2RIE)); + + /* Temper Interrupt */ + if (temper->u32_InterruptEN) + { + RTC->IE |= temper->u32_TemperEdge ? RTC_IE_STP2FIE : RTC_IE_STP2RIE; + } + + }break; + + default: break; + } +} + +/****************************************************************************** +* @brief : RTC Tamper Enable. +* @param : temperx: RTC_TEMPER_1 or RTC_TEMPER_2 +* @return: none +******************************************************************************/ +void HAL_RTC_TamperEnable(RTC_Temper_t temperx) +{ + if (temperx == RTC_TEMPER_1) + { + RTC->CR |= RTC_CR_TAMP1EN; + } + else + { + RTC->CR |= RTC_CR_TAMP2EN; + } +} + +/****************************************************************************** +* @brief : RTC Tamper Disable. +* @param : temperx: RTC_TEMPER_1 or RTC_TEMPER_2 +* @return: none +******************************************************************************/ +void HAL_RTC_TamperDisable(RTC_Temper_t temperx) +{ + if (temperx == RTC_TEMPER_1) + { + RTC->CR &= ~RTC_CR_TAMP1EN; + } + else + { + RTC->CR &= ~RTC_CR_TAMP2EN; + } +} + +/****************************************************************************** +* @brief : Sets wakeup timer. +* @param : hrtcTimer: pointer to a RTC_HandleTypeDef structure +* @return: none +******************************************************************************/ +void HAL_RTC_SetWakeUpTimer(RTC_WUTimerTypeDef *hrtcTimer) +{ + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(hrtcTimer->u32_WuckSel)); + assert_param(IS_RTC_WAKEUP_COUNTER(hrtcTimer->WakeUpCounter)); + assert_param(IS_FUNCTIONAL_STATE(hrtcTimer->u32_InterruptEN)); + + //Disable WakeUp Timer + RTC->CR &= ~RTC_CR_WUTE; + + while(!(RTC->SR & RTC_SR_WUTWF)); + + RTC->WUTR = hrtcTimer->WakeUpCounter; + + RTC->CR &= ~RTC_CR_WUCKSEL_Msk; + RTC->CR |= hrtcTimer->u32_WuckSel; + + RTC->IE &= ~RTC_IE_WUTIE_Msk; + if(hrtcTimer->u32_InterruptEN == ENABLE) + { + RTC->IE |= RTC_IE_WUTIE; + } + + //Enable Wakeup Timer + RTC->CR |= RTC_CR_WUTE; + while(!(RTC->SR & RTC_SR_WUTWF)); + +} + +/****************************************************************************** +* @brief: Writes a data in a specified RTC Backup data register. +* @param: RTC_BKP_DR: RTC Backup data Register number. +* This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to +* specify the register. +* @param: Data: Data to be written in the specified RTC Backup data register. +* @return: None +******************************************************************************/ +void HAL_RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + RTC->BAKUP[RTC_BKP_DR] = Data; +} + +/****************************************************************************** +* @brief: Reads data from the specified RTC Backup data Register. +* @param: RTC_BKP_DR: RTC Backup data Register number. +* This parameter can be: RTC_BKP_DRx where x can be from 0 to 15 to +* specify the register. +* @return: Read value +******************************************************************************/ +uint32_t HAL_RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_RTC_BKP(RTC_BKP_DR)); + + tmp = RTC->BAKUP[RTC_BKP_DR]; + + /* Read the specified register */ + return tmp; +} + + +/****************************************************************************** +* @brief: Enables or disables the specified RTC interrupts. +* @param: RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. +* @param: NewState: new state of the specified RTC interrupts. +* This parameter can be: ENABLE or DISABLE. +* @return: None +******************************************************************************/ +void HAL_RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT_FLAG(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RTC_IT Interrupt in the RTC_IE */ + RTC->IE |= RTC_IT ; + } + else + { + /* Disable the RTC_IT Interrupt in the RTC_IE */ + RTC->IE &= (~RTC_IT); + } +} + +/****************************************************************************** +* @brief: Checks whether the specified RTC flag is set or not. +* @param: RTC_FLAG: specifies the flag to check. +* @return: The new state of RTC_FLAG (SET or RESET). +******************************************************************************/ +FlagStatus HAL_RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_IT_FLAG(RTC_FLAG)); + + /* Return the status of the flag */ + if ((RTC->SR & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/****************************************************************************** +* @brief: Clears the RTC's pending flags. +* @param: RTC_FLAG: specifies the RTC flag to clear. +* @return: None +******************************************************************************/ +void HAL_RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->SR = RTC_FLAG; +} + +/****************************************************************************** +* @brief: Checks whether the specified RTC interrupt has occurred or not. +* @param: RTC_IT: specifies the RTC interrupt source to check. +* @return: The new state of RTC_IT (SET or RESET). +******************************************************************************/ +ITStatus HAL_RTC_GetITStatus(uint32_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_IT_FLAG(RTC_IT)); + + /* Get the status of the Interrupt */ + if (((RTC->IE & RTC_IT) != (uint32_t)RESET) && ((RTC->SR & RTC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/****************************************************************************** +* @brief: Clears the RTC's interrupt pending bits. +* @param: RTC_IT: specifies the RTC interrupt pending bit to clear. +* @return: none +******************************************************************************/ +void HAL_RTC_ClearITPendingBit(uint32_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT_FLAG(RTC_IT)); + + if((RTC->IE & RTC_IT)!= RESET) + { + /* Clear the interrupt pending bits in the RTC_SR register */ + RTC->SR = RTC_IT; + } +} + + +#endif + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sdmmc.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sdmmc.c new file mode 100644 index 0000000000000000000000000000000000000000..20355bab3a0d5f2c0ac78139d7ddce9c84eefd92 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sdmmc.c @@ -0,0 +1,1312 @@ +/* + ****************************************************************************** + * @file HAL_SDMMC.c + * @version V1.0.0 + * @date 2020 + * @brief SDIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital Input/Output(SDIO) Peripheral. + * @ Initialization and de-initialization functions + * @ Peripheral Control functions + * @ Standard commnad process functions + ****************************************************************************** +*/ +#include "hal.h" + +#ifdef HAL_SDMMC_MODULE_ENABLED + +static const uint32_t BitWidthTbl[] = {SDMMC_BW_1, SDMMC_BW_4, SDMMC_BW_8, SDMMC_BW_1, SDMMC_BW_1, SDMMC_BW_4, SDMMC_BW_8}; + + + +static void sdmmc_set_blk_size(SDMMC_HandleTypeDef *hsdmmc, uint16_t BlkSize) +{ + hsdmmc->Instance->SDMMC_BLKSIZ = BlkSize; +} + + +void sdmmc_card_clk_en(SDMMC_HandleTypeDef *hsdmmc) +{ + hsdmmc->Instance->SDMMC_CLKENA |= (1<Init.Ch); + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | SDMMC_WAIT_PRVDATA_END); + while((hsdmmc->Instance->SDMMC_CMD & SDMMC_START_CMD) != 0); +} + + +void sdmmc_card_clk_dis(SDMMC_HandleTypeDef *hsdmmc) +{ + hsdmmc->Instance->SDMMC_CLKENA &= (~(1<Init.Ch)); + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | SDMMC_WAIT_PRVDATA_END); + while((hsdmmc->Instance->SDMMC_CMD & SDMMC_START_CMD) != 0); + +} + + +/********************************************************************************* +* Function : HAL_SDMMC_MspInit +* Description : Initialize the SDIO MSP. +* Input : hsdmmc: SDIO handle. +* Output : status +**********************************************************************************/ +__weak void HAL_SDMMC_MspInit(SDMMC_HandleTypeDef *hsdmmc) +{ + ; +} + + +__weak void HAL_SDMMC_Sel_IO_Voltage(uint8_t LDO_SEL) +{ + ; +} + + +/********************************************************************************* +* Function : HAL_SDMMC_MspDeInit +* Description : DeInitialize the SDMMC MSP. +* Input : hsdmmc: SDIO handle. +* Output : status +**********************************************************************************/ +void HAL_SDMMC_MspDeInit(SDMMC_HandleTypeDef *hsdmmc) +{ + /* + NOTE: This function should be modified, when the callback is needed, + the HAL_SDIO_MspDeInit can be implemented in the user file. + */ + ; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Init +* Description : Initialize the SDIO according to the specified parameters +* in the SDMMC_InitTypeDef +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Init(SDMMC_HandleTypeDef *hsdmmc) +{ + int i; + +#ifdef USE_FULL_ASSERT + if(!IS_SDMMC_CH_VLD(hsdmmc->Init.Ch)) return HAL_ERROR; + if(!IS_SDMMC_ALL_INSTANCE(hsdmmc->Instance)) return HAL_ERROR; + if (!IS_SDMMC_VLD_MODE(hsdmmc->Init.TransMode)) return HAL_ERROR; + if(!IS_SDMMC_VLD_BW(hsdmmc->Init.TransBW)) return HAL_ERROR; +#endif + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SDMMC_MspInit(hsdmmc); + + HAL_RCC_SDMMCClockSourceConfig(SDMMC_CLK_SRC_SYS_CLK); + HAL_RCC_SDMMCSampleClockSourceConfig(SDMMC_SAMPLE_CLK_SDIO); + + hsdmmc->Instance->SDMMC_CTRL |= (SDMMC_CTRL_CTRL_RST | SDMMC_CTRL_FIFO_RST | SDMMC_CTRL_IDMA_RST); //reset SDIO Controller/FIFO/DMA + while(hsdmmc->Instance->SDMMC_CTRL & (SDMMC_CTRL_CTRL_RST | SDMMC_CTRL_FIFO_RST | SDMMC_CTRL_IDMA_RST)); + + hsdmmc->Instance->SDMMC_PWREN |= SDMMC_POWER_ON(hsdmmc->Init.Ch); + if(SD_IO_VCC_3V3==hsdmmc->Init.SDSigVoltage) + { + hsdmmc->Instance->SDMMC_CLKENA |= SDMMC_LOW_POWER(hsdmmc->Init.Ch); //low power mode + } + + hsdmmc->Instance->SDMMC_RINTSTS = 0x03FFFF; //clear all int status of current sdio channel + hsdmmc->Instance->SDMMC_UHS_REG = 0; + + +#ifdef SDMMC_INT_MODE + NVIC_ClearPendingIRQ(SDMMC_IRQn); + NVIC_EnableIRQ(SDMMC_IRQn); + hsdmmc->Instance->SDMMC_INTMASK = (0xFF|(1<Init.Ch)); //enable all int src of current sdio channel +// hsdmmc->Instance->SDMMC_INTMASK = (((1<<2)|(1<<11))|(1<Init.Ch)); //enable all int src of current sdio channel + hsdmmc->Instance->SDMMC_CTRL |= SDMMC_CTRL_INT_EN; +#endif + + if(hsdmmc->Init.IDmaEn) //IDMA enabled + { + hsdmmc->Instance->SDMMC_CTRL |= SDMMC_CTRL_USE_IDMA; + hsdmmc->Instance->SDMMC_BMOD = (SDMMC_BMOD_IDMA_PBL|SDMMC_BMOD_IDMA_EN); + } + + hsdmmc->Instance->SDMMC_CTYPE = (SDMMC_BW_1<Init.Ch); //Sigle wire mode while initialize + hsdmmc->Instance->SDMMC_TMOUT = SDMMC_TIMEOUT_RW | SDMMC_TIMEOUT_RESP ; //Set read data and wait response timeout value + hsdmmc->Instance->SDMMC_BLKSIZ = SDMMC_BLOCK_SIZE; + hsdmmc->Instance->SDMMC_FIFOTH = SDMMC_RX_LEVEL | SDMMC_TX_LEVEL; + hsdmmc->Instance->SDMMC_DEBNCE = SDMMC_DEBOUNCE_COUNT; + + if(hsdmmc->Init.CardType ==EMMC_CARD) + { + hsdmmc->SdEmmcRegInfo.rca = EMMC_RCA_VALUE; + hsdmmc->SdEmmcRegInfo.hcs = EMMC_HCS; + } + else + { + hsdmmc->SdEmmcRegInfo.rca = 0; + hsdmmc->SdEmmcRegInfo.hcs = SD_HCS; + } + + HAL_SDMMC_Sel_IO_Voltage(SD_IO_VCC_3V3); + + return HAL_OK; +} + + +void sdio_idma_desc_link(SDMMC_IDMA_DESC_INFO * sdio_idma_desc) +{ + uint32_t i; + SDMMC_IDMA_DESC_INFO *idam_desc; + + idam_desc = sdio_idma_desc; + + for(i=0; i<16; i++) + { + idam_desc->IDMA_Desc3_buf_addr2 = (uint32_t)(idam_desc+1); + idam_desc++; + } + idam_desc->IDMA_Desc3_buf_addr2 = 0; +} + + +/********************************************************************************* +* Function : HAL_SDMMC_SetClk +* Description : Set SDIO clock source and clock divide value +* Input : hsdmmc: SDMMC handle. +* div: divide value +* clk_src:clock source +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_SetClk(SDMMC_HandleTypeDef *hsdmmc, uint32_t div, uint32_t clk_src) +{ +// RCC->PER_CFGR = ((RCC->PER_CFGR & ~SDMMC_CLK_SRC_MSK) | SDMMC_CLK_SRC); + + hsdmmc->Instance->SDMMC_CLKENA &= ~(1<Init.Ch); //stop clk + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | SDMMC_WAIT_PRVDATA_END); + while((hsdmmc->Instance->SDMMC_CMD & SDMMC_START_CMD) != 0); + + hsdmmc->Instance->SDMMC_CLKSRC = ((hsdmmc->Instance->SDMMC_CLKSRC & (~(3<<(hsdmmc->Init.Ch<<1))))| (clk_src<<(hsdmmc->Init.Ch<<1))); + hsdmmc->Instance->SDMMC_CLKDIV = ((hsdmmc->Instance->SDMMC_CLKDIV & (~(0xFF<<(clk_src<<3))))|(div<<(clk_src<<3))); + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | SDMMC_WAIT_PRVDATA_END); + while((hsdmmc->Instance->SDMMC_CMD & SDMMC_START_CMD) != 0); + + hsdmmc->Instance->SDMMC_CLKENA |= (1<Init.Ch); //enable clk + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | SDMMC_WAIT_PRVDATA_END); + while((hsdmmc->Instance->SDMMC_CMD & (SDMMC_START_CMD)) != 0); + + hsdmmc->Instance->SDMMC_CLKENA |= (1<Init.Ch); //enable clk + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | SDMMC_WAIT_PRVDATA_END); + while((hsdmmc->Instance->SDMMC_CMD & (SDMMC_START_CMD)) != 0); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd_NoDat +* Description : Send command without argument +* Input : hsdmmc: SDMMC handle. +* cmd: command +* cmd_arg:argument of current command +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd_NoDat(SDMMC_HandleTypeDef *hsdmmc, uint32_t cmd, uint32_t cmd_arg) +{ + while(hsdmmc->Instance->SDMMC_STATUS&(1<<9)); //wait idle + hsdmmc->Instance->SDMMC_RINTSTS = 0x03FFFF; + + hsdmmc->Instance->SDMMC_CMDARG = cmd_arg; + + hsdmmc->Instance->SDMMC_CMD = (cmd | (hsdmmc->Init.Ch<<16)); + +#ifdef SDMMC_INT_MODE + while(!(hsdmmc->Intflg&SDMMC_RINT_CMD_CMPLT)); //wait for fifo empty + hsdmmc->Intflg &= ~SDMMC_RINT_CMD_CMPLT; +#else + while(!(hsdmmc->Instance->SDMMC_RINTSTS&SDMMC_RINT_CMD_CMPLT)); //wait for command transfer completed + hsdmmc->Instance->SDMMC_RINTSTS = SDMMC_RINT_CMD_CMPLT; //clear flg +#endif + + if(cmd == CMD1_MATCH_VCC) //R3 + { + if(hsdmmc->Instance->SDMMC_RINTSTS & SDMMC_RINT_RESP_TIMOUT) + { + hsdmmc->Instance->SDMMC_RINTSTS = SDMMC_RINT_RESP_TIMOUT; + return HAL_ERROR; + } + } + else + { + //error:ack/ack_crc,ack_timeout + if(hsdmmc->Instance->SDMMC_RINTSTS & (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT)) + { + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT); + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd_RdDat +* Description : command process which return data +* Input : hsdmmc: SDMMC handle. +* cmd: Command +* cmd_arg:Argument of current command +* length: Read data length +* buff: Read data buffer +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd_RdDat(SDMMC_HandleTypeDef *hsdmmc, uint32_t cmd, uint32_t cmd_arg, uint32_t length, uint32_t *buff) +{ + uint32_t i; + uint32_t mask; + uint32_t len, addr; + uint32_t idma_trans_cnt=0; + SDMMC_IDMA_DESC_INFO IdmaDesc[SDMMC_IDMA_DESC_NUM]; + + hsdmmc->Instance->SDMMC_CTRL |= (SDMMC_CTRL_FIFO_RST | SDMMC_CTRL_IDMA_RST); //reset SDIO FIFO/DMA + while(hsdmmc->Instance->SDMMC_CTRL & (SDMMC_CTRL_FIFO_RST | SDMMC_CTRL_IDMA_RST)); + + if(hsdmmc->Init.IDmaEn) + { + hsdmmc->Instance->SDMMC_CTRL = SDMMC_CTRL_IDMA_RST; + hsdmmc->Instance->SDMMC_BMOD |= SDMMC_BMOD_SWR; + len = length; + addr = (uint32_t)buff; + for(i=0; i=SDMMC_IDMA_MAX_SIZE)? SDMMC_IDMA_MAX_SIZE:len); + IdmaDesc[i].IDMA_Desc2_buf_addr1 = addr; + len -= IdmaDesc[i].IDMA_Desc1_buf_size; + addr += IdmaDesc[i].IDMA_Desc1_buf_size; + idma_trans_cnt++; + if(i==(SDMMC_IDMA_DESC_NUM-1)) + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[0]; + } + else + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[i+1]; + } + + if(0==len) + { + IdmaDesc[i].IDMA_Desc0_ctrl_stas &= ~SDMMC_IDMA_DESC_CHAINED; + IdmaDesc[i].IDMA_Desc0_ctrl_stas |= (SDMMC_IDMA_DESC_LAST); + break; + } + } + hsdmmc->Instance->SDMMC_CTRL |= SDMMC_CTRL_USE_IDMA; + hsdmmc->Instance->SDMMC_DBADDR = (uint32_t)IdmaDesc; + hsdmmc->Instance->SDMMC_IDINTEN |= SDMMC_IDINTEN_RI; + } + + while(hsdmmc->Instance->SDMMC_STATUS&(1<<9)); //wait idle + hsdmmc->Instance->SDMMC_RINTSTS = 0x03FFFF; //clear all int status + + hsdmmc->Instance->SDMMC_BYTCNT = length; + hsdmmc->Instance->SDMMC_CMDARG = cmd_arg; + hsdmmc->Instance->SDMMC_CMD = (cmd | (hsdmmc->Init.Ch<<16)); + +#ifdef SDMMC_INT_MODE + while(!(hsdmmc->Intflg&SDMMC_RINT_CMD_CMPLT)); //wait for fifo empty + hsdmmc->Intflg &= ~SDMMC_RINT_CMD_CMPLT; +#else + while(!(hsdmmc->Instance->SDMMC_RINTSTS&SDMMC_RINT_CMD_CMPLT)); //wait for command transfer completed + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_CMD_CMPLT|(1<<(hsdmmc->Init.Ch+16))); + +#endif + + if(hsdmmc->Init.IDmaEn) + { + i=0; + while(idma_trans_cnt) + { + while(!(hsdmmc->Instance->SDMMC_IDSTS&SDMMC_IDSTS_RI)); + hsdmmc->Instance->SDMMC_IDSTS = SDMMC_IDSTS_RI; + + //error:ack/ack_crc,ack_timeout + if(hsdmmc->Instance->SDMMC_RINTSTS & (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT)) + { + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT | (1<Init.Ch)); + return HAL_TIMEOUT; + } + + idma_trans_cnt--; + if(len) + { + IdmaDesc[i].IDMA_Desc0_ctrl_stas = (SDMMC_IDMA_DESC_OWN|SDMMC_IDMA_DESC_CHAINED); //addr2 include next descriptor address + IdmaDesc[i].IDMA_Desc1_buf_size = ((len>=SDMMC_IDMA_MAX_SIZE)? SDMMC_IDMA_MAX_SIZE:len); + IdmaDesc[i].IDMA_Desc2_buf_addr1 = addr; + len -= IdmaDesc[i].IDMA_Desc1_buf_size; + addr += IdmaDesc[i].IDMA_Desc1_buf_size; + idma_trans_cnt++; + if(i==(SDMMC_IDMA_DESC_NUM-1)) + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)IdmaDesc; + } + else + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[i+1]; + } + + if(0==len) + { + IdmaDesc[i].IDMA_Desc0_ctrl_stas |= SDMMC_IDMA_DESC_LAST; + } + } + } + } + else + { + //error:ack/ack_crc,ack_timeout + if(hsdmmc->Instance->SDMMC_RINTSTS & (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT)) + { + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT | (1<Init.Ch)); + return HAL_TIMEOUT; + } + + for(i=0;i<((length+3)>>2);i++) + { + while(hsdmmc->Instance->SDMMC_STATUS&SDMMC_FIFO_EMPTY); //wait while fifo is empty + buff[i] = hsdmmc->Instance->SDMMC_DATA; + } + } + +#ifdef SDMMC_INT_MODE + while(hsdmmc->Intflg&SDMMC_RINT_DAT_TRANS_CMPLT); //wait for data transfer completed + hsdmmc->Intflg &= ~SDMMC_RINT_DAT_TRANS_CMPLT; +#else + while(!(hsdmmc->Instance->SDMMC_RINTSTS & SDMMC_RINT_DAT_TRANS_CMPLT)); //wait for data transfer completed + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_DAT_TRANS_CMPLT | (1<Init.Ch)); //clear flg +#endif + + while(hsdmmc->Instance->SDMMC_STATUS & (1<<9)); //Wait D0 idle + + if(hsdmmc->Instance->SDMMC_STATUS & 0x3FFE0000) //FIFO not empty + { + hsdmmc->Instance->SDMMC_CTRL |= SDMMC_CTRL_FIFO_RST; //Reset fifo + while(hsdmmc->Instance->SDMMC_CTRL & SDMMC_CTRL_FIFO_RST); + } + + mask = ((cmd ==CMD14_BUSTEST_R)? 0xA200 : 0xA280); + + if(hsdmmc->Instance->SDMMC_RINTSTS & mask) + { + hsdmmc->Instance->SDMMC_RINTSTS = (mask | (1<Init.Ch)); + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd_WrDat +* Description : command process which write data +* Input : hsdmmc: SDMMC handle. +* cmd: Command +* cmd_arg:Argument of current command +* length: Read data length +* buff: Read data buffer +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd_WrDat(SDMMC_HandleTypeDef *hsdmmc, uint32_t cmd, uint32_t cmd_arg, uint32_t length, uint32_t *buff) +{ + uint32_t i; + uint32_t len, addr; + uint32_t idma_trans_cnt=0; + SDMMC_IDMA_DESC_INFO IdmaDesc[SDMMC_IDMA_DESC_NUM]; + + if(hsdmmc->Init.IDmaEn) + { + hsdmmc->Instance->SDMMC_CTRL = SDMMC_CTRL_IDMA_RST; + hsdmmc->Instance->SDMMC_BMOD |= SDMMC_BMOD_SWR; + len = length; + addr = (uint32_t)buff; + for(i=0; i=SDMMC_IDMA_MAX_SIZE)? SDMMC_IDMA_MAX_SIZE:len); + IdmaDesc[i].IDMA_Desc2_buf_addr1 = addr; + len -= IdmaDesc[i].IDMA_Desc1_buf_size; + addr += IdmaDesc[i].IDMA_Desc1_buf_size; + idma_trans_cnt++; + if(i==(SDMMC_IDMA_DESC_NUM-1)) + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[0]; + } + else + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[i+1]; + } + if(0==len) + { + IdmaDesc[i].IDMA_Desc0_ctrl_stas &= ~SDMMC_IDMA_DESC_CHAINED; + IdmaDesc[i].IDMA_Desc0_ctrl_stas |= (SDMMC_IDMA_DESC_LAST); + break; + } + } + + hsdmmc->Instance->SDMMC_CTRL |= SDMMC_CTRL_USE_IDMA; + hsdmmc->Instance->SDMMC_DBADDR = (uint32_t)IdmaDesc; + hsdmmc->Instance->SDMMC_IDINTEN |= SDMMC_IDINTEN_TI; + } + + while(hsdmmc->Instance->SDMMC_STATUS&(1<<9)); //wait idle + hsdmmc->Instance->SDMMC_RINTSTS = 0x03FFFF; //clear all int status + + hsdmmc->Instance->SDMMC_BYTCNT = length; + hsdmmc->Instance->SDMMC_CMDARG = cmd_arg; + hsdmmc->Instance->SDMMC_CMD = (cmd | (hsdmmc->Init.Ch<<16)); + +#ifdef SDMMC_INT_MODE + while(!(hsdmmc->Intflg&SDMMC_RINT_CMD_CMPLT)); //wait for fifo empty + hsdmmc->Intflg &= ~SDMMC_RINT_CMD_CMPLT; +#else + while(!(hsdmmc->Instance->SDMMC_RINTSTS&SDMMC_RINT_CMD_CMPLT)); //wait for command transfer completed + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_CMD_CMPLT | (1<<(hsdmmc->Init.Ch+16))); //clear flg +#endif + + if(hsdmmc->Init.IDmaEn) + { + i=0; + while(idma_trans_cnt) + { + while(!(hsdmmc->Instance->SDMMC_IDSTS&SDMMC_IDSTS_TI)); + hsdmmc->Instance->SDMMC_IDSTS = SDMMC_IDSTS_TI; + + //error:ack/ack_crc,ack_timeout + if(hsdmmc->Instance->SDMMC_RINTSTS & (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT)) + { + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT | (1<Init.Ch)); + return HAL_TIMEOUT; + } + + idma_trans_cnt--; + if(len) + { + IdmaDesc[i].IDMA_Desc0_ctrl_stas = (SDMMC_IDMA_DESC_OWN|SDMMC_IDMA_DESC_CHAINED); //addr2 include next descriptor address + IdmaDesc[i].IDMA_Desc1_buf_size = ((len>=SDMMC_IDMA_MAX_SIZE)? SDMMC_IDMA_MAX_SIZE:len); + IdmaDesc[i].IDMA_Desc2_buf_addr1 = addr; + len -= IdmaDesc[i].IDMA_Desc1_buf_size; + addr += IdmaDesc[i].IDMA_Desc1_buf_size; + idma_trans_cnt++; + if(i==(SDMMC_IDMA_DESC_NUM-1)) + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[0]; + } + else + { + IdmaDesc[i].IDMA_Desc3_buf_addr2 = (uint32_t)&IdmaDesc[i+1]; + } + if(0==len) + { + IdmaDesc[i].IDMA_Desc0_ctrl_stas |= SDMMC_IDMA_DESC_LAST; + } + } + } + } + else + { + //error:ack/ack_crc,ack_timeout + if(hsdmmc->Instance->SDMMC_RINTSTS & (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT)) + { + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_RESP_ERR | SDMMC_RINT_RESP_CRC_ERR | SDMMC_RINT_RESP_TIMOUT | (1<Init.Ch)); + return HAL_TIMEOUT; + } + + for(i=0;i<((length+3)>>2);i++) + { + while(!(hsdmmc->Instance->SDMMC_STATUS&SDMMC_FIFO_TX_LEV_DOWN)); //wait while fifo level is low than tx level + hsdmmc->Instance->SDMMC_DATA = buff[i]; + } + } + +#ifdef SDMMC_INT_MODE + while(hsdmmc->Intflg&SDMMC_RINT_DAT_TRANS_CMPLT); //wait for fifo empty + hsdmmc->Intflg &= ~SDMMC_RINT_DAT_TRANS_CMPLT; +#else + while(!(hsdmmc->Instance->SDMMC_RINTSTS & SDMMC_RINT_DAT_TRANS_CMPLT)); //wait for command transfer completed + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_DAT_TRANS_CMPLT | (1<Init.Ch)); //clear flg +#endif + + hsdmmc->Instance->SDMMC_CTRL |= SDMMC_CTRL_FIFO_RST; //Reset fifo + while(hsdmmc->Instance->SDMMC_STATUS & (1<<9)); //Wait card idle + + if(cmd !=CMD19_BUSTEST_W) + { + if(hsdmmc->Instance->SDMMC_RINTSTS & (SDMMC_RINT_DAT_CRC_ERR | SDMMC_RINT_EBIT_WCRC_ERR)) + { + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_DAT_CRC_ERR | SDMMC_RINT_EBIT_WCRC_ERR | (1<Init.Ch)); + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd0_GoIdle +* Description : command process which write data +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd0_GoIdle(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t cmd_arg; + + cmd_arg = ((hsdmmc->Init.CardType==EMMC_CARD)? 0xF0F0F0F0 : 0); + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD0_GO_IDLE, cmd_arg); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd1_SendOp +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd1_SendOp(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t cmd_arg; + uint32_t i, t=0; + uint32_t resp_tbl[10]; + + if(hsdmmc->Init.CardType != EMMC_CARD) return 0xFF; + + cmd_arg= (hsdmmc->SdEmmcRegInfo.hcs<<30)|EMMC_VDD_WINDOW; + + while(1) + { + if(HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD1_MATCH_VCC, cmd_arg)) + { + return HAL_ERROR; + } + + if(t<10) + { + resp_tbl[t++] = hsdmmc->Instance->SDMMC_RESP0; + } + if(hsdmmc->Instance->SDMMC_RESP0 & (1UL<<31)) //Wait internal power up routine finish + { + for(i=0; iInstance->SDMMC_RESP0>>30)&0x01) != hsdmmc->SdEmmcRegInfo.hcs) //capacity is not compatible + { + hsdmmc->SdEmmcRegInfo.hcs = ((hsdmmc->Instance->SDMMC_RESP0>>30)&0x01); + } + + hsdmmc->SdEmmcRegInfo.ocr = hsdmmc->Instance->SDMMC_RESP0; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd2_GetCid +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd2_GetCid(SDMMC_HandleTypeDef *hsdmmc) +{ + if(HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD2_CID, 0)) //enter pre idle state + { + return HAL_ERROR; + } + + hsdmmc->SdEmmcRegInfo.cid[0] = hsdmmc->Instance->SDMMC_RESP0; + hsdmmc->SdEmmcRegInfo.cid[1] = hsdmmc->Instance->SDMMC_RESP1; + hsdmmc->SdEmmcRegInfo.cid[2] = hsdmmc->Instance->SDMMC_RESP2; + hsdmmc->SdEmmcRegInfo.cid[3] = hsdmmc->Instance->SDMMC_RESP3; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd3_Rca +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd3_Rca(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t result; + uint32_t cmd_arg; + + cmd_arg = ((hsdmmc->Init.CardType==EMMC_CARD)? (hsdmmc->SdEmmcRegInfo.rca<<16) : 0); + + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD3_RCA, cmd_arg))) + { + return result; + } + + if(hsdmmc->Init.CardType == SD_CARD) + { + hsdmmc->SdEmmcRegInfo.rca = (hsdmmc->Instance->SDMMC_RESP0>>16); + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd5_Sleep +* Description : Switch eMMC card to sleep/awake mode. +* Input : hsdmmc: SDMMC handle. +* sleep_awake: 1-sleep 0-awake +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd5_Sleep(SDMMC_HandleTypeDef *hsdmmc, uint8_t sleep_awake) +{ + uint32_t cmd_arg; + + if(hsdmmc->Init.CardType == SD_CARD) + { + return HAL_OK; + } + + cmd_arg = (sleep_awake? (hsdmmc->SdEmmcRegInfo.rca|(1<<15)) : hsdmmc->SdEmmcRegInfo.rca); + + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD5_SLEEP, cmd_arg); +} + + + +/********************************************************************************* +* Function : HAL_EMMC_Cmd6_Switch +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ + +HAL_StatusTypeDef HAL_EMMC_Cmd6_Switch(SDMMC_HandleTypeDef *hsdmmc, uint8_t index, uint8_t Val) +{ + uint32_t cmd_arg; + + cmd_arg = (MMC_SWITCH_MODE_WRITE_BYTE<<24) | (index<<16) | (Val<<8); + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD6_SWTICH, cmd_arg); +} + + +HAL_StatusTypeDef HAL_SD_Cmd6_Switch(SDMMC_HandleTypeDef *hsdmmc, uint32_t cmd_arg, uint32_t *pRespBuf) +{ + uint32_t result=0; + + if(NULL == pRespBuf) + { + return 0x02; + } + sdmmc_set_blk_size(hsdmmc, 64); + result = HAL_SDMMC_Cmd_RdDat(hsdmmc, CMD6_SWTICH, cmd_arg, 64, pRespBuf); + sdmmc_set_blk_size(hsdmmc, SDMMC_BLOCK_SIZE); + + if(result) + { + return 0x01; + } + return 0; +} + +//switch access mode of SD card +HAL_StatusTypeDef HAL_SD_Cmd6_Switch_AM(SDMMC_HandleTypeDef *hsdmmc, uint8_t AccessMode) +{ + uint32_t result=0; + uint32_t cmd_arg; + uint8_t tmp_buf[64]; + + //bit31: 0-check mode 1-switch mode + cmd_arg = ((1UL<<31) | 0x00000000 | (AccessMode<<0) | (3<<12)); //DDR50 mode and 800mA limit + + sdmmc_set_blk_size(hsdmmc, 64); + if(0!=(result=HAL_SDMMC_Cmd_RdDat(hsdmmc, (CMD6_SWTICH|(1<<9)), cmd_arg, 64, (uint32_t *)tmp_buf))) + { + return result; + } + + sdmmc_set_blk_size(hsdmmc, SDMMC_BLOCK_SIZE); + if(SD_ACCESS_MODE_DDR50==AccessMode) + { + hsdmmc->Instance->SDMMC_UHS_REG |= (1UL<<(hsdmmc->Init.Ch+16)); + } + else + { + hsdmmc->Instance->SDMMC_UHS_REG &= (~(1UL<<(hsdmmc->Init.Ch+16))); + } + + return 0; +} + + +//send tuning pattern +HAL_StatusTypeDef HAL_SD_Cmd19_Tuning_Pattern(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t result=0; + + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD19_BUSTEST_W, 0))) + { + return result; + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd6_SwitchBitW +* Description : +* Input : hsdmmc: SDMMC handle. +* bus_width: destinate bus width +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd6_SwitchBitW(SDMMC_HandleTypeDef *hsdmmc, uint32_t bus_width) +{ + uint32_t result=0; + uint32_t cmd_arg; + uint32_t temp; + + if((bus_width)==SDMMC_TRANS_BW_4) cmd_arg = 0x03B70100; + else if ((bus_width)==SDMMC_TRANS_BW_8) cmd_arg = 0x03B70200; + else if ((bus_width)==SDMMC_TRANS_DDR_4) cmd_arg = 0x03B70500; + else if ((bus_width)==SDMMC_TRANS_DDR_8) cmd_arg = 0x03B70600; + else return 0x01; + + result=HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD6_SWTICH, cmd_arg); + if(result) + { + return 0x02; + } + + hsdmmc->Instance->SDMMC_CTYPE &= ~((1UL<Init.Ch) | (1UL<<(16+hsdmmc->Init.Ch))); + hsdmmc->Instance->SDMMC_CTYPE |= (BitWidthTbl[hsdmmc->Init.TransBW]<Init.Ch); + + if(SDMMC_MODE_DDR==hsdmmc->Init.TransMode) + { + hsdmmc->Instance->SDMMC_UHS_REG |= (1<<(hsdmmc->Init.Ch+16)); + } + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_SD_Acmd6_set_bus_width(SDMMC_HandleTypeDef *hsdmmc, uint32_t bus_width) +{ + uint32_t result=0; + uint32_t cmd_arg; + uint32_t temp; + + result=HAL_SDMMC_cmd55_app(hsdmmc); + if(result) + { + return 0x01; + } + + if((bus_width&0x03)==SDMMC_TRANS_BW_1) cmd_arg = 0x00; + else if ((bus_width&0x03)==SDMMC_TRANS_BW_4) cmd_arg = 0x02; + else return 0x02; + + result=HAL_SDMMC_Cmd_NoDat(hsdmmc, ACMD6_SET_BUS_WIDTH, cmd_arg); + if(result) + { + return 0x03; + } + + hsdmmc->Instance->SDMMC_CTYPE &= ~((1UL<Init.Ch) | (1UL<<(16+hsdmmc->Init.Ch))); + hsdmmc->Instance->SDMMC_CTYPE |= (BitWidthTbl[hsdmmc->Init.TransBW]<Init.Ch); + + return 0; +} + + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd7_Sel +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd7_Sel(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t cmd_arg; + + cmd_arg = hsdmmc->SdEmmcRegInfo.rca<<16; + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD7_SELECT_CARD, cmd_arg); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd8_GetExtCsd +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd8_GetExtCsd(SDMMC_HandleTypeDef *hsdmmc, uint32_t *buff) +{ + uint32_t cmd_arg; + uint32_t result=0; + + if(hsdmmc->Init.CardType==EMMC_CARD) + { + cmd_arg = 0; + return HAL_SDMMC_Cmd_RdDat(hsdmmc, CMD8_EXT_CSD_EMMC, cmd_arg, 512, buff); + } + else + { + cmd_arg = ((1<<8)|0xAA); //2.7V~3.3V + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD8_EXT_CSD_SD, cmd_arg))) + { + return result; + } + + if(hsdmmc->Instance->SDMMC_RESP0 != cmd_arg) + { + return HAL_ERROR; //VCC out of range + } + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd9_GetCsd +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd9_GetCsd(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t result=0; + + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD9_CSD, (hsdmmc->SdEmmcRegInfo.rca<<16)))) + { + return result; + } + + hsdmmc->SdEmmcRegInfo.csd[0] = hsdmmc->Instance->SDMMC_RESP0; + hsdmmc->SdEmmcRegInfo.csd[1] = hsdmmc->Instance->SDMMC_RESP1; + hsdmmc->SdEmmcRegInfo.csd[2] = hsdmmc->Instance->SDMMC_RESP2; + hsdmmc->SdEmmcRegInfo.csd[3] = hsdmmc->Instance->SDMMC_RESP3; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd11_SwitchVoltage +* Description : switch to 1.8V bus signal level, only for SD card +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd11_SwitchVoltage(SDMMC_HandleTypeDef *hsdmmc) +{ + if(hsdmmc->Init.CardType==EMMC_CARD) + { + return HAL_OK; + } + + while(hsdmmc->Instance->SDMMC_STATUS&(1<<9)); //wait idle + hsdmmc->Instance->SDMMC_RINTSTS = 0x03FFFF; + hsdmmc->Instance->SDMMC_CMDARG = 0; + hsdmmc->Instance->SDMMC_CMD = (CMD11_SWITCH_VOLTAGE | (hsdmmc->Init.Ch<<16)); + + //wait for Volt_switch_int + HAL_Delay(2); + if(!(hsdmmc->Instance->SDMMC_RINTSTS & SDMMC_RINT_DTO_VSHINT)) //Wait IO voltage switch interrupt flg + { + return HAL_TIMEOUT; + } + hsdmmc->Instance->SDMMC_RINTSTS = SDMMC_RINT_DTO_VSHINT; //clear Volt_switch_int flg + + //stop clk + hsdmmc->Instance->SDMMC_CLKENA &= (~(1<Init.Ch)); + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | (1<<28)); + + //switch voltage + HAL_SDMMC_Sel_IO_Voltage(SD_IO_VCC_1V8); + hsdmmc->Instance->SDMMC_UHS_REG |= (1<Init.Ch); + HAL_Delay(5); + + //start clk + hsdmmc->Instance->SDMMC_CLKENA |= (1<Init.Ch); + HAL_Delay(1); + hsdmmc->Instance->SDMMC_CMD = (SDMMC_START_CMD | SDMMC_UPDATE_CLK_ONLY | (1<<28)); + HAL_Delay(1); + + while(!(hsdmmc->Instance->SDMMC_RINTSTS&SDMMC_RINT_CMD_CMPLT)); //wait for command transfer completed + hsdmmc->Instance->SDMMC_RINTSTS = (SDMMC_RINT_CMD_CMPLT|SDMMC_RINT_DTO_VSHINT); //clear Command done flg + + return 0; +} + + +HAL_StatusTypeDef HAL_SDMMC_Cmd12_StopStream(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t cmd_arg; + + cmd_arg= hsdmmc->SdEmmcRegInfo.rca<<16; + + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD12_STOP_STEARM, cmd_arg); +} + + + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd16_SetBlkLen +* Description : +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd16_SetBlkLen(SDMMC_HandleTypeDef *hsdmmc, uint32_t block_size) +{ + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD16_SET_BLOCKLEN, block_size); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd17_RdSingle +* Description : read single block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd17_RdSingle(SDMMC_HandleTypeDef *hsdmmc, uint32_t blk_addr, uint32_t *buff) +{ + uint32_t addr; + + addr = ((hsdmmc->SdEmmcRegInfo.hcs==STANDRAD_CAPACITY)? blk_addr*SDMMC_BLOCK_SIZE : blk_addr); + + return HAL_SDMMC_Cmd_RdDat(hsdmmc, CMD17_READ_SINGLE, addr, SDMMC_BLOCK_SIZE, buff); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd18_RdMul +* Description : read multiple block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd18_RdMul(SDMMC_HandleTypeDef *hsdmmc, uint32_t blk_addr, uint32_t blk_num, uint32_t *buff) +{ + uint32_t addr; + + addr = ((hsdmmc->SdEmmcRegInfo.hcs==STANDRAD_CAPACITY)? blk_addr*SDMMC_BLOCK_SIZE : blk_addr); + + return HAL_SDMMC_Cmd_RdDat(hsdmmc, CMD18_READ_MUL, addr, blk_num*SDMMC_BLOCK_SIZE, buff); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd24_WrSingle +* Description : write single block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd24_WrSingle(SDMMC_HandleTypeDef *hsdmmc, uint32_t blk_addr, uint32_t *buff) +{ + uint32_t addr; + + addr = ((hsdmmc->SdEmmcRegInfo.hcs==STANDRAD_CAPACITY)? blk_addr*SDMMC_BLOCK_SIZE : blk_addr); + + return HAL_SDMMC_Cmd_WrDat(hsdmmc, CMD24_WRITE_SINGLE, addr, SDMMC_BLOCK_SIZE, buff); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd25_WrMul +* Description : write single block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd25_WrMul(SDMMC_HandleTypeDef *hsdmmc, uint32_t blk_addr, uint32_t blk_num, uint32_t *buff) +{ + uint32_t addr; + + addr = ((hsdmmc->SdEmmcRegInfo.hcs==STANDRAD_CAPACITY)? blk_addr*SDMMC_BLOCK_SIZE : blk_addr); + + return HAL_SDMMC_Cmd_WrDat(hsdmmc, CMD25_WRITE_MUL, addr, blk_num*SDMMC_BLOCK_SIZE, buff); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Cmd28_Erase +* Description : erase destinate block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Cmd28_Erase(SDMMC_HandleTypeDef *hsdmmc, uint32_t blk_start_addr, uint32_t blk_num) +{ + uint32_t cmd; + uint32_t addr; + uint32_t result; + + cmd = ((hsdmmc->Init.CardType==EMMC_CARD)? CMD35_ERASESD_START : CMD32_ERASESD_START); + addr = ((hsdmmc->SdEmmcRegInfo.hcs==STANDRAD_CAPACITY)? blk_start_addr*SDMMC_BLOCK_SIZE : blk_start_addr); + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, cmd, addr))) + { + return result; + } + + cmd = ((hsdmmc->Init.CardType==EMMC_CARD)? CMD36_ERASESD_END : CMD33_ERASESD_END); + addr += ((hsdmmc->SdEmmcRegInfo.hcs==STANDRAD_CAPACITY)? ((blk_num-1)*SDMMC_BLOCK_SIZE) : ((blk_num-1))); + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, cmd, addr))) + { + return result; + } + + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD38_ERASE, 0); +} + +/********************************************************************************* +* Function : HAL_SDMMC_cmd55_app +* Description : +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_cmd55_app(SDMMC_HandleTypeDef *hsdmmc) +{ + return HAL_SDMMC_Cmd_NoDat(hsdmmc, CMD55_APP, (hsdmmc->SdEmmcRegInfo.rca<<16)); +} + +/********************************************************************************* +* Function : HAL_SDMMC_Acmd6_SetBusW +* Description : erase destinate block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Acmd6_SetBusW(SDMMC_HandleTypeDef *hsdmmc) +{ + uint32_t result=0; + uint32_t cmd_arg; + + if(0!= (result=HAL_SDMMC_cmd55_app(hsdmmc))) + { + return result; + } + + if(hsdmmc->Init.TransBW==SDMMC_TRANS_BW_1) + { + cmd_arg = 0x00; + } + else if(hsdmmc->Init.TransBW==SDMMC_TRANS_BW_4) + { + cmd_arg = 0x02; + } + else + { + return HAL_ERROR; + } + + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, ACMD6_SET_BUS_WIDTH, cmd_arg))) + { + return result; + } + + hsdmmc->Instance->SDMMC_CTYPE &= ~((1UL<Init.Ch) | (1UL<<(16+hsdmmc->Init.Ch))); + hsdmmc->Instance->SDMMC_CTYPE |= (BitWidthTbl[hsdmmc->Init.TransBW]<Init.Ch); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_SDMMC_Acmd41_SendCond +* Description : erase destinate block +* Input : hsdmmc: SDMMC handle. +* block_size: +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SDMMC_Acmd41_SendCond(SDMMC_HandleTypeDef *hsdmmc, uint8_t power_level) +{ + uint32_t result=0; + uint32_t arg; + + while(1) + { + if(0!=(result=HAL_SDMMC_cmd55_app(hsdmmc))) + { + return result; + } + + if(SD_IO_VCC_3V3==power_level) + { + arg = (hsdmmc->SdEmmcRegInfo.hcs<<30)|SD_VDD_WINDOW; + } + else + { + arg = (hsdmmc->SdEmmcRegInfo.hcs<<30)|SD_VDD_WINDOW|(1<<24)|(1<<28); + } + + if(0!=(result=HAL_SDMMC_Cmd_NoDat(hsdmmc, ACMD41_SEND_COND, arg))) + { + return result; + } + + if(hsdmmc->Instance->SDMMC_RESP0 & (1UL<<31)) + { + break; + } + } + + if(((hsdmmc->Instance->SDMMC_RESP0>>30)&0x01) != hsdmmc->SdEmmcRegInfo.hcs) //capacity is not accordance + { + hsdmmc->SdEmmcRegInfo.hcs = ((hsdmmc->Instance->SDMMC_RESP0>>30)&0x01); + } + + hsdmmc->SdEmmcRegInfo.ocr = hsdmmc->Instance->SDMMC_RESP0; + + if(SD_IO_VCC_1V8==power_level) + { + if(!(hsdmmc->Instance->SDMMC_RESP0&(1<<24))) //SD card not support 1.8V signal voltage + { + hsdmmc->Init.SDSigVoltage = SD_IO_VCC_3V3; + } + } + + return HAL_OK; +} + + +HAL_StatusTypeDef HAL_SDMMC_Acmd51_SendScr(SDMMC_HandleTypeDef *hsdmmc, uint8_t *pScr) +{ + uint32_t result=0; + uint32_t arg; + uint32_t scrbuf[2]; + + while(1) + { + if(0!=(result=HAL_SDMMC_cmd55_app(hsdmmc))) + { + return result; + } + + if(0!=(result=HAL_SDMMC_Cmd_RdDat(hsdmmc, ACMD51_GET_SCR, 0, 2, (uint32_t *)pScr))) + { + return result; + } + + if(hsdmmc->Instance->SDMMC_RESP0 & (1UL<<31)) + { + break; + } + } + + if(((hsdmmc->Instance->SDMMC_RESP0>>30)&0x01) != hsdmmc->SdEmmcRegInfo.hcs) //capacity is not accordance + { + hsdmmc->SdEmmcRegInfo.hcs = ((hsdmmc->Instance->SDMMC_RESP0>>30)&0x01); + } + + hsdmmc->SdEmmcRegInfo.ocr = hsdmmc->Instance->SDMMC_RESP0; + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_MMC_Enum +* Description : erase destinate block +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_EMMC_Enum(SDMMC_HandleTypeDef *hsdmmc, uint32_t SrcClk) +{ + uint32_t result=0; + uint32_t div; + +// div=(SrcClk/400000)+4; //set SDIO bus clock to (0~400KHz) + div=(SrcClk/100000)+4; //set SDIO bus clock to (0~400KHz) +// div=div/2; + + if(0!=(result = HAL_SDMMC_SetClk(hsdmmc, div, SDMMC_CLK_SRC_DIV0))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Cmd0_GoIdle(hsdmmc))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Cmd1_SendOp(hsdmmc))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Cmd2_GetCid(hsdmmc))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Cmd3_Rca(hsdmmc))) + { + return result; + } + + div = SrcClk/hsdmmc->Init.BusClk; + if(SrcClk%hsdmmc->Init.BusClk) + { + div++; + } + printfS("SDMMC CLK= %d Mhz\n", (SrcClk/div)/1000000); + + return HAL_SDMMC_SetClk(hsdmmc, div, SDMMC_CLK_SRC_DIV1); +} + +/********************************************************************************* +* Function : HAL_SD_Enum +* Description : +* Input : hsdmmc: SDMMC handle. +* Output : status +**********************************************************************************/ +HAL_StatusTypeDef HAL_SD_Enum(SDMMC_HandleTypeDef *hsdmmc, uint32_t SrcClk) +{ + uint32_t result=0; + uint32_t div; + + div=(SrcClk/400000)+4; //set SDIO bus clock to (0~400KHz) + div=div/2; + + if(0!=(result = HAL_SDMMC_SetClk(hsdmmc, div, SDMMC_CLK_SRC_DIV0))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Cmd0_GoIdle(hsdmmc))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Cmd8_GetExtCsd(hsdmmc, NULL))) + { + return result; + } + + if(0!=(result = HAL_SDMMC_Acmd41_SendCond(hsdmmc, hsdmmc->Init.SDSigVoltage))) + { + return result; + } + + if(SD_IO_VCC_1V8==hsdmmc->Init.SDSigVoltage) //use only while switch to 1.8V + { + if(0!=(result = HAL_SDMMC_Cmd11_SwitchVoltage(hsdmmc))) + { + return result; + } + } + + if(0!=(result = HAL_SDMMC_Cmd2_GetCid(hsdmmc))) + { + return result; + } + + return HAL_SDMMC_Cmd3_Rca(hsdmmc); +} + + + +#endif + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sha1_20230713.lib b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sha1_20230713.lib new file mode 100644 index 0000000000000000000000000000000000000000..c99d18a27a051ef7bed58bc2f9ddcfeb490d159e Binary files /dev/null and b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sha1_20230713.lib differ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sha256_20230713.lib b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sha256_20230713.lib new file mode 100644 index 0000000000000000000000000000000000000000..21a89ec011b23e0bcd16c8ba7512ae7cbb3e51ac Binary files /dev/null and b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_sha256_20230713.lib differ diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_spi.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..c098a7bc51a57967061ed40e076bc761d08c0175 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_spi.c @@ -0,0 +1,1663 @@ +/****************************************************************************** +*@file : hal_spi.c +*@brief : This file provides firmware functions to manage the SPI HAL module +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ +#include "hal_spi.h" + +#ifdef HAL_SPI_MODULE_ENABLED + +/****************************************************************************** +*@brief : SPI interrupt handler +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: None +*@note : Execute HAL_SPI_IRQHandler funcion in SRAM may speed up the TXFIFO/RXFIFO operation +******************************************************************************/ +__weak void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + if ( (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_NOT_EMPTY) && ((hspi->Instance->IE) & SPI_IE_RX_FIFO_NOT_EMPTY_EN) ) + { + do{ + if (hspi->Rx_Count < hspi->Rx_Size) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + } + else break; + }while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_NOT_EMPTY); + } + + if ( (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_HALF_EMPTY) && ((hspi->Instance->IE) & SPI_IE_TX_FIFO_HALF_EMPTY_EN) ) + { + while (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + if(hspi->Tx_Count < hspi->Tx_Size) + { + hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + } + else + { + /* Disable TxFIFO half empty interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN); + break; + } + } + } + + if ((hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_IE_TX_BATCH_DONE_EN) ) + { + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(hspi->Instance, SPI_STATUS_TX_BATCH_DONE); + + /* Disable TX Batch Done Interrupt, Tx FIFO half empty Interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_BATCH_DONE_EN | SPI_IE_TX_FIFO_HALF_EMPTY_EN); + + if ( (hspi->Init.SPI_Mode == SPI_MODE_MASTER) && (hspi->KeepCS == false) ) + { + /* CS de-active */ + __HAL_SPI_CS_RELEASE(hspi); + } + + /* Tx Disable */ + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_EN); + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_DMA_REQ_EN); + + hspi->TxState = SPI_TX_STATE_IDLE; + } + + if ( (hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_STATUS_RX_BATCH_DONE) ) + { + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(hspi->Instance, SPI_STATUS_RX_BATCH_DONE); + + /* Disable RX Batch Done Interrupt, RXFIFO not Empty interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_RX_BATCH_DONE_EN | SPI_IE_RX_FIFO_NOT_EMPTY_EN); + + while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_NOT_EMPTY) + { + if (hspi->Rx_Count < hspi->Rx_Size) + { + hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT; + } + else break; + } + ///////////// + + if ( (hspi->Init.SPI_Mode == SPI_MODE_MASTER) && (hspi->KeepCS == false) ) + { + /* CS de-active */ + __HAL_SPI_CS_RELEASE(hspi); + } + + /* Rx Disable */ + CLEAR_BIT(hspi->Instance->RX_CTL, SPI_RX_CTL_DMA_REQ_EN); + CLEAR_BIT(hspi->Instance->RX_CTL, SPI_RX_CTL_EN); + + hspi->RxState = SPI_RX_STATE_IDLE; + } +} + +/****************************************************************************** +*@brief : Init low level of SPI module: GPIO, CLK, NVIC +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: None +******************************************************************************/ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); +} + +/****************************************************************************** +*@brief : SPI De-Initialize the SPI clock, GPIO, IRQ. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: None +******************************************************************************/ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); +} + +/****************************************************************************** +*@brief : Initialize the SPI module with parameters +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param (IS_SPI_ALL_MODE(hspi->Init.SPI_Mode)); + assert_param (IS_SPI_WORK_MODE(hspi->Init.SPI_Work_Mode)); + assert_param (IS_SPI_X_MODE(hspi->Init.X_Mode)); + assert_param (IS_SPI_FIRST_BIT(hspi->Init.First_Bit)); + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + assert_param (IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRate_Prescaler)); + } + else + { + assert_param (IS_SPI_INSTANCE_SLAVE_MODE(hspi->Instance)); + } + + if(hspi->Init.X_Mode == SPI_4X_MODE) + { + assert_param (IS_SPI_INSTANCE_4X_MODE(hspi->Instance)); + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SPI_MspInit(hspi); + + /* Automatic change direction */ + hspi->Instance->CTL |= (SPI_CTL_IO_MODE); + + /* Set SPI Work mode */ + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + SET_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE); + MODIFY_REG(hspi->Instance->RX_CTL, SPI_RX_CTL_SSHIFT_Msk, hspi->Init.Master_SShift); + + assert_param(IS_SPI_CS_SEL(hspi->CSx)); + + if((hspi->CSx == SPI_CS_CS1) || (hspi->CSx == SPI_CS_CS2)) + { + //SET_BIT(hspi->Instance->CS, SPI_CSMAP_EN); + + hspi->Instance->CS = SPI_CSMAP_EN; + } + else + { + //CLEAR_BIT(hspi->Instance->CS, SPI_CSMAP_EN); + + hspi->Instance->CS = 0; + } + } + else + { + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE); + + if(hspi->Init.Slave_SofteCs_En == SPI_SLAVE_SOFT_CS_ENABLE) + { + SET_BIT(hspi->Instance->CTL, SPI_CTL_SWCS_EN); + SET_BIT(hspi->Instance->CTL, SPI_CTL_SWCS); //Soft CS set to HIGH. + } + else + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_SWCS_EN); + + hspi->Instance->BATCH = (hspi->Instance->BATCH & (~0x000FFFFFU)) | (1 << 0); + + hspi->Instance->TX_CTL |= SPI_TX_CTL_MODE | (0x88 << 8); // dummy data = 0x88 + + //if (hspi->Init.X_Mode != SPI_1X_MODE) + { + hspi->Instance->CTL |= SPI_CTL_SFILTER | SPI_CTL_CS_FILTER; + } + + /* Slave Alternate Enable */ + hspi->Instance->CTL |= SPI_CTL_SLAVE_EN; + + /* Slave Mode Enable Rx By Default */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + } + + /* Set SPI First Bit */ + if (hspi->Init.First_Bit == SPI_FIRSTBIT_LSB) + SET_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST); + else + CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST); + + /* Set SPI Work Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~(SPI_CTL_CPHA | SPI_CTL_CPOL))) | (hspi->Init.SPI_Work_Mode); + + /* Set SPI X_Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | (hspi->Init.X_Mode); + + /* Set SPI BaudRate Prescaler */ + hspi->Instance->BAUD = ((hspi->Instance->BAUD) & (~0x0000FFFF)) | (hspi->Init.BaudRate_Prescaler); + + /* Disable All Interrupt */ + hspi->Instance->IE = 0x00000000; + + assert_param(hspi->Instance->STATUS != 0); + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_SPI_MEMACCInit(SPI_HandleTypeDef* hspi, SPI_MemACCInitTypeDef* MemACCParam) +{ + SPI_TypeDef* SPIx; + assert_param (IS_SPI_MEM_INSTANCE(hspi->Instance)); + assert_param (hspi->Init.SPI_Mode == SPI_MODE_MASTER); + + SPIx = hspi->Instance; + + SPIx->ALTER_BYTE = MemACCParam->MemAlterByte; + SPIx->CMD = MemACCParam->MemCMD; + SPIx->MEMO_ACC = MemACCParam->MemACC; + SPIx->CS_TOUT_VAL = MemACCParam->MemCSTimeout; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : e-Initialize the SPI peripheral +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param (IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->RxState = SPI_RX_STATE_IDLE; + hspi->TxState = SPI_TX_STATE_IDLE; + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->Rx_Size = 0; + hspi->Tx_Size = 0; + hspi->Rx_Count = 0; + hspi->Tx_Count = 0; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_SPI_Switch_CS(SPI_HandleTypeDef *hspi, uint8_t CSx) +{ + assert_param(IS_SPI_CS_SEL(CSx)); + + hspi->CSx = CSx; + + if((hspi->CSx == SPI_CS_CS1) || (hspi->CSx == SPI_CS_CS2)) + { + SET_BIT(hspi->Instance->CS, SPI_CSMAP_EN); + } + else + { + CLEAR_BIT(hspi->Instance->CS, SPI_CSMAP_EN); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef _HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + uint32_t send_cnt = 0; + uint32_t recv_cnt = 0; + __IO uint32_t uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + SPI_TypeDef* SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Clear TX FIFO */ + __SPI_TXFIFO_RESET(SPIx); + + /* Set Data Size */ + SPIx->BATCH = Size; + + while((!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (Size > send_cnt)) + { + SPIx->DAT = pData[send_cnt++]; + } + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + while(Size > send_cnt) + { + /* Wait Tx FIFO Not Full */ + if(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + SPIx->DAT = pData[send_cnt++]; + uiTimeout = Timeout; + } + else + { + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + + /* Wait Transmit Done */ + while (!(SPIx->STATUS & SPI_STATUS_TX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_EN); + + hspi->Tx_Count = send_cnt; + + return Status; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_Transmit(hspi, pData, Size, Timeout); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by loop mode witch CS kept low(Master mode). +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +*@note : CS will NOT kept low if transmitting is timed out. +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_TransmitKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_Transmit(hspi, pData, Size, Timeout); + + if ( (hspi->Init.SPI_Mode == SPI_MODE_MASTER) && (Status == HAL_TIMEOUT) ) + { + /* Transmit End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef _HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + uint32_t i; + uint32_t recv_cnt = 0; + + SPI_TypeDef* SPIx = hspi->Instance; + + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + if (pData == NULL) return HAL_ERROR; + + hspi->Rx_Count = 0; + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + uiTimeout = Timeout; + + /* Clear RX FIFO */ + __SPI_RXFIFO_RESET(SPIx); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + SPIx->RX_CTL |= SPI_RX_CTL_EN; + SPIx->TX_CTL &= ~SPI_TX_CTL_EN; //tx_en = 0, why send 88? + + SPIx->BATCH = 1; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Set Data Size */ + SPIx->BATCH = Size; + /* Receive Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + while ( Size > recv_cnt ) + { + if (!READ_BIT(SPIx->STATUS, SPI_STATUS_RX_FIFO_EMPTY)) + { + pData[recv_cnt++] = SPIx->DAT; + uiTimeout = Timeout; + + } + else + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + + /* Wait Transmit Done */ + while (!(SPIx->STATUS & SPI_STATUS_RX_BATCH_DONE)); + +End: + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Rx Disable */ + CLEAR_BIT(SPIx->RX_CTL, SPI_RX_CTL_EN); + + hspi->Rx_Count = recv_cnt; + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_Receive(hspi, pData, Size, Timeout); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode witch CS contorl. +* This function is same as HAL_SPI_Receive except that it will +* control the CS state according to the param Init.KeepCS at the end of transmission +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@param : CSState : The CS control State at the end of current transmission. +* This param can be a value of: +* CS_RELEASE: Relase the CS Pin at the end of transmission(CS release to HIGH) +* CS_HOLD : Keep the CS Pin for next transmission(CS keep LOW) +*@return: HAL_StatusTypeDef +*@note : It will always release CS when transmission is timed out. +* This function can be compatible with HAL_SPI_Receive by always setting Init.KeepCS to false. +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_ReceiveKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_Receive(hspi, pData, Size, Timeout); + + if ( (hspi->Init.SPI_Mode == SPI_MODE_MASTER) && (Status == HAL_TIMEOUT) ) + { + /* Receive End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +/****************************************************************************** +*@brief : SPI Wire Config +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : X_Mode : 1x/2x/4x Mode, see@ref X_MODE +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode) +{ + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(hspi->Instance)); + + /* Set SPI X_Mode */ + hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | X_Mode; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by IT mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef _HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + SPI_TypeDef* SPIx = hspi->Instance; + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + /* Tx machine is running */ + if (hspi->TxState != SPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + hspi->Tx_Count = 0; + + /* Clear TX FIFO */ + __SPI_TXFIFO_RESET(SPIx); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Set Data Size */ + SPIx->BATCH = Size; + + /* Tx Enable */ + SPIx->TX_CTL |= SPI_TX_CTL_EN; + /* Rx Disable */ + SPIx->RX_CTL &= (~SPI_RX_CTL_EN); + + while (hspi->Tx_Count < hspi->Tx_Size) + { + if (!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + SPIx->DAT = hspi->Tx_Buffer[hspi->Tx_Count++]; + else + break; + } + + /* Enable Tx FIFO half empty Interrupt and Tx batch done Interrupt*/ + SET_BIT(SPIx->IE, (SPI_IE_TX_FIFO_HALF_EMPTY_EN | SPI_IE_TX_BATCH_DONE_EN)); + + /* Set machine is Sending */ + hspi->TxState = SPI_TX_STATE_SENDING; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Transmits an amount of data by IT mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + hspi->KeepCS = false; + + return _HAL_SPI_Transmit_IT(hspi, pData, Size); +} + +/****************************************************************************** +*@brief : Transmits an amount of data by IT mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit_IT_KeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + hspi->KeepCS = true; + } + + return _HAL_SPI_Transmit_IT(hspi, pData, Size); +} + +/****************************************************************************** +*@brief : Receive an amount of data by IT mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef _HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + SPI_TypeDef* SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + /* Rx machine is running */ + if (hspi->RxState != SPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + + /* Clear RX FIFO */ + __SPI_RXFIFO_RESET(SPIx); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Rx Enable */ + SPIx->RX_CTL |= SPI_RX_CTL_EN; + + /* Set Data Size */ + SPIx->BATCH = Size; + + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + hspi->Rx_Count = 0; + + /* Enable Rx FIFO Not Empty Interrupt */ + SET_BIT(SPIx->IE, SPI_IE_RX_FIFO_NOT_EMPTY_EN | SPI_IE_RX_BATCH_DONE_EN); + + /* Set Slave machine is receiving */ + hspi->RxState = SPI_RX_STATE_RECEIVING; + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data by IT mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + hspi->KeepCS = false; + + return _HAL_SPI_Receive_IT(hspi, pData, Size); +} + +/****************************************************************************** +*@brief : Receive an amount of data by IT mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_Receive_IT_KeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + hspi->KeepCS = true; + } + + return _HAL_SPI_Receive_IT(hspi, pData, Size); +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Transmits an amount of data by DMA mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef _HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + SPI_TypeDef* SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + /* Rx machine is running */ + if (hspi->TxState != SPI_TX_STATE_IDLE) + { + return HAL_ERROR; + } + + /* Clear TX FIFO */ + __SPI_TXFIFO_RESET(SPIx); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Enable Tx Batch Done Interrupt */ + SET_BIT(SPIx->IE, SPI_STATUS_TX_BATCH_DONE); + + /* Set Data Size */ + SPIx->BATCH = Size; + + /* Tx FIFO */ + SPIx->TX_CTL &= ~SPI_TX_CTL_DMA_LEVEL; + SPIx->TX_CTL |= SPI_TX_CTL_DMA_LEVEL_0; + + /* Tx Enable */ + SPIx->TX_CTL |= SPI_TX_CTL_EN; + /* Rx Disable */ + SPIx->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Set machine is Sending */ + hspi->TxState = SPI_TX_STATE_SENDING; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + HAL_DMA_Start(hspi->HDMA_Tx, (uint32_t)pData, (uint32_t)&SPIx->DAT, Size); + + SPIx->TX_CTL |= SPI_TX_CTL_DMA_REQ_EN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + hspi->KeepCS = false; + + return _HAL_SPI_Transmit_DMA(hspi, pData, Size); +} + +HAL_StatusTypeDef HAL_SPI_Transmit_DMA_KeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + hspi->KeepCS = false; + + return _HAL_SPI_Transmit_DMA(hspi, pData, Size); +} + +/****************************************************************************** +*@brief : Receive an amount of data by DMA mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef _HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + SPI_TypeDef* SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(hspi->Instance)); + + /* Rx machine is running */ + if (hspi->RxState != SPI_RX_STATE_IDLE) + { + return HAL_ERROR; + } + + /* Clear RX FIFO */ + __SPI_RXFIFO_RESET(SPIx); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Enable Rx Batch Done Interrupt */ + SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE); + + /* Set Data Size */ + hspi->Instance->BATCH = Size; + + /* Rx Enable */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_EN; + /* Rx FIFO */ + hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_LEVEL_0; + + /* Set Slave machine is receiving */ + hspi->RxState = SPI_RX_STATE_RECEIVING; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + HAL_DMA_Start(hspi->HDMA_Rx, (uint32_t)&hspi->Instance->DAT, (uint32_t)pData, Size); + + hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_REQ_EN; + + return HAL_OK; +} + +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + hspi->KeepCS = false; + + return _HAL_SPI_Receive_DMA(hspi, pData, Size); +} + +HAL_StatusTypeDef HAL_SPI_Receive_DMA_KeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size) +{ + assert_param(hspi); + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + hspi->KeepCS = true; + } + + return _HAL_SPI_Receive_DMA(hspi, pData, Size); +} +#endif + +/****************************************************************************** +*@brief : Transmits and recieve an amount of data in loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pTxData : Pointer to transmit data buffer +*@param : pRxData : Pointer to recieve data buffer +*@param : Size : Amount of data to be sent and receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + __IO uint32_t uiTimeout; + uint32_t send_cnt = 0; + uint32_t recv_cnt = 0; + HAL_StatusTypeDef Status = HAL_OK; + SPI_TypeDef * SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Rx_Count = 0; + hspi->Tx_Buffer = pTxData; + hspi->Rx_Buffer = pRxData; + hspi->Tx_Size = Size; + hspi->Rx_Size = Size; + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + SPIx->TX_CTL |= SPI_TX_CTL_EN; + + /* Rx Enable */ + SPIx->RX_CTL |= SPI_RX_CTL_EN; + + /* Clear TX/RX FIFO */ + __SPI_TXFIFO_RESET(SPIx); + __SPI_RXFIFO_RESET(SPIx); + + while((!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (Size > send_cnt)) + { + SPIx->DAT = pTxData[send_cnt++]; + } + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Set Data Size */ + SPIx->BATCH = Size; + + /* Transmit Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + + while(1) + { + if(Size > send_cnt) + { + /* Wait Tx FIFO Not Full */ + if(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + SPIx->DAT = pTxData[send_cnt++]; + uiTimeout = Timeout; + } + } + + /* Wait Rx FIFO Not Empty */ + if(!(SPIx->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) + { + pRxData[recv_cnt++] = SPIx->DAT; + uiTimeout = Timeout; + } + + if(Size == recv_cnt) + break; + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + + } + else + { + while(1) + { + /* Wait Rx FIFO Not Empty */ + if(Size > recv_cnt) + { + if((!(SPIx->STATUS & SPI_STATUS_RX_FIFO_EMPTY))) + { + pRxData[recv_cnt++] = SPIx->DAT; + uiTimeout = Timeout; + } + } + /* Wait Tx FIFO Not Full */ + if(Size > send_cnt) + { + if(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + SPIx->DAT = pTxData[send_cnt++]; + uiTimeout = Timeout; + } + } + + if(Size == recv_cnt && Size == send_cnt) + break; + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + + /* Wait Transmit Done */ + while (!(SPIx->STATUS & SPI_STATUS_TX_BATCH_DONE)); + + Status = HAL_OK; + +End: + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Tx Disable */ + SPIx->TX_CTL &= (~SPI_TX_CTL_EN); + + /* Rx Disable */ + SPIx->RX_CTL &= (~SPI_RX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + hspi->Tx_Count = send_cnt; + hspi->Rx_Count = recv_cnt; + + return Status; +} + +/****************************************************************************** +*@brief : Get Tx state. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: SPI Tx State +******************************************************************************/ +uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi) +{ + return hspi->TxState; +} + +/****************************************************************************** +*@brief : Get Rx state. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@return: SPI Rx State +******************************************************************************/ +uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi) +{ + return hspi->RxState; +} + +////////////////////////////////////////////////////////////////////////////////// +static void HAL_SPI_CloseTx(SPI_HandleTypeDef* hspi) +{ + /* Tx Disable */ + hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN); + + /* Disable TxFIFO half empty interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN | SPI_IE_TX_BATCH_DONE_EN); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(hspi->Instance, SPI_STATUS_BATCH_DONE); + + __SPI_TXFIFO_RESET(hspi->Instance); + + /* Set machine is DILE */ + hspi->TxState = SPI_TX_STATE_IDLE; + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + __HAL_SPI_CS_RELEASE(hspi); + } +} + +static void HAL_SPI_CloseRx(SPI_HandleTypeDef* hspi) +{ + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Disable RxFIFO not empty interrupt */ + CLEAR_BIT(hspi->Instance->IE, SPI_IE_RX_FIFO_NOT_EMPTY_EN | SPI_IE_RX_BATCH_DONE_EN); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(hspi->Instance, SPI_STATUS_BATCH_DONE); + + __SPI_RXFIFO_RESET(hspi->Instance); + + /* Set machine is DILE */ + hspi->RxState = SPI_RX_STATE_IDLE; + + if(hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + __HAL_SPI_CS_RELEASE(hspi); + } +} + +HAL_StatusTypeDef HAL_SPI_WaitTxTimeout(SPI_HandleTypeDef *hspi, uint32_t timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + + while(hspi->TxState != SPI_TX_STATE_IDLE) + { + /* Wait Timeout */ + if(timeout) + { + timeout--; + if(timeout == 0) + { + status = HAL_TIMEOUT; + break; + } + } + } + + if(status == HAL_TIMEOUT) + { + HAL_SPI_CloseTx(hspi); + } + + return status; +} + +HAL_StatusTypeDef HAL_SPI_WaitRxTimeout(SPI_HandleTypeDef *hspi, uint32_t timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + + while(hspi->RxState != SPI_RX_STATE_IDLE) + { + /* Wait Timeout */ + if(timeout) + { + timeout--; + if(timeout == 0) + { + status = HAL_TIMEOUT; + break; + } + } + } + + if(status == HAL_TIMEOUT) + { + HAL_SPI_CloseRx(hspi); + } + + return status; +} + +/*--------------------------------------------------------------------------------------*/ +/****************************************************************************** +*@brief : Transmits and recieve an amount of data in loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pTxData : Pointer to transmit data buffer +*@param : pRxData : Pointer to recieve data buffer +*@param : Size : Amount of data to be sent and receive +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_TransmitReceiveNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + __IO uint32_t uiTimeout; + uint32_t send_cnt = 0; + uint32_t recv_cnt = 0; + HAL_StatusTypeDef Status = HAL_OK; + SPI_TypeDef * SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + if ((pTxData == NULL)||(pRxData == NULL)) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Rx_Count = 0; + hspi->Tx_Buffer = pTxData; + hspi->Rx_Buffer = pRxData; + hspi->Tx_Size = Size; + hspi->Rx_Size = Size; + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + SPIx->TX_CTL |= SPI_TX_CTL_EN; + + /* Rx Enable */ + SPIx->RX_CTL |= SPI_RX_CTL_EN; + + /* Clear TX/RX FIFO */ + __SPI_TXFIFO_RESET(SPIx); + __SPI_RXFIFO_RESET(SPIx); + + while((!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (Size > send_cnt)) + { + SPIx->DAT = pTxData[send_cnt++]; + } + + /* Set Data Size */ + SPIx->BATCH = 0; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + + while(1) + { + if(Size > send_cnt) + { + /* Wait Tx FIFO Not Full */ + if(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + SPIx->DAT = pTxData[send_cnt++]; + uiTimeout = Timeout; + } + } + + /* Wait Rx FIFO Not Empty */ + if(!(SPIx->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) + { + pRxData[recv_cnt++] = SPIx->DAT; + uiTimeout = Timeout; + } + + if(Size == recv_cnt) + break; + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + + } + else + { + while(1) + { + /* Wait Rx FIFO Not Empty */ + if(Size > recv_cnt) + { + if((!(SPIx->STATUS & SPI_STATUS_RX_FIFO_EMPTY))) + { + pRxData[recv_cnt++] = SPIx->DAT; + uiTimeout = Timeout; + } + } + /* Wait Tx FIFO Not Full */ + if(Size > send_cnt) + { + if(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + SPIx->DAT = pTxData[send_cnt++]; + uiTimeout = Timeout; + } + } + + if(Size == recv_cnt && Size == send_cnt) + break; + + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + +End: +// /* Clear Batch Done Flag */ +// __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + + /* Rx Disable */ + SPIx->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Tx Disable */ + SPIx->TX_CTL &= (~SPI_TX_CTL_EN); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + hspi->Tx_Count = send_cnt; + hspi->Rx_Count = recv_cnt; + + return Status; +} + +/****************************************************************************** +*@brief : Transmits an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to be sent +*@param : Timeout : Transmit Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef _HAL_SPI_TransmitNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + uint32_t i; + uint32_t send_cnt = 0; + uint32_t recv_cnt = 0; + __IO uint32_t uiTimeout; + HAL_StatusTypeDef Status = HAL_OK; + SPI_TypeDef* SPIx = hspi->Instance; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + if(!Size) return HAL_ERROR; + if (pData == NULL) return HAL_ERROR; + + hspi->Tx_Count = 0; + hspi->Tx_Size = Size; + hspi->Tx_Buffer = pData; + + uiTimeout = Timeout; + + /* Clear Batch Done Flag */ +// __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + /* Tx Enable */ + hspi->Instance->TX_CTL |= SPI_TX_CTL_EN; + /* Rx Disable */ + hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN); + + /* Clear TX FIFO */ + __SPI_TXFIFO_RESET(SPIx); + + SPIx->BATCH = 0; + + while((!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (Size > send_cnt)) + { + SPIx->DAT = pData[send_cnt++]; + } + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + while(Size > send_cnt) + { + /* Wait Tx FIFO Not Full */ + if(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_FULL)) + { + SPIx->DAT = pData[send_cnt++]; + uiTimeout = Timeout; + } + else + { + /* Wait Timeout */ + if(uiTimeout) + { + uiTimeout--; + if(uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + +End: + while(!(SPIx->STATUS & SPI_STATUS_TX_FIFO_EMPTY)); + while(READ_BIT(SPIx->STATUS, SPI_STATUS_TX_BUSY)); + + /* Tx Disable */ + CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_EN); + + hspi->Tx_Count = send_cnt; + + return Status; +} + +HAL_StatusTypeDef HAL_SPI_TransmitNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_TransmitNoneBatch(hspi, pData, Size, Timeout); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Transmit End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +HAL_StatusTypeDef HAL_SPI_TransmitNoneBatchKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_TransmitNoneBatch(hspi, pData, Size, Timeout); + + if ( (hspi->Init.SPI_Mode == SPI_MODE_MASTER) && (Status == HAL_TIMEOUT) ) + { + /* Transmit End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef _HAL_SPI_ReceiveNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + __IO uint32_t uiTimeout; + uint32_t i; + uint32_t recv_cnt = 0; + + SPI_TypeDef* SPIx = hspi->Instance; + + HAL_StatusTypeDef Status = HAL_OK; + + /* Check SPI Parameter */ + assert_param (IS_SPI_ALL_INSTANCE(SPIx)); + + if (pData == NULL) return HAL_ERROR; + + hspi->Rx_Count = 0; + hspi->Rx_Size = Size; + hspi->Rx_Buffer = pData; + uiTimeout = Timeout; + + /* Clear RX FIFO */ + __SPI_RXFIFO_RESET(SPIx); + + /* Clear Batch Done Flag */ + __SPI_CLEAR_FLAG(SPIx, SPI_STATUS_BATCH_DONE); + + SPIx->RX_CTL |= SPI_RX_CTL_EN; + SPIx->TX_CTL &= ~SPI_TX_CTL_EN; //tx_en = 0, why send 88? + + SPIx->BATCH = 0; + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive Start */ + __HAL_SPI_TRANSSTART_CS_LOW(hspi); + } + + while ( Size > recv_cnt ) + { + if (!READ_BIT(SPIx->STATUS, SPI_STATUS_RX_FIFO_EMPTY)) + { + pData[recv_cnt++] = SPIx->DAT; + uiTimeout = Timeout; + + } + else + { + if(uiTimeout) + { + uiTimeout--; + if (uiTimeout == 0) + { + Status = HAL_TIMEOUT; + goto End; + } + } + } + } + +End: + /* Rx Disable */ + CLEAR_BIT(SPIx->RX_CTL, SPI_RX_CTL_EN); + + hspi->Rx_Count = recv_cnt; + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode. +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_ReceiveNoneBatch(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + +// Status = _HAL_SPI_ReceiveNoneBatch(hspi, pData, Size, Timeout); + if(((hspi->Instance->CTL & SPI_CTL_X_MODE_Msk) == SPI_1X_MODE) && (hspi->Instance->CTL & SPI_CTL_MST_MODE)) + Status = HAL_SPI_TransmitReceiveNoneBatch(hspi, pData, pData, Size, Timeout); + else + Status = _HAL_SPI_ReceiveNoneBatch(hspi, pData, Size, Timeout); + + if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) + { + /* Receive End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode witch CS contorl. +* This function is same as HAL_SPI_Receive except that it will +* control the CS state according to the param Init.KeepCS at the end of transmission +* +*@param : hspi: a pointer of SPI_HandleTypeDef structure which contains +* the configuration information for the specified SPI. +*@param : pData : Pointer to data buffer +*@param : Size : Amount of data to receive +*@param : Timeout : Receive Timeout +*@param : CSState : The CS control State at the end of current transmission. +* This param can be a value of: +* CS_RELEASE: Relase the CS Pin at the end of transmission(CS release to HIGH) +* CS_HOLD : Keep the CS Pin for next transmission(CS keep LOW) +*@return: HAL_StatusTypeDef +*@note : It will always release CS when transmission is timed out. +* This function can be compatible with HAL_SPI_Receive by always setting Init.KeepCS to false. +******************************************************************************/ +HAL_StatusTypeDef HAL_SPI_ReceiveNoneBatchKeepCS(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout) +{ + HAL_StatusTypeDef Status; + + Status = _HAL_SPI_Receive(hspi, pData, Size, Timeout); + + if ( (hspi->Init.SPI_Mode == SPI_MODE_MASTER) && (Status == HAL_TIMEOUT) ) + { + /* Receive End */ + __HAL_SPI_CS_RELEASE(hspi); + } + + return Status; +} + +#endif //HAL_SPI_MODULE_ENABLED + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_timer.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..19204808354b7534a03a93fd137583fbe2d4612e --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_timer.c @@ -0,0 +1,2055 @@ +/*********************************************************************** + * Filename : hal_lpuart.c + * Description : lpuart driver source file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2019-11-19 + ***********************************************************************/ +#include "hal.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); +static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter); + +__weak void HAL_TIM_Update_Event_Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +__weak void HAL_TIM_Trig_Event_Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if( (htim->Instance->SR & (TIMER_SR_CC1IF|TIMER_SR_CC1OF) ) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, (TIMER_SR_CC1IF|TIMER_SR_CC1OF) ); + + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if( ((htim->Instance->CCMR1) & (BIT0|BIT1) ) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + + } + } + /* Capture compare 2 event */ + if( (htim->Instance->SR & (TIMER_SR_CC2IF|TIMER_SR_CC2OF) ) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, (TIMER_SR_CC2IF|TIMER_SR_CC2OF) ); + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & (BIT8|BIT9) ) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if( (htim->Instance->SR & (TIMER_SR_CC3IF|TIMER_SR_CC3OF) ) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, (TIMER_SR_CC3IF|TIMER_SR_CC3OF) ); + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & (BIT0|BIT1)) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if( (htim->Instance->SR & (TIMER_SR_CC4IF|TIMER_SR_CC4OF) ) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, (TIMER_SR_CC4IF|TIMER_SR_CC4OF) ); + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & (BIT8|BIT9) ) != 0x00U) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->activeChannel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + + + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIMER_SR_UIF) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIMER_SR_UIF); + HAL_TIM_Update_Event_Callback(htim); + } + } + + + if(__HAL_TIM_GET_FLAG(htim, TIMER_SR_TIF) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIMER_SR_TIF); + HAL_TIM_Trig_Event_Callback(htim); + } + } + +} + +/********************************************************************************* +* Function : HAL_TIMER_MSP_Init +* Description : MSP init, mainly about clock, nvic +* Input : timer handler +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +__weak uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim) +{ + uint32_t Timer_Instance; + + + Timer_Instance = (uint32_t)(htim->Instance); + + switch(Timer_Instance) + { + case TIM1_BASE_ADDR: + + __HAL_RCC_TIM1_CLK_ENABLE(); + __HAL_RCC_TIM1_RESET(); + NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + + case TIM2_BASE_ADDR: + + __HAL_RCC_TIM2_CLK_ENABLE(); + __HAL_RCC_TIM2_RESET(); + NVIC_ClearPendingIRQ(TIM2_IRQn); + NVIC_EnableIRQ(TIM2_IRQn); + break; + + case TIM3_BASE_ADDR: + + __HAL_RCC_TIM3_CLK_ENABLE(); + __HAL_RCC_TIM3_RESET(); + NVIC_ClearPendingIRQ(TIM3_IRQn); + NVIC_EnableIRQ(TIM3_IRQn); + break; + + case TIM4_BASE_ADDR: + __HAL_RCC_TIM4_CLK_ENABLE(); + __HAL_RCC_TIM4_RESET(); + NVIC_ClearPendingIRQ(TIM4_IRQn); + NVIC_EnableIRQ(TIM4_IRQn); + break; + + case TIM5_BASE_ADDR: + __HAL_RCC_TIM5_CLK_ENABLE(); + __HAL_RCC_TIM5_RESET(); + NVIC_ClearPendingIRQ(TIM5_IRQn); + NVIC_EnableIRQ(TIM5_IRQn); + break; + + case TIM6_BASE_ADDR: + __HAL_RCC_TIM6_CLK_ENABLE(); + __HAL_RCC_TIM6_RESET(); + NVIC_ClearPendingIRQ(TIM6_IRQn); + NVIC_EnableIRQ(TIM6_IRQn); + break; + + case TIM7_BASE_ADDR: + __HAL_RCC_TIM7_CLK_ENABLE(); + __HAL_RCC_TIM7_RESET(); + NVIC_ClearPendingIRQ(TIM7_IRQn); + NVIC_EnableIRQ(TIM7_IRQn); + break; + + case TIM8_BASE_ADDR: + __HAL_RCC_TIM8_CLK_ENABLE(); + __HAL_RCC_TIM8_RESET(); + NVIC_ClearPendingIRQ(TIM8_BRK_UP_TRG_COM_IRQn); + NVIC_EnableIRQ(TIM8_BRK_UP_TRG_COM_IRQn); + break; + + case TIM9_BASE_ADDR: + __HAL_RCC_TIM9_CLK_ENABLE(); + __HAL_RCC_TIM9_RESET(); + NVIC_ClearPendingIRQ(TIM9_IRQn); + NVIC_EnableIRQ(TIM9_IRQn); + break; + + case TIM10_BASE_ADDR: + __HAL_RCC_TIM10_CLK_ENABLE(); + __HAL_RCC_TIM10_RESET(); + NVIC_ClearPendingIRQ(TIM10_IRQn); + NVIC_EnableIRQ(TIM10_IRQn); + break; + + case TIM11_BASE_ADDR: + __HAL_RCC_TIM11_CLK_ENABLE(); + __HAL_RCC_TIM11_RESET(); + NVIC_ClearPendingIRQ(TIM11_IRQn); + NVIC_EnableIRQ(TIM11_IRQn); + break; + + case TIM12_BASE_ADDR: + __HAL_RCC_TIM12_CLK_ENABLE(); + __HAL_RCC_TIM12_RESET(); + NVIC_ClearPendingIRQ(TIM12_IRQn); + NVIC_EnableIRQ(TIM12_IRQn); + break; + + case TIM13_BASE_ADDR: + __HAL_RCC_TIM13_CLK_ENABLE(); + __HAL_RCC_TIM13_RESET(); + NVIC_ClearPendingIRQ(TIM13_IRQn); + NVIC_EnableIRQ(TIM13_IRQn); + break; + + case TIM14_BASE_ADDR: + __HAL_RCC_TIM14_CLK_ENABLE(); + __HAL_RCC_TIM14_RESET(); + NVIC_ClearPendingIRQ(TIM14_IRQn); + NVIC_EnableIRQ(TIM14_IRQn); + break; + + case TIM15_BASE_ADDR: + __HAL_RCC_TIM15_CLK_ENABLE(); + __HAL_RCC_TIM15_RESET(); + NVIC_ClearPendingIRQ(TIM15_IRQn); + NVIC_EnableIRQ(TIM15_IRQn); + break; + + case TIM16_BASE_ADDR: + __HAL_RCC_TIM16_CLK_ENABLE(); + __HAL_RCC_TIM16_RESET(); + NVIC_ClearPendingIRQ(TIM16_IRQn); + NVIC_EnableIRQ(TIM16_IRQn); + break; + + case TIM17_BASE_ADDR: + __HAL_RCC_TIM17_CLK_ENABLE(); + __HAL_RCC_TIM17_RESET(); + NVIC_ClearPendingIRQ(TIM17_IRQn); + NVIC_EnableIRQ(TIM17_IRQn); + break; + + case TIM18_BASE_ADDR: + __HAL_RCC_TIM18_CLK_ENABLE(); + __HAL_RCC_TIM18_RESET(); + NVIC_ClearPendingIRQ(TIM18_IRQn); + NVIC_EnableIRQ(TIM18_IRQn); + break; + + case TIM19_BASE_ADDR: + __HAL_RCC_TIM19_CLK_ENABLE(); + __HAL_RCC_TIM19_RESET(); + NVIC_ClearPendingIRQ(TIM19_IRQn); + NVIC_EnableIRQ(TIM19_IRQn); + break; + + case TIM20_BASE_ADDR: + __HAL_RCC_TIM20_CLK_ENABLE(); + __HAL_RCC_TIM20_RESET(); + NVIC_ClearPendingIRQ(TIM20_BRK_UP_TRG_COM_IRQn); + NVIC_EnableIRQ(TIM20_BRK_UP_TRG_COM_IRQn); + break; + + case TIM21_BASE_ADDR: + __HAL_RCC_TIM21_CLK_ENABLE(); + __HAL_RCC_TIM21_RESET(); + NVIC_ClearPendingIRQ(TIM21_IRQn); + NVIC_EnableIRQ(TIM21_IRQn); + break; + + case TIM22_BASE_ADDR: + __HAL_RCC_TIM22_CLK_ENABLE(); + __HAL_RCC_TIM22_RESET(); + NVIC_ClearPendingIRQ(TIM22_IRQn); + NVIC_EnableIRQ(TIM22_IRQn); + break; + + case TIM23_BASE_ADDR: + __HAL_RCC_TIM23_CLK_ENABLE(); + __HAL_RCC_TIM23_RESET(); + NVIC_ClearPendingIRQ(TIM23_IRQn); + NVIC_EnableIRQ(TIM23_IRQn); + break; + + case TIM24_BASE_ADDR: + __HAL_RCC_TIM24_CLK_ENABLE(); + __HAL_RCC_TIM24_RESET(); + NVIC_ClearPendingIRQ(TIM24_IRQn); + NVIC_EnableIRQ(TIM24_IRQn); + break; + + case TIM25_BASE_ADDR: + __HAL_RCC_TIM25_CLK_ENABLE(); + __HAL_RCC_TIM25_RESET(); + NVIC_ClearPendingIRQ(TIM25_IRQn); + NVIC_EnableIRQ(TIM25_IRQn); + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + + +__weak uint32_t HAL_TIMER_Base_MspDeInit(TIM_HandleTypeDef * htim) +{ + uint32_t Timer_Instance; + + + Timer_Instance = (uint32_t)(htim->Instance); + + switch(Timer_Instance) + { + case TIM1_BASE_ADDR: + __HAL_RCC_TIM1_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_DisableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + break; + + case TIM2_BASE_ADDR: + __HAL_RCC_TIM2_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM2_IRQn); + NVIC_DisableIRQ(TIM2_IRQn); + break; + + case TIM3_BASE_ADDR: + __HAL_RCC_TIM3_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM3_IRQn); + NVIC_DisableIRQ(TIM3_IRQn); + break; + + case TIM4_BASE_ADDR: + __HAL_RCC_TIM4_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM4_IRQn); + NVIC_DisableIRQ(TIM4_IRQn); + break; + + case TIM6_BASE_ADDR: + __HAL_RCC_TIM6_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM6_IRQn); + NVIC_DisableIRQ(TIM6_IRQn); + break; + + case TIM7_BASE_ADDR: + __HAL_RCC_TIM7_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM7_IRQn); + NVIC_DisableIRQ(TIM7_IRQn); + break; + + case TIM8_BASE_ADDR: +// System_Module_Disable(EN_TIM8); +// NVIC_ClearPendingIRQ(TIM8_BRK_UP_TRG_COM_IRQn); +// NVIC_DisableIRQ(TIM8_BRK_UP_TRG_COM_IRQn); + break; + + case TIM15_BASE_ADDR: + __HAL_RCC_TIM15_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM15_IRQn); + NVIC_DisableIRQ(TIM15_IRQn); + break; + + case TIM16_BASE_ADDR: + __HAL_RCC_TIM16_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM16_IRQn); + NVIC_DisableIRQ(TIM16_IRQn); + break; + + case TIM17_BASE_ADDR: + __HAL_RCC_TIM17_CLK_ENABLE(); + NVIC_ClearPendingIRQ(TIM17_IRQn); + NVIC_DisableIRQ(TIM17_IRQn); + break; + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_TIMER_Slave_Mode_Config +* Description : configure timer in slave mode +* Input : + htim: timer handler + sSlaveConfig: slave mode parameter strcture + SlaveMode: TIM_SLAVE_MODE_DIS, TIM_SLAVE_MODE_ENC1... + InputTrigger: TIM_TS_ITR0, TIM_TS_ITR1... + TriggerPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + TriggerPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /*reset SMS and TS bits*/ + htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2|TIM_SMCR_TS_Msk)); + /*SET SMS bits*/ + htim->Instance->SMCR |= (sSlaveConfig->SlaveMode & (BIT0|BIT1|BIT2) ); + /*SET TS bits*/ + htim->Instance->SMCR |= (sSlaveConfig->InputTrigger); + + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_TI1FP1: + TIMER_TI1FP1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TS_TI2FP2: + TIMER_TI2FP2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TS_ETRF: + TIMER_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter); + break; + + case TIM_TS_TI1F_ED: + htim->Instance->CR2 |= BIT7; //ch1/2/3 xor to TI1 + break; + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + case TIM_TS_ITR4: + case TIM_TS_ITR5: + case TIM_TS_ITR6: + case TIM_TS_ITR7: + case TIM_TS_ITR8: + case TIM_TS_ITR9: + case TIM_TS_ITR10: + // don't need do anything here + break; + + default: + return 1; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Master_Mode_Config +* Description : configure timer in master mode +* Input : + TIMx: timer instance + sMasterConfig: master mode parameter structure + MasterSlaveMode: TIM_TRGO_RESET, TIM_TRGO_ENABLE... + MasterOutputTrigger: TIM_MASTERSLAVEMODE_DISABLE, TIM_MASTERSLAVEMODE_ENABLE +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig) +{ + /*reset bits*/ + TIMx->SMCR &= (~BIT7); + TIMx->CR2 &= (~(BIT4|BIT5|BIT6)); + + TIMx->SMCR |= sMasterConfig->MasterSlaveMode; + TIMx->CR2 |= sMasterConfig->MasterOutputTrigger; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(TIMx)) + { + /* Clear the MMS2 bits */ + TIMx->CR2 &= (~(BIT20|BIT21|BIT22|BIT23)); + /* Select the TRGO2 source*/ + TIMx->CR2 |= (sMasterConfig->MasterOutputTrigger2 & (BIT20|BIT21|BIT22|BIT23) ) ; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Output_Config +* Description : configure output parameter +* Input : + TIMx: timer instance + Output_Config: output configration parameter structure + OCMode: OUTPUT_MODE_FROZEN, OUTPUT_MODE_MATCH_HIGH... + Pulse: write to ccrx register + OCPolarity: OC channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW + OCNPolarity: OCN channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW + OCFastMode: OUTPUT_FAST_MODE_DISABLE, OUTPUT_FAST_MODE_ENABLE + OCIdleState: OC channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 + OCNIdleState: OCN channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~BIT0); //disable OC1 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT1); + } + else + { + TIMx->CCER |= (BIT1); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT2); //disable OC1N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT3); + } + else + { + TIMx->CCER |= (BIT3); + } + } + + TIMx->CCMR1 &= (~0x00FFU); // reset low 8 bits + TIMx->CCR1 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR1 |= (BIT2); + } + TIMx->CCMR1 |= (BIT3); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT8); + } + else + { + TIMx->CR2 |= BIT8; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT9); + } + else + { + TIMx->CR2 |= BIT9; + } + + } + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~BIT4); //disable OC2 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT5); + } + else + { + TIMx->CCER |= (BIT5); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT6); //disable OC2N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT7); + } + else + { + TIMx->CCER |= (BIT7); + } + } + + TIMx->CCMR1 &= (~0xFF00U); // reset high 8 bits + TIMx->CCR2 = Output_Config->Pulse; // write value to ccr before preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR1 |= (BIT10); + } + TIMx->CCMR1 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT10); + } + else + { + TIMx->CR2 |= BIT10; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT11); + } + else + { + TIMx->CR2 |= BIT11; + } + + } + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~BIT8); //disable OC3 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT9); + } + else + { + TIMx->CCER |= (BIT9); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT10); //disable OC3N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT11); + } + else + { + TIMx->CCER |= (BIT11); + } + } + + TIMx->CCMR2 &= (~0x00FF); // reset low 8 bits + TIMx->CCMR2 |= (BIT3); // preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR2 |= (BIT2); + } + + TIMx->CCR3 = Output_Config->Pulse; + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT12); + } + else + { + TIMx->CR2 |= BIT12; + } + + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState) + { + TIMx->CR2 &= (~BIT13); + } + else + { + TIMx->CR2 |= BIT13; + } + + } + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~BIT12); //disable OC4 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT13); + } + else + { + TIMx->CCER |= (BIT13); + } + + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER &= (~BIT14); //disable OC4N + + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity) + { + TIMx->CCER &= (~BIT15); + } + else + { + TIMx->CCER |= (BIT15); + } + } + + TIMx->CCMR2 &= (~0xFF00); // reset high 8 bits + TIMx->CCR4 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR2 |= (BIT10); // fast mode + } + TIMx->CCMR2 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT14); + } + else + { + TIMx->CR2 |= BIT14; + } + + } + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + case TIM_CHANNEL_5: + TIMx->CCER &= (~BIT16); //disable OC5 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT17); + } + else + { + TIMx->CCER |= (BIT17); + } + + TIMx->CCMR3 &= (~0x00FF); // reset low 8 bits + TIMx->CCMR3 |= (BIT3); // preload enable + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR3 |= (BIT2); + } + + TIMx->CCR5 = Output_Config->Pulse; + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT16); + } + else + { + TIMx->CR2 |= BIT16; + } + } + TIMx->CCMR3 = (TIMx->CCMR3 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4); + break; + + case TIM_CHANNEL_6: + TIMx->CCER &= (~BIT20); //disable OC6 + if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity) + { + TIMx->CCER &= (~BIT21); + } + else + { + TIMx->CCER |= (BIT21); + } + + TIMx->CCMR3 &= (~0xFF00); // reset high 8 bits + TIMx->CCR6 = Output_Config->Pulse; + if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode) + { + TIMx->CCMR3 |= (BIT10); // fast mode + } + TIMx->CCMR3 |= (BIT11); // preload enable + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState) + { + TIMx->CR2 &= (~BIT18); + } + else + { + TIMx->CR2 |= BIT18; + } + + } + TIMx->CCMR3 = (TIMx->CCMR3 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12); + break; + + default: + return 1; // error parameter + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIMER_Capture_Config +* Description : configure capture parameters +* Input : + TIMx: timer instance + Capture_Config: capture configuration parameter strcture + ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + ICSelection: TIM_ICSELECTION_DIRECTTI, TIM_ICSELECTION_INDIRECTTI + ICFilter: TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x), x:0-15 + ICPrescaler: TIM_IC1_PRESCALER_1, TIM_IC2_PRESCALER_1... + Channel: channel id, TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel) +{ + switch(Channel) + { + case TIM_CHANNEL_1: + TIMER_IC1_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (~BIT2|BIT3); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= Capture_Config->ICPrescaler; + break; + + case TIM_CHANNEL_2: + TIMER_IC2_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (~BIT10|BIT11); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= Capture_Config->ICPrescaler; + break; + + case TIM_CHANNEL_3: + TIMER_IC3_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (~BIT2|BIT3); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= Capture_Config->ICPrescaler; + + break; + + case TIM_CHANNEL_4: + TIMER_IC4_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (~BIT10|BIT11); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= Capture_Config->ICPrescaler; + break; + + default: + return 1; + } + + return 0; +} + + + +/********************************************************************************* +* Function : HAL_TIMER_SelectClockSource +* Description : select timer counter source, internal or external +* Input: + htim : timer handler + sClockSourceConfig: configuration parameters, includes following members: + ClockSource: TIM_CLOCKSOURCE_ITR0, TIM_CLOCKSOURCE_ETR... + ClockPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + ClockPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... + ClockFilter: TIM_ETR_FILTER_LVL(x), TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x) +* Output : HAL_ERROR:error, HAL_OK:OK +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) +{ + htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2)); + + switch (sClockSourceConfig->ClockSource) + { +// case TIM_CLOCKSOURCE_INT: +// { +// // do nothing here +// break; +// } + case TIM_CLOCKSOURCE_ETR: + { + + /* Configure the ETR Clock source */ + TIMER_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= BIT14; // ECE=1,external clock mode 2 + break; + } + + case TIM_CLOCKSOURCE_TI1FP1: + { + + TIMER_TI1FP1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_TS_Msk, TIM_CLOCKSOURCE_TI1FP1); //Clock source select TI1FP1 + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + + case TIM_CLOCKSOURCE_TI2FP2: + { + TIMER_TI2FP2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_TS_Msk, TIM_CLOCKSOURCE_TI2FP2); //Clock source select TI2FP2 + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); // select external clock mode 1 + break; + } + case TIM_CLOCKSOURCE_TI1F_ED: + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + case TIM_CLOCKSOURCE_ITR4: + case TIM_CLOCKSOURCE_ITR5: + case TIM_CLOCKSOURCE_ITR6: + case TIM_CLOCKSOURCE_ITR7: + case TIM_CLOCKSOURCE_ITR8: + case TIM_CLOCKSOURCE_ITR9: + case TIM_CLOCKSOURCE_ITR10: + { + MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_TS_Msk, sClockSourceConfig->ClockSource); //Clock source set + + htim->Instance->SMCR |= (BIT0|BIT1|BIT2); //select external clock mode 1 + break; + } + + default: + return HAL_ERROR; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Init +* Description : timer base initiation +* Input : timer handler +* Output : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim) +{ + + htim->Instance->CR1 = BIT2; // CEN=0, URS=1, OPM = 0 + + //up/down/center mode + htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT4|BIT5|BIT6))) | ((htim->Init.CounterMode) & (BIT4|BIT5|BIT6)); + + if (htim->Init.ARRPreLoadEn) + { + htim->Instance->CR1 |= (BIT7); + } + else + { + htim->Instance->CR1 &= (~BIT7); + } + + htim->Instance->ARR = htim->Init.Period; + htim->Instance->PSC = htim->Init.Prescaler; + if (IS_TIM_REPETITION_COUNTER_INSTANCE(htim->Instance)) + { + htim->Instance->RCR = htim->Init.RepetitionCounter; + } + htim->Instance->EGR = BIT0; // no UIF generated because URS=1 + + + htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT8|BIT9))) | ((htim->Init.ClockDivision) & (BIT8|BIT9)); + + htim->Instance->CR1 &= (~BIT2); //URS = 0 + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_DeInit +* Description : timer base deinitiation, disable Timer, turn off module clock and nvic +* Input : timer handler +* Output : HAL_OK: success; HAL_ERROR:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_DeInit(TIM_HandleTypeDef *htim) +{ + htim->Instance->CR1 &= (~BIT0); + + HAL_TIMER_Base_MspDeInit(htim); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Base_Start +* Description : start timer +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx) +{ + if (0 == IS_TIM_SLAVE_INSTANCE(TIMx) ) + { + TIMx->CR1 |= BIT0; + return; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + return; + } + + return; +} +#ifdef HAL_DMA_MODULE_ENABLED +/********************************************************************************* +* Function : HAL_TIMER_Base_Start_DMA +* Description : start timer, +* Input : timer instance +* Output : HAL status +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t start_addr, uint32_t transfer_size) +{ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_UPDATE_INDEX], start_addr, (uint32_t)(&(htim->Instance->ARR)), transfer_size)) + { + return HAL_ERROR; + } + + if (0 == IS_TIM_SLAVE_INSTANCE(htim->Instance) ) + { + htim->Instance->CR1 |= BIT0; + return HAL_OK; + } + + if (TIM_SLAVE_MODE_TRIG != (htim->Instance->SMCR & (BIT0|BIT1|BIT2) ) ) + { + htim->Instance->CR1 |= BIT0; + return HAL_OK; + } + + return HAL_OK; +} +#endif +/********************************************************************************* +* Function : HAL_TIMER_Base_Stop +* Description : stop timer +* Input : timer handler +* Output : none +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx) +{ + TIMx->CR1 &= (~BIT0); + HAL_TIM_DISABLE_IT_EX(TIMx, TIM_IT_UPDATE); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_OnePulse_Init +* Description : start timer with one pulse mode +* Input : + htim: timer handler + mode: 0 means normal mode, 1 means one pulse mode +* Output : HAL_OK, success; HAL_ERROR, fail +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t mode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + HAL_TIMER_Base_Init(htim); + + /*reset the OPM Bit */ + htim->Instance->CR1 &= (~BIT3); + if (0 != mode) + { + /*set the OPM Bit */ + htim->Instance->CR1 |= BIT3; + } + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIM_PWM_Output_Start +* Description : start timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT14; + } + break; + + case TIM_CHANNEL_5: + TIMx->CCER |= BIT16; + break; + + case TIM_CHANNEL_6: + TIMx->CCER |= BIT20; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} +/********************************************************************************* +* Function : HAL_TIM_PWM_Output_Stop +* Description : stop timer pwm output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~(BIT0 | BIT2)); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~(BIT4 | BIT6)); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~(BIT8 | BIT10)); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~(BIT12)); + break; + + case TIM_CHANNEL_5: + TIMx->CCER &= (~(BIT16)); + break; + + case TIM_CHANNEL_6: + TIMx->CCER &= (~(BIT20)); + break; + + default: + return HAL_ERROR; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR &= (~BIT15); + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_OC_Start +* Description : start timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + case TIM_CHANNEL_5: + TIMx->CCER |= BIT16; + break; + + case TIM_CHANNEL_6: + TIMx->CCER |= BIT20; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_OCxN_Start +* Description : start timer OCxN output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT2; + } + break; + + case TIM_CHANNEL_2: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT6; + } + break; + + case TIM_CHANNEL_3: + if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) ) + { + TIMx->CCER |= BIT10; + } + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR |= BIT15; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + +/********************************************************************************* +* Function : HAL_TIMER_OC_Stop +* Description : stop timer output +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~(BIT0 | BIT2)); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~(BIT4 | BIT6)); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~(BIT8 | BIT10)); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~(BIT12)); + break; + + case TIM_CHANNEL_5: + TIMx->CCER &= (~(BIT16)); + break; + + case TIM_CHANNEL_6: + TIMx->CCER &= (~(BIT20)); + break; + + default: + return HAL_ERROR; + } + + if(IS_TIM_BREAK_INSTANCE(TIMx) != 0) + { + /* Enable the main output */ + TIMx->BDTR &= (~BIT15); + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + /* Return function status */ + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIM_Capture_Start +* Description : start timer capture +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER |= BIT0; + break; + + case TIM_CHANNEL_2: + TIMx->CCER |= BIT4; + break; + + case TIM_CHANNEL_3: + TIMx->CCER |= BIT8; + break; + + case TIM_CHANNEL_4: + TIMx->CCER |= BIT12; + break; + + default: + return 1; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 |= BIT0; + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIM_Capture_Stop +* Description : stop timer capture +* Input : + TIMx: timer instance + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : : 0: success; else:error +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel) +{ + + switch(Channel) + { + case TIM_CHANNEL_1: + TIMx->CCER &= (~BIT0); + break; + + case TIM_CHANNEL_2: + TIMx->CCER &= (~BIT4); + break; + + case TIM_CHANNEL_3: + TIMx->CCER &= (~BIT8); + break; + + case TIM_CHANNEL_4: + TIMx->CCER &= (~BIT12); + break; + + default: + return 1; + } + + if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) ) + { + TIMx->CR1 &= (~BIT0); + } + + return 0; +} + + +/********************************************************************************* +* Function : HAL_TIMEx_ETRSelection +* Description : select ETR signal, it can ben GPIO, COMP1_OUT, COMP2_OUT, ADC analog watchdog output +* Input : + htim: timer handler + ETRSelection: ETR_SELECT_GPIO, ETR_SELECT_IN1... +* Output : HAL_OK, Success; HAL_ERROR:Fail +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ETRSelection(TIM_HandleTypeDef *htim, uint32_t ETRSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + + htim->Instance->AF1 &= (~ETR_SELECT_MASK); + htim->Instance->AF1 |= ETRSelection; + + return status; +} + +/********************************************************************************* +* Function : HAL_TIMER_ReadCapturedValue +* Description : read capture value as channel +* Input : + htim: timer handler + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : capture value +* Author : xwl +**********************************************************************************/ +uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t capture_data = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Return the capture 1 value */ + capture_data = htim->Instance->CCR1; + break; + } + case TIM_CHANNEL_2: + { + /* Return the capture 2 value */ + capture_data = htim->Instance->CCR2; + break; + } + case TIM_CHANNEL_3: + { + /* Return the capture 3 value */ + capture_data = htim->Instance->CCR3; + break; + } + case TIM_CHANNEL_4: + { + /* Return the capture 4 value */ + capture_data = htim->Instance->CCR4; + break; + } + default: + break; + } + + return capture_data; +} + +/********************************************************************************* +* Function : HAL_TIMER_GenerateEvent +* Description : Generate event by software +* Input: + htim : timer handler + EventSource: TIM_EVENTSOURCE_UPDATE, TIM_EVENTSOURCE_CC1... +* Output : HAL_ERROR:error, HAL_OK:OK +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMER_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + htim->Instance->EGR = EventSource; + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMER_Clear_Capture_Flag +* Description : clear capture flag as channel id +* Input : + htim: timer handler + Channel: TIM_CHANNEL_1, TIM_CHANNEL_2... +* Output : capture value +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + switch (Channel) + { + case TIM_CHANNEL_1: + { + htim->Instance->SR &= (~(BIT1|BIT9)); + break; + } + case TIM_CHANNEL_2: + { + htim->Instance->SR &= (~(BIT2|BIT10)); + break; + } + case TIM_CHANNEL_3: + { + htim->Instance->SR &= (~(BIT3|BIT11)); + break; + } + case TIM_CHANNEL_4: + { + htim->Instance->SR &= (~(BIT4|BIT12)); + break; + } + default: + break; + } +} + +/********************************************************************************* +* Function : TIMER_ETR_SetConfig +* Description : configure ETR channel polarity, prescaler and filter +* Input: + TIMx : timer instance + TIM_ExtTRGPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... + TIM_ExtTRGPolarity: TIM_ETR_POLAIRTY_HIGH, TIM_ETR_POLAIRTY_LOW + ExtTRGFilter: TIM_ETR_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + /* Reset the ETR Bits */ + TIMx->SMCR &= (~0xFF00U); + + /* Set the Prescaler, the Filter value and the Polarity */ + TIMx->SMCR |= (TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | ExtTRGFilter); +} + +/********************************************************************************* +* Function : TIMER_TI1FP1_ConfigInputStage +* Description : configure TI1FP1 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI1_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter) +{ + TIMx->CCER &= (~BIT0); //Disable the Channel 1: Reset the CC1E Bit + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1)) | BIT0); // CH1 as input + + TIMx->CCMR1 &= (~0xF0U); // reset TI1 filter + TIMx->CCMR1 |= Filter; + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING; + } + else + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH; + } +} + +/********************************************************************************* +* Function : TIMER_TI2FP2_ConfigInputStage +* Description : configure TI2FP2 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI2_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter) +{ + TIMx->CCER &= (~BIT4); //Disable the Channel 2: Reset the CC2E Bit + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9)) | BIT8); // CH2 as input + + TIMx->CCMR1 &= (~0xF000U); // reset TI2 filter + TIMx->CCMR1 |= Filter; + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING; + } + else + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH; + } +} + +/********************************************************************************* +* Function : TIMER_IC1_SetConfig +* Description : configure TI1FP1 or TI2FP1 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI1_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (~BIT0); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT0; + TIMx->CCMR1 &= (~0xF0U); + } + else + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT1; + TIMx->CCMR1 &= (~0xF000U); + } + + TIMx->CCMR1 |= Filter; + +} + +/********************************************************************************* +* Function : TIMER_IC2_SetConfig +* Description : configure TI1FP2 or TI2FP2 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI2_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 2, Reset the CC2E Bit */ + TIMx->CCER &= (~BIT4); + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT8; + TIMx->CCMR1 &= (~0xF000U); + } + else + { + TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT9; + TIMx->CCMR1 &= (~0xF0U); + } + + TIMx->CCMR1 |= Filter; + +} + +/********************************************************************************* +* Function : TIMER_IC3_SetConfig +* Description : configure TI3FP3 or TI4FP3 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI3_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 3, Reset the CC3E Bit */ + TIMx->CCER &= (~BIT8); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT0; + TIMx->CCMR2 &= (~0xF0U); + } + else + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT1; + TIMx->CCMR2 &= (~0xF000U); + } + + + TIMx->CCMR2 |= Filter; +} + + +/********************************************************************************* +* Function : TIMER_IC4_SetConfig +* Description : configure TI3FP4 or TI4FP4 channel polarity and filter +* Input: + TIMx : timer instance + TIM_ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... + Filter: TIM_TI4_FILTER_LVL(x), x=0-15 +* Output : none +* Author : xwl +**********************************************************************************/ +static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter) +{ + /* Disable the Channel 3, Reset the CC3E Bit */ + TIMx->CCER &= (~BIT12); + + if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_RISING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_FALLING; + } + else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity) + { + TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_BOTH; + } + + if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection) + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT8; + TIMx->CCMR2 &= (~0xF000U); + } + else + { + TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT9; + TIMx->CCMR2 &= (~0xF0U); + } + + TIMx->CCMR2 |= Filter; + +} + + + + + + + + +/********************************************************************************* +* Function : HAL_TIMER_64_Base_Init +* Description : start 64 bit timer +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_64_Base_Init(TIM_64_HandleTypeDef *htim) +{ + + htim->Instance->CTRL = htim->Instance->CTRL & (~(0x7FU << 1)); + htim->Instance->CTRL |= ( (htim->Init.Cnt_Mode << 1) | (htim->Init.Prescaler << 2) ); + + htim->Instance->CTRL = (htim->Instance->CTRL & (~(1U << 9) ) ) | (htim->Init.ARR_Preload_En << 9); + + if (TIM_64_ARR_MODE == htim->Init.Cnt_Mode) + { + htim->Instance->ARR_LOW = htim->Init.Period_Low; + htim->Instance->ARR_HIGH = htim->Init.Period_High; + htim->Instance->CTRL |= BIT10; // Load ARR value + } + + htim->Instance->CNT_LOW = htim->Init.Count_Low; + htim->Instance->CNT_HIGH = htim->Init.Count_High; + + htim->Instance->CTRL |= BIT11; // Load Initial count value + + return; +} + +/********************************************************************************* +* Function : HAL_TIMER_64_Enable_Interrupt +* Description : enable 64 bit timer interrupt +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_64_Enable_Interrupt(TIM_64BIT_TypeDef *TIMx) +{ + TIMx->CTRL |= BIT8; + + return; +} + + +/********************************************************************************* +* Function : HAL_TIMER_64_Base_Start +* Description : start 64 bit timer +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMER_64_Base_Start(TIM_64BIT_TypeDef *TIMx) +{ + TIMx->CTRL |= BIT0; + + return; +} + + +/********************************************************************************* +* Function : HAL_TIMER_64_Base_Start +* Description : start 64 bit timer +* Input : timer instance +* Output : none +* Author : xwl +**********************************************************************************/ +long long HAL_TIMER_64_Base_Read_Count(TIM_64BIT_TypeDef *TIMx) +{ + volatile long long low, high, high_2; + + while(1) + { + high = TIMx->CNT_HIGH; + low = TIMx->CNT_LOW; + high_2 = TIMx->CNT_HIGH; + + if (high_2 == high) + { + break; + } + } + + + return (high << 32) + low; +} + +#endif + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_timer_ex.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_timer_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..1db1deb733aea784d0d4f37df62931414a16f8a3 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_timer_ex.c @@ -0,0 +1,282 @@ +/*********************************************************************** + * Filename : hal_timer_ex.c + * Description : TIMER driver source file + * Author(s) : xwl + * version : V1.0 + * Modify date : 2021-04-02 + ***********************************************************************/ +#include "hal.h" + +#ifdef HAL_TIMER_MODULE_ENABLED + +/********************************************************************************* +* Function : HAL_TIMER_ConfigBreakDeadTime +* Description : configure deadtime parameter +* Input : timer handler, break and deadtime configuration +* Output : none +* Author : xwl +**********************************************************************************/ +void HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t break_deadtime_reg = 0U; + + /* Set the BDTR bits */ + MODIFY_REG(break_deadtime_reg, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = break_deadtime_reg; + +} + +/********************************************************************************* +* Function : HAL_TIMEx_ConfigBreakInput +* Description : Configures the break input source. +* Input : + htim: timer handler + BreakInput: TIM_BREAKINPUT_BRK + sBreakInputConfig: Break input source configuration +* Output : +* Author : xwl +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + switch(sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP3: + { + bkin_enable_mask = TIM1_AF1_BKCMP3E; + bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP3P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP4: + { + bkin_enable_mask = TIM1_AF1_BKCMP4E; + bkin_enable_bitpos = TIM1_AF1_BKCMP4E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP4P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP4P_Pos; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + return HAL_ERROR; + } + } + + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + + return HAL_OK; +} + + +/********************************************************************************* +* Function : HAL_TIMEx_ConfigCommutEvent +* Description : Configure the TIM commutation event sequence. This function is mandatory to use the commutation event + in order to update the configuration at each commutation detection on the TRGI input of the Timer. +* Input : + htim: timer handler + InputTrigger: TIM_TS_ITR0, TIM_TS_ITR1... + CommutationSource: TIM_COMMUTATION_TRGI, TIM_COMMUTATION_SOFTWARE +* Output : +* Author : xwl +**********************************************************************************/ +void HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +{ + + if ((InputTrigger == TIM_TS_ITR0) || \ + (InputTrigger == TIM_TS_ITR1) || \ + (InputTrigger == TIM_TS_ITR2) || \ + (InputTrigger == TIM_TS_ITR3) || \ + (InputTrigger == TIM_TS_ITR4) || \ + (InputTrigger == TIM_TS_ITR5) || \ + (InputTrigger == TIM_TS_ITR6) || \ + (InputTrigger == TIM_TS_ITR7) || \ + (InputTrigger == TIM_TS_ITR8) || \ + (InputTrigger == TIM_TS_ITR9) || \ + (InputTrigger == TIM_TS_ITR10)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= (~TIM_SMCR_TS_Msk); + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + +} + +/********************************************************************************* +* Function : HAL_TIMEx_ConfigCommutEvent +* Description : Configure the TIM commutation event sequence. This function is mandatory to use the commutation event + in order to update the configuration at each commutation detection on the TRGI input of the Timer. +* Input : + htim: timer handler + Channel: specifies the TIM Channel + TISelection specifies the timer input source. + please refer the define. + For example for TIM1: +* For TIM1 this parameter can be one of the following values: +* TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO +* TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output +* TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output +* TIM_TIM1_TI1_COMP3: TIM1 TI1 is connected to COMP3 output +* TIM_TIM1_TI1_COMP4: TIM1 TI1 is connected to COMP4 output +* Output : HAL status +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + case TIM_CHANNEL_4: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/********************************************************************************* +* Function : HAL_TIMEx_Encoder_MspInit +* Description : Initializes Encoder MSP. +* Input : + htim: timer handler +* Output : None +**********************************************************************************/ +__WEAK void HAL_TIMEx_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + +} + +/********************************************************************************* +* Function : HAL_TIMEx_Encoder_MspDeInit +* Description : DeInitializes Encoder MSP. +* Input : + htim: timer handler +* Output : None +**********************************************************************************/ +__WEAK void HAL_TIMEx_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + +} + +/********************************************************************************* +* Function : HAL_TIMEx_HallSensor_Init +* Description : Configure the TIM encoder mode. +* Input : + htim: timer handler + EncoderMode: TIM encoder mode, only can be: TIM_SLAVE_MODE_ENC1, TIM_SLAVE_MODE_ENC2, TIM_SLAVE_MODE_ENC3; +* Output : HAL status +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_Encoder_Init(TIM_HandleTypeDef *htim, uint8_t EncoderMode) +{ + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_Encoder_MspInit(htim); + + /* Configure the encoder mode */ + htim->Instance->SMCR = (htim->Instance->SMCR & ~(BIT0|BIT1|BIT2) | EncoderMode); + + return HAL_OK; +} + +/********************************************************************************* +* Function : HAL_TIMEx_Encoder_Enable +* Description : Enable the TIM encoder. +* Input : + htim: timer handler +* Output : HAL status +**********************************************************************************/ +HAL_StatusTypeDef HAL_TIMEx_Encoder_Enable(TIM_HandleTypeDef *htim) +{ + + /* Enable the TIM */ + htim->Instance->CR1 |= BIT0; + + return HAL_OK; +} + +uint32_t HAL_TIMEx_Encoder_GetValue(TIM_HandleTypeDef *htim) +{ + return ((uint32_t)htim->Instance->CNT); +} + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_tkey .c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_tkey .c new file mode 100644 index 0000000000000000000000000000000000000000..504988d04faee51c1609ee3c0ee609bce98ed4be --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_tkey .c @@ -0,0 +1,720 @@ +/****************************************************************************** +*@file : hal_tkey.c +*@brief : TKEY HAL module driver. +******************************************************************************/ +#include "hal.h" + + +#ifdef HAL_TKEY_MODULE_ENABLED + + +/****************************************************************************** +*@brief : TKEY interrupt handler +*@param : None. +*@return: None +******************************************************************************/ +__weak void HAL_TKEY_IRQHandler(void) +{ + /* + NOTE: This function should be modified, when the callback is needed + */ + + /* For Example */ + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_EOC)) //Scanning completed + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_EOC); + } + + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_YESTOUCH)) //Key touch event has occurred + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_YESTOUCH); + } + + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_TIMEOUT)) //Channel scan timeout + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_TIMEOUT); + } + + if(SET == HAL_TKEY_GetFlagStatus(TKEY_IT_FLAG_BUSY)) //Channel scan busy + { + TKEY->CR |= TKEY_CR_START; + } + + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_DONE)) //Comparator flipping completed + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_DONE); + } + + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_CHG)) //Each charge is completed + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_CHG); + } + + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_CHGDONE)) //Charging frequency reaches the set number of times + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_CHGDONE); + } + + if(SET == HAL_TKEY_GetITStatus(TKEY_IT_FLAG_MEOC)) //Mutual inductance mode channel scan completed + { + HAL_TKEY_ClearITPendingBit(TKEY_IT_FLAG_MEOC); + } + +} + + +/****************************************************************************** +*@brief : Initialize the TKEY MSP: GPIO, CLK, NVIC +*@param : htkey: a pointer of TKEY_HandleTypeDef structure which contains +* the configuration information for the specified TKEY. +*@return: None +******************************************************************************/ +__weak void HAL_TKEY_MspInit(TKEY_HandleTypeDef* htkey) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(htkey); +} + +/****************************************************************************** +*@brief : TKEY De-Initialize the TKEY clock, GPIO, IRQ. +*@param : htkey: a pointer of TKEY_HandleTypeDef structure which contains +* the configuration information for the specified TKEY. +*@return: None +******************************************************************************/ +__weak void HAL_TKEY_MspDeInit(TKEY_HandleTypeDef* htkey) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(htkey); +} + + +/****************************************************************************** +*@brief : Initialize the TKEY module with parameters +*@param : hospi: a pointer of TKEY_HandleTypeDef structure which contains +* the configuration information for the specified TKEY. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_Init(TKEY_HandleTypeDef* htkey) +{ + uint32_t u32RegTemp; + + /* Check the TKEY handle allocation */ + if (htkey == NULL) + { + return HAL_ERROR; + } + + /* Check TKEY Parameter */ + assert_param(IS_TKEY_MODE(htkey->Init.Mode)); + assert_param(IS_TKEY_WORK_MODE(htkey->Init.WorkMode)); + assert_param(IS_TKEY_SCAN_MODE(htkey->Init.ScanMode)); + assert_param(IS_TKEY_SHIELD(htkey->Init.ShieldEn)); + assert_param(IS_TKEY_FILTER(htkey->Init.FilterNum)); + assert_param(IS_TKEY_VLDO(htkey->Init.Vldo)); + assert_param(IS_TKEY_VREF(htkey->Init.Vref)); + assert_param(IS_TKEY_SPREAD(htkey->Init.SpreadEn)); + assert_param(IS_TKEY_SMAPLE(htkey->Init.SampleNum)); + assert_param(IS_TKEY_CHANNEL_STATE(htkey->Init.ChannelEn)); + + assert_param(IS_TKEY_RADOM_JITTER(htkey->Timing.RandomJitterNum)); + assert_param(IS_TKEY_SCAN_INTERVAL(htkey->Timing.ScanInterval)); + assert_param(IS_TKEY_SCAN_CLK_PRESCALE(htkey->Timing.ScanClkPrescale)); + assert_param(IS_TKEY_SCAN_CLK_SW1HSW2L(htkey->Timing.ScanClkSW1HSW2L)); + assert_param(IS_TKEY_SCAN_CLK_SW1LSW2H(htkey->Timing.ScanClkSW1LSW2H)); + assert_param(IS_TKEY_SCAN_TIMEOUT_PWM_CYCLE(htkey->Timing.TimeoutOrPwmCycle)); + assert_param(IS_TKEY_CSDISCHARGETIME_CMPWAITTIME(htkey->Timing.DischargeTimeOrCMPWaitTime)); +// assert_param(IS_TKEY_SCAN_CLK_SOURCE(htkey->Timing.ScanClkSrc)); +// assert_param(IS_TKEY_CTRL_CLK_SOURCE(htkey->Timing.CtrlClkSrc)); + + /* Init the low level hardware : GPIO, CLOCK, NVIC, DMA */ + HAL_TKEY_MspInit(htkey); + + /* Check if the Tkey scan is busy */ + while(TKEY->SR & TKEY_SR_BUSY); + + /* disable the Tkey scan */ + TKEY->CR &= ~(TKEY_CR_START); + + /*---------------------------- TKEY CR Configuration -----------------*/ + u32RegTemp = ( htkey->Init.Mode | htkey->Init.WorkMode | htkey->Init.ScanMode | \ + htkey->Init.ShieldEn | htkey->Init.SpreadEn); + if(htkey->Init.SpreadEn == TKEY_SPREAD_ENABLE) + { + u32RegTemp |= htkey->Timing.RandomJitterNum; + } + TKEY->CR = u32RegTemp; + + /*---------------------------- TKEY CFGR1 Configuration -----------------*/ + TKEY->CFGR1 = ( htkey->Init.FilterNum | htkey->Init.SampleNum | htkey->Init.Vldo | htkey->Init.Vref); + + /*---------------------------- TKEY INTVLR Configuration -----------------*/ + TKEY->INTVLR = (htkey->Timing.ScanInterval); + + /*---------------------------- TKEY DIVR Scan CLK div Configuration -----------------*/ + TKEY->DIVR = (TKEY->DIVR & (~TKEY_DIVR_SCANCLKDIV_Msk)) | (htkey->Timing.ScanClkPrescale << TKEY_DIVR_SCANCLKDIV_Pos); + + /*---------------------------- TKEY SCCR Configuration -----------------*/ + TKEY->SCCR = ((htkey->Timing.ScanClkSW1HSW2L << TKEY_SCCR_SW1H_Pos) | htkey->Timing.ScanClkSW1LSW2H); + + /*---------------------------- TKEY TSETR Configuration -----------------*/ + u32RegTemp = ( htkey->Timing.TimeoutOrPwmCycle<< TKEY_TSETR_TSET_Pos) | (htkey->Timing.DischargeTimeOrCMPWaitTime <TSETR = u32RegTemp; + + /*---------------------------- TKEY CXENR Configuration -----------------*/ + TKEY->CXENR = (htkey->Init.ChannelEn); + + + /* Enable channel overall control */ + TKEY->CR |= TKEY_CR_CHEN; + + /* Enable TKEY module */ + TKEY->CR |= TKEY_CR_TKEN; + + /* TKEY's internal simulation module requires 10us to stabilize */ + HAL_SimpleDelay(10000);//ӳʱ + + return HAL_OK; +} + +/****************************************************************************** +*@brief : De-Initialize the OSPI peripheral +*@param : hospi: a pointer of OSPI_HandleTypeDef structure which contains +* the configuration information for the specified OSPI. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_DeInit(TKEY_HandleTypeDef* htkey) +{ + /* Check the TKEY handle allocation */ + if (htkey == NULL) + { + return HAL_ERROR; + } + + htkey->Init.Mode = 0; + htkey->Init.WorkMode = 0; + htkey->Init.ScanMode = 0; + htkey->Init.ShieldEn = 0;; + htkey->Init.FilterNum = 0; + htkey->Init.Vldo = 0; + htkey->Init.Vref = 0; + htkey->Init.SpreadEn = 0; + htkey->Init.ChannelEn = 0; + + htkey->Timing.RandomJitterNum = 0; + htkey->Timing.ScanInterval = 0; + htkey->Timing.ScanClkPrescale = 0; + htkey->Timing.ScanClkSW1HSW2L = 0; + htkey->Timing.ScanClkSW1LSW2H = 0; + htkey->Timing.TimeoutOrPwmCycle = 0; + + /*Check if the Tkey scan is busy*/ + while(TKEY->SR & TKEY_SR_BUSY); + + /*disable the Tkey scan*/ + TKEY->CR &= ~(TKEY_CR_START); + + /*disable the Tkey moudle*/ + TKEY->CR &= ~TKEY_CR_TKEN; + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_TKEY_MspDeInit(htkey); + + + return HAL_OK; +} + +/****************************************************************************** +*@brief : TKEY module enable or disable +*@param : NewState: Specify the new state of the TKEY module. +*@return: None +******************************************************************************/ +void HAL_TKEY_EnableDisable(uint32_t NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + TKEY->CR &= ~TKEY_CR_TKEN; + } + else + { + TKEY->CR |= TKEY_CR_TKEN; + HAL_SimpleDelay(10000);//ӳʱ + } +} + +/****************************************************************************** +*@brief : TKEY start to scan +*@param : None. +*@return: None +******************************************************************************/ +void HAL_TKEY_StartScan(void) +{ + /*Start the Tkey scan*/ + TKEY->CR |= TKEY_CR_START; + /* Waiting for START flag to turn to 0 */ + while(TKEY->CR & TKEY_CR_START); +} + + +/****************************************************************************** +*@brief : TKEY stop to scan +*@param : None. +*@return: None +******************************************************************************/ +void HAL_TKEY_StopScan(void) +{ + /* Waiting for BUSY flag to be 0 when stopping scanning */ + while(TKEY->SR & TKEY_SR_BUSY); + /*disable the Tkey scan*/ + TKEY->CR &= ~(TKEY_CR_START); +} + +/****************************************************************************** +*@brief : Read the count number of the all channels +*@param : pScanCount : Pointing to the channel scan count buffer. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_ReadChannelCount(uint16_t *pScanCount) +{ + uint8_t temp; + uint32_t u32RegTemp; + + if(pScanCount == NULL) + { + return HAL_ERROR; + } + + u32RegTemp = TKEY->CXENR; + + if(u32RegTemp == 0) + { + return HAL_ERROR; + } + for(temp = 0; temp < 16; temp++) + { + if (u32RegTemp & 0x01) + { + *pScanCount++ = TKEY->CH[temp]; + } + u32RegTemp >>= 1; + if(u32RegTemp == 0) + { + break; + } + } + return HAL_OK; +} + +/****************************************************************************** +*@brief : Read the count number of the last channel +*@param : None. +*@return: The scan count result of the last channel or button touch event channel +******************************************************************************/ +uint16_t HAL_TKEY_ReadLastChannelCount(void) +{ + return TKEY->DR; +} + +/****************************************************************************** +*@brief : Get the scanning channel number in normal mode or +* the channel number for scanning timeout +* get the key touch channel number in automatic mode +*@param : None. +*@return: channel number +******************************************************************************/ +uint8_t HAL_TKEY_GetSacnTimeoutAutoChannelNumber(void) +{ + return ((TKEY->SR & TKEY_SR_CHNUM_Msk)>> TKEY_SR_CHNUM_Pos); +} + + +/****************************************************************************** +*@brief : Parameter configuration for automatic mode +*@param : pBaseline: Pointing to the channel baseline buffer +*@param : pThreshold: Pointing to the channel threshold buffer +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_AutoConfig(TKEY_AutoConfigTypeDef *hauto) +{ + uint8_t temp; + uint32_t u32RegTemp; + + /* Check the parameters */ + assert_param(IS_TKEY_FILTER(hauto->FilterNum)); + + u32RegTemp = TKEY->CXENR; + + if(u32RegTemp == 0) + { + return HAL_ERROR; + } + for(temp = 0; temp < 16; temp++) + { + if (u32RegTemp & 0x01) + { + /* Set the baseline value for channel x */ + TKEY->CH[temp] = hauto->Baseline[temp]; + + /* Set the threshold value for channel x */ + TKEY->TH[temp] = hauto->Threshold[temp]; + } + u32RegTemp >>= 1; + if(u32RegTemp == 0) + { + break; + } + } + + /* Set hardware filtering times */ + TKEY->CFGR1 = (TKEY->CFGR1 & (~(TKEY_CFGR1_FLTSEL_Msk))) | hauto->FilterNum; + + /* Enable automatic mode */ + TKEY->CR |= TKEY_CR_AUTO; + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : CSA mode parameter configuration +*@param : hcsa: a pointer of TKEY_CSAConfigTypeDef structure which contains +* the CSA mode configuration information for the specified TKEY. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_CSAConfig(TKEY_CSAConfigTypeDef* hcsa) +{ + /* Check the parameters */ + assert_param(IS_TKEY_CHGNUMDONE(hcsa->ChargeNumDoneEn)); + assert_param(IS_TKEY_CHGEACHDONE(hcsa->ChargeEachDoneEN)); + assert_param(IS_TKEY_CSDISCHARGETIME_CMPWAITTIME(hcsa->DischargeTime)); + assert_param(IS_TKEY_COMPFILTERNUM(hcsa->ComparerFilterNum)); + assert_param(IS_TKEY_COMPFILTER(hcsa->ComparerFilterEN)); + assert_param(IS_TKEY_CHARGENUM(hcsa->ChargeNum)); + assert_param(IS_TKEY_CHARGEDONEWAITTIME(hcsa->ChargeDoneWaitTime)); + + /* Cs capacitor discharge time */ + TKEY->TSETR = (TKEY->TSETR & (~TKEY_TSETR_CST_Msk)) | hcsa->DischargeTime; + + /* Comparator filtering settings */ + if(hcsa->ComparerFilterEN == TKEY_COMPFILTER_ENABLE) + { + TKEY->CFLTR = (hcsa->ComparerFilterNum << TKEY_CFLTR_CFLTNUM_Pos | hcsa->ComparerFilterEN); + } + else + { + TKEY->CFLTR = hcsa->ComparerFilterEN; + } + + /* Charging numbers setting */ + TKEY->NSETR = hcsa->ChargeNum; + + /* Set the waiting time after reaching the set number of charges */ + TKEY->TWAITR = hcsa->ChargeDoneWaitTime; + + /* Enable charging times to reach the function, enable each charge to complete the function*/ + TKEY->CR = (TKEY->CR & (~(TKEY_CR_CHGDONEEN_Msk | TKEY_CR_CHGEN_Msk))) | hcsa->ChargeNumDoneEn | hcsa->ChargeEachDoneEN; + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : CSD mode parameter configuration +*@param : hcsd: a pointer of TKEY_CSDConfigTypeDef structure which contains +* the CSD mode configuration information for the specified TKEY. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_CSDConfig(TKEY_CSDConfigTypeDef* hcsd) +{ + /* Check the parameters */ + assert_param(IS_TKEY_DISMS(hcsd->DischargeMode)); + assert_param(IS_TKEY_PRECHARGE(hcsd->PrechargeEn)); + assert_param(IS_TKEY_DISCHARGECURRENT(hcsd->DischargeCurrent)); + assert_param(IS_TKEY_DISCHARGERES(hcsd->DischargeRes)); + assert_param(IS_TKEY_SAMPLEBITCLKDIV(hcsd->SampleBitClkDiv)); + + /* Set discharge current and resistance */ + TKEY->CFGR2 = (hcsd->DischargeCurrent << TKEY_CFGR2_IDISSEL_Pos) | (hcsd->DischargeRes); + + /* Set clock division for sampling bit streams */ + TKEY->DIVR = (TKEY->DIVR & (~TKEY_DIVR_SMPCLKDIV_Msk)) | hcsd->SampleBitClkDiv; + + /* Set discharge mode, enable precharge */ + TKEY->CR = (TKEY->CR & (~(TKEY_CR_DISMS_Msk | TKEY_CR_PCEN_Msk))) | (hcsd->DischargeMode) | (hcsd->PrechargeEn); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Mutual inductance mode parameter configuration +*@param : hmutual: a pointer of TKEY_MutualConfigTypeDef structure which contains +* the CSD Mutual inductance configuration information for the specified TKEY. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_TKEY_MutualConfig(TKEY_MutualConfigTypeDef* hmutual) +{ + /* Check the parameters */ + assert_param(IS_TKEY_MUTUAL_DELAY_TIME(hmutual->MutualDelayTime)); + assert_param(IS_TKEY_MUTUAL_DELAY_STATE(hmutual->MutualDelayEn)); + assert_param(IS_TKEY_MUTUAL_RESET(hmutual->MutualResetEn)); + assert_param(IS_TKEY_MUTUAL_CHANNEL_STATE(hmutual->MutualChannelEn)); + + /* Disable mutual inductance mode */ + TKEY->MUTUALR &= ~TKEY_MUTUALR_MUTUALEN; + + /* clear MTXDLY MTXDLYEN MTXRST bits */ + TKEY->MUTUALR &= ~(TKEY_MUTUALR_MTXDLY_Msk | TKEY_MUTUALR_MTXDLYEN_Msk | TKEY_MUTUALR_MTXRST_Msk); + + /* set MTXDLY MTXDLYEN MTXRST bits */ + TKEY->MUTUALR |= (hmutual->MutualDelayTime << TKEY_MUTUALR_MTXDLY_Pos) | (hmutual->MutualDelayEn) | (hmutual->MutualResetEn); + + /* Enable mutual inductance transmission channel */ + if(hmutual->MutualChannelEn > 0xffff) + { + TKEY->TXENR[0] = hmutual->MutualChannelEn & 0xffff; + TKEY->TXENR[1] = (hmutual->MutualChannelEn >> 16) & 0x3ff; + } + else + { + TKEY->TXENR[0] = hmutual->MutualChannelEn; + } + + /* Enable mutual inductance mode */ + TKEY->MUTUALR |= TKEY_MUTUALR_MUTUALEN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : TKEY mutual inductance mode enable or disable +*@param : NewState: Specify the new state of the TKEY mutual inductance mode. +*@return: None +******************************************************************************/ +void HAL_TKEY_MutualEnableDisable(uint32_t NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + TKEY->MUTUALR &= ~TKEY_MUTUALR_MUTUALEN; + } + else + { + TKEY->MUTUALR |= TKEY_MUTUALR_MUTUALEN; + } +} + + +/****************************************************************************** +*@brief : TKEY automatic mode enable or disable +*@param : NewState: Specify the new state of the TKEY automatic mode. +*@return: None +******************************************************************************/ +void HAL_TKEY_AutoEnableDisable(uint32_t NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == DISABLE) + { + TKEY->CR &= ~TKEY_CR_AUTO; + } + else + { + TKEY->CR |= TKEY_CR_AUTO; + } +} + +/****************************************************************************** +*@brief : Set resistance compensation +*@param : res: Compensated resistance. +*@return: None +******************************************************************************/ +void HAL_TKEY_ResCompensate(uint8_t res) +{ + /* Check the parameters */ + assert_param(IS_TKEY_RESCOMPENSTATE(res)); + TKEY->CFGR1 = (TKEY->CFGR1 & (~TKEY_CFGR1_RCPSEL_Msk)) | (res << TKEY_CFGR1_RCPSEL_Pos); +} + +/****************************************************************************** +*@brief : Set capacitance compensation +*@param : cap: Compensated capacitance. +*@return: None +******************************************************************************/ +void HAL_TKEY_CapCompensate(uint8_t cap) +{ + /* Check the parameters */ + assert_param(IS_TKEY_CAPCOMPENSTATE(cap)); + TKEY->CFGR1 = (TKEY->CFGR1 & (~TKEY_CFGR1_CCPSEL_Msk)) | (cap << TKEY_CFGR1_CCPSEL_Pos); +} + + +/****************************************************************************** +*@brief : Set the interval time between two sets of scans +*@param : time : the interval time. +*@return: None +******************************************************************************/ +void HAL_TKEY_ScanIntervalConfig(uint16_t time) +{ + /* Check TKEY Parameter */ + assert_param(IS_TKEY_SCAN_INTERVAL(time)); + /* TKEY INTVLR Configuration */ + TKEY->INTVLR = time; +} + + +/****************************************************************************** +*@brief : Read the interval time between two sets of scans +*@param : None. +*@return: the interval time +******************************************************************************/ +uint16_t HAL_TKEY_ReadScanInterval(void) +{ + return TKEY->INTVLR; +} + +/****************************************************************************** +*@brief : Enables or disables the specified TKEY interrupts. +*@param : irq: specifies the TKEY interrupt sources to be enabled or disabled. +*@param : NewState: new state of the specified TKEY interrupts. +* This parameter can be: ENABLE or DISABLE. +*@return: None. +******************************************************************************/ +void HAL_TKEY_ITConfig(uint32_t irq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_TKEY_IT_FLAG(irq)); + + if (NewState != DISABLE) + { + /* Enable the selected TKEY interrupts */ + TKEY->IER |= irq; + } + else + { + /* Disable the selected TKEY interrupts */ + TKEY->IER &= (~irq); + } +} + +/****************************************************************************** +*@brief : Checks whether the specified TKEY flag is set or not. +*@param : flag: specifies the flag to check. +*@return: The new state of flag (SET or RESET). +******************************************************************************/ +FlagStatus HAL_TKEY_GetFlagStatus(uint32_t flag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TKEY_IT_FLAG(flag)); + + /* Check the status of the specified TKEY flag */ + if ((TKEY->SR & flag) != RESET) + { + /* flag is set */ + bitstatus = SET; + } + else + { + /* flag is reset */ + bitstatus = RESET; + } + /* Return the TKEY_FLAG status */ + return bitstatus; +} + +/****************************************************************************** +*@brief : Clears the TKEY's pending flags. +*@param : flag: specifies the flag to clear. +*@return: None +******************************************************************************/ +void HAL_TKEY_ClearFlag(uint32_t flag) +{ + /* Check the parameters */ + assert_param(IS_TKEY_IT_FLAG(flag)); + + /* Clear the selected TKEY flags */ + TKEY->SR = flag; +} + +/****************************************************************************** +*@brief : Checks whether the specified TKEY interrupt has occurred or not. +*@param : irq: specifies the TKEY interrupt source to check. +*@return: The new state of irq (SET or RESET). +******************************************************************************/ +ITStatus HAL_TKEY_GetITStatus(uint32_t irq) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_TKEY_IT_FLAG(irq)); + + /* Get the irq enable bit status */ + enablestatus = (TKEY->IER & irq) ; + + /* Check the status of the specified TKEY interrupt */ + if (((TKEY->SR & irq) != RESET) && enablestatus) + { + /* irq is set */ + bitstatus = SET; + } + else + { + /* irq is reset */ + bitstatus = RESET; + } + /* Return the irq status */ + return bitstatus; +} + +/****************************************************************************** +*@brief : Clears the TKEY's interrupt pending bits. +*@param : irq: specifies the TKEY interrupt pending bit to clear. +*@return: None +******************************************************************************/ +void HAL_TKEY_ClearITPendingBit(uint32_t irq) +{ + /* Check the parameters */ + assert_param(IS_TKEY_IT_FLAG(irq)); + + if((TKEY->IER & irq)!= RESET) + { + /* Clear the interrupt pending bits in the TKEY_SR register */ + TKEY->SR = irq; + } +} + + +/****************************************************************************** +*@brief : Get enabled TKEY interrupt. +*@param : None. +*@return: TKEY interrupt enabled. +******************************************************************************/ +uint16_t HAL_TKEY_GetIT(void) +{ + /* Return the irq */ + return TKEY->IER; +} + +#endif + + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart.c new file mode 100644 index 0000000000000000000000000000000000000000..1c5fd5705513780bf2857a52a89d668f7ff314bc --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart.c @@ -0,0 +1,1255 @@ +/****************************************************************************** +* @file : hal_uart.c +* @brief : UART HAL module driver. +* This file provides firmware functions to manage the following +* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). +* @ver : V1.0.0 +* @date : 2020 +******************************************************************************/ +#include "hal.h" + + +#ifdef HAL_UART_MODULE_ENABLED + +UART_TypeDef *g_DebugUart = NULL; //printf UARTx + +/* Private function prototypes -----------------------------------------------*/ +static void UART_Config_BaudRate(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart); + +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +__weak void HAL_UART_IdleCallback(UART_HandleTypeDef *huart); +/****************************************************************************** +*@brief : Handle UART interrupt request +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags; + uint32_t ieits; + uint32_t errorflags; + uint16_t *pbuf_16; + + assert_param(IS_UART_ALL_INSTANCE(huart->Instance)); + + isrflags = READ_REG(huart->Instance->ISR); + ieits = READ_REG(huart->Instance->IE); + + errorflags =(isrflags & (uint32_t)(UART_ISR_PEI | UART_ISR_OEI | UART_ISR_FEI | UART_ISR_BEI)); + + /* which isr actually occured */ + isrflags &= ieits; + + /* TXI */ + if (isrflags & UART_ISR_TXI) + { + /* Clear TXI Status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_TXI); + + pbuf_16 = (uint16_t *)huart->TxData; + + for(;;) + { + if(huart->TxCount == huart->TxSize) + { + huart->TxBusy = false; + + /* Disable TX interrupt && error interrupt*/ + CLEAR_BIT(huart->Instance->IE, UART_IE_TXI | + UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI); + + HAL_UART_TxCpltCallback(huart); + return; + } + + if (READ_BIT(huart->Instance->FR, UART_FR_TXFF)) + { + break; + } + + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + huart->Instance->DR = (uint16_t)(pbuf_16[huart->TxCount++] & 0x01FFU); + } + else + { + huart->Instance->DR = huart->TxData[huart->TxCount++]; + } + } + } + + /* RXI */ + if (isrflags & UART_ISR_RXI) + { + /* Clear RXI Status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_RXI); + + pbuf_16 = (uint16_t *)huart->RxData; + + while(huart->RxCount < huart->RxSize ) + { + if(!READ_BIT(huart->Instance->FR, UART_FR_RXFE)) + { + /* Store Data in buffer */ + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + pbuf_16[huart->RxCount++] = (uint16_t)(huart->Instance->DR & 0x1FFU); + } + else + { + huart->RxData[huart->RxCount++] = (uint8_t)huart->Instance->DR; + } + } + else + { + break; + } + } + + if(huart->RxCount == huart->RxSize ) + { + huart->RxBusy = false; + + /* Disable RX and RTI interrupt && error interrupt*/ + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI | UART_IE_IDLEI | + UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI)); + + HAL_UART_RxCpltCallback(huart); + } + } + /* IDLEI */ + else if(isrflags & UART_ISR_IDLEI) + { + /*clear IDLE Status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_IDLEI); + + pbuf_16 = (uint16_t *)huart->RxData; + + while(!READ_BIT(huart->Instance->FR, UART_FR_RXFE)) + { + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + pbuf_16[huart->RxCount++] = (uint16_t)(huart->Instance->DR & 0x1FFU); + } + else + { + huart->RxData[huart->RxCount++] = (uint8_t)huart->Instance->DR; + } + } + + huart->RxBusy = false; + + /* Disable RX and RTI interrupt && error interrupt*/ + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI | UART_IE_IDLEI | + UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI)); + + + + HAL_UART_IdleCallback(huart); + } + + if(isrflags & UART_ISR_TCI) + { + /*clear IDLE Status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_TCI); + } + + /* if some errors occurred */ + if(errorflags != 0) + { + /* UART parity error interrupt occurred */ + if (((errorflags & UART_ISR_PEI) != 0)) + { + /* Clear parity error status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_PEI); + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART break error interrupt occurred */ + if (((errorflags & UART_ISR_BEI) != 0)) + { + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_BEI); + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred */ + if (((errorflags & UART_ISR_FEI) != 0)) + { + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_FEI); + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred */ + if (((errorflags & UART_ISR_OEI) != 0)) + { + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_OEI); + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + HAL_UART_ErrorCallback(huart); + } +} + + +/****************************************************************************** +*@brief : wait Tx FIFO empty +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart) +{ + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + /* wait TX not busy*/ + while(READ_BIT(huart->Instance->FR, UART_FR_BUSY)); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the UART MSP: CLK, GPIO, NVIC +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); +} + +/****************************************************************************** +*@brief : Initialize the UART DE Pin for RS485 +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_RS485Msp_Init(UART_HandleTypeDef *huart) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); +} + +/****************************************************************************** +*@brief : Initialize the UART according to the specified parameters in huart. +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + assert_param (IS_UART_WORDLENGTH(huart->Init.WordLength)); + assert_param (IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param (IS_UART_PARITY(huart->Init.Parity)); + assert_param (IS_UART_MODE(huart->Init.Mode)); + assert_param (IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_UART_MspInit(huart); + + /* Config BaudRate */ + UART_Config_BaudRate(huart); + + /* Set the UART Communication parameters */ + huart->Instance->CR3 = huart->Init.WordLength | UART_CR3_FEN | huart->Init.StopBits | huart->Init.Parity | (5<Instance->CR1 = huart->Init.HwFlowCtl | huart->Init.Mode; + + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + SET_BIT(huart->Instance->CR2, UART_CR2_HDSEL); + } + + __HAL_UART_ENABLE(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the UART RS485 according to the specified parameters in huart. +* +*@param : huart: uart handle with UART parameters. +*@param : de_polarity: RS485 DE Pin polarity. see @UART_RS485_DE_POL_Enum +*@param : deat_time: the time between the DE Pin activated and data transmiting. +*@param : dedt_time: the time between the last transmiting of data and the DE Pin de-activated. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_RS485_Init(UART_HandleTypeDef *huart, UART_RS485_DE_POL_Enum de_polarity, uint8_t deat_time, uint8_t dedt_time) +{ + assert_param(IS_RS485_INSTANCE(huart->Instance)); + + if(HAL_UART_Init(huart) == HAL_OK) + { + UART_TypeDef *instance = huart->Instance; + + /* uart RTS can not be used in RS485DE. + clear bit UART RTSen */ + CLEAR_BIT(instance->CR1, UART_CR1_RTSEN); + + HAL_UART_RS485Msp_Init(huart); + + SET_BIT(instance->BCNT, UART_BCNT_DEM); + + /* config DE Pin polarity */ + MODIFY_REG(instance->BCNT, UART_BCNT_DEP, (de_polarity << UART_BCNT_DEP_Pos)); + + /* config deat time */ + MODIFY_REG(instance->BCNT, UART_BCNT_DEAT, (deat_time << UART_BCNT_DEAT_Pos)); + + /* config dedt time */ + MODIFY_REG(instance->BCNT, UART_BCNT_DEDT, (dedt_time << UART_BCNT_DEDT_Pos)); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the UART IRDA Mode according to the specified parameters in huart. +* +*@param : huart: uart handle with UART parameters. +*@param : is_lowpwr: config IRDA low power mode. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_IRDA_Init(UART_HandleTypeDef *huart, bool is_lowpwr) +{ + assert_param(IS_IRDA_INSTANCE(huart->Instance)); + + if(HAL_UART_Init(huart) == HAL_OK) + { + uint32_t Uart_Clk; + UART_TypeDef *instance = huart->Instance; + + if(instance == USART1) + { + Uart_Clk = HAL_RCC_GetPCLK2Freq(); + } + else + { + Uart_Clk = HAL_RCC_GetPCLK1Freq(); + } + + SET_BIT(instance->CR1, UART_CR1_SIREN); + + if(is_lowpwr) + { + SET_BIT(instance->CR1, UART_CR1_SIRLP); + instance->GTPR = (uint8_t)(Uart_Clk / (115200 * 16)); + } + else + { + CLEAR_BIT(instance->CR1, UART_CR1_SIRLP); + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + + +/****************************************************************************** +*@brief : Initialize the Multi-UART Communication Mode +* according to the specified parameters in huart. +* +*@param : huart: uart handle with UART parameters. +*@param : addr: uart address +*@param : wakeupMode: UART waked up by idle line or address mark, +* see @UART_WakeupMode_Enum for more information +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t addr, UART_WakeupMode_Enum wakeupMode) +{ + if(HAL_UART_Init(huart) == HAL_OK) + { + /* config uart addr mode & addr */ + if(IS_UART_7BIT_ADDR_MODE(addr)) + { + SET_BIT(huart->Instance->CR2, UART_CR2_ADDM7); + } + else + { + CLEAR_BIT(huart->Instance->CR2, UART_CR2_ADDM7); + } + MODIFY_REG(huart->Instance->CR2, UART_CR2_ADDR, (addr << UART_CR2_ADDR_Pos)); + + /* config uart wakeup mode */ + MODIFY_REG(huart->Instance->CR2, UART_CR2_WAKE, (wakeupMode << UART_CR2_WAKE_Pos)); + } + else + { + return HAL_ERROR; + } + + __HAL_UART_ENABLE(huart); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DeInitialize the UART MSP +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); +} + +/****************************************************************************** +*@brief : DeInitialize the UART module +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + /* DeInit the low level hardware : GPIO, CLOCK, NVIC */ + HAL_UART_MspDeInit(huart); + + return HAL_OK; + +} + +/****************************************************************************** +*@brief : Send an amount of data by loop mode within timeout period. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to be sent. +*@param : timeout: Timeout duration, unit MS, 1(ms)~~0xFFFFFFFF(wait forever) +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint16_t *pbuf_16; + uint32_t Start_Tick; + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if ((buf == NULL) || (size == 0U)) + { + return HAL_ERROR; + } + + huart->TxCount = 0; + huart->TxData = buf; + pbuf_16 = (uint16_t *)huart->TxData; + + SET_BIT(huart->Instance->CR1, UART_CR1_TXE); + + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + /* disable RX in half-duplex mode */ + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXE); + } + + Start_Tick = HAL_GetTick(); + + while (size--) + { + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + huart->Instance->DR = (uint16_t)(pbuf_16[huart->TxCount++] & 0x01FFU); + } + else + { + huart->Instance->DR = huart->TxData[huart->TxCount++]; + } + while (huart->Instance->FR & UART_FR_TXFF) + { + if ((HAL_GetTick() - Start_Tick) > timeout) + { + return HAL_TIMEOUT; + } + } + } + + HAL_UART_Wait_Tx_Done(huart); + + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + SET_BIT(huart->Instance->CR1, UART_CR1_RXE); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode within timeout period. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@param : timeout: Timeout duration, unit MS, 1(ms)~~0xFFFFFFFF(wait forever) +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint16_t *pbuf_16; + uint32_t Start_Tick; + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if ((buf == NULL) || (size == 0U)) + { + return HAL_ERROR; + } + + huart->RxCount = 0; + huart->RxData = buf; + pbuf_16 = (uint16_t *)huart->RxData; + + /* In case RXE is disabled in transmit funtion */ + SET_BIT(huart->Instance->CR1, UART_CR1_RXE); + + Start_Tick = HAL_GetTick(); + + while (size--) + { + while(huart->Instance->FR & UART_FR_RXFE) + { + if ((HAL_GetTick() - Start_Tick) > timeout) + { + return HAL_TIMEOUT; + } + } + + /* Store Data in buffer */ + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + pbuf_16[huart->RxCount++] = (uint16_t)(huart->Instance->DR & 0x1FFU); + } + else + { + huart->RxData[huart->RxCount++] = (uint8_t)huart->Instance->DR; + } + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data to Idle line or BCNT time. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@param : rece_mode: by idle line, or by bit value count reached +*@param : timeout: BCNT value(relative to UART baudrate), when UART BaudRate = 115200, + then set timeout = 115200,it is approximately 1 second. MAX BCNT value can be 0xFFFFFF. +* Only used when 'rece_mode' = RECEIVE_TOBCNT +* when 'rece_mode' = RECEIVE_TOIDLE, it is meaningless. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_To_IDLEorBCNT(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, + UART_Receive_Mode_Enum rece_mode, uint32_t timeout) +{ + uint16_t *pbuf_16; +// uint32_t Start_Tick; + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if ((buf == NULL) || (size == 0U)) + { + return HAL_ERROR; + } + + huart->RxCount = 0; + huart->RxData = buf; + pbuf_16 = (uint16_t *)huart->RxData; + + /* In case RXE is disabled in transmit funtion */ + SET_BIT(huart->Instance->CR1, UART_CR1_RXE); + + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_IDLEI | UART_ISR_BCNTI); + + if(rece_mode == RECEIVE_TOBCNT) + { + MODIFY_REG(huart->Instance->BCNT, UART_BCNT_BCNTVALUE, timeout); + SET_BIT(huart->Instance->BCNT, UART_BCNT_AUTO_START_EN); + } + + while (size--) + { + while(huart->Instance->FR & UART_FR_RXFE) + { + if(rece_mode == RECEIVE_TOBCNT) + { + if(READ_BIT(huart->Instance->ISR, UART_ISR_BCNTI)) + { + CLEAR_BIT(huart->Instance->BCNT, UART_BCNT_AUTO_START_EN); + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_BCNTI); + return HAL_TIMEOUT; + } + } + else + { + if(READ_BIT(huart->Instance->ISR, UART_ISR_IDLEI)) + { + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_IDLEI); + while(READ_BIT(huart->Instance->ISR, UART_ISR_IDLEI)) + { + CLEAR_STATUS(huart->Instance->ISR, 0); + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_IDLEI); + } + return HAL_TIMEOUT; + } + } + } + + /* Store Data in buffer */ + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + pbuf_16[huart->RxCount++] = (uint16_t)(huart->Instance->DR & 0x1FFU); + } + else + { + huart->RxData[huart->RxCount++] = (uint8_t)huart->Instance->DR; + } + } + + CLEAR_BIT(huart->Instance->BCNT, UART_BCNT_AUTO_START_EN); + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send an amount of data in interrupt mode. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to send. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size) +{ + uint16_t *pbuf_16; + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if (huart->TxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + huart->TxSize = size; + huart->TxCount = 0; + huart->TxData = buf; + huart->TxBusy = true; + pbuf_16 = (uint16_t *)huart->TxData; + + SET_BIT(huart->Instance->CR1, UART_CR1_TXE); + + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + /* disable RX in half-duplex mode */ + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXE); + } + + /* Clear TXI Status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_TXI); + /* FIFO Enable */ + SET_BIT(huart->Instance->CR3, UART_CR3_FEN); + /*FIFO Select*/ + __HAL_UART_TXI_FIFO_LEVEL_SET(huart->Instance, UART_TX_FIFO_1_2); + + for(;;) + { + /*Data Size less than 16Byte */ + if(size == huart->TxCount) + { + huart->TxBusy = false; + + while ((huart->Instance->FR & UART_FR_BUSY)){} + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; + } + if(READ_BIT(huart->Instance->FR, UART_FR_TXFF)) + { + break; + } + + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + huart->Instance->DR = (uint16_t)(pbuf_16[huart->TxCount++] & 0x01FFU); + } + else + { + huart->Instance->DR = huart->TxData[huart->TxCount++]; + } + } + + /* Enable TX interrupt */ + SET_BIT(huart->Instance->IE, UART_IE_TXI); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in interrupt mode. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@return: HAL_StatusTypeDef +*@note : HAL_UART_Receive_IT() function will stop receiving data when: + 1. Total amount of data have been received. + 2. Idle line occured.(You can use __HAL_UART_Resume_Receive_IT(__HANDLE__) Macro + in HAL_UART_IdleCallback() fucntion in user code to resume receving data + if you still want to recive all the size of data) + + There will be already datas in UART FIFO before call this function. + use __HAL_UART_FIFO_FLUSH(__HANDLE__) macro before calling HAL_UART_Receive_IT() + to flush FIFO if the data is useless. +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size) +{ + uint16_t *pbuf_16; + + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if (huart->RxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + huart->RxSize = size; + huart->RxCount = 0; + huart->RxData = buf; + huart->RxBusy = true; + pbuf_16 = (uint16_t *)huart->RxData; + + SET_BIT(huart->Instance->CR1, UART_CR1_RXE); + + /* FIFO Enable */ + SET_BIT(huart->Instance->CR3, UART_CR3_FEN); + /*FIFO Select*/ + __HAL_UART_RXI_FIFO_LEVEL_SET(huart->Instance, UART_RX_FIFO_1_4); + + /* Clear RXI && IDLEI Status */ + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_RXI | UART_ISR_IDLEI); + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_PEI | UART_ISR_BEI | UART_ISR_OEI | UART_ISR_FEI); + + /* In case there are datas(which exceeded the FIFO LEVEL of triggering RXI ISR) already in UART FIFO before enabling RXI IE */ + while (size--) + { + if(huart->Instance->FR & UART_FR_RXFE) + { + goto start_recv_it; + } + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + { + pbuf_16[huart->RxCount++] = (uint16_t)(huart->Instance->DR & 0x1FFU); + } + else + { + huart->RxData[huart->RxCount++] = (uint8_t)huart->Instance->DR; + } + } + + /* have been received all the size of data */ + HAL_UART_RxCpltCallback(huart); + return HAL_OK; + +start_recv_it: + /* Enable the UART Errors interrupt */ + SET_BIT(huart->Instance->IE, UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI); + /* Enable RX and RTI interrupt */ + SET_BIT(huart->Instance->IE, UART_IE_RXI | UART_IE_IDLEI); + + return HAL_OK; +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Send an amount of data in DMA mode. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to send. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if (huart->TxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + huart->TxSize = size; + huart->TxCount = 0; + huart->TxData = buf; + huart->TxBusy = true; + + SET_BIT(huart->Instance->CR1, UART_CR1_TXE); + + if (huart->Init.Mode == UART_MODE_HALF_DUPLEX) + { + /* disable RX in half-duplex mode */ + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXE); + } + + SET_BIT(huart->Instance->CR1, UART_CR1_TXDMAE); + + __HAL_UART_TXI_FIFO_LEVEL_SET(huart->Instance, UART_TX_FIFO_1_16); + + if (HAL_DMA_Start_IT(huart->HDMA_Tx, (uint32_t)buf, (uint32_t)(&huart->Instance->DR), size)) + { + CLEAR_BIT(huart->Instance->CR1, UART_CR1_TXDMAE); + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in DMA mode. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if (huart->RxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + huart->RxSize = size; + huart->RxCount = 0; + huart->RxData = buf; + huart->RxBusy = true; + + /* In case RXE is disabled in transmit funtion */ + SET_BIT(huart->Instance->CR1, UART_CR1_RXE); + + CLEAR_STATUS(huart->Instance->ISR, UART_ISR_IDLEI); + + SET_BIT(huart->Instance->CR1, UART_CR1_RXDMAE); + + __HAL_UART_RXI_FIFO_LEVEL_SET(huart->Instance, UART_RX_FIFO_1_16); + + SET_BIT(huart->Instance->IE, UART_IE_IDLEI); + + /* Enable the UART Errors interrupt */ + SET_BIT(huart->Instance->IE, UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI); + + if (HAL_DMA_Start_IT(huart->HDMA_Rx, (uint32_t)(&huart->Instance->DR), (uint32_t)buf, size)) + { + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXDMAE); + CLEAR_BIT(huart->Instance->IE, UART_IE_IDLEI | UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI); + return HAL_ERROR; + } + + return HAL_OK; +} +#endif + +/****************************************************************************** +*@brief : Tx Transfer completed callbacks. +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Rx Transfer completed callbacks. +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Rx Transfer idleline callbacks. +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_IdleCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Recv Error callbacks. +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Config UART BaudRate +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +static void UART_Config_BaudRate(UART_HandleTypeDef *huart) +{ + uint32_t pclk; + uint32_t ibaud, fbaud; + uint64_t tmp; + + if (USART1 == huart->Instance) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + } + + /* Integral part */ + ibaud = pclk / (huart->Init.BaudRate * 16); + + /* Fractional part */ + tmp = pclk % (huart->Init.BaudRate * 16); + tmp = (tmp * 1000000) / (huart->Init.BaudRate * 16); + fbaud = (tmp * 64 + 500000) / 1000000; + + if (fbaud >= 64) + { + MODIFY_REG(huart->Instance->BRR, UART_BRR_IBAUD_Msk, ((ibaud + 1) << UART_BRR_IBAUD_Pos)); + MODIFY_REG(huart->Instance->BRR, UART_BRR_FBAUD_Msk, (0 << UART_BRR_FBAUD_Pos)); + } + else + { + MODIFY_REG(huart->Instance->BRR, UART_BRR_IBAUD_Msk, (ibaud << UART_BRR_IBAUD_Pos)); + MODIFY_REG(huart->Instance->BRR, UART_BRR_FBAUD_Msk, (fbaud << UART_BRR_FBAUD_Pos)); + } +} + +/****************************************************************************** +*@brief : Return the uart State +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_BUSY or HAL_OK +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if(huart->TxBusy || huart->RxBusy) + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Return the uart Error +* +*@param : huart: uart handle with UART parameters. +*@return: uart errcode +******************************************************************************/ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Abort ongoing transfers(blocking mode) +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + /*disble all interrupt*/ + huart->Instance->IE =0x00; + + /* Disable the UART DMA Tx request if enable */ + if(READ_BIT(huart->Instance->CR1, UART_CR1_TXDMAE)) + { + CLEAR_BIT(huart->Instance->CR1, UART_CR1_TXDMAE); + + /* Abort the UART Tx Channel */ + if(huart->HDMA_Tx) + { + /*Set the UART DMA Abort callback to Null */ + huart->HDMA_Tx->XferCpltCallback =NULL; + + if(HAL_DMA_Abort(huart->HDMA_Tx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /* Disable the UART DMA Rx request if enable */ + if(READ_BIT(huart->Instance->CR1, UART_CR1_RXDMAE)) + { + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXDMAE); + + /* Abort the UART Rx Channel */ + if(huart->HDMA_Rx) + { + /*Set the UART DMA Abort callback to Null */ + huart->HDMA_Rx->XferCpltCallback =NULL; + + if(HAL_DMA_Abort(huart->HDMA_Rx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /*Reset Tx and Rx Transfer size*/ + huart->TxSize = 0; + huart->RxSize = 0; + + /* Restore huart->TxBusy and huart->RxBusy to Ready */ + huart->TxBusy = false; + huart->RxBusy = false; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Pause the UART DMA Transfer +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if(READ_BIT(huart->Instance->CR1, UART_CR1_TXDMAE)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR1, UART_CR1_TXDMAE); + } + + if (READ_BIT(huart->Instance->CR1, UART_CR1_RXDMAE)) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->IE, UART_IE_OEI | UART_IE_PEI | UART_IE_BEI | UART_IE_FEI); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXDMAE); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Resume the UART DMA Transfer +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if (huart->TxBusy == false) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR1, UART_CR1_TXDMAE); + } + + if (huart->RxBusy == false) + { + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->IE, UART_IE_OEI | UART_IE_PEI | UART_IE_BEI | UART_IE_FEI); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR1, UART_CR1_RXDMAE); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the UART DMA Transfer +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + assert_param (IS_UART_ALL_INSTANCE(huart->Instance)); + + if(huart->Instance->CR1 & UART_CR1_TXDMAE) + { + CLEAR_BIT(huart->Instance->CR1, UART_CR1_TXDMAE); + if(huart->HDMA_Tx != NULL) + { + HAL_DMA_Abort(huart->HDMA_Tx); + } + + CLEAR_BIT(huart->Instance->IE, (UART_IE_TXI)); + } + + if(huart->Instance->CR1 & UART_CR1_RXDMAE) + { + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXDMAE); + if(huart->HDMA_Rx != NULL) + { + HAL_DMA_Abort(huart->HDMA_Rx); + } + + CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI | UART_IE_PEI)); + + CLEAR_BIT(huart->Instance->IE, UART_IE_IDLEI); + } + + return HAL_OK; +} +#endif + +/****************************************************************************** +*@brief : uart module enter into mute mode +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_OK +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + SET_BIT(huart->Instance->CR2, UART_CR2_RWU); + return HAL_OK; +} + +/****************************************************************************** +*@brief : uart module exit from mute mode +* +*@param : huart: uart handle with UART parameters. +*@return: HAL_OK +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) +{ + CLEAR_BIT(huart->Instance->CR2, UART_CR2_RWU); + return HAL_OK; +} + +/****************************************************************************** +*@brief : which uart instance is selected for debug using +* +*@param : UARTx: UART instance. +*@return: None +******************************************************************************/ +void HAL_UART_SetDebugUart(UART_TypeDef *UARTx) +{ + if(UARTx != NULL) + { + assert_param (IS_UART_ALL_INSTANCE(UARTx)); + } + g_DebugUart = UARTx; +} +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +/****************************************************************************** +*@brief : re-direct fputc to uart port +* +*@param : ch: character to send +*@param : f: a pointer to FILE struct, no use in uart re-directing +*@return: character sent +******************************************************************************/ +__weak int fputc(int ch, FILE *f) +{ + if(g_DebugUart) + { + g_DebugUart->DR = ch; + while ((g_DebugUart->FR & UART_FR_BUSY)); + } + return ch; +} +#elif defined (__GNUC__) + +__weak int __io_putchar(int ch) +{ + g_DebugUart->DR = ch; + while ((g_DebugUart->FR & UART_FR_BUSY)); + return ch; +} + +#endif +#endif //HAL_UART_MODULE_ENABLED + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart_7816m.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart_7816m.c new file mode 100644 index 0000000000000000000000000000000000000000..2a00c0a64cc0585405f9214c92d9cfebd397e224 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart_7816m.c @@ -0,0 +1,281 @@ +/****************************************************************************** +* @file : hal_uart_7816m.c +* @brief : UART HAL module driver for ISO7816 Master. +* This file provides firmware functions to manage the following +* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). +* @ver : V1.0.0 +* @date : 2020 +******************************************************************************/ +#include "hal.h" + +#ifdef HAL_UART_7816M_MODULE_ENABLED + +/****************************************************************************** +*@brief : Config baudrate of 7816 clk +* +*@param : uartx_instance: which uart instance +*@param : clk_hz: uart module clk freq +*@param : baud_rate: 7816 clk baudrate +*@return: None +******************************************************************************/ +static void uart_set_baud_rate(UART_TypeDef *uartx_instance, uint32_t clk_hz, uint32_t baud_rate) +{ + uint32_t temp, divider, remainder, fraction; + + temp = 16 * baud_rate; + divider = clk_hz / temp; + remainder = clk_hz % temp; + temp = 1 + (128 * remainder) / temp; + fraction = temp / 2; + + uartx_instance->BRR = (divider<<6)| fraction; +} + +/****************************************************************************** +*@brief : Initialize the UART MSP: CLK, GPIO, NVIC +* +*@param : huart: uart handle with UART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_UART_7816M_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct ={0}; + + UART_TypeDef *instance = huart->Instance; + + if(instance == USART1) + { + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_USART1_CLK_ENABLE(); + + /*7816 IO: PA9*/ + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*7816 RST: PA10*/ + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*7816 CLK: PA8*/ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_6; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + NVIC_ClearPendingIRQ(USART1_IRQn); + NVIC_EnableIRQ(USART1_IRQn); + } + else if(instance == USART2) + { + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_USART2_CLK_ENABLE(); + + + /*7816 IO: PB3*/ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_5; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + + /*7816 RST: PB4*/ + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_0; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*7816 CLK: PB5*/ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Drive = GPIO_DRIVE_LEVEL3; + GPIO_InitStruct.Alternate = GPIO_FUNCTION_5; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + NVIC_ClearPendingIRQ(USART2_IRQn); + NVIC_EnableIRQ(USART2_IRQn); + } +} + +/****************************************************************************** +*@brief : Initialize the UART 7816 Master mode + according to the specified parameters in huart. +* +*@param : huart: uart handle with UART parameters. +*@param : clk_psc: clk divison for 7816 clock output. +*@param : guard_time: 7816 Guard Time. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_7816M_Init(UART_HandleTypeDef *huart, uint32_t clk_psc, uint32_t guard_time) +{ + uint32_t uart_clk_hz, j = 0; + volatile uint8_t temp; + + UART_TypeDef *instance = huart->Instance; + + if(!huart) + { + return HAL_ERROR; + } + + if (USART1 == huart->Instance) + { + uart_clk_hz = HAL_RCC_GetPCLK2Freq(); + } + else + { + uart_clk_hz = HAL_RCC_GetPCLK1Freq(); + } + + HAL_UART_7816M_MspInit(huart); + + + __HAL_UART_DISABLE(huart); + + uart_set_baud_rate(instance, uart_clk_hz, huart->Init.BaudRate); + + + instance->CR3 = UART_WORDLENGTH_8B | UART_STOPBITS_1 | UART_PARITY_NONE | UART_TX_FIFO_1_16 | UART_RX_FIFO_1_16; //FIFO off + + SET_BIT(instance->CR3, UART_CR3_PEN); //1 parity bit + SET_BIT(instance->CR3, UART_CR3_EPS); //even + + SET_BIT(instance->CR2, UART_CR2_SCEN | UART_CR2_NACK | UART_CR2_HDSEL); //SC EN, NACK, 1 wire mode + + MODIFY_REG(instance->GTPR, UART_GTPR_PSC, (clk_psc << UART_GTPR_PSC_Pos)); //PSC 48MHz/((5+1)*2) = 12 about 4MHz + + MODIFY_REG(instance->GTPR, UART_GTPR_GT, (guard_time << UART_GTPR_GT_Pos)); + + instance->CR1 = (UART_CR1_RXE | UART_CR1_TXE |UART_CR1_UARTEN); //enable uart,rxe + + return HAL_OK; + +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode within timeout period. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@param : timeout: BCNT value +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_7816M_Receive(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint8_t i; + uint8_t errortimes; + volatile uint8_t temp; + HAL_StatusTypeDef err = HAL_OK; + + errortimes = 0; + + SET_BIT(huart->Instance->CR1, UART_CR1_RXE); + + huart->Instance->BCNT &= ~0x0A000000; //clear DEM and AUTO_START_EN + huart->Instance->BCNT = (huart->Instance->BCNT & ~0xFFFFFF) | timeout; + huart->Instance->BCNT |= 0x03000000; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + for (i = 0; i < size;) + { + while (((huart->Instance->FR & UART_FR_RXFE)==UART_FR_RXFE) && ((huart->Instance->ISR & UART_ISR_PEI)==0))//No data and no Parity Error + { + if(huart->Instance->ISR & UART_ISR_BCNTI) + { + SET_BIT(huart->Instance->ISR, UART_ISR_BCNTI); + err = HAL_TIMEOUT; + goto rxend; + } + } + if((huart->Instance->ISR & UART_ISR_PEI))//PE error + { + huart->Instance->ISR = UART_ISR_PEI; + errortimes++; + if(errortimes > 3) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + err = HAL_ERROR; + goto rxend; + } + + while ((huart->Instance->FR & UART_FR_RXFE)==UART_FR_RXFE) //No data + { + ; + } + + while ((huart->Instance->FR & UART_FR_RXFE)!= UART_FR_RXFE) //have data + { + temp = huart->Instance->DR; + } + } + else + { + buf[i] = huart->Instance->DR; + i++; + } + } + +rxend: + + huart->RxCount = i; + return err; +} + +/****************************************************************************** +*@brief : Send an amount of data by loop mode within timeout period. +* +*@param : huart: uart handle with UART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to be sent. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_UART_7816M_Transmit(UART_HandleTypeDef *huart, uint8_t *buf, uint32_t size) +{ + uint8_t i; + uint8_t errortimes; + HAL_StatusTypeDef err = HAL_OK; + + CLEAR_BIT(huart->Instance->CR1, UART_CR1_RXE); + + huart->TxCount = 0; + + for (i = 0; i < size; i++) + { + huart->Instance->DR = *buf++; + + while (huart->Instance->FR & UART_FR_TXFF) + { + if (huart->Instance->ISR & UART_ISR_FEI) //FE error + { + err = HAL_ERROR; + goto txend; + } + } + } + +txend: + + + + huart->TxCount = i; + + return err; +} + +#endif //HAL_UART_7816M_MODULE_ENABLED diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart_ex.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart_ex.c new file mode 100644 index 0000000000000000000000000000000000000000..869be9aaaf091ec7d4d0fc404fa3fe7310432a06 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_uart_ex.c @@ -0,0 +1,239 @@ +/****************************************************************************** +*@file : hal_uart_ex.c +*@brief : This file provides firmware functions to manage the UART LIN HAL module driver +*@ver : 1.0.0 +*@date : 2022.10.20 +******************************************************************************/ +#include "hal.h" + +/****************************************************************************** +*@brief : Uart lin master transmit data +* +*@param : huart: a pointer of UART_HandleTypeDef structure which contains +* the configuration information for the specified UART. +*@param : Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. +*@param : Lin_Id: LIN id +*@param : pData: point to the transmit data buffer. +*@param : Size: Transmit buffer Size. +*@return: None +******************************************************************************/ +void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size) +{ + uint8_t Lin_P0,Lin_P1,ucI; + uint16_t Lin_Check_Sum = 0; + + if((Size>8)||(pData == 0)) + return; + + CLEAR_BIT(huart->Instance->IE, UART_IE_LBDI); + huart->Instance->CR1 = 0x0101; //disable uart_rx + + MODIFY_REG(huart->Instance->BCNT, UART_BCNT_BCNTVALUE_Msk, (13)<Instance->BCNT, UART_BCNT_BCNTSTART); + SET_BIT(huart->Instance->CR3, UART_CR3_BRK); + + while(!(READ_BIT(huart->Instance->ISR, UART_ISR_BCNTI))){} //Check BCNTI. + CLEAR_BIT(huart->Instance->CR3, UART_CR3_BRK); + huart->Instance->ISR = UART_ISR_BCNTI; + + HAL_UART_Transmit(huart, (uint8_t*)"\x55", 1, 0); //Transmit sync field + + Lin_Id &= 0x3F; //Lin address check, 0-63. + Lin_P0 = (Lin_Id^(Lin_Id>>1)^(Lin_Id>>2)^(Lin_Id>>4))&0x01; //P0 = ID0^ID1^ID2^ID4 + Lin_P1 = (~((Lin_Id>>1)^(Lin_Id>>3)^(Lin_Id>>4)^(Lin_Id>>5)))&0x01; //P1 = ~(ID1^ID3^ID4^ID5) + Lin_Id = Lin_Id | (Lin_P0<<6) | (Lin_P1<<7); + + HAL_UART_Transmit(huart, &Lin_Id, 1, 0); //Transmit pid field + + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Id !=0x3C && Lin_Id!=0x3D)) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + if(Size) + { + for(ucI=0;ucI0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + + HAL_UART_Transmit(huart, pData, Size, 0); //Transmit data field + + HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0); //Transmit Lin_Check_Sum field + } +} + +/****************************************************************************** +*@brief : Uart lin slave transmit data +* +*@param : huart: a pointer of UART_HandleTypeDef structure which contains +* the configuration information for the specified UART. +*@param : Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. +*@param : Lin_Id: LIN id +*@param : pData: point to the transmit data buffer. +*@param : Size: Transmit buffer Size. +*@return: None +******************************************************************************/ +void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size) +{ + uint8_t ucI; + uint16_t Lin_Check_Sum = 0; + + if((Size>8)||(pData == 0)) + return; + + CLEAR_BIT(huart->Instance->IE, UART_IE_LBDI);//disable LBDI int + huart->Instance->CR1 = 0x0101; //disable uart_rx + + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Id !=0x3C && Lin_Id!=0x3D)) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + for(ucI=0;ucI0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + + HAL_UART_Transmit(huart, pData, Size, 0); //Transmit data field + + HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0); //Transmit Lin_Check_Sum field +} + +/****************************************************************************** +*@brief : Uart lin master receive data +* +*@param : huart: a pointer of UART_HandleTypeDef structure which contains +* the configuration information for the specified UART. +*@param : Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. +*@param : Lin_Id: LIN id +*@param : pData: point to the transmit data buffer. +*@param : Timeout: timeout. +*@return: RxSize +******************************************************************************/ +uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout) +{ + uint8_t ucI,RxSize; + uint8_t Lin_Rx_Buf[16]; + uint16_t Lin_Check_Sum = 0; + + if(pData == 0) + return 0; + + huart->Instance->CR3 = 0x48E0; //FIFO send and receive number is 8 + //8 data bit,1 stop bit,0 verify bit,enable FIFO + huart->Instance->CR1 = 0x0201; //disable uart_tx + huart->Instance->IE = 0x00; //Disable all interrupt + huart->Instance->ISR = 0x7fff; //clear int + + HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout); + + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Id !=0x3C && Lin_Id!=0x3D)) + Lin_Check_Sum = Lin_Id; //LIN 2.X check sum calc with PID. + + if(huart->RxCount) + { + for(ucI=0;ucI<(huart->RxCount-1);ucI++) + { + Lin_Check_Sum += Lin_Rx_Buf[ucI]; + if(Lin_Check_Sum>0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI]) + { + RxSize = huart->RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0xFF; + } + else + RxSize = 0; + + return RxSize; +} + +/****************************************************************************** +*@brief : Uart lin slave receive data +* +*@param : huart: a pointer of UART_HandleTypeDef structure which contains +* the configuration information for the specified UART. +*@param : Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX. +*@param : Lin_Id: LIN id +*@param : pData: point to the transmit data buffer. +*@param : Timeout: timeout. +*@return: RxSize +******************************************************************************/ +uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout) +{ + uint8_t ucI,RxSize; + uint8_t Lin_Rx_Buf[16]; + uint16_t Lin_Check_Sum = 0; + uint32_t u32_Timeout; + + if(pData == 0) + return 0; + + huart->Instance->CR3 = 0x48E0; //FIFO send and receive number is 8 + //8 data bit,1 stop bit,0 verify bit,enable FIFO + huart->Instance->CR1 = 0x0201; //disable uart_tx + huart->Instance->IE = 0x00; //Disable all interrupt + huart->Instance->ISR = 0x7fff; //clear int + + if (Timeout == 0) + { + while(!READ_BIT(huart->Instance->ISR, UART_ISR_LBDI)); + } + else + { + u32_Timeout = Timeout * 0xFF; + + while(!READ_BIT(huart->Instance->ISR, UART_ISR_LBDI)) + { + if (u32_Timeout-- == 0) + { + return 0; + } + } + } + SET_BIT(huart->Instance->ISR, UART_ISR_LBDI); + + HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout); //waitting rx completed. + + if(huart->RxCount > 3) + { + if((Lin_Version==UART_LIN_V2DX)&&(Lin_Rx_Buf[2] !=0x3C && Lin_Rx_Buf[2]!=0x3D)) + Lin_Check_Sum = Lin_Rx_Buf[2]; //LIN 2.X check sum calc with PID. + + if(huart->RxCount) + { + for(ucI=3;ucI<(huart->RxCount-1);ucI++) + { + Lin_Check_Sum += Lin_Rx_Buf[ucI]; + if(Lin_Check_Sum>0xFF) + Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF; + } + Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF; + if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI]) + { + RxSize = huart->RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0xFF; + } + } + else if(huart->RxCount<=3) + { + RxSize = huart->RxCount; + memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize); + } + else + RxSize = 0; + + return RxSize; +} diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_usart.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..44e1b734ea30cc35ba15dce48034feef9db9496b --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_usart.c @@ -0,0 +1,1026 @@ +/****************************************************************************** +* @file : hal_usart.c +* @brief : USART HAL module driver. +* This file provides firmware functions to manage the following +* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (USART). +* @ver : V1.0.0 +* @date : 2020 +******************************************************************************/ +#include "hal.h" + + +#ifdef HAL_USART_MODULE_ENABLED + +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) + +/* Private function prototypes -----------------------------------------------*/ +static void USART_Config_BaudRate(USART_HandleTypeDef *husart); +static void USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef HAL_USART_Wait_Tx_Done(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t flag, FlagStatus status, + uint32_t tick_start, uint32_t timeout); + +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +__weak void HAL_USART_IdleCallback(USART_HandleTypeDef *husart); +/****************************************************************************** +*@brief : Handle USART interrupt request +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags; + uint32_t ieits; + uint32_t errorflags; + uint16_t *pbuf_16; + + assert_param(IS_USART_ALL_INSTANCE(husart->Instance)); + + isrflags = READ_REG(husart->Instance->ISR); + ieits = READ_REG(husart->Instance->IE); + + errorflags =(isrflags & (uint32_t)(USART_ISR_PEI | USART_ISR_OEI | USART_ISR_FEI | USART_ISR_BEI)); + + /* which isr actually occured */ + isrflags &= ieits; + + /* TXI */ + if (isrflags & USART_ISR_TXI) + { + /* Clear TXI Status */ + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_TXI); + + pbuf_16 = (uint16_t *)husart->TxData; + + for(;;) + { + if(husart->TxCount == husart->TxSize) + { + husart->TxBusy = false; + + /* Disable TX interrupt && error interrupt*/ + CLEAR_BIT(husart->Instance->IE, USART_IE_TXI | + USART_IE_OEI | USART_IE_BEI | USART_IE_PEI | USART_IE_FEI); + + HAL_USART_TxCpltCallback(husart); + return; + } + + if (READ_BIT(husart->Instance->FR, USART_FR_TXFF)) + { + break; + } + + if (husart->Init.WordLength == USART_WORDLENGTH_9B) + { + husart->Instance->DR = (uint16_t)(pbuf_16[husart->TxCount++] & 0x01FFU); + } + else + { + husart->Instance->DR = husart->TxData[husart->TxCount++]; + } + } + } + + /* RXI */ + if (isrflags & USART_ISR_RXI) + { + /* Clear RXI Status */ + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_RXI); + + pbuf_16 = (uint16_t *)husart->RxData; + + while(husart->RxCount < husart->RxSize ) + { + if(!READ_BIT(husart->Instance->FR, USART_FR_RXFE)) + { + /* Store Data in buffer */ + if (husart->Init.WordLength == USART_WORDLENGTH_9B) + { + pbuf_16[husart->RxCount++] = (uint16_t)(husart->Instance->DR & 0x1FFU); + } + else + { + husart->RxData[husart->RxCount++] = (uint8_t)husart->Instance->DR; + } + } + else + { + break; + } + } + + if(husart->RxCount == husart->RxSize ) + { + husart->RxBusy = false; + + /* Disable RX and RTI interrupt && error interrupt*/ + CLEAR_BIT(husart->Instance->IE, (USART_IE_RXI | USART_IE_IDLEI | + USART_IE_OEI | USART_IE_BEI | USART_IE_PEI | USART_IE_FEI)); + + HAL_USART_RxCpltCallback(husart); + } + } + /* IDLEI */ + else if(isrflags & USART_ISR_IDLEI) + { + /*clear IDLE Status */ + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_IDLEI); + + pbuf_16 = (uint16_t *)husart->RxData; + + while(!READ_BIT(husart->Instance->FR, USART_FR_RXFE)) + { + if (husart->Init.WordLength == USART_WORDLENGTH_9B) + { + pbuf_16[husart->RxCount++] = (uint16_t)(husart->Instance->DR & 0x1FFU); + } + else + { + husart->RxData[husart->RxCount++] = (uint8_t)husart->Instance->DR; + } + } + + husart->RxBusy = false; + + /* Disable RX and RTI interrupt && error interrupt*/ + CLEAR_BIT(husart->Instance->IE, (USART_IE_RXI | USART_IE_IDLEI | + USART_IE_OEI | USART_IE_BEI | USART_IE_PEI | USART_IE_FEI)); + + + + HAL_USART_IdleCallback(husart); + } + + /* if some errors occurred */ + if(errorflags != 0) + { + /* USART parity error interrupt occurred */ + if (((errorflags & USART_ISR_PEI) != 0)) + { + /* Clear parity error status */ + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_PEI); + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART break error interrupt occurred */ + if (((errorflags & USART_ISR_BEI) != 0)) + { + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_BEI); + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART frame error interrupt occurred */ + if (((errorflags & USART_ISR_FEI) != 0)) + { + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_FEI); + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART Over-Run interrupt occurred */ + if (((errorflags & USART_ISR_OEI) != 0)) + { + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_OEI); + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + HAL_USART_ErrorCallback(husart); + } +} + + +/****************************************************************************** +*@brief : wait Tx FIFO empty +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +static HAL_StatusTypeDef HAL_USART_Wait_Tx_Done(USART_HandleTypeDef *husart) +{ + + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + /* wait TX not busy*/ + while(READ_BIT(husart->Instance->FR, USART_FR_BUSY)); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the USART MSP: CLK, GPIO, NVIC +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); +} + +/****************************************************************************** +*@brief : Initialize the USART according to the specified parameters in husart. +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); +// assert_param (IS_USART_WORDLENGTH(husart->Init.WordLength)); +// assert_param (IS_USART_STOPBITS(husart->Init.StopBits)); +// assert_param (IS_USART_PARITY(husart->Init.Parity)); +// assert_param (IS_USART_MODE(husart->Init.Mode)); +// assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); +// assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); +// assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); +// assert_param (IS_USART_HARDWARE_FLOW_CONTROL(husart->Init.HwFlowCtl)); + + + if(husart->Instance == USART1) + __HAL_RCC_USART1_RESET(); + else if(husart->Instance == USART2) + __HAL_RCC_USART2_RESET(); + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_USART_MspInit(husart); + +// /* Config BaudRate */ +// USART_Config_BaudRate(husart); + + /* Set the USART Communication parameters */ + USART_SetConfig(husart); + + + /* In USART mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register */ + //CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_SCEN | USART_CR2_HDSEL)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_SIREN)); +// /* Set the USART Communication parameters */ +// husart->Instance->CR3 = husart->Init.WordLength | USART_CR3_FEN | husart->Init.StopBits | husart->Init.Parity; +// husart->Instance->CR1 = husart->Init.HwFlowCtl | husart->Init.Mode; +// +// if (husart->Init.Mode == USART_MODE_HALF_DUPLEX) +// { +// SET_BIT(husart->Instance->CR2, USART_CR2_HDSEL); +// } + + __HAL_USART_ENABLE(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : DeInitialize the USART MSP +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* + NOTE : This function is implemented in user xxx_hal_msp.c + */ + + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); +} + +/****************************************************************************** +*@brief : DeInitialize the USART module +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + /* DeInit the low level hardware : GPIO, CLOCK, NVIC */ + HAL_USART_MspDeInit(husart); + + return HAL_OK; + +} + +/****************************************************************************** +*@brief : Send an amount of data by loop mode within timeout period. +* +*@param : husart: usart handle with USART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to be sent. +*@param : timeout: Timeout duration, unit MS, 1(ms)~~0xFFFFFFFF(wait forever) +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint16_t *pbuf_16; + uint32_t Start_Tick; + + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if ((buf == NULL) || (size == 0U)) + { + return HAL_ERROR; + } + + + + husart->TxCount = 0; + husart->TxData = buf; + pbuf_16 = (uint16_t *)husart->TxData; + + SET_BIT(husart->Instance->CR1, USART_CR1_TXE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXE);//add 0204 + + Start_Tick = HAL_GetTick(); + + while (size--) + { + if (husart->Init.WordLength == UART_WORDLENGTH_9B) + { + husart->Instance->DR = (uint16_t)(pbuf_16[husart->TxCount++] & 0x01FFU); + } + else + { + husart->Instance->DR = husart->TxData[husart->TxCount++]; + } + while (husart->Instance->FR & USART_FR_TXFF) + { + if ((HAL_GetTick() - Start_Tick) > timeout) + { + return HAL_TIMEOUT; + } + } + } + + HAL_USART_Wait_Tx_Done(husart); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data by loop mode within timeout period. +* +*@param : husart: usart handle with USART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@param : timeout: Timeout duration, unit MS, 1(ms)~~0xFFFFFFFF(wait forever) +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *buf, uint32_t size, uint32_t timeout) +{ + uint16_t *pbuf_16; + uint32_t Start_Tick; + + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if ((buf == NULL) || (size == 0U)) + { + return HAL_ERROR; + } + + husart->RxCount = 0; + husart->RxData = buf; + pbuf_16 = (uint16_t *)husart->RxData; + + /* In case RXE is disabled in transmit funtion */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXE); + + Start_Tick = HAL_GetTick(); + + while (size--) + { + while (husart->Instance->FR & USART_FR_TXFF) + { + if ((HAL_GetTick() - Start_Tick) > timeout) + { + return HAL_TIMEOUT; + } + } + + //husart->Instance->DR = (USART_DUMMY_DATA & (uint16_t)0x1FF); + + husart->Instance->DR = (USART_DUMMY_DATA & 0xFF); + + while(husart->Instance->FR & USART_FR_RXFE) + { + if ((HAL_GetTick() - Start_Tick) > timeout) + { + return HAL_TIMEOUT; + } + } + + /* Store Data in buffer */ + if (husart->Init.WordLength == UART_WORDLENGTH_9B) + { + pbuf_16[husart->RxCount++] = (uint16_t)(husart->Instance->DR & 0x1FFU); + } + else + { + husart->RxData[husart->RxCount++] = (uint8_t)husart->Instance->DR; + } + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Send an amount of data in interrupt mode. +* +*@param : husart: usart handle with USART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to send. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *buf, uint32_t size) +{ + uint16_t *pbuf_16; + + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if (husart->TxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + husart->TxSize = size; + husart->TxCount = 0; + husart->TxData = buf; + husart->TxBusy = true; + + SET_BIT(husart->Instance->CR1, USART_CR1_TXE); + /* Clear TXI Status */ + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_TXI); + /* FIFO Enable */ + SET_BIT(husart->Instance->CR3, USART_CR3_FEN); + /*FIFO Select*/ + __USART_TXI_FIFO_LEVEL_SET(USART_TX_FIFO_1_2); + + for(;;) + { + /*Data Size less than 16Byte */ + if(size == husart->TxCount) + { + husart->TxBusy = false; + + while ((husart->Instance->FR & USART_FR_BUSY)){} + + HAL_USART_TxCpltCallback(husart); + + return HAL_OK; + } + if(READ_BIT(husart->Instance->FR, USART_FR_TXFF)) + { + break; + } + if (husart->Init.WordLength == USART_WORDLENGTH_9B) + { + husart->Instance->DR = (uint16_t)(pbuf_16[husart->TxCount++] & 0x01FFU); + } + else + { + husart->Instance->DR = husart->TxData[husart->TxCount++]; + } + } + + /* Enable TX interrupt */ + SET_BIT(husart->Instance->IE, USART_IE_TXI); + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in interrupt mode. +* +*@param : husart: usart handle with USART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *buf, uint32_t size) +{ + uint16_t *pbuf_16; + + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if (husart->RxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + husart->RxSize = size; + husart->RxCount = 0; + husart->RxData = buf; + husart->RxBusy = true; + pbuf_16 = (uint16_t *)husart->RxData; + + SET_BIT(husart->Instance->CR1, USART_CR1_RXE); + /* FIFO Enable */ + SET_BIT(husart->Instance->CR3, USART_CR3_FEN); + /*FIFO Select*/ + __USART_RXI_FIFO_LEVEL_SET(USART_RX_FIFO_1_2); + /* Clear RXI && IDLEI Status */ + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_RXI | USART_ISR_IDLEI); + CLEAR_STATUS(husart->Instance->ISR, UART_ISR_PEI | UART_ISR_BEI | UART_ISR_OEI | UART_ISR_FEI); + /* Enable the USART Errors interrupt */ + SET_BIT(husart->Instance->IE, USART_IE_OEI | USART_IE_BEI | USART_IE_PEI | USART_IE_FEI); + /* Enable RX and RTI interrupt */ + SET_BIT(husart->Instance->IE, USART_IE_RXI | USART_IE_IDLEI); + + return HAL_OK; +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Send an amount of data in DMA mode. +* +*@param : husart: usart handle with USART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to send. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *buf, uint32_t size) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if (husart->TxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + husart->TxSize = size; + husart->TxCount = 0; + husart->TxData = buf; + husart->TxBusy = true; + + SET_BIT(husart->Instance->CR1, USART_CR1_TXE); + + SET_BIT(husart->Instance->CR1, USART_CR1_TXDMAE); + + __USART_TXI_FIFO_LEVEL_SET(USART_TX_FIFO_1_16); + + if (HAL_DMA_Start_IT(husart->HDMA_Tx, (uint32_t)buf, (uint32_t)(&husart->Instance->DR), size)) + { + CLEAR_BIT(husart->Instance->CR1, UART_CR1_TXDMAE); + return HAL_ERROR; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Receive an amount of data in DMA mode. +* +*@param : husart: usart handle with USART parameters. +*@param : buf: Pointer to data buffer. +*@param : size: Amount of data elements to receive. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *buf, uint32_t size) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if (husart->RxBusy == true) + { + return HAL_BUSY; + } + + if (size == 0 || buf == NULL) + { + return HAL_ERROR; + } + + husart->RxSize = size; + husart->RxCount = 0; + husart->RxData = buf; + husart->RxBusy = true; + + /* In case RXE is disabled in transmit funtion */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXE); + + CLEAR_STATUS(husart->Instance->ISR, USART_ISR_IDLEI); + + SET_BIT(husart->Instance->CR1, USART_CR1_RXDMAE); + + __USART_RXI_FIFO_LEVEL_SET(USART_RX_FIFO_1_16); + + SET_BIT(husart->Instance->IE, USART_IE_IDLEI); + + /* Enable the USART Errors interrupt */ + SET_BIT(husart->Instance->IE, USART_IE_OEI | USART_IE_BEI | USART_IE_PEI | USART_IE_FEI); + + if (HAL_DMA_Start_IT(husart->HDMA_Rx, (uint32_t)(&husart->Instance->DR), (uint32_t)buf, size)) + { + CLEAR_BIT(husart->Instance->CR1, UART_CR1_RXDMAE); + CLEAR_BIT(husart->Instance->IE, UART_IE_IDLEI | UART_IE_OEI | UART_IE_BEI | UART_IE_PEI | UART_IE_FEI); + return HAL_ERROR; + } + + return HAL_OK; +} +#endif + +/****************************************************************************** +*@brief : Tx Transfer completed callbacks. +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_USART_TxCpltCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Rx Transfer completed callbacks. +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_USART_RxCpltCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Rx Transfer idleline callbacks. +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_IdleCallback(USART_HandleTypeDef *husart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_USART_RxCpltCallback could be implemented in the user file. + */ +} + +/****************************************************************************** +*@brief : Recv Error callbacks. +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* + NOTE: This function Should be modified, when the callback is needed, + the HAL_USART_ErrorCallback could be implemented in the user file. + */ +} + + +/****************************************************************************** +*@brief : Return the usart State +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_BUSY or HAL_OK +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if(husart->TxBusy || husart->RxBusy) + { + return HAL_BUSY; + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Return the usart Error +* +*@param : husart: usart handle with USART parameters. +*@return: usart errcode +******************************************************************************/ +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +#ifdef HAL_DMA_MODULE_ENABLED +/****************************************************************************** +*@brief : Abort ongoing transfers(blocking mode) +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + /*disble all interrupt*/ + husart->Instance->IE =0x00; + + /* Disable the USART DMA Tx request if enable */ + if(READ_BIT(husart->Instance->CR1, USART_CR1_TXDMAE)) + { + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXDMAE); + + /* Abort the USART Tx Channel */ + if(husart->HDMA_Tx) + { + /*Set the USART DMA Abort callback to Null */ + husart->HDMA_Tx->XferCpltCallback =NULL; + + if(HAL_DMA_Abort(husart->HDMA_Tx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /* Disable the USART DMA Rx request if enable */ + if(READ_BIT(husart->Instance->CR1, USART_CR1_RXDMAE)) + { + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXDMAE); + + /* Abort the USART Rx Channel */ + if(husart->HDMA_Rx) + { + /*Set the USART DMA Abort callback to Null */ + husart->HDMA_Rx->XferCpltCallback =NULL; + + if(HAL_DMA_Abort(husart->HDMA_Rx)!=HAL_OK) + { + return HAL_TIMEOUT; + } + } + } + + /*Reset Tx and Rx Transfer size*/ + husart->TxSize = 0; + husart->RxSize = 0; + + /* Restore husart->TxBusy and husart->RxBusy to Ready */ + husart->TxBusy = false; + husart->RxBusy = false; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Pause the USART DMA Transfer +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if(READ_BIT(husart->Instance->CR1, USART_CR1_TXDMAE)) + { + /* Disable the USART DMA Tx request */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXDMAE); + } + + if (READ_BIT(husart->Instance->CR1, USART_CR1_RXDMAE)) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->IE, USART_IE_OEI | USART_IE_PEI | USART_IE_BEI | USART_IE_FEI); + + /* Disable the USART DMA Rx request */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXDMAE); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Resume the USART DMA Transfer +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if (husart->TxBusy == false) + { + /* Enable the USART DMA Tx request */ + SET_BIT(husart->Instance->CR1, USART_CR1_TXDMAE); + } + + if (husart->RxBusy == false) + { + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(husart->Instance->IE, USART_IE_OEI | USART_IE_PEI | USART_IE_BEI | USART_IE_FEI); + + /* Enable the USART DMA Rx request */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXDMAE); + } + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Stop the USART DMA Transfer +* +*@param : husart: usart handle with USART parameters. +*@return: HAL_StatusTypeDef +******************************************************************************/ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + assert_param (IS_USART_ALL_INSTANCE(husart->Instance)); + + if(husart->Instance->CR1 & USART_CR1_TXDMAE) + { + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXDMAE); + if(husart->HDMA_Tx != NULL) + { + HAL_DMA_Abort(husart->HDMA_Tx); + } + + CLEAR_BIT(husart->Instance->IE, (USART_IE_TXI)); + } + + if(husart->Instance->CR1 & USART_CR1_RXDMAE) + { + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXDMAE); + if(husart->HDMA_Rx != NULL) + { + HAL_DMA_Abort(husart->HDMA_Rx); + } + + CLEAR_BIT(husart->Instance->IE, (USART_IE_RXI | USART_IE_PEI)); + + CLEAR_BIT(husart->Instance->IE, USART_IE_IDLEI); + } + + return HAL_OK; +} +#endif + +/** + * @brief Handle USART Communication Timeout. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t flag, FlagStatus status, + uint32_t tick_start, uint32_t timeout) +{ + /* Wait until flag is set */ + while ((__HAL_USART_GET_FLAG(husart, flag) ? SET : RESET) == status) + { + /* Check for the Timeout */ + if (timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tick_start) > timeout) || (timeout == 0U)) + { + //husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + //__HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/****************************************************************************** +*@brief : Config USART BaudRate +* +*@param : husart: usart handle with USART parameters. +*@return: None +******************************************************************************/ +static void USART_Config_BaudRate(USART_HandleTypeDef *husart) +{ + uint32_t pclk; + uint32_t ibaud, fbaud; + uint64_t tmp; + + if (USART1 == husart->Instance) + { + pclk = HAL_RCC_GetPCLK2Freq(); + } + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + } + + /* Integral part */ + ibaud = pclk / (husart->Init.BaudRate * 16); + + /* Fractional part */ + tmp = pclk % (husart->Init.BaudRate * 16); + tmp = (tmp * 1000000) / (husart->Init.BaudRate * 16); + fbaud = (tmp * 64 + 500000) / 1000000; + + if (fbaud >= 64) + { + MODIFY_REG(husart->Instance->BRR, USART_BRR_IBAUD_Msk, ((ibaud + 1) << USART_BRR_IBAUD_Pos)); + MODIFY_REG(husart->Instance->BRR, USART_BRR_FBAUD_Msk, (0 << USART_BRR_FBAUD_Pos)); + } + else + { + MODIFY_REG(husart->Instance->BRR, USART_BRR_IBAUD_Msk, (ibaud << USART_BRR_IBAUD_Pos)); + MODIFY_REG(husart->Instance->BRR, USART_BRR_FBAUD_Msk, (fbaud << USART_BRR_FBAUD_Pos)); + } +} + +/** + * @brief Configures the USART peripheral. + * @param husart Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg = 0x00U; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORDLENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + + /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the + receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXE | USART_CR1_RXE)); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + tmpreg = husart->Instance->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)); + /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/ + /* Set CPOL bit according to husart->Init.CLKPolarity value */ + /* Set CPHA bit according to husart->Init.CLKPhase value */ + /* Set LBCL bit according to husart->Init.CLKLastBit value */ + tmpreg |= (uint32_t)(USART_CLOCK_ENABLE | husart->Init.CLKPolarity | + husart->Init.CLKPhase | husart->Init.CLKLastBit); + /* Write to USART CR2 */ + WRITE_REG(husart->Instance->CR2, (uint32_t)tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = husart->Instance->CR3; + + /* Clear M, PCE, PS, TE, RE and OVER8 bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR3_WLEN | USART_CR3_PEN | USART_CR3_SPS | USART_CR3_EPS| \ + USART_CR3_STP2)); + + /* Configure the USART Word Length, Parity and mode, stop bits */ + tmpreg |= (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.StopBits; + + /* Write to USART CR1 */ + WRITE_REG(husart->Instance->CR3, (uint32_t)tmpreg); + + + husart->Instance->CR1 = husart->Init.Mode; + + /* Clear CTSE and RTSE bits */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RTSEN | USART_CR1_CTSEN)); + + USART_Config_BaudRate(husart); +} + +#endif //HAL_USART_MODULE_ENABLED + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_wdt.c b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..5bc9429c901a426f85e84fa9eda67a5d42857e1d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/HAL_Driver/Src/hal_wdt.c @@ -0,0 +1,118 @@ + +/****************************************************************************** +*@file : hal_wdt.c +*@brief : WDT HAL module driver. +******************************************************************************/ + +#include "hal.h" + +#ifdef HAL_WDT_MODULE_ENABLED + + +/****************************************************************************** +*@brief : WDT interrupt request. +*@param : hwdt: pointer to a WDT_HandleTypeDef structure that contains +* the configuration information for the specified WDT module. +*@return: None +******************************************************************************/ +void HAL_WDT_IRQHandler(WDT_HandleTypeDef *hwdt) +{ + /* Check the parameters */ + assert_param(IS_WDT_ALL_INSTANCE(hwdt->Instance)); + + HAL_WDT_Callback(hwdt); +} + + +/****************************************************************************** +*@brief : WDT interrupt callback. +*@param : hwdt: pointer to a WDT_HandleTypeDef structure that contains +* the configuration information for the specified WDT module. +*@return: None +******************************************************************************/ +__weak void HAL_WDT_Callback(WDT_HandleTypeDef *hwdt) +{ + UNUSED(hwdt); +} + +/****************************************************************************** +*@brief : Initialize the WDG according to the specified. +* parameters in the WDG_InitTypeDef of associated handle. +*@param : hwdt: pointer to a WDT_HandleTypeDef structure that contains +* the configuration information for the specified WDT module. +*@return: HAL status +******************************************************************************/ +HAL_StatusTypeDef HAL_WDT_Init(WDT_HandleTypeDef *hwdt) +{ + /* Check the WWDG handle allocation */ + if (hwdt == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_WDT_ALL_INSTANCE(hwdt->Instance)); + assert_param(IS_WDT_PRESCALER(hwdt->Init.Prescaler)); + assert_param(IS_WDT_MODE(hwdt->Init.Mode)); + + HAL_WDT_MspInit(hwdt); + + /* disable the WDT */ + hwdt->Instance->CTRL &= ~WDT_CTRL_EN; + + /* Set WDG Prescaler and Mode*/ + hwdt->Instance->CTRL &= ~(WDT_CTRL_DIVISOR | WDT_CTRL_MODE); + hwdt->Instance->CTRL |= hwdt->Init.Prescaler | hwdt->Init.Mode; + + /* Set WDG load */ + hwdt->Instance->LOAD = hwdt->Init.Load; + + /* Set WDG interrupt clear time */ + if (hwdt->Init.Mode == WDT_MODE_INTERRUPT) + { + assert_param(IS_WDT_INTCLRTIME(hwdt->Init.IntClrTime)); + hwdt->Instance->INTCLRTIME = hwdt->Init.IntClrTime; + } + + /* enable the WDT */ + hwdt->Instance->CTRL |= WDT_CTRL_EN; + + return HAL_OK; +} + +/****************************************************************************** +*@brief : Initialize the WDT MSP. +*@param : hwdt: pointer to a WDT_HandleTypeDef structure that contains +* the configuration information for the specified WDT module. +*@return: None +******************************************************************************/ +__weak void HAL_WDT_MspInit(WDT_HandleTypeDef * hwdt) +{ + UNUSED(hwdt); +} + + + + +/****************************************************************************** +*@brief : Refresh the WDT. +*@param : hwdt: pointer to a WDT_HandleTypeDef structure that contains +* the configuration information for the specified WDT module. +*@return: None +******************************************************************************/ + +/** + * @brief Refresh the WWDG. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WDT_Refresh(WDT_HandleTypeDef *hwdt) +{ + hwdt->Instance->FEED = WDT_CMD_FEED_WATCHDOG; + + return HAL_OK; +} + +#endif /* HAL_WDT_MODULE_ENABLED */ + diff --git a/bsp/acm32/acm32h5xx-nucleo/libraries/SConscript b/bsp/acm32/acm32h5xx-nucleo/libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..812c529fde87b4324338c96d11cabaabecada536 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/libraries/SConscript @@ -0,0 +1,35 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +src = Split(""" +Device/System_ACM32F4.c +HAL_Driver/Src/HAL_EFlash.c +HAL_Driver/Src/HAL_DMA.c +HAL_Driver/Src/HAL_GPIO.c +HAL_Driver/Src/HAL_UART.c +HAL_Driver/Src/HAL_EXTI.c +""") + + +libpath = ['.', cwd + '/Device', cwd + '/HAL_Driver/Src'] +libs = ['System_Accelerate', 'HAL_EFlash_EX'] + +if rtconfig.PLATFORM in ['gcc']: + src += ['Device/startup_ACM32F4_gcc.s'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += ['Device/Startup_ACM32F4.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += ['Device/Startup_ACM32F4_iar.s'] + +path = [cwd + '/HAL_Driver/Inc', + cwd + '/Device', + cwd + '/CMSIS'] + +group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath) + +Return('group') + diff --git a/bsp/acm32/acm32h5xx-nucleo/project.ewp b/bsp/acm32/acm32h5xx-nucleo/project.ewp new file mode 100644 index 0000000000000000000000000000000000000000..1ddd37ba8277cea923dbdea2253d75c54eef22a8 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/project.ewp @@ -0,0 +1,2324 @@ + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + 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$PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + + CPU + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + 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$PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler_up.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + POSIX + + diff --git a/bsp/acm32/acm32h5xx-nucleo/project.eww b/bsp/acm32/acm32h5xx-nucleo/project.eww new file mode 100644 index 0000000000000000000000000000000000000000..c2cb02eb1e89d73e24183274c1c886ddf74f9537 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/project.uvoptx b/bsp/acm32/acm32h5xx-nucleo/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..796336dcf08961b5d27a080a8b0929d3f0678cb9 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/project.uvoptx @@ -0,0 +1,1296 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ACM32H5XX_RTT + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + UL2V8M + -UV0VVV123 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20008000 -FC8000 -FN1 -FF0ACM32H5_SPI_FLASH -FS08002000 -FL0FFE000 + + + 0 + CMSIS_AGDI_V8M + -X"CMSIS-DAP Debugger HS" -U202112A1 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO3 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### uVision Project, (C) Keil Software
+ + + + ACM32H5XX_RTT + 0x4 + ARM-ADS + 6150000::V6.15::ARMCLANG + 6150000::V6.15::ARMCLANG + 1 + + + ACM32H5XX + Aisinochip + Aisinochip.ACM32H5XX.1.0.1 + https://www.Aisinochip.com/ + IRAM(0x20008000,0x00050000) IRAM2(0x20000000,0x00008000) IROM(0x08002000,0x001FE000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CDECP(0xFF) CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20008000 -FC8000 -FN1 -FF0ACM32H5_SPI_FLASH -FS08002000 -FL01FE000 -FP0($$Device:ACM32H5XX$Flash\ACM32H5_SPI_FLASH.FLM)) + 0 + + + + + + + + + + + $$Device:ACM32H5XX$ACM32H5XX.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + ACM32H5XX + 1 + 0 + 1 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin --output ./build/ACM32F4.bin ./build/ACM32F4.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 255 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20008000 + 0x50000 + + + 1 + 0x8002000 + 0x1fe000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8002000 + 0x800000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20008000 + 0x50000 + + + 0 + 0x20000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 6 + 4 + 1 + 1 + 0 + 0 + 0 + + + RT_USING_LIBC, __STDC_NO_ATOMICS__ , __RTTHREAD__, __STDC_LIMIT_MACROS, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, VECT_TAB_SPI_FLASH, __DSP_PRESENT, VECT_TAB_QSPI7_FLASH + + ..\..\..\components\libc\posix\io\poll;..\..\..\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;libraries\HAL_Driver\Inc;libraries\CMSIS;applications;..\..\..\components\drivers\include;libraries\Device;..\..\..\libcpu\arm\common;..\..\..\components\libc\compilers\common\extension\fcntl\octal;.;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\eventfd;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;.\board;.\drivers\config;.\drivers\Inc;..\..\..\components\gui\lvgl_9_0_0\src\core;..\..\..\components\gui\lvgl_9_0_0\src\draw;..\..\..\components\gui\lvgl_9_0_0\src\draw\acm32_dma2d;..\..\..\components\gui\lvgl_9_0_0\src\font;..\..\..\components\gui\lvgl_9_0_0\src\hal;..\..\..\components\gui\lvgl_9_0_0\src\layouts;..\..\..\components\gui\lvgl_9_0_0\src\layouts\flex;..\..\..\components\gui\lvgl_9_0_0\src\layouts\grid;..\..\..\components\gui\lvgl_9_0_0\src\libs\barcode;..\..\..\components\gui\lvgl_9_0_0\src\libs\bmp;..\..\..\components\gui\lvgl_9_0_0\src\libs\ffmpeg;..\..\..\components\gui\lvgl_9_0_0\src\libs\freetype;..\..\..\components\gui\lvgl_9_0_0\src\libs\fsdrv;..\..\..\components\gui\lvgl_9_0_0\src\libs\gif;..\..\..\components\gui\lvgl_9_0_0\src\libs\png;..\..\..\components\gui\lvgl_9_0_0\src\libs\qrcode;..\..\..\components\gui\lvgl_9_0_0\src\libs\rlottie;..\..\..\components\gui\lvgl_9_0_0\src\libs\sjpg;..\..\..\components\gui\lvgl_9_0_0\src\libs\tiny_ttf;..\..\..\components\gui\lvgl_9_0_0\src\misc;..\..\..\components\gui\lvgl_9_0_0\src\others\file_explorer;..\..\..\components\gui\lvgl_9_0_0\src\others\fragment;..\..\..\components\gui\lvgl_9_0_0\src\others\gridnav;..\..\..\components\gui\lvgl_9_0_0\src\others\ime;..\..\..\components\gui\lvgl_9_0_0\src\others\imgfont;..\..\..\components\gui\lvgl_9_0_0\src\others\monkey;..\..\..\components\gui\lvgl_9_0_0\src\others\msg;..\..\..\components\gui\lvgl_9_0_0\src\others\snapshot;..\..\..\components\gui\lvgl_9_0_0\src\themes\basic;..\..\..\components\gui\lvgl_9_0_0\src\themes\default;..\..\..\components\gui\lvgl_9_0_0\src\themes\mono;..\..\..\components\gui\lvgl_9_0_0\src\themes;..\..\..\components\gui\lvgl_9_0_0\src;..\..\..\components\gui\lvgl_9_0_0\src\widgets\animimg;..\..\..\components\gui\lvgl_9_0_0\src\widgets\arc;..\..\..\components\gui\lvgl_9_0_0\src\widgets\bar;..\..\..\components\gui\lvgl_9_0_0\src\widgets\btn;..\..\..\components\gui\lvgl_9_0_0\src\widgets\btnmatrix;..\..\..\components\gui\lvgl_9_0_0\src\widgets\calendar;..\..\..\components\gui\lvgl_9_0_0\src\widgets\canvas;..\..\..\components\gui\lvgl_9_0_0\src\widgets\chart;..\..\..\components\gui\lvgl_9_0_0\src\widgets\checkbox;..\..\..\components\gui\lvgl_9_0_0\src\widgets\colorwheel;..\..\..\components\gui\lvgl_9_0_0\src\widgets\dropdown;..\..\..\components\gui\lvgl_9_0_0\src\widgets\img;..\..\..\components\gui\lvgl_9_0_0\src\widgets\imgbtn;..\..\..\components\gui\lvgl_9_0_0\src\widgets\keyboard;..\..\..\components\gui\lvgl_9_0_0\src\widgets\label;..\..\..\components\gui\lvgl_9_0_0\src\widgets\led;..\..\..\components\gui\lvgl_9_0_0\src\widgets\line;..\..\..\components\gui\lvgl_9_0_0\src\widgets\list;..\..\..\components\gui\lvgl_9_0_0\src\widgets\menu;..\..\..\components\gui\lvgl_9_0_0\src\widgets\meter;..\..\..\components\gui\lvgl_9_0_0\src\widgets\msgbox;..\..\..\components\gui\lvgl_9_0_0\src\widgets\objx_templ;..\..\..\components\gui\lvgl_9_0_0\src\widgets\roller;..\..\..\components\gui\lvgl_9_0_0\src\widgets\slider;..\..\..\components\gui\lvgl_9_0_0\src\widgets\span;..\..\..\components\gui\lvgl_9_0_0\src\widgets\spinbox;..\..\..\components\gui\lvgl_9_0_0\src\widgets\spinner;..\..\..\components\gui\lvgl_9_0_0\src\widgets\switch;..\..\..\components\gui\lvgl_9_0_0\src\widgets\table;..\..\..\components\gui\lvgl_9_0_0\src\widgets\tabview;..\..\..\components\gui\lvgl_9_0_0\src\widgets\textarea;..\..\..\components\gui\lvgl_9_0_0\src\widgets\tileview;..\..\..\components\gui\lvgl_9_0_0\src\widgets\win;.\applications\lvgl;..\..\..\components\gui\lvgl_9_0_0\env_support\rt-thread;.\packages\CherryUSB-master\class\hub;.\packages\CherryUSB-master\common;.\packages\CherryUSB-master\core;.\packages\CherryUSB-master\port\acm32H5;.\packages\CherryUSB-master\class\hid;.\packages\CherryUSB-master\class\msc;.\packages\CherryUSB-master\class\audio;..\..\..\components\dfs\dfs_v2\include;..\..\..\components\dfs\dfs_v2\src;..\..\..\components\dfs\dfs_v2\filesystems\elmfat;..\..\..\components\dfs\dfs_v2\filesystems\devfs;..\..\..\components\libc\compilers\common\extension\sys + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + C:\Keil\ARM\INC\ARM + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\Project_user_xflash.sct + + + + + + + + + + + ACM32_HAL + + + startup_acm32h5xx.s + 2 + .\libraries\Device\Templates\ARM\startup_acm32h5xx.s + + + system_acm32h5xx.c + 1 + .\libraries\Device\system_acm32h5xx.c + + + system_accelerate.c + 1 + .\libraries\Device\system_accelerate.c + + + hal.c + 1 + .\libraries\HAL_Driver\Src\hal.c + + + hal_cortex.c + 1 + .\libraries\HAL_Driver\Src\hal_cortex.c + + + hal_rcc.c + 1 + .\libraries\HAL_Driver\Src\hal_rcc.c + + + HAL_UART.c + 1 + libraries\HAL_Driver\Src\HAL_UART.c + + + HAL_DMA.c + 1 + libraries\HAL_Driver\Src\HAL_DMA.c + + + HAL_EXTI.c + 1 + libraries\HAL_Driver\Src\HAL_EXTI.c + + + HAL_GPIO.c + 1 + libraries\HAL_Driver\Src\HAL_GPIO.c + + + hal_fmc.c + 1 + .\libraries\HAL_Driver\Src\hal_fmc.c + + + hal_efuse.c + 1 + .\libraries\HAL_Driver\Src\hal_efuse.c + + + + + Applications + + + main.c + 1 + applications\main.c + + + acm32h5xx_it.c + 1 + .\applications\acm32h5xx_it.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + CPU + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m33\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m33\cpuport.c + + + syscall_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + + + trustzone.c + 1 + ..\..\..\libcpu\arm\cortex-m33\trustzone.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + completion_up.c + 1 + ..\..\..\components\drivers\ipc\completion_up.c + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + dev_pin.c + 1 + ..\..\..\components\drivers\pin\dev_pin.c + + + dev_serial.c + 1 + ..\..\..\components\drivers\serial\dev_serial.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + drv_dma.c + 1 + .\drivers\drv_dma.c + + + board.c + 1 + .\board\board.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + mem.c + 1 + ..\..\..\src\mem.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + + + + + + + + + RTE\USB\USBD_Config_MSC_0.h + + + + + + + + + + + project + 0 + 1 + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/project_flash.BAT b/bsp/acm32/acm32h5xx-nucleo/project_flash.BAT new file mode 100644 index 0000000000000000000000000000000000000000..81ded61659db424904fd2915fdd9e98bb4903ba0 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/project_flash.BAT @@ -0,0 +1,152 @@ +SET PATH=C:\Keil_v5\ARM\ARMCLANG\Bin;C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\bin;C:\Program Files (x86)\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Strawberry\c\bin;C:\Strawberry\perl\site\bin;C:\Strawberry\perl\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files\Microsoft SQL Server\120\Tools\Binn\;C:\Program Files (x86)\Windows Kits\10\Windows Performance Toolkit\;C:\Program Files\Git\cmd;C:\Program Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Qt\Qt5.12.0\5.12.0\msvc2015_64\bin;C:\Qt\Qt5.12.0\Tools\QtCreator\bin;C:\Program Files\IDM Computer Solutions\UltraEdit;C:\Program Files\CMake\bin;C:\openssl\openssl-1.1.1j;C:\Program Files\NASM;C:\Program Files (x86)\GnuWin32\bin;C:\WinDDK\7600.16385.1\bin\x86\ia64;C:\Program Files\Microsoft VS Code\bin;C:\Program Files (x86)\WinMerge;C:\Users\peter\AppData\Local\Programs\Python\Python38\Scripts\;C:\Users\peter\AppData\Local\Programs\Python\Python38\;C:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\bin;C:\Program Files (x86)\Microsoft Visual Studio\Common\Tools\WinNT;C:\Program Files (x86)\Microsoft Visual Studio\Common\MSDev98\Bin;C:\Program Files (x86)\Microsoft Visual Studio\Common\Tools;C:\Program Files (x86)\Microsoft Visual Studio\VC98\bin;C:\Qt\Qt5.12.0\5.12.0\msvc2015_64\bin;C:\Qt\Qt5.12.0\Tools\QtCreator\bin;C:\openssl\openssl-1.1.1j;C:\Program Files\NASM;C:\Program Files (x86)\GnuWin32\bin;C:\WinDDK\7600.16385.1\bin\x86\ia64;C:\Users\peter\MSYS2;C:\Users\peter\MSYS2\mingw64\bin;C:\Users\peter\MSYS2\mingw32\bin +SET CPU_TYPE=ACM32H5XX +SET CPU_VENDOR=Aisinochip +SET UV2_TARGET=project_flash +SET CPU_CLOCK=0x00B71B00 +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\startup_acm32h5xx._ac" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\main._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\main._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\main.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\app_usbd._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\app_usbd._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\app_usbd.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\app_dcmi._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\app_dcmi._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\app_dcmi.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\app_disp._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\app_disp._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\app_disp.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\app_sdcard._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\APP_SD~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\app_sdcard.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\app_net._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\app_net._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\app_net.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\acm32h5xx_it._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\ACM32H~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\acm32h5xx_it.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\acm32h5xx_hal_msp._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\ACM32H~2._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\acm32h5xx_hal_msp.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\acm32h5xx_coreboard._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\ACM32H~3._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\acm32h5xx_coreboard.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\acm32h5xx_eth_for_cyclone_tcp_mii_lan8710_single_packet._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\ACM32H~4._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\acm32h5xx_eth_for_cyclone_tcp_mii_lan8710_single_packet.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\usbd_core._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\USBD_C~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\usbd_core.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\usbd_ctlreq._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\USBD_C~2._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\usbd_ctlreq.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\usbd_ioreq._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\USBD_I~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\usbd_ioreq.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\usbd_conf._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\USBD_C~3._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\usbd_conf.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\usbd_bulk_transfer._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\USBD_B~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\usbd_bulk_transfer.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\usbd_desc._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\USBD_D~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\usbd_desc.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_disp._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\bsp_disp._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_disp.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_sdcard._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\BSP_SD~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_sdcard.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_sdram._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\BSP_SD~2._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_sdram.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_usbd._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\bsp_usbd._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_usbd.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_dcmi._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\bsp_dcmi._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_dcmi.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_i2c._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\bsp_i2c._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_i2c.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\bsp_ov2640._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\BSP_OV~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\bsp_ov2640.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_eth._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_eth._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_eth.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_rcc._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_rcc._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_rcc.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_cortex._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\HAL_CO~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_cortex.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_exti._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_exti._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_exti.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_gpio._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_gpio._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_gpio.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_dma._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_dma._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_dma.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_uart._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_uart._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_uart.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_fmc._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_fmc._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_fmc.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_sdmmc._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\HAL_SD~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_sdmmc.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_dcmi._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_dcmi._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_dcmi.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_dma2d._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\HAL_DM~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_dma2d.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_ltdc._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_ltdc._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_ltdc.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\ll_usb._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\ll_usb._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\ll_usb.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_pcd._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_pcd._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_pcd.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_pcd_ex._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\HAL_PC~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_pcd_ex.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\hal_i2c._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\hal_i2c._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\hal_i2c.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\system_acm32h5xx._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\SYSTEM~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\system_acm32h5xx.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\irq_armv8mml._ac" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_delay._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\RTX_DE~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\rtx_delay.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_evflags._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\RTX_EV~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\rtx_evflags.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_evr._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\rtx_evr._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\rtx_evr.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_kernel._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\RTX_KE~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\rtx_kernel.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_lib._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\rtx_lib._ip" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\rtx_lib.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_memory._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\RTX_ME~1._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\objects\rtx_memory.__i" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @".\listings\rtx_mempool._ll" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmClang.exe" @"listings\RTX_ME~2._IP" +"C:\Keil_v5\ARM\ARMCLANG\Bin\ArmLink" --Via ".\Objects\Project.lnp" +"C:\Keil_v5\ARM\ARMCLANG\Bin\fromelf.exe" ".\Objects\Project.axf" --i32combined --output ".\Objects\Project.hex" diff --git a/bsp/acm32/acm32h5xx-nucleo/rtconfig.h b/bsp/acm32/acm32h5xx-nucleo/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..cb8d6d2a141550fba6d620c2e10616ecb1759d28 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/rtconfig.h @@ -0,0 +1,346 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +#define __RT_IPC_SOURCE__ + + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +//#define RT_USING_TIMER_SOFT +//#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_CPUS_NR 1 +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_POSIX_DEVIO +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_VER_NUM 0x50002 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +//#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_SDRAM +//#define RT_USING_SDMMC + +/* Using USB */ +#define RT_USING_OTG +#ifdef RT_USING_OTG + #define RT_USING_USB_HOST + #ifdef RT_USING_USB_HOST + #define PKG_CHERRYUSB_HOST + #endif + + #define RT_USING_USB_DEVICE + +#endif + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +//#define PKG_USING_LVGL + #ifdef PKG_USING_LVGL + #define PKG_LVGL_THREAD_PRIO 5 + #define PKG_LVGL_THREAD_STACK_SIZE (1024*16)//4096 + #define PKG_LVGL_DISP_REFR_PERIOD 5 + #define PKG_LVGL_VER_NUM 0x99999 + #define PKG_USING_GUI_GUIDER_DEMO + #endif + +/*info config to spi flash*/ +#define PKG_DISP_UPDATE_REFR_PERIOD 100 + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_ACM32F403RET7 + +/* ACM32F403RET7 */ + +#define SOC_SRAM_START_ADDR 0x20008000 +#define SOC_SRAM_SIZE 320 +#define SOC_FLASH_START_ADDR 0x00000000 +#define SOC_FLASH_SIZE 0x8000 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +/* Hardware GPIO */ + +#define BSP_USING_GPIOA +#define BSP_USING_GPIOB +#define BSP_USING_GPIOC +#define BSP_USING_GPIOD +#define BSP_USING_GPIOE +#define BSP_USING_GPIOF +#define BSP_USING_GPIOG +#define BSP_USING_GPIOH + + +/* Hardware USART */ + +#define BSP_USING_UART1 +/* +#define BSP_USING_UART2 +#define BSP_UART2_RX_USING_DMA +#define BSP_UART2_TX_USING_DMA +#define BSP_USING_UART3 +#define BSP_UART3_RX_USING_DMA +#define BSP_UART3_TX_USING_DMA +#define BSP_USING_UART4 +#define BSP_UART4_RX_USING_DMA +#define BSP_UART4_TX_USING_DMA +*/ + +/* Hardware I2C */ + + +/* Hardware I2S */ + + +/* Hardware CAN */ + + +/* Hardware TIMER */ + + +/* Hardware LTDC */ + + +/* Hardware DMA2D */ + + +/* Hardware DCMI */ +//#define BSP_USING_DCMI +//#define BSP_USING_OV2640 + + +/* Hardware SDRAM */ +//#define BSP_USING_SDRAM1 + + +/* Hardware WDT */ + + +/* Hardware SPI */ + + +/* Hardware CRYPTO */ + + +/* Hardware memory operation using DMA, include memset() and memcpy() */ +#define RT_USING_HW_MEM_OPERATION + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/acm32/acm32h5xx-nucleo/rtconfig.py b/bsp/acm32/acm32h5xx-nucleo/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..55e06a0552513ad79be3cc58f5a7834c3eab5114 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/rtconfig.py @@ -0,0 +1,144 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'D:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = ' -xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c' + CFLAGS += ' -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__MICROLIB -mlittle-endian -ffunction-sections' + + AFLAGS = ' --cpu=Cortex-M33 --fpu=FPv5-SP --li --pd "__MICROLIB SETA 1" --pd "__UVISION_VERSION SETA 531" --pd "ARMCM33_DSP_FP SETA 1"' + + LFLAGS = ' --cpu=Cortex-M33 --info sizes --info totals --info unused --info veneers --list ./build/ACM32F4.map --scatter ./build/ACM32F4.sct' + LFLAGS += ' --library_type=microlib --strict' + LFLAGS += ' --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols' + + EXEC_PATH += '/ARM/ARMCLANG/bin' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-3 -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -gdwarf-3 -O1' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + CXXFLAGS = CFLAGS + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' diff --git a/bsp/acm32/acm32h5xx-nucleo/template.ewp b/bsp/acm32/acm32h5xx-nucleo/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..bbd1adf10c1e73a7fe9432505646c8602464b0d2 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/template.ewp @@ -0,0 +1,2074 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 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0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028 --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/template.uvoptx b/bsp/acm32/acm32h5xx-nucleo/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..6668d384aabf873760fe65333d8cf530f3526a9f --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/template.uvoptx @@ -0,0 +1,321 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ACM32F4XX + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + CMSIS_AGDI_V8M + -X"CMSIS-DAP AISINOCHIP V1.0" -UCMSIS-DAP AISINOCHIP V1.0 -O206 -S10 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000 + + + 0 + UL2V8M + -UV0VVV123 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000 + + + 0 + DLGTARM + (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + + + 0 + 0 + 69 + 1 +
10834
+ 0 + 0 + 0 + 0 + 0 + 1 + Z:\Aisinochip\rt-thread\bsp\RT_Thread_v3.13\bsp\uart.c + + \\ACM32F4\../RT_Thread_v3.13/bsp/uart.c\69 + + + 1 + 0 + 140 + 1 +
21958
+ 0 + 0 + 0 + 0 + 0 + 1 + Z:\Aisinochip\rt-thread\bsp\RT_Thread_v3.13\components\finsh\shell.c + + \\ACM32F4\../RT_Thread_v3.13/components/finsh/shell.c\140 + + + + + 0 + 1 + gu32_DataBackup + + + 1 + 1 + gu8_EncrptionData + + + 2 + 1 + lp32_Data + + + 3 + 1 + str_GPIOAB + + + 4 + 1 + str_SCU + + + 5 + 1 + gu32_GPIOCD + + + 6 + 1 + gu32_GPIOAB + + + 7 + 1 + gu8_TxBuffer + + + 8 + 1 + UART1_Handle + + + 9 + 1 + gu8_RxBuffer + + + 10 + 1 + DMA1 + + + 11 + 1 + gu32_APBClock,0x0A + + + 12 + 1 + gu32_SystemClock,0x0A + + + 13 + 1 + shell + + + + + 1 + 1 + shell + 0 + + + + + 2 + 1 + 0x40010800 + 0 + + + + + 3 + 1 + 0x10080800 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + diff --git a/bsp/acm32/acm32h5xx-nucleo/template.uvprojx b/bsp/acm32/acm32h5xx-nucleo/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..f7bcb794353fb99011b3bfee049f6ae14349f27d --- /dev/null +++ b/bsp/acm32/acm32h5xx-nucleo/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ACM32F4XX + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM33_DSP_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\ + ACM32F4XX + 1 + 0 + 1 + 1 + 1 + .\build\keil\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin --output ./build/ACM32F4.bin ./build/ACM32F4.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + +