| Tutorial
| Kernel
| Description
|
| Getting Started with RTL Kernels |
RTL |
This tutorial demonstrates how to use the Vitis core development kit to program an RTL kernel into an FPGA and build a Hardware Emulation using a common development flow. |
| Mixing C and RTL |
C and RTL |
This tutorial demonstrates working with an application containing RTL and OpenCL™ kernels to familiarize yourself with the Vitis core development kit flow, along with various design analysis features. |
| Host Code Optimization |
C and RTL |
This tutorial demonstrates applying host code optimization techniques to your design. |
| Using Multiple DDR Banks |
C and RTL |
This tutorial demonstrates how using multiple DDRs can improve data transfer between kernels and global memory. |
## Advanced
