From 748a47de10ac2941af21a4e3258419f73eb26a81 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Fri, 14 Jul 2023 08:33:59 +0800 Subject: [PATCH 01/12] arm64: Add MIDR encoding for Phytium CPUs This patch adds the MIDR encodings for Phytium FTC3xx/6xx CPUs. Signed-off-by: Wang Yinfeng Signed-off-by: Chen Baozi Change-Id: I952615535a288e796e70979cecddb5393f52fbdb Signed-off-by: liutianyu1250 --- arch/arm64/include/asm/cputype.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 8e3b6da741..b30c199cf7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -107,10 +107,15 @@ #define NVIDIA_CPU_PART_DENVER 0x003 #define NVIDIA_CPU_PART_CARMEL 0x004 -#define PHYTIUM_CPU_PART_FTC662 0x662 - #define HISI_CPU_PART_TSV110 0xD01 +#define PHYTIUM_CPU_PART_FTC310 0x660 +#define PHYTIUM_CPU_PART_FTC660 0x660 +#define PHYTIUM_CPU_PART_FTC661 0x661 +#define PHYTIUM_CPU_PART_FTC662 0x662 +#define PHYTIUM_CPU_PART_FTC663 0x663 +#define PHYTIUM_CPU_PART_FTC664 0x664 + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) @@ -139,7 +144,12 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_PHYTIUM_FTC310 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC310) +#define MIDR_PHYTIUM_FTC660 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC660) +#define MIDR_PHYTIUM_FTC661 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC661) #define MIDR_PHYTIUM_PS17064 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC662) +#define MIDR_PHYTIUM_FTC663 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC663) +#define MIDR_PHYTIUM_FTC664 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC664) #ifndef __ASSEMBLY__ -- Gitee From 0ad07902694f501bfc511ece2b9c5dd8b18390d4 Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Fri, 14 Jul 2023 08:33:59 +0800 Subject: [PATCH 02/12] arm64: kpti: Add Phytium FTC3xx/6xx CPU cores to kpti safelist Since Phytium FTC3xx/6xx CPU cores are all meltdown safe, add them to kpti_safe_list[]. Signed-off-by: Chen Baozi Change-Id: I8db79ef0b2513c8dfd9c5f7cbf03ceabb829da16 Signed-off-by: liutianyu1250 --- arch/arm64/kernel/cpufeature.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 787635e4ad..39f01261ed 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -928,6 +928,12 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC660), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC661), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_PS17064), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC663), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC664), { /* sentinel */ } }; char const *str = "kpti command line option"; -- Gitee From 2250d589ed3d27cfa19f62b3c39b717facf75a3b Mon Sep 17 00:00:00 2001 From: Chen Baozi Date: Fri, 14 Jul 2023 08:33:59 +0800 Subject: [PATCH 03/12] arm64: proton-pack: Add Phytium FTC310 CPU core to spectre-v2/v4 safelist FTC310 (LITTLE) CPUs are spectre-v2 and spectre-v4 safe, hence add them to the safe list. Signed-off-by: Chen Baozi Change-Id: I21b27be8d02d56f03792a0c7656b7d29437e3776 Signed-off-by: liutianyu1250 --- arch/arm64/kernel/cpu_errata.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index d0b7dd6086..3b4999e482 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -481,6 +481,7 @@ static const struct midr_range arm64_ssb_cpus[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), {}, }; @@ -580,6 +581,7 @@ static const struct midr_range spectre_v2_safe_list[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), { /* sentinel */ } }; -- Gitee From 889ddb0cfa9aa0ed6a4ec896dfce7ce5daec5fc4 Mon Sep 17 00:00:00 2001 From: Wang Yinfeng Date: Wed, 8 May 2024 14:25:03 +0800 Subject: [PATCH 04/12] arm/arm64: Bugfix the CPU MPIDR definition of phytium FTC303 core This patch Fixed MPIDR definition to 0x303 in phytium FTC303 series core. Mainline: Open-Source Signed-off-by: Wang Yinfeng Signed-off-by: Li Mingzhe Change-Id: I013783e6774661a67726a11ea09b0413b921017e Signed-off-by: liutianyu1250 --- arch/arm64/include/asm/cputype.h | 4 ++-- arch/arm64/kernel/cpu_errata.c | 4 ++-- arch/arm64/kernel/cpufeature.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index b30c199cf7..6ada8da330 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -109,7 +109,7 @@ #define HISI_CPU_PART_TSV110 0xD01 -#define PHYTIUM_CPU_PART_FTC310 0x660 +#define PHYTIUM_CPU_PART_FTC303 0x303 #define PHYTIUM_CPU_PART_FTC660 0x660 #define PHYTIUM_CPU_PART_FTC661 0x661 #define PHYTIUM_CPU_PART_FTC662 0x662 @@ -144,7 +144,7 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) -#define MIDR_PHYTIUM_FTC310 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC310) +#define MIDR_PHYTIUM_FTC303 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC303) #define MIDR_PHYTIUM_FTC660 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC660) #define MIDR_PHYTIUM_FTC661 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC661) #define MIDR_PHYTIUM_PS17064 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC662) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 3b4999e482..3f82c0ef0b 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -481,7 +481,7 @@ static const struct midr_range arm64_ssb_cpus[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), - MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC303), {}, }; @@ -581,7 +581,7 @@ static const struct midr_range spectre_v2_safe_list[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), - MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC303), { /* sentinel */ } }; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 39f01261ed..f64e1648f2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -928,7 +928,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), - MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC310), + MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC303), MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC660), MIDR_ALL_VERSIONS(MIDR_PHYTIUM_FTC661), MIDR_ALL_VERSIONS(MIDR_PHYTIUM_PS17064), -- Gitee From 6902d3d5c3456383c435c9eddf361affd48c25a3 Mon Sep 17 00:00:00 2001 From: liutianyu1250 Date: Tue, 23 Sep 2025 11:09:29 +0800 Subject: [PATCH 05/12] net: phy: motorcomm: imporve yt8521 read_status Add reset phydev->speed & duplex when not link. When link is down, ethtool will show: ... Speed: Unknown! Duplex: Unknown! (255) ... rather than the old speed & duplex info at link up. Signed-off-by: liutianyu1250 --- drivers/net/phy/motorcomm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c index 79ea717672..6bd0460398 100755 --- a/drivers/net/phy/motorcomm.c +++ b/drivers/net/phy/motorcomm.c @@ -1559,6 +1559,8 @@ static int yt8521_read_status(struct phy_device *phydev) ytxxxx_adjust_status(phydev, val_utp, 1); } else { link_utp = 0; + phydev->speed = SPEED_UNKNOWN; + phydev->duplex = DUPLEX_UNKNOWN; } if (link_utp) { -- Gitee From 1e22ecf5d9f22fd32f9a4ff857ea99f63a92b86d Mon Sep 17 00:00:00 2001 From: Huangjie Date: Wed, 17 Sep 2025 17:20:24 +0800 Subject: [PATCH 06/12] drivers: edac/phytium: add support for pd2208 Signed-off-by: Huangjie --- drivers/edac/phytium_edac.c | 243 ++++++++++++++++++++++++++++++++---- 1 file changed, 221 insertions(+), 22 deletions(-) diff --git a/drivers/edac/phytium_edac.c b/drivers/edac/phytium_edac.c index df38935ac9..c37bfeb00f 100644 --- a/drivers/edac/phytium_edac.c +++ b/drivers/edac/phytium_edac.c @@ -14,6 +14,8 @@ #include #include #include "edac_module.h" +#include +#include #define EDAC_MOD_STR "phytium_edac" @@ -36,21 +38,21 @@ #define CORRECTED_ERROR 0 #define UNCORRECTED_ERROR 1 -#define MAX_ERR_GROUP 3 +#define EDAC_DRIVER_VERSION "1.1.2" -#define EDAC_DRIVER_VERSION "1.1.1" +struct ras_error_info { + u32 index; + u32 error_type; + const char *error_str; +}; struct phytium_edac { struct device *dev; void __iomem **ras_base; struct dentry *dfs; struct edac_device_ctl_info *edac_dev; -}; - -struct ras_error_info { - u32 index; - u32 error_type; - const char *error_str; + int num_err_group; + const struct ras_error_info **error_info; }; /* error severity definition */ @@ -128,8 +130,182 @@ static const struct ras_error_info pe220x_ras_peu_error[] = { { 5, CORRECTED_ERROR, "axi_r_rsp_error" }, }; +/* pd2208 error */ +static const struct ras_error_info pd2208_ras_err[] = { + {0, CORRECTED_ERROR, "lmu0_ras_ecc_corrected_err"}, + {1, UNCORRECTED_ERROR, "lmu0_ras_ecc_uncorrected_err"}, + {2, CORRECTED_ERROR, "lmu1_ras_ecc_corrected_err"}, + {3, UNCORRECTED_ERROR, "lmu1_ras_ecc_uncorrected_err"}, + {4, CORRECTED_ERROR, "sram_corrected_err"}, + {5, UNCORRECTED_ERROR, "sram_uncorrected_err"}, + {6, UNCORRECTED_ERROR, "qspi_ras_addr_err"}, + {7, UNCORRECTED_ERROR, "qspi_ras_pstrb_err"}, + {8, UNCORRECTED_ERROR, "intreq_err"}, + {9, UNCORRECTED_ERROR, "gic_axim_err"}, + {10, UNCORRECTED_ERROR, "gic_ecc_fatal"}, + {11, UNCORRECTED_ERROR, "lsd_lbc_ras_err"}, + {12, UNCORRECTED_ERROR, "nEXTERRIRQ_cluster0"}, + {13, UNCORRECTED_ERROR, "nINTERRIRQ_cluster0"}, + {14, UNCORRECTED_ERROR, "nEXTERRIRQ_cluster1"}, + {15, UNCORRECTED_ERROR, "nINTERRIRQ_cluster1"}, + {16, UNCORRECTED_ERROR, "nEXTERRIRQ_cluster2"}, + {17, UNCORRECTED_ERROR, "nINTERRIRQ_cluster2"}, + {18, UNCORRECTED_ERROR, "nEXTERRIRQ_cluster3"}, + {19, UNCORRECTED_ERROR, "nINTERRIRQ_cluster3"}, + {20, CORRECTED_ERROR, "lbc_ecc_corrected_err"}, + {21, UNCORRECTED_ERROR, "lbc_ecc_uncorrected_err"}, +}; + +static const struct ras_error_info pd2208_ras_sram_err[] = { + {0, CORRECTED_ERROR, "scp_sram_corrected_err"}, + {1, UNCORRECTED_ERROR, "scp_sram_uncorrected_err"}, + {2, CORRECTED_ERROR, "scp_sharemem_corrected_err"}, + {3, UNCORRECTED_ERROR, "scp_sharemem_uncorrected_err"}, + {4, CORRECTED_ERROR, "wr_cmd_buf_corrected_err"}, + {5, UNCORRECTED_ERROR, "wr_cmd_buf_uncorrected_err"}, + {6, CORRECTED_ERROR, "rd_dat_buf_corrected_err"}, + {7, UNCORRECTED_ERROR, "rd_dat_buf_uncorrected_err"}, + {8, CORRECTED_ERROR, "wr_cmd_buf_corrected_err"}, + {9, UNCORRECTED_ERROR, "wr_cmd_buf_uncorrected_err"}, + {10, CORRECTED_ERROR, "wr_dat_buf_corrected_err"}, + {11, UNCORRECTED_ERROR, "wr_dat_buf_uncorrected_err"}, + {12, CORRECTED_ERROR, "drtrch0_corrected_err"}, + {13, UNCORRECTED_ERROR, "drtrch0_uncorrected_err"}, + {14, CORRECTED_ERROR, "drtrch0_corrected_err"}, + {15, UNCORRECTED_ERROR, "drtrch0_uncorrected_err"}, + {16, CORRECTED_ERROR, "dmac_corrected_err"}, + {17, UNCORRECTED_ERROR, "dmac_uncorrected_err"}, + {18, CORRECTED_ERROR, "rmram0_corrected_err"}, + {19, UNCORRECTED_ERROR, "rmram0_uncorrected_err"}, + {20, CORRECTED_ERROR, "rmram1_corrected_err"}, + {21, UNCORRECTED_ERROR, "rmram1_uncorrected_err"}, + {22, CORRECTED_ERROR, "rmram2_corrected_err"}, + {23, UNCORRECTED_ERROR, "rmram2_uncorrected_err"}, + {24, CORRECTED_ERROR, "rmram3_corrected_err"}, + {25, UNCORRECTED_ERROR, "rmram3_uncorrected_err"}, + {26, CORRECTED_ERROR, "gmactx0_corrected_err"}, + {27, UNCORRECTED_ERROR, "gmactx0_uncorrected_err"}, + {28, CORRECTED_ERROR, "gmactx1_corrected_err"}, + {29, UNCORRECTED_ERROR, "gmactx1_uncorrected_err"}, + {30, CORRECTED_ERROR, "gmactx2_corrected_err"}, + {31, UNCORRECTED_ERROR, "gmactx2_uncorrected_err"}, + {32, CORRECTED_ERROR, "gmactx3_corrected_err"}, + {33, UNCORRECTED_ERROR, "gmactx3_uncorrected_err"}, +}; + +static const struct ras_error_info pd2208_ras_peu_sram0_err[] = { + {0, CORRECTED_ERROR, "c0p2a_corrected_err"}, + {1, UNCORRECTED_ERROR, "c0p2a_uncorrected_err"}, + {2, CORRECTED_ERROR, "c0a2p_corrected_err"}, + {3, UNCORRECTED_ERROR, "c0a2p_uncorrected_err"}, + {4, CORRECTED_ERROR, "c0rxbuf0_corrected_err"}, + {5, UNCORRECTED_ERROR, "c0rxbuf0_uncorrected_err"}, + {6, CORRECTED_ERROR, "c0rxbuf1_corrected_err"}, + {7, UNCORRECTED_ERROR, "c0rxbuf1 _uncorrected_err"}, + {8, CORRECTED_ERROR, "c0rxbuf2_corrected_err"}, + {9, UNCORRECTED_ERROR, "c0rxbuf2 _uncorrected_err"}, + {10, CORRECTED_ERROR, "c0rxbuf3_corrected_err"}, + {11, UNCORRECTED_ERROR, "c0rxbuf3 _uncorrected_err"}, + {12, CORRECTED_ERROR, "c0txbuf0_corrected_err"}, + {13, UNCORRECTED_ERROR, "c0txbuf0_uncorrected_err"}, + {14, CORRECTED_ERROR, "c0txbuf1_corrected_err"}, + {15, UNCORRECTED_ERROR, "c0txbuf1 _uncorrected_err"}, + {16, CORRECTED_ERROR, "c0txbuf2_corrected_err"}, + {17, UNCORRECTED_ERROR, "c0txbuf2 _uncorrected_err"}, + {18, CORRECTED_ERROR, "c0txbuf3_corrected_err"}, + {19, UNCORRECTED_ERROR, "c0txbuf3 _uncorrected_err"}, + {20, CORRECTED_ERROR, "c1p2a_corrected_err"}, + {21, UNCORRECTED_ERROR, "c1p2a_uncorrected_err"}, + {22, CORRECTED_ERROR, "c1a2p_corrected_err"}, + {23, UNCORRECTED_ERROR, "c1a2p_uncorrected_err"}, + {24, CORRECTED_ERROR, "c1rxbuf0_corrected_err"}, + {25, UNCORRECTED_ERROR, "c1rxbuf0_uncorrected_err"}, + {26, CORRECTED_ERROR, "c1rxbuf1_corrected_err"}, + {27, UNCORRECTED_ERROR, "c1rxbuf1 _uncorrected_err"}, + {28, CORRECTED_ERROR, "c1rxbuf2_corrected_err"}, + {29, UNCORRECTED_ERROR, "c1rxbuf2 _uncorrected_err"}, + {30, CORRECTED_ERROR, "c1rxbuf3_corrected_err"}, + {31, UNCORRECTED_ERROR, "c1rxbuf3 _uncorrected_err"}, + {32, CORRECTED_ERROR, "c1txbuf0_corrected_err"}, + {33, UNCORRECTED_ERROR, "c1txbuf0_uncorrected_err"}, + {34, CORRECTED_ERROR, "c1txbuf1_corrected_err"}, + {35, UNCORRECTED_ERROR, "c1txbuf1 _uncorrected_err"}, + {36, CORRECTED_ERROR, "c1txbuf2_corrected_err"}, + {37, UNCORRECTED_ERROR, "c1txbuf2 _uncorrected_err"}, + {38, CORRECTED_ERROR, "c1txbuf3_corrected_err"}, + {39, UNCORRECTED_ERROR, "c1txbuf3 _uncorrected_err"}, + {40, CORRECTED_ERROR, "c2p2a_corrected_err"}, + {41, UNCORRECTED_ERROR, "c2p2a_uncorrected_err"}, + {42, CORRECTED_ERROR, "c2a2p_corrected_err"}, + {43, UNCORRECTED_ERROR, "c2a2p_uncorrected_err"}, + {44, CORRECTED_ERROR, "c2rxbuf0_corrected_err"}, + {45, UNCORRECTED_ERROR, "c2rxbuf0_uncorrected_err"}, + {46, CORRECTED_ERROR, "c2rxbuf1_corrected_err"}, + {47, UNCORRECTED_ERROR, "c2rxbuf1 _uncorrected_err"}, + {48, CORRECTED_ERROR, "c2rxbuf2_corrected_err"}, + {49, UNCORRECTED_ERROR, "c2rxbuf2 _uncorrected_err"}, + {50, CORRECTED_ERROR, "c2rxbuf3_corrected_err"}, + {51, UNCORRECTED_ERROR, "c2rxbuf3 _uncorrected_err"}, + {52, CORRECTED_ERROR, "c2txbuf0_corrected_err"}, + {53, UNCORRECTED_ERROR, "c2txbuf0_uncorrected_err"}, + {54, CORRECTED_ERROR, "c2txbuf1_corrected_err"}, + {55, UNCORRECTED_ERROR, "c2txbuf1 _uncorrected_err"}, +}; + +static const struct ras_error_info pd2208_ras_peu_sram1_err[] = { + {0, CORRECTED_ERROR, "c2txbuf2_corrected_err"}, + {1, UNCORRECTED_ERROR, "c2txbuf2_uncorrected_err"}, + {2, CORRECTED_ERROR, "c2txbuf3_corrected_err"}, + {3, UNCORRECTED_ERROR, "c2txbuf3_uncorrected_err"}, + {4, CORRECTED_ERROR, "phy0_sram0_corrected_err"}, + {5, UNCORRECTED_ERROR, "phy0_sram0_uncorrected_err"}, + {6, CORRECTED_ERROR, "phy0_sram1_corrected_err"}, + {7, UNCORRECTED_ERROR, "phy0_sram1 _uncorrected_err"}, + {8, CORRECTED_ERROR, "phy0_sram2_corrected_err"}, + {9, UNCORRECTED_ERROR, "phy0_sram2 _uncorrected_err"}, + {10, CORRECTED_ERROR, "phy0_sram3_corrected_err"}, + {11, UNCORRECTED_ERROR, "phy0_sram3 _uncorrected_err"}, + {12, CORRECTED_ERROR, "phy1_sram0_corrected_err"}, + {13, UNCORRECTED_ERROR, "phy1_sram0_uncorrected_err"}, + {14, CORRECTED_ERROR, "mac0_rxdpram_corrected_err"}, + {15, UNCORRECTED_ERROR, "mac0_rxdpram _uncorrected_err"}, + {16, CORRECTED_ERROR, "mac0_txdpram_corrected_err"}, + {17, UNCORRECTED_ERROR, "mac0_txdpram _uncorrected_err"}, + {18, CORRECTED_ERROR, "mac1_rxdpram_corrected_err"}, + {19, UNCORRECTED_ERROR, "mac1_rxdpram _uncorrected_err"}, + {20, CORRECTED_ERROR, "mac1_txdpram_corrected_err"}, + {21, UNCORRECTED_ERROR, "mac1_txdpram _uncorrected_err"}, +}; + +static const struct ras_error_info pd2208_ras_peu_base_err[] = { + {0, UNCORRECTED_ERROR, "pio_rd_addr_error"}, + {1, UNCORRECTED_ERROR, "pio_rd_timeout"}, + {2, UNCORRECTED_ERROR, "pio_wr_addr_error"}, + {3, UNCORRECTED_ERROR, "pio_wr_timeout"}, + {4, CORRECTED_ERROR, "axi_b_rsp_error"}, + {5, UNCORRECTED_ERROR, "axi_r_rsp_error"}, + {6, UNCORRECTED_ERROR, "mac0_asf_trans_to_err"}, + {7, UNCORRECTED_ERROR, "mac0_asf_protocol_err"}, + {8, UNCORRECTED_ERROR, "mac0_asf_nonfatal_int"}, + {9, UNCORRECTED_ERROR, "mac0_asf_fatal_int"}, + {10, UNCORRECTED_ERROR, "mac1_asf_trans_to_err"}, + {11, UNCORRECTED_ERROR, "mac1_asf_protocol_err"}, + {12, UNCORRECTED_ERROR, "mac1_asf_nonfatal_int"}, + {13, UNCORRECTED_ERROR, "mac1_asf_fatal_int"}, +}; + static const struct ras_error_info *pe220x_ras_error[] = { - pe220x_ras_soc_error, pe220x_ras_peu_psu_error, pe220x_ras_peu_error + pe220x_ras_soc_error, + pe220x_ras_peu_psu_error, + pe220x_ras_peu_error, +}; + +static const struct ras_error_info *pd2208_ras_error[] = { + pd2208_ras_err, + pd2208_ras_sram_err, + pd2208_ras_peu_sram0_err, + pd2208_ras_peu_sram1_err, + pd2208_ras_peu_base_err, }; static inline unsigned int get_error_num(const struct phytium_edac *edac, @@ -146,11 +322,11 @@ static inline void phytium_ras_setup(const struct phytium_edac *edac) { u64 val = 0; unsigned int i = 0; + /* * enable error report and generate interrupt for corrected error event - * first error record owned by node present the node configuration */ - for (i = 0; i < MAX_ERR_GROUP; i++) { + for (i = 0; i < edac->num_err_group; i++) { val = readq(edac->ras_base[i] + ERR_CTLR(0)); val |= CTLR_ED | CTLR_UI | CTLR_CFI; writeq(val, edac->ras_base[i] + ERR_CTLR(0)); @@ -190,7 +366,7 @@ static ssize_t phytium_edac_inject_ctrl_write(struct file *filp, goto out; res = kstrtouint(tmp, 0, &error_group); - if (res || error_group >= MAX_ERR_GROUP) { + if (res || error_group >= edac->num_err_group) { dev_err(edac->dev, "invalid error group parameters"); goto out; } @@ -207,11 +383,11 @@ static ssize_t phytium_edac_inject_ctrl_write(struct file *filp, goto out; } - dev_dbg(edac->dev, "inject group%d, error_id: %d\n", + dev_dbg(edac->dev, "inject group: %d, error_id: %d\n", error_group, error_id); - if (pe220x_ras_error[error_group][error_id].error_type == - CORRECTED_ERROR) { + if (edac->error_info[error_group][error_id].error_type + == CORRECTED_ERROR) { writeq(MISC0_CEC(0xFF), edac->ras_base[error_group] + ERR_MISC0(error_id)); } @@ -295,7 +471,7 @@ static int get_error_id(struct phytium_edac *edac, int *error_id, int err_id = 0; /* Iterate over the ras node to check error status */ - for (i = 0; i < MAX_ERR_GROUP; i++) { + for (i = 0; i < edac->num_err_group; i++) { error_num = get_error_num(edac, i); error_bit = readq(edac->ras_base[i] + ERR_GSR); for (err_id = 0; err_id < error_num; err_id++) { @@ -311,7 +487,7 @@ static int get_error_id(struct phytium_edac *edac, int *error_id, } } - if (i >= MAX_ERR_GROUP) { + if (i >= edac->num_err_group) { ret = -1; dev_warn(edac->dev, "no error detect.\n"); } @@ -324,7 +500,7 @@ static void phytium_edac_error_report(struct phytium_edac *edac, const int error_group) { const struct ras_error_info *err_info = - pe220x_ras_error[error_group]; + edac->error_info[error_group]; if (err_info[error_id].error_type == UNCORRECTED_ERROR) { edac_printk(KERN_CRIT, EDAC_MOD_STR, "uncorrected error: %s\n", @@ -382,6 +558,17 @@ static irqreturn_t phytium_edac_isr(int irq, void *dev_id) return IRQ_HANDLED; } +static inline int of_address_count(struct device_node *np) +{ + struct resource res; + int count = 0; + + while (of_address_to_resource(np, count, &res) == 0) + count++; + + return count; +} + static int phytium_edac_probe(struct platform_device *pdev) { struct phytium_edac *edac; @@ -400,14 +587,23 @@ static int phytium_edac_probe(struct platform_device *pdev) edac->dev = &pdev->dev; platform_set_drvdata(pdev, edac); - edac->ras_base = devm_kcalloc(&pdev->dev, 3, - sizeof(*edac->ras_base), GFP_KERNEL); + edac->error_info = + (const struct ras_error_info **)of_device_get_match_data(&pdev->dev); + + edac->num_err_group = of_address_count(pdev->dev.of_node); + if (edac->num_err_group <= 0) { + dev_err(&pdev->dev, "can't get error group count"); + goto out; + } + + edac->ras_base = devm_kcalloc(&pdev->dev, edac->num_err_group, + sizeof(*edac->ras_base), GFP_KERNEL); if (!edac->ras_base) { return -ENOMEM; goto out; } - for (i = 0; i < MAX_ERR_GROUP; i++) { + for (i = 0; i < edac->num_err_group; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); edac->ras_base[i] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(edac->ras_base[i])) { @@ -465,7 +661,10 @@ static int phytium_edac_remove(struct platform_device *pdev) } static const struct of_device_id phytium_edac_of_match[] = { - { .compatible = "phytium,pe220x-edac" }, + { .compatible = "phytium,pe220x-edac", + .data = pe220x_ras_error }, + { .compatible = "phytium,pd2208-edac", + .data = pd2208_ras_error }, {}, }; MODULE_DEVICE_TABLE(of, phytium_edac_of_match); -- Gitee From 8be31160a5828ef28bf32ce7ec3f1288e584075a Mon Sep 17 00:00:00 2001 From: zuoqian Date: Sun, 28 Sep 2025 14:38:21 +0800 Subject: [PATCH 07/12] net: phytmac: fix fixed-link link down ethtool status Add reset pdata->speed & duplex when not link in fixed-link mode. When link is down, ethtool will show: ... Speed: Unknown! Duplex: Unknown! (255) ... rather than the old speed & duplex info at link up. Signed-off-by: zuoqian --- drivers/net/ethernet/phytium/phytmac_ethtool.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/phytium/phytmac_ethtool.c b/drivers/net/ethernet/phytium/phytmac_ethtool.c index b3f61d4808..bd37392a87 100644 --- a/drivers/net/ethernet/phytium/phytmac_ethtool.c +++ b/drivers/net/ethernet/phytium/phytmac_ethtool.c @@ -381,8 +381,13 @@ static int phytmac_get_link_ksettings(struct net_device *ndev, if (!ndev->phydev) { kset->base.port = PORT_FIBRE; kset->base.transceiver = XCVR_INTERNAL; - kset->base.duplex = pdata->duplex; - kset->base.speed = pdata->speed; + if (netif_carrier_ok(ndev)) { + kset->base.duplex = pdata->duplex; + kset->base.speed = pdata->speed; + } else { + kset->base.duplex = DUPLEX_UNKNOWN; + kset->base.speed = SPEED_UNKNOWN; + } if (pdata->phy_interface == PHY_INTERFACE_MODE_USXGMII) { supported = SUPPORTED_10000baseT_Full -- Gitee From f9774cc88aba9eb0c214163af0c93ff4a7393d44 Mon Sep 17 00:00:00 2001 From: zuoqian Date: Mon, 29 Sep 2025 14:32:09 +0800 Subject: [PATCH 08/12] arm64: phytium_defconfig: select REALTEK_PHY as Y Signed-off-by: zuoqian --- arch/arm64/configs/phytium_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/phytium_defconfig b/arch/arm64/configs/phytium_defconfig index 4589a28aed..81ecc6a195 100644 --- a/arch/arm64/configs/phytium_defconfig +++ b/arch/arm64/configs/phytium_defconfig @@ -249,7 +249,7 @@ CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m CONFIG_MICREL_PHY=y CONFIG_MOTORCOMM_PHY=y -CONFIG_REALTEK_PHY=m +CONFIG_REALTEK_PHY=y CONFIG_PPP=y CONFIG_PPP_DEFLATE=y CONFIG_PPP_ASYNC=y -- Gitee From 238305dcfc99be8bff58dbf94270c9d0b5704f58 Mon Sep 17 00:00:00 2001 From: Huangjie Date: Thu, 16 Oct 2025 15:58:28 +0800 Subject: [PATCH 09/12] drivers: edac/phytium: ignore pe220x soc_err 40~43 soc_err 40-43 is for debug not open for user Signed-off-by: Huangjie --- drivers/edac/phytium_edac.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/edac/phytium_edac.c b/drivers/edac/phytium_edac.c index c37bfeb00f..060dc46b34 100644 --- a/drivers/edac/phytium_edac.c +++ b/drivers/edac/phytium_edac.c @@ -190,7 +190,7 @@ static const struct ras_error_info pd2208_ras_sram_err[] = { {30, CORRECTED_ERROR, "gmactx2_corrected_err"}, {31, UNCORRECTED_ERROR, "gmactx2_uncorrected_err"}, {32, CORRECTED_ERROR, "gmactx3_corrected_err"}, - {33, UNCORRECTED_ERROR, "gmactx3_uncorrected_err"}, + {33, UNCORRECTED_ERROR, "gmactx3_uncorrected_err"}, }; static const struct ras_error_info pd2208_ras_peu_sram0_err[] = { @@ -502,6 +502,11 @@ static void phytium_edac_error_report(struct phytium_edac *edac, const struct ras_error_info *err_info = edac->error_info[error_group]; + /* ignore pe220x soc_err id 40~43 */ + if ((err_info == pe220x_ras_soc_error) && + (error_id >= 40) && (error_id <= 43)) + return; + if (err_info[error_id].error_type == UNCORRECTED_ERROR) { edac_printk(KERN_CRIT, EDAC_MOD_STR, "uncorrected error: %s\n", err_info[error_id].error_str); -- Gitee From 707e659f2ff451732b1d24ce9fa1eaf2c6716894 Mon Sep 17 00:00:00 2001 From: zuoqian Date: Thu, 16 Oct 2025 17:26:01 +0800 Subject: [PATCH 10/12] net: phytmac: support ipv6 TSO Signed-off-by: zuoqian --- drivers/net/ethernet/phytium/phytmac_main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/phytium/phytmac_main.c b/drivers/net/ethernet/phytium/phytmac_main.c index 49f7ba5816..b8c715dbaa 100644 --- a/drivers/net/ethernet/phytium/phytmac_main.c +++ b/drivers/net/ethernet/phytium/phytmac_main.c @@ -2302,7 +2302,7 @@ static netdev_features_t phytmac_features_check(struct sk_buff *skb, hdrlen = skb_transport_offset(skb); if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, PHYTMAC_TX_LEN_ALIGN)) - return features & ~NETIF_F_TSO; + return features & ~(NETIF_F_TSO | NETIF_F_TSO6); nr_frags = skb_shinfo(skb)->nr_frags; /* No need to check last fragment */ @@ -2311,7 +2311,7 @@ static netdev_features_t phytmac_features_check(struct sk_buff *skb, const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; if (!IS_ALIGNED(skb_frag_size(frag), PHYTMAC_TX_LEN_ALIGN)) - return features & ~NETIF_F_TSO; + return features & ~(NETIF_F_TSO | NETIF_F_TSO6); } return features; } @@ -2603,7 +2603,7 @@ void phytmac_default_config(struct phytmac *pdata) ndev->hw_features = NETIF_F_SG; if (pdata->capacities & PHYTMAC_CAPS_LSO) - ndev->hw_features |= NETIF_F_TSO; + ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; if (pdata->use_ncsi) { ndev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM); -- Gitee From 6f9a562683de5ba7f781b391abe431f9092de090 Mon Sep 17 00:00:00 2001 From: zuoqian Date: Fri, 17 Oct 2025 17:17:42 +0800 Subject: [PATCH 11/12] net: macb: support ipv6 TSO Signed-off-by: zuoqian --- drivers/net/ethernet/cadence/macb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index bcaab7f552..1d9318da02 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -78,7 +78,7 @@ #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0) #define GEM_MTU_MIN_SIZE ETH_MIN_MTU -#define MACB_NETIF_LSO NETIF_F_TSO +#define MACB_NETIF_LSO (NETIF_F_TSO | NETIF_F_TSO6) #define HS_SPEED_100M 0 #define HS_SPEED_1000M 1 -- Gitee From 181bd6bbe2ea5d8f0ac0dd03bf962c3ce18010ff Mon Sep 17 00:00:00 2001 From: liutianyu1250 Date: Tue, 21 Oct 2025 14:05:13 +0800 Subject: [PATCH 12/12] arm64: phytium_defconfig: default enable CIFS Signed-off-by: liutianyu1250 --- arch/arm64/configs/phytium_defconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/configs/phytium_defconfig b/arch/arm64/configs/phytium_defconfig index 81ecc6a195..bfd9785ca3 100644 --- a/arch/arm64/configs/phytium_defconfig +++ b/arch/arm64/configs/phytium_defconfig @@ -567,15 +567,14 @@ CONFIG_NFSD_SCSILAYOUT=y CONFIG_NFSD_FLEXFILELAYOUT=y CONFIG_NFSD_V4_SECURITY_LABEL=y CONFIG_NFSD_FAULT_INJECTION=y +CONFIG_CIFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y CONFIG_CRYPTO_USER=y CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DRBG_HASH=y CONFIG_CRYPTO_USER_API_HASH=y -- Gitee