From 6d386eebd232eab8f46adfe9a54fea405a7ab777 Mon Sep 17 00:00:00 2001 From: taolan Date: Mon, 28 Nov 2022 20:20:02 +0000 Subject: [PATCH 1/5] hix5hd2: Add I2C_M_STOP flag support for hix5hd2 driver. driver inclusion category: bugfix bugzilla: -------------------------------------------------------- For compatibility, some devices need to work with controller between messages using a stop. Signed-off-by: taolan --- drivers/i2c/busses/i2c-hix5hd2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-hix5hd2.c b/drivers/i2c/busses/i2c-hix5hd2.c index 8993534bc510..eafe55a86f95 100644 --- a/drivers/i2c/busses/i2c-hix5hd2.c +++ b/drivers/i2c/busses/i2c-hix5hd2.c @@ -360,7 +360,11 @@ static int hix5hd2_i2c_xfer(struct i2c_adapter *adap, pm_runtime_get_sync(priv->dev); for (i = 0; i < num; i++, msgs++) { - stop = (i == num - 1); + if ((i == num - 1) || (msgs->flags & I2C_M_STOP)) + stop = 1; + else + stop = 0; + ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop); if (ret < 0) goto out; -- Gitee From 9ba16b35c64372c9c266850471570a55ec3a9fe2 Mon Sep 17 00:00:00 2001 From: taolan Date: Mon, 28 Nov 2022 20:20:04 +0000 Subject: [PATCH 2/5] module: add hi3516dv300 clk driver driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5XHIQ ----------------------------------------------------------- Add clk driver support to series socs including 3516dv300,3519av100,etc. Signed-off-by: taolan --- drivers/clk/hisilicon/Kconfig | 194 +++++- drivers/clk/hisilicon/Makefile | 1 + drivers/clk/hisilicon/clk-hi3516dv300.c | 269 +++++++++ drivers/clk/hisilicon/clk-hi3519av100.c | 559 ++++++++++++++++++ drivers/clk/hisilicon/clk-hisi-phase.c | 2 +- drivers/clk/hisilicon/clk.c | 4 + drivers/clk/hisilicon/crg-hi3516cv300.c | 4 +- drivers/clk/hisilicon/crg-hi3798cv200.c | 4 +- drivers/clk/hisilicon/crg.h | 2 +- drivers/clk/hisilicon/reset.c | 30 + drivers/clk/hisilicon/reset.h | 3 + include/dt-bindings/clock/hi3516dv300-clock.h | 100 ++++ 12 files changed, 1165 insertions(+), 7 deletions(-) create mode 100644 drivers/clk/hisilicon/clk-hi3516dv300.c create mode 100644 drivers/clk/hisilicon/clk-hi3519av100.c create mode 100644 include/dt-bindings/clock/hi3516dv300-clock.h diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index 6a9e93a0bb95..4d212e5a193a 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -22,6 +22,38 @@ config COMMON_CLK_HI3660 help Build the clock driver for hi3660. +config COMMON_CLK_HI3531DV200 + tristate "Hi3531DV200 Clock Driver" + depends on ARCH_HI3531DV200 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for Hi3531DV200. + +config COMMON_CLK_HI3535AV100 + tristate "Hi3535AV100 Clock Driver" + depends on ARCH_HI3535AV100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for Hi3535AV100. + +config COMMON_CLK_HI3521DV200 + tristate "Hi3521DV200 Clock Driver" + depends on ARCH_HI3521DV200 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3521DV200. + +config COMMON_CLK_HI3520DV500 + tristate "Hi3520DV500 Clock Driver" + depends on ARCH_HI3520DV500 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3520DV500. + config COMMON_CLK_HI3670 bool "Hi3670 Clock Driver" depends on ARCH_HISI || COMPILE_TEST @@ -37,6 +69,166 @@ config COMMON_CLK_HI3798CV200 help Build the clock driver for hi3798cv200. +config COMMON_CLK_HI3516A + tristate "Hi3516A Clock Driver" + depends on ARCH_HI3516A || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3516A. + +config COMMON_CLK_HI3516CV500 + tristate "Hi3516CV500 Clock Driver" + depends on ARCH_HI3516CV500 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3516CV500. + +config COMMON_CLK_HI3516EV200 + tristate "Hi3516EV200 Clock Driver" + depends on ARCH_HI3516EV200 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3516EV200. + +config COMMON_CLK_HI3516EV300 + tristate "Hi3516EV300 Clock Driver" + depends on ARCH_HI3516EV300 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3516EV300. + +config COMMON_CLK_HI3518EV300 + tristate "Hi3518EV300 Clock Driver" + depends on ARCH_HI3518EV300 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3518EV300. + +config COMMON_CLK_HI3516DV200 + tristate "Hi3516DV200 Clock Driver" + depends on ARCH_HI3516DV200 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3516DV200. + +config COMMON_CLK_HI3516DV300 + tristate "Hi3516DV300 Clock Driver" + depends on ARCH_HI3516DV300 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3516DV300. + +config COMMON_CLK_HI3556V200 + tristate "Hi3556V200 Clock Driver" + depends on ARCH_HI3556V200 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3556V200. + +config COMMON_CLK_HI3559V200 + tristate "Hi3559V200 Clock Driver" + depends on ARCH_HI3559V200 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3559V200. + +config COMMON_CLK_HI3562V100 + tristate "Hi3562V100 Clock Driver" + depends on ARCH_HI3562V100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3562V100. + +config COMMON_CLK_HI3566V100 + tristate "Hi3566V100 Clock Driver" + depends on ARCH_HI3566V100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3566V100. + +config COMMON_CLK_HI3518EV20X + tristate "Hi3518EV20X Clock Driver" + depends on ARCH_HI3518EV20X || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3516A. + +config COMMON_CLK_HI3536DV100 + tristate "Hi3536DV100 Clock Driver" + depends on ARCH_HI3536DV100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3536DV100. + +config COMMON_CLK_HI3559AV100 + tristate "Hi3559AV100 Clock Driver" + depends on ARCH_HI3559AV100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3559av100. + +config COMMON_CLK_HI3569V100 + tristate "Hi3569V100 Clock Driver" + depends on ARCH_HI3569V100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3569v100. + +config COMMON_CLK_HI3521A + tristate "Hi3521A Clock Driver" + depends on ARCH_HI3521A || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3521A. + +config COMMON_CLK_HI3531A + tristate "Hi3531A Clock Driver" + depends on ARCH_HI3531A || COMPILE_TEST + select RESET_HISI + default ARCH_HISI_BVT + help + Build the clock driver for hi3531A. + +config COMMON_CLK_HI3556AV100 + tristate "Hi3556AV100 Clock Driver" + depends on ARCH_HI3556AV100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3556av100. + +config COMMON_CLK_HI3519AV100 + tristate "Hi3519AV100 Clock Driver" + depends on ARCH_HI3519AV100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3519av100. + +config COMMON_CLK_HI3568V100 + tristate "Hi3568V100 Clock Driver" + depends on ARCH_HI3568V100 || COMPILE_TEST + select RESET_HISI + default ARCH_HISI + help + Build the clock driver for hi3568v100. + config COMMON_CLK_HI6220 bool "Hi6220 Clock Driver" depends on ARCH_HISI || COMPILE_TEST @@ -46,7 +238,7 @@ config COMMON_CLK_HI6220 config RESET_HISI bool "HiSilicon Reset Controller Driver" - depends on ARCH_HISI || COMPILE_TEST + depends on ARCH_HISI || COMPILE_TEST || ARCH_HISI_BVT select RESET_CONTROLLER help Build reset controller driver for HiSilicon device chipsets. diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index b2441b99f3d5..91dc23fdb9c3 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o +obj-$(CONFIG_COMMON_CLK_HI3516DV300) += clk-hi3516dv300.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o diff --git a/drivers/clk/hisilicon/clk-hi3516dv300.c b/drivers/clk/hisilicon/clk-hi3516dv300.c new file mode 100644 index 000000000000..5ecb34abb2df --- /dev/null +++ b/drivers/clk/hisilicon/clk-hi3516dv300.c @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include +#include "clk.h" +#include "crg.h" +#include "reset.h" + +static struct hisi_fixed_rate_clock hi3516dv300_fixed_rate_clks[] __initdata = { + { HI3516DV300_FIXED_3M, "3m", NULL, 0, 3000000, }, + { HI3516DV300_FIXED_6M, "6m", NULL, 0, 6000000, }, + { HI3516DV300_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3516DV300_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3516DV300_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3516DV300_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3516DV300_FIXED_54M, "54m", NULL, 0, 54000000, }, + { HI3516DV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, }, + { HI3516DV300_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3516DV300_FIXED_125M, "125m", NULL, 0, 125000000, }, + { HI3516DV300_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3516DV300_FIXED_163M, "163m", NULL, 0, 163000000, }, + { HI3516DV300_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3516DV300_FIXED_250M, "250m", NULL, 0, 250000000, }, + { HI3516DV300_FIXED_257M, "257m", NULL, 0, 257000000, }, + { HI3516DV300_FIXED_300M, "300m", NULL, 0, 300000000, }, + { HI3516DV300_FIXED_324M, "324m", NULL, 0, 324000000, }, + { HI3516DV300_FIXED_342M, "342m", NULL, 0, 342000000, }, + { HI3516DV300_FIXED_342M, "375m", NULL, 0, 375000000, }, + { HI3516DV300_FIXED_396M, "396m", NULL, 0, 396000000, }, + { HI3516DV300_FIXED_400M, "400m", NULL, 0, 400000000, }, + { HI3516DV300_FIXED_448M, "448m", NULL, 0, 448000000, }, + { HI3516DV300_FIXED_500M, "500m", NULL, 0, 500000000, }, + { HI3516DV300_FIXED_540M, "540m", NULL, 0, 540000000, }, + { HI3516DV300_FIXED_600M, "600m", NULL, 0, 600000000, }, + { HI3516DV300_FIXED_750M, "750m", NULL, 0, 750000000, }, + { HI3516DV300_FIXED_1000M, "1000m", NULL, 0, 1000000000, }, + { HI3516DV300_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, }, +}; + +static const char *sysaxi_mux_p[] __initconst = { + "24m", "200m", "300m" +}; +static const char *sysapb_mux_p[] __initconst = {"24m", "50m"}; +static const char *uart_mux_p[] __initconst = {"24m", "6m"}; +static const char *fmc_mux_p[] __initconst = {"24m", "100m", "150m", "163m", "200m", "257m", "300m", "396m"}; +static const char *eth_mux_p[] __initconst = {"100m", "54m"}; +static const char *mmc_mux_p[] __initconst = {"100m", "50m", "25m"}; +static const char *pwm_mux_p[] __initconst = {"3m", "50m", "24m", "24m"}; + +static u32 sysaxi_mux_table[] = {0, 1, 2}; +static u32 sysapb_mux_table[] = {0, 1}; +static u32 uart_mux_table[] = {0, 1}; +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; +static u32 eth_mux_table[] = {0, 1}; +static u32 mmc_mux_table[] = {1, 2, 3}; +static u32 pwm_mux_table[] = {0, 1, 2, 3}; + +static struct hisi_mux_clock hi3516dv300_mux_clks[] __initdata = { + { + HI3516DV300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p, + ARRAY_SIZE(sysaxi_mux_p), + CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table, + }, + { + HI3516DV300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p, + ARRAY_SIZE(sysapb_mux_p), + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table, + }, + { + HI3516DV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p), + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table, + }, + { + HI3516DV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table, + }, + { + HI3516DV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table, + }, + { + HI3516DV300_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table, + }, + { + HI3516DV300_UART_MUX, "uart_mux0", uart_mux_p, + ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table, + }, + { + HI3516DV300_UART1_MUX, "uart_mux1", uart_mux_p, + ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table, + }, + { + HI3516DV300_UART2_MUX, "uart_mux2", uart_mux_p, + ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table, + }, + { + HI3516DV300_UART3_MUX, "uart_mux3", uart_mux_p, + ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table, + }, + { + HI3516DV300_UART4_MUX, "uart_mux4", uart_mux_p, + ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table, + }, + { + HI3516DV300_PWM_MUX, "pwm_mux", pwm_mux_p, + ARRAY_SIZE(pwm_mux_p), + CLK_SET_RATE_PARENT, 0x1bc, 8, 2, 0, pwm_mux_table, + }, + /* ethernet clock select */ + { + HI3516DV300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p), + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table, + }, +}; + +static struct hisi_fixed_factor_clock hi3516dv300_fixed_factor_clks[] __initdata + = { + { + HI3516DV300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4, + CLK_SET_RATE_PARENT + }, +}; + +static struct hisi_gate_clock hi3516dv300_gate_clks[] __initdata = { + { + HI3516DV300_FMC_CLK, "clk_fmc", "fmc_mux", + CLK_SET_RATE_PARENT, 0x144, 1, 0, + }, + { + HI3516DV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", + CLK_SET_RATE_PARENT, 0x148, 1, 0, + }, + { + HI3516DV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", + CLK_SET_RATE_PARENT, 0x160, 1, 0, + }, + { + HI3516DV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", + CLK_SET_RATE_PARENT, 0x154, 1, 0, + }, + { + HI3516DV300_UART0_CLK, "clk_uart0", "uart_mux0", + CLK_SET_RATE_PARENT, 0x1b8, 0, 0, + }, + { + HI3516DV300_UART1_CLK, "clk_uart1", "uart_mux1", + CLK_SET_RATE_PARENT, 0x1b8, 1, 0, + }, + { + HI3516DV300_UART2_CLK, "clk_uart2", "uart_mux2", + CLK_SET_RATE_PARENT, 0x1b8, 2, 0, + }, + { + HI3516DV300_UART3_CLK, "clk_uart3", "uart_mux3", + CLK_SET_RATE_PARENT, 0x1b8, 3, 0, + }, + { + HI3516DV300_UART4_CLK, "clk_uart4", "uart_mux4", + CLK_SET_RATE_PARENT, 0x1b8, 4, 0, + }, + { + HI3516DV300_I2C0_CLK, "clk_i2c0", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 11, 0, + }, + { + HI3516DV300_I2C1_CLK, "clk_i2c1", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 12, 0, + }, + { + HI3516DV300_I2C2_CLK, "clk_i2c2", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 13, 0, + }, + { + HI3516DV300_I2C3_CLK, "clk_i2c3", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 14, 0, + }, + { + HI3516DV300_I2C4_CLK, "clk_i2c4", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 15, 0, + }, + { + HI3516DV300_I2C5_CLK, "clk_i2c5", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 16, 0, + }, + { + HI3516DV300_I2C6_CLK, "clk_i2c6", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 17, 0, + }, + { + HI3516DV300_I2C7_CLK, "clk_i2c7", "50m", + CLK_SET_RATE_PARENT, 0x1b8, 18, 0, + }, + { + HI3516DV300_SPI0_CLK, "clk_spi0", "100m", + CLK_SET_RATE_PARENT, 0x1bc, 12, 0, + }, + { + HI3516DV300_SPI1_CLK, "clk_spi1", "100m", + CLK_SET_RATE_PARENT, 0x1bc, 13, 0, + }, + { + HI3516DV300_SPI2_CLK, "clk_spi2", "100m", + CLK_SET_RATE_PARENT, 0x1bc, 14, 0, + }, + { + HI3516DV300_ETH0_CLK, "clk_eth0", "eth_mux", + CLK_SET_RATE_PARENT, 0x16c, 1, 0, + }, + { + HI3516DV300_DMAC_CLK, "clk_dmac", NULL, + CLK_SET_RATE_PARENT, 0x194, 1, 0, + }, + { + HI3516DV300_DMAC_AXICLK, "axiclk_dmac", NULL, + CLK_SET_RATE_PARENT, 0x194, 2, 0, + }, + { + HI3516DV300_PWM_CLK, "clk_pwm", "pwm_mux", + CLK_SET_RATE_PARENT, 0x1bc, 7, 0, + }, +}; + +static void __init hi3516dv300_clk_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + + clk_data = hisi_clk_init(np, HI3516DV300_NR_CLKS); + if (!clk_data) + return; + + hisi_clk_register_fixed_rate(hi3516dv300_fixed_rate_clks, + ARRAY_SIZE(hi3516dv300_fixed_rate_clks), + clk_data); + hisi_clk_register_mux(hi3516dv300_mux_clks, ARRAY_SIZE(hi3516dv300_mux_clks), + clk_data); + hisi_clk_register_fixed_factor(hi3516dv300_fixed_factor_clks, + ARRAY_SIZE(hi3516dv300_fixed_factor_clks), clk_data); + hisi_clk_register_gate(hi3516dv300_gate_clks, + ARRAY_SIZE(hi3516dv300_gate_clks), clk_data); +} + +CLK_OF_DECLARE(hi3516dv300_clk, "hisilicon,hi3516dv300-clock", + hi3516dv300_clk_init); + diff --git a/drivers/clk/hisilicon/clk-hi3519av100.c b/drivers/clk/hisilicon/clk-hi3519av100.c new file mode 100644 index 000000000000..88b6d627cbe7 --- /dev/null +++ b/drivers/clk/hisilicon/clk-hi3519av100.c @@ -0,0 +1,559 @@ +/* + * Hi3519A Clock Driver + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include "clk.h" +#include "reset.h" + +struct hi3519av100_pll_clock { + u32 id; + const char *name; + const char *parent_name; + u32 ctrl_reg1; + u8 frac_shift; + u8 frac_width; + u8 postdiv1_shift; + u8 postdiv1_width; + u8 postdiv2_shift; + u8 postdiv2_width; + u32 ctrl_reg2; + u8 fbdiv_shift; + u8 fbdiv_width; + u8 refdiv_shift; + u8 refdiv_width; +}; + +struct hi3519av100_clk_pll { + struct clk_hw hw; + u32 id; + void __iomem *ctrl_reg1; + u8 frac_shift; + u8 frac_width; + u8 postdiv1_shift; + u8 postdiv1_width; + u8 postdiv2_shift; + u8 postdiv2_width; + void __iomem *ctrl_reg2; + u8 fbdiv_shift; + u8 fbdiv_width; + u8 refdiv_shift; + u8 refdiv_width; +}; + +static struct hi3519av100_pll_clock hi3519av100_pll_clks[] __initdata = { + { + HI3519AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3, + 0x4, 0, 12, 12, 6 + }, +}; + +#define to_pll_clk(_hw) container_of(_hw, struct hi3519av100_clk_pll, hw) + +/* soc clk config */ +static struct hisi_fixed_rate_clock hi3519av100_fixed_rate_clks[] __initdata = { + { HI3519AV100_FIXED_2376M, "2376m", NULL, 0, 2376000000UL, }, + { HI3519AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, }, + { HI3519AV100_FIXED_594M, "594m", NULL, 0, 594000000, }, + { HI3519AV100_FIXED_297M, "297m", NULL, 0, 297000000, }, + { HI3519AV100_FIXED_148P5M, "148p5m", NULL, 0, 148500000, }, + { HI3519AV100_FIXED_74P25M, "74p25m", NULL, 0, 74250000, }, + { HI3519AV100_FIXED_792M, "792m", NULL, 0, 792000000, }, + { HI3519AV100_FIXED_475M, "475m", NULL, 0, 475000000, }, + { HI3519AV100_FIXED_340M, "340m", NULL, 0, 340000000, }, + { HI3519AV100_FIXED_72M, "72m", NULL, 0, 72000000, }, + { HI3519AV100_FIXED_400M, "400m", NULL, 0, 400000000, }, + { HI3519AV100_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3519AV100_FIXED_54M, "54m", NULL, 0, 54000000, }, + { HI3519AV100_FIXED_27M, "27m", NULL, 0, 1188000000, }, + { HI3519AV100_FIXED_37P125M, "37p125m", NULL, 0, 37125000, }, + { HI3519AV100_FIXED_3000M, "3000m", NULL, 0, 3000000000UL, }, + { HI3519AV100_FIXED_1500M, "1500m", NULL, 0, 1500000000, }, + { HI3519AV100_FIXED_500M, "500m", NULL, 0, 500000000, }, + { HI3519AV100_FIXED_250M, "250m", NULL, 0, 250000000, }, + { HI3519AV100_FIXED_125M, "125m", NULL, 0, 125000000, }, + { HI3519AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, }, + { HI3519AV100_FIXED_600M, "600m", NULL, 0, 600000000, }, + { HI3519AV100_FIXED_750M, "750m", NULL, 0, 750000000, }, + { HI3519AV100_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3519AV100_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3519AV100_FIXED_300M, "300m", NULL, 0, 300000000, }, + { HI3519AV100_FIXED_60M, "60m", NULL, 0, 60000000, }, + { HI3519AV100_FIXED_214M, "214m", NULL, 0, 214000000, }, + { HI3519AV100_FIXED_107M, "107m", NULL, 0, 107000000, }, + { HI3519AV100_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3519AV100_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3519AV100_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3519AV100_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3519AV100_FIXED_3M, "3m", NULL, 0, 3000000, }, + { HI3519AV100_FIXED_100K, "100k", NULL, 0, 100000, }, + { HI3519AV100_FIXED_400K, "400k", NULL, 0, 400000, }, + { HI3519AV100_FIXED_49P5M, "49p5m", NULL, 0, 49500000, }, + { HI3519AV100_FIXED_99M, "99m", NULL, 0, 99000000, }, + { HI3519AV100_FIXED_187P5M, "187p5m", NULL, 0, 187500000, }, + { HI3519AV100_FIXED_198M, "198m", NULL, 0, 198000000, }, +}; + + +static const char *fmc_mux_p[] __initconst = { + "24m", "100m", "150m", "198m", "250m", "300m", "396m" +}; +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6}; + +static const char *mmc_mux_p[] __initconst = { + "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k" +}; +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; + +static const char *sysapb_mux_p[] __initconst = { + "24m", "50m", +}; +static u32 sysapb_mux_table[] = {0, 1}; + +static const char *sysbus_mux_p[] __initconst = { + "24m", "300m" +}; +static u32 sysbus_mux_table[] = {0, 1}; + +static const char *uart_mux_p[] __initconst = {"50m", "24m", "3m"}; +static u32 uart_mux_table[] = {0, 1, 2}; + +static const char *a53_1_clksel_mux_p[] __initconst = { + "24m", "apll", "vpll", "792m" +}; +static u32 a53_1_clksel_mux_table[] = {0, 1, 2, 3}; + +static struct hisi_mux_clock hi3519av100_mux_clks[] __initdata = { + { + HI3519AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p), + CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table, + }, + + { + HI3519AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table, + }, + + { + HI3519AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table, + }, + + { + HI3519AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), + CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table, + }, + + { + HI3519AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p), + CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table + }, + + { + HI3519AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p), + CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table + }, + + { + HI3519AV100_UART0_MUX, "uart0_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART1_MUX, "uart1_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART2_MUX, "uart2_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART3_MUX, "uart3_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART4_MUX, "uart4_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART5_MUX, "uart5_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART6_MUX, "uart6_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART7_MUX, "uart7_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table + }, + + { + HI3519AV100_UART8_MUX, "uart8_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p), + CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table + }, + + { + HI3519AV100_A53_1_MUX, "a53_1_mux", a53_1_clksel_mux_p, ARRAY_SIZE(a53_1_clksel_mux_p), + CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table + }, + +}; + +static struct hisi_fixed_factor_clock hi3519av100_fixed_factor_clks[] __initdata + = { + +}; + +static struct hisi_gate_clock hi3519av100_gate_clks[] __initdata = { + { + HI3519AV100_FMC_CLK, "clk_fmc", "fmc_mux", + CLK_SET_RATE_PARENT, 0x170, 1, 0, + }, + { + HI3519AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux", + CLK_SET_RATE_PARENT, 0x1a8, 28, 0, + }, + { + HI3519AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux", + CLK_SET_RATE_PARENT, 0x1ec, 28, 0, + }, + { + HI3519AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux", + CLK_SET_RATE_PARENT, 0x214, 28, 0, + }, + { + HI3519AV100_UART0_CLK, "clk_uart0", "uart0_mux", + CLK_SET_RATE_PARENT, 0x198, 16, 0, + }, + { + HI3519AV100_UART1_CLK, "clk_uart1", "uart1_mux", + CLK_SET_RATE_PARENT, 0x198, 17, 0, + }, + { + HI3519AV100_UART2_CLK, "clk_uart2", "uart2_mux", + CLK_SET_RATE_PARENT, 0x198, 18, 0, + }, + { + HI3519AV100_UART3_CLK, "clk_uart3", "uart3_mux", + CLK_SET_RATE_PARENT, 0x198, 19, 0, + }, + { + HI3519AV100_UART4_CLK, "clk_uart4", "uart4_mux", + CLK_SET_RATE_PARENT, 0x198, 20, 0, + }, + { + HI3519AV100_UART5_CLK, "clk_uart5", "uart5_mux", + CLK_SET_RATE_PARENT, 0x198, 21, 0, + }, + { + HI3519AV100_UART6_CLK, "clk_uart6", "uart6_mux", + CLK_SET_RATE_PARENT, 0x198, 22, 0, + }, + { + HI3519AV100_UART7_CLK, "clk_uart7", "uart7_mux", + CLK_SET_RATE_PARENT, 0x198, 23, 0, + }, + { + HI3519AV100_UART8_CLK, "clk_uart8", "uart8_mux", + CLK_SET_RATE_PARENT, 0x198, 29, 0, + }, + { + HI3519AV100_ETH_CLK, "clk_eth", NULL, + CLK_SET_RATE_PARENT, 0x0174, 1, 0, + }, + { + HI3519AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL, + CLK_SET_RATE_PARENT, 0x0174, 5, 0, + }, + /* i2c */ + { + HI3519AV100_I2C0_CLK, "clk_i2c0", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 16, 0, + }, + { + HI3519AV100_I2C1_CLK, "clk_i2c1", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 17, 0, + }, + { + HI3519AV100_I2C2_CLK, "clk_i2c2", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 18, 0, + }, + { + HI3519AV100_I2C3_CLK, "clk_i2c3", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 19, 0, + }, + { + HI3519AV100_I2C4_CLK, "clk_i2c4", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 20, 0, + }, + { + HI3519AV100_I2C5_CLK, "clk_i2c5", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 21, 0, + }, + { + HI3519AV100_I2C6_CLK, "clk_i2c6", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 22, 0, + }, + { + HI3519AV100_I2C7_CLK, "clk_i2c7", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 23, 0, + }, + { + HI3519AV100_I2C8_CLK, "clk_i2c8", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 24, 0, + }, + { + HI3519AV100_I2C9_CLK, "clk_i2c9", "50m", + CLK_SET_RATE_PARENT, 0x01a0, 25, 0, + }, + { + HI3519AV100_SPI0_CLK, "clk_spi0", "100m", + CLK_SET_RATE_PARENT, 0x0198, 24, 0, + }, + { + HI3519AV100_SPI1_CLK, "clk_spi1", "100m", + CLK_SET_RATE_PARENT, 0x0198, 25, 0, + }, + { + HI3519AV100_SPI2_CLK, "clk_spi2", "100m", + CLK_SET_RATE_PARENT, 0x0198, 26, 0, + }, + { + HI3519AV100_SPI3_CLK, "clk_spi3", "100m", + CLK_SET_RATE_PARENT, 0x0198, 27, 0, + }, + { + HI3519AV100_SPI4_CLK, "clk_spi4", "100m", + CLK_SET_RATE_PARENT, 0x0198, 28, 0, + }, + { + HI3519AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL, + CLK_SET_RATE_PARENT, 0x16c, 6, 0, + }, + { + HI3519AV100_EDMAC_CLK, "clk_edmac", NULL, + CLK_SET_RATE_PARENT, 0x16c, 5, 0, + }, + { + HI3519AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL, + CLK_SET_RATE_PARENT, 0x16c, 9, 0, + }, + { + HI3519AV100_EDMAC1_CLK, "clk_edmac1", NULL, + CLK_SET_RATE_PARENT, 0x16c, 8, 0, + }, + { + HI3519AV100_VDMAC_CLK, "clk_vdmac", NULL, + CLK_SET_RATE_PARENT, 0x14c, 5, 0, + }, +}; + +static void hi3519av100_calc_pll(u32 *frac_val, + u32 *postdiv1_val, + u32 *postdiv2_val, + u32 *fbdiv_val, + u32 *refdiv_val, + u64 rate) +{ + u64 rem; + *frac_val = 0; + rem = do_div(rate, 1000000); + *fbdiv_val = rate; + *refdiv_val = 24; + if ((rem * (1 << 24)) > ULLONG_MAX) { + pr_err("Data over limits!\n"); + return; + } + rem = rem * (1 << 24); + do_div(rem, 1000000); + *frac_val = rem; +} + +static int clk_pll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct hi3519av100_clk_pll *clk = to_pll_clk(hw); + u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val; + u32 val; + + postdiv1_val = postdiv2_val = 0; + + hi3519av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val, + &fbdiv_val, &refdiv_val, rate); + + val = readl_relaxed(clk->ctrl_reg1); + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift); + + val |= frac_val << clk->frac_shift; + val |= postdiv1_val << clk->postdiv1_shift; + val |= postdiv2_val << clk->postdiv2_shift; + writel_relaxed(val, clk->ctrl_reg1); + + val = readl_relaxed(clk->ctrl_reg2); + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift); + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift); + + val |= fbdiv_val << clk->fbdiv_shift; + val |= refdiv_val << clk->refdiv_shift; + writel_relaxed(val, clk->ctrl_reg2); + + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct hi3519av100_clk_pll *clk = to_pll_clk(hw); + u64 frac_val, fbdiv_val; + u32 val; + u64 tmp, rate; + u32 refdiv_val; + + val = readl_relaxed(clk->ctrl_reg1); + val = val >> clk->frac_shift; + val &= ((1 << clk->frac_width) - 1); + frac_val = val; + + val = readl_relaxed(clk->ctrl_reg2); + val = val >> clk->fbdiv_shift; + val &= ((1 << clk->fbdiv_width) - 1); + fbdiv_val = val; + + val = readl_relaxed(clk->ctrl_reg2); + val = val >> clk->refdiv_shift; + val &= ((1 << clk->refdiv_width) - 1); + refdiv_val = val; + + /* rate = 24000000 * (fbdiv + frac / (1<<24) ) / refdiv */ + rate = 0; + if ((24000000 * fbdiv_val) > ULLONG_MAX) { + pr_err("Data over limits!\n"); + return 0; + } + tmp = 24000000 * fbdiv_val; + rate += tmp; + do_div(rate, refdiv_val); + + return rate; +} + +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return req->rate; +} + +static struct clk_ops clk_pll_ops = { + .set_rate = clk_pll_set_rate, + .determine_rate = clk_pll_determine_rate, + .recalc_rate = clk_pll_recalc_rate, +}; + +void __init hi3519av100_clk_register_pll(struct hi3519av100_pll_clock *clks, + int nums, struct hisi_clock_data *data) +{ + int i; + void __iomem *base = NULL; + + if (clks == NULL || data == NULL) + return; + + base = data->base; + for (i = 0; i < nums; i++) { + struct hi3519av100_clk_pll *p_clk = NULL; + struct clk *clk = NULL; + struct clk_init_data init; + + p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); + if (!p_clk) + return; + + init.name = clks[i].name; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + init.parent_names = + (clks[i].parent_name ? &clks[i].parent_name : NULL); + init.num_parents = (clks[i].parent_name ? 1 : 0); + init.ops = &clk_pll_ops; + + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1; + p_clk->frac_shift = clks[i].frac_shift; + p_clk->frac_width = clks[i].frac_width; + p_clk->postdiv1_shift = clks[i].postdiv1_shift; + p_clk->postdiv1_width = clks[i].postdiv1_width; + p_clk->postdiv2_shift = clks[i].postdiv2_shift; + p_clk->postdiv2_width = clks[i].postdiv2_width; + + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2; + p_clk->fbdiv_shift = clks[i].fbdiv_shift; + p_clk->fbdiv_width = clks[i].fbdiv_width; + p_clk->refdiv_shift = clks[i].refdiv_shift; + p_clk->refdiv_width = clks[i].refdiv_width; + p_clk->hw.init = &init; + + clk = clk_register(NULL, &p_clk->hw); + if (IS_ERR(clk)) { + kfree(p_clk); + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + continue; + } + + data->clk_data.clks[clks[i].id] = clk; + } +} + +static void __init hi3519av100_clk_init(struct device_node *np) +{ + struct hisi_clock_data *clk_data; + + clk_data = hisi_clk_init(np, HI3519AV100_NR_CLKS); + if (!clk_data) + return; + if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) + hibvt_reset_init(np, HI3519AV100_NR_RSTS); + + hisi_clk_register_fixed_rate(hi3519av100_fixed_rate_clks, + ARRAY_SIZE(hi3519av100_fixed_rate_clks), + clk_data); + hisi_clk_register_mux(hi3519av100_mux_clks, ARRAY_SIZE(hi3519av100_mux_clks), + clk_data); + hisi_clk_register_fixed_factor(hi3519av100_fixed_factor_clks, + ARRAY_SIZE(hi3519av100_fixed_factor_clks), clk_data); + hisi_clk_register_gate(hi3519av100_gate_clks, + ARRAY_SIZE(hi3519av100_gate_clks), clk_data); + + hi3519av100_clk_register_pll(hi3519av100_pll_clks, + ARRAY_SIZE(hi3519av100_pll_clks), clk_data); +} + +CLK_OF_DECLARE(hi3519av100_clk, "hisilicon,hi3519av100-clock", + hi3519av100_clk_init); diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c index ba6afad66a2b..b13b916097fe 100644 --- a/drivers/clk/hisilicon/clk-hisi-phase.c +++ b/drivers/clk/hisilicon/clk-hisi-phase.c @@ -77,7 +77,7 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees) val = readl(phase->reg); val &= ~phase->mask; - val |= regval << phase->shift; + val |= (unsigned int)regval << phase->shift; writel(val, phase->reg); spin_unlock_irqrestore(phase->lock, flags); diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 54d9fdc93599..9ca4fc05fa57 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -82,6 +82,10 @@ struct hisi_clock_data *hisi_clk_init(struct device_node *np, of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); return clk_data; err_data: + if (base) { + iounmap(base); + base = NULL; + } kfree(clk_data); err: return NULL; diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c index 5d4e61c7a429..50a598c91ce4 100644 --- a/drivers/clk/hisilicon/crg-hi3516cv300.c +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c @@ -170,7 +170,7 @@ static struct hisi_clock_data *hi3516cv300_clk_register( return ERR_PTR(ret); } -static void hi3516cv300_clk_unregister(struct platform_device *pdev) +static void hi3516cv300_clk_unregister(const struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); @@ -229,7 +229,7 @@ static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register( return ERR_PTR(ret); } -static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev) +static void hi3516cv300_sysctrl_clk_unregister(const struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 08a19ba776e6..d461f6e4fafd 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -251,7 +251,7 @@ static struct hisi_clock_data *hi3798cv200_clk_register( return ERR_PTR(ret); } -static void hi3798cv200_clk_unregister(struct platform_device *pdev) +static void hi3798cv200_clk_unregister(const struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); @@ -316,7 +316,7 @@ static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( return ERR_PTR(ret); } -static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev) +static void hi3798cv200_sysctrl_clk_unregister(const struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h index 803f6ba6d7a2..a847586605b7 100644 --- a/drivers/clk/hisilicon/crg.h +++ b/drivers/clk/hisilicon/crg.h @@ -13,7 +13,7 @@ struct hisi_reset_controller; struct hisi_crg_funcs { struct hisi_clock_data* (*register_clks)(struct platform_device *pdev); - void (*unregister_clks)(struct platform_device *pdev); + void (*unregister_clks)(const struct platform_device *pdev); }; struct hisi_crg_dev { diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c index 93cee17db8b1..9e56eeb016e6 100644 --- a/drivers/clk/hisilicon/reset.c +++ b/drivers/clk/hisilicon/reset.c @@ -87,6 +87,36 @@ static const struct reset_control_ops hisi_reset_ops = { .deassert = hisi_reset_deassert, }; +#ifdef CONFIG_ARCH_HISI_BVT +int __init hibvt_reset_init(struct device_node *np, + int nr_rsts) +{ + struct hisi_reset_controller *rstc; + + rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); + if (!rstc) + return -ENOMEM; + + rstc->membase = of_iomap(np, 0); + if (!rstc->membase) { + kfree(rstc); + return -EINVAL; + } + + spin_lock_init(&rstc->lock); + + rstc->rcdev.owner = THIS_MODULE; + rstc->rcdev.nr_resets = nr_rsts; + rstc->rcdev.ops = &hisi_reset_ops; + rstc->rcdev.of_node = np; + rstc->rcdev.of_reset_n_cells = 2; + rstc->rcdev.of_xlate = hisi_reset_of_xlate; + + return reset_controller_register(&rstc->rcdev); +} +EXPORT_SYMBOL_GPL(hibvt_reset_init); +#endif + struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev) { struct hisi_reset_controller *rstc; diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h index 81ff9e9e3678..5954bdf911e9 100644 --- a/drivers/clk/hisilicon/reset.h +++ b/drivers/clk/hisilicon/reset.h @@ -11,6 +11,9 @@ struct hisi_reset_controller; #ifdef CONFIG_RESET_CONTROLLER struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev); +#ifdef CONFIG_ARCH_HISI_BVT +int __init hibvt_reset_init(struct device_node *np, int nr_rsts); +#endif void hisi_reset_exit(struct hisi_reset_controller *rstc); #else static inline diff --git a/include/dt-bindings/clock/hi3516dv300-clock.h b/include/dt-bindings/clock/hi3516dv300-clock.h new file mode 100644 index 000000000000..408c9b09df9c --- /dev/null +++ b/include/dt-bindings/clock/hi3516dv300-clock.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#ifndef __DTS_HI3516DV300_CLOCK_H +#define __DTS_HI3516DV300_CLOCK_H + +/* clk in Hi3516CV500 CRG */ +/* fixed rate clocks */ +#define HI3516DV300_FIXED_3M 1 +#define HI3516DV300_FIXED_6M 2 +#define HI3516DV300_FIXED_12M 3 +#define HI3516DV300_FIXED_24M 4 +#define HI3516DV300_FIXED_50M 5 +#define HI3516DV300_FIXED_83P3M 6 +#define HI3516DV300_FIXED_100M 7 +#define HI3516DV300_FIXED_125M 8 +#define HI3516DV300_FIXED_148P5M 9 +#define HI3516DV300_FIXED_150M 10 +#define HI3516DV300_FIXED_200M 11 +#define HI3516DV300_FIXED_250M 12 +#define HI3516DV300_FIXED_300M 13 +#define HI3516DV300_FIXED_324M 14 +#define HI3516DV300_FIXED_342M 15 +#define HI3516DV300_FIXED_375M 16 +#define HI3516DV300_FIXED_400M 17 +#define HI3516DV300_FIXED_448M 18 +#define HI3516DV300_FIXED_500M 19 +#define HI3516DV300_FIXED_540M 20 +#define HI3516DV300_FIXED_600M 21 +#define HI3516DV300_FIXED_750M 22 +#define HI3516DV300_FIXED_1000M 23 +#define HI3516DV300_FIXED_1500M 24 +#define HI3516DV300_FIXED_54M 25 +#define HI3516DV300_FIXED_25M 26 +#define HI3516DV300_FIXED_163M 27 +#define HI3516DV300_FIXED_257M 28 +#define HI3516DV300_FIXED_396M 29 + +/* mux clocks */ +#define HI3516DV300_SYSAXI_CLK 30 +#define HI3516DV300_SYSAPB_CLK 31 +#define HI3516DV300_FMC_MUX 32 +#define HI3516DV300_UART_MUX 33 +#define HI3516DV300_MMC0_MUX 34 +#define HI3516DV300_MMC1_MUX 35 +#define HI3516DV300_MMC2_MUX 36 +#define HI3516DV300_UART1_MUX 33 +#define HI3516DV300_UART2_MUX 37 +#define HI3516DV300_UART4_MUX 38 +#define HI3516DV300_ETH_MUX 39 + +/* gate clocks */ +#define HI3516DV300_UART0_CLK 40 +#define HI3516DV300_UART1_CLK 41 +#define HI3516DV300_UART2_CLK 42 +#define HI3516DV300_FMC_CLK 43 +#define HI3516DV300_ETH0_CLK 44 +#define HI3516DV300_USB2_BUS_CLK 45 +#define HI3516DV300_USB2_CLK 46 +#define HI3516DV300_DMAC_CLK 47 +#define HI3516DV300_SPI0_CLK 48 +#define HI3516DV300_SPI1_CLK 49 +#define HI3516DV300_MMC0_CLK 50 +#define HI3516DV300_MMC1_CLK 51 +#define HI3516DV300_MMC2_CLK 52 +#define HI3516DV300_UART4_CLK 53 +#define HI3516DV300_SPI2_CLK 54 +#define HI3516DV300_I2C0_CLK 55 +#define HI3516DV300_I2C1_CLK 56 +#define HI3516DV300_I2C2_CLK 57 +#define HI3516DV300_I2C3_CLK 58 +#define HI3516DV300_I2C4_CLK 59 +#define HI3516DV300_I2C5_CLK 60 +#define HI3516DV300_I2C6_CLK 61 +#define HI3516DV300_I2C7_CLK 62 +#define HI3516DV300_UART3_MUX 63 +#define HI3516DV300_UART3_CLK 64 +#define HI3516DV300_DMAC_AXICLK 70 +#define HI3516DV300_PWM_CLK 71 +#define HI3516DV300_PWM_MUX 72 + +#define HI3516DV300_NR_CLKS 256 +#define HI3516DV300_NR_RSTS 256 + +#endif /* __DTS_HI3516DV300_CLOCK_H */ -- Gitee From a6cbad48f6c83f15091d773292172c1d27eb02a8 Mon Sep 17 00:00:00 2001 From: taolan Date: Mon, 28 Nov 2022 20:20:05 +0000 Subject: [PATCH 3/5] module: add hisi machine support driver inclusion category: bugfix bugzilla:https://gitee.com/openeuler/kernel/issues/I5XHIQ ----------------------------------------------------------------- Add support for hi3516dv300 soc. Signed-off-by: taolan --- arch/arm/mach-hibvt/Kconfig | 258 ++++++++++++++++++ arch/arm/mach-hibvt/Makefile | 27 ++ arch/arm/mach-hibvt/Makefile.boot | 7 + .../mach-hibvt/include/mach/hi3516dv300_io.h | 26 ++ .../include/mach/hi3516dv300_platform.h | 4 + arch/arm/mach-hibvt/include/mach/io.h | 52 ++++ arch/arm/mach-hibvt/include/mach/platform.h | 52 ++++ arch/arm/mach-hibvt/mach-common.h | 9 + arch/arm/mach-hibvt/mach-hi3516dv300.c | 68 +++++ arch/arm/mach-hibvt/platsmp.c | 62 +++++ 10 files changed, 565 insertions(+) create mode 100644 arch/arm/mach-hibvt/Kconfig create mode 100644 arch/arm/mach-hibvt/Makefile create mode 100644 arch/arm/mach-hibvt/Makefile.boot create mode 100644 arch/arm/mach-hibvt/include/mach/hi3516dv300_io.h create mode 100644 arch/arm/mach-hibvt/include/mach/hi3516dv300_platform.h create mode 100644 arch/arm/mach-hibvt/include/mach/io.h create mode 100644 arch/arm/mach-hibvt/include/mach/platform.h create mode 100644 arch/arm/mach-hibvt/mach-common.h create mode 100644 arch/arm/mach-hibvt/mach-hi3516dv300.c create mode 100644 arch/arm/mach-hibvt/platsmp.c diff --git a/arch/arm/mach-hibvt/Kconfig b/arch/arm/mach-hibvt/Kconfig new file mode 100644 index 000000000000..cfb9576b2108 --- /dev/null +++ b/arch/arm/mach-hibvt/Kconfig @@ -0,0 +1,258 @@ +config ARCH_HISI_BVT + bool "Hisilicon BVT SoC Support" + select ARM_AMBA + select ARM_GIC if ARCH_MULTI_V7 + select ARM_VIC if ARCH_MULTI_V5 + select ARM_TIMER_SP804 + select POWER_RESET + select POWER_SUPPLY + +if ARCH_HISI_BVT + +menu "Hisilicon BVT platform type" + +config ARCH_HI3521DV200 + bool "Hisilicon Hi3521DV200 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3521DV200 Soc family. + +config ARCH_HI3520DV500 + bool "Hisilicon Hi3520DV500 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3520DV500 Soc family. + +config ARCH_HI3516A + bool "Hisilicon Hi3516A Cortex-A7(Single) family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select ARM_GIC + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + help + Support for Hisilicon Hi3516A Soc family. + +config ARCH_HI3516CV500 + bool "Hisilicon Hi3516CV500 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3516CV500 Soc family. + +config ARCH_HI3516DV300 + bool "Hisilicon Hi3516DV300 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3516DV300 Soc family. + +config ARCH_HI3516EV200 + bool "Hisilicon Hi3516EV200 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3516EV200 Soc family. + +config ARCH_HI3516EV300 + bool "Hisilicon Hi3516EV300 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3516EV300 Soc family. + +config ARCH_HI3518EV300 + bool "Hisilicon Hi3518EV300 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3518EV300 Soc family. + +config ARCH_HI3516DV200 + bool "Hisilicon Hi3516DV200 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3516DV200 Soc family. +config ARCH_HI3556V200 + bool "Hisilicon Hi3556V200 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3556V200 Soc family. + +config ARCH_HI3559V200 + bool "Hisilicon Hi3559V200 Cortex-A7 family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + select POWER_RESET_HISI + help + Support for Hisilicon Hi3559V200 Soc family. + +config ARCH_HI3518EV20X + bool "Hisilicon Hi3518ev20x ARM926T(Single) family" + depends on ARCH_MULTI_V5 + select PINCTRL + select PINCTRL_SINGLE + help + Support for Hisilicon Hi3518ev20x Soc family. + +config ARCH_HI3536DV100 + bool "Hisilicon Hi3536DV100 Cortex-A7(Single) family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select PINCTRL + help + Support for Hisilicon Hi3536DV100 Soc family. + +config ARCH_HI3521A + bool "Hisilicon Hi3521A A7(Single) family" + depends on ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select ARM_GIC + select PINCTRL + select PINCTRL_SINGLE + help + Support for Hisilicon Hi3521a Soc family. + +config ARCH_HI3531A + bool "Hisilicon Hi3531A A9 family" if ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select ARM_GIC + select CACHE_L2X0 + select PINCTRL + select PINCTRL_SINGLE + select HAVE_ARM_SCU if SMP + select NEED_MACH_IO_H if PCI + help + Support for Hisilicon Hi3531a Soc family. + +config ARCH_HI3556AV100 + bool "Hisilicon Hi3556AV100 Cortex-a53 family" if ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select ARM_CCI + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + select PMC if SMP + help + Support for Hisilicon Hi3556AV100 Soc family +if ARCH_HI3556AV100 + +config PMC + bool + depends on ARCH_HI3556AV100 + help + support power control for Hi3556AV100 Cortex-a53 + +endif + +config ARCH_HI3519AV100 + bool "Hisilicon Hi3519AV100 Cortex-a53 family" if ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select ARM_CCI + select ARM_GIC + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + select NEED_MACH_IO_H if PCI + select PMC if SMP + help + Support for Hisilicon Hi3519AV100 Soc family +if ARCH_HI3519AV100 + +config PMC + bool + depends on ARCH_HI3519AV100 + help + support power control for Hi3519AV100 Cortex-a53 + +endif + +config ARCH_HI3568V100 + bool "Hisilicon Hi3568V100 Cortex-a53 family" if ARCH_MULTI_V7 + select HAVE_ARM_ARCH_TIMER + select ARM_CCI + select ARM_GIC + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER + select NEED_MACH_IO_H if PCI + select PMC if SMP + help + Support for Hisilicon Hi3568V100 Soc family +if ARCH_HI3568V100 + +config PMC + bool + depends on ARCH_HI3568V100 + help + support power control for Hi3568V100 Cortex-a53 + +endif + +config ARCH_HISI_BVT_AMP + bool "Hisilicon AMP solution support" + depends on ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200 || ARCH_HI3562V100 || ARCH_HI3566V100 || ARCH_HI3568V100 + help + support for Hisilicon AMP solution + +config HISI_MC + bool "Hisilicon mc platform solution" + default n + help + support for Hisilicon mc platform solution + +config AMP_ZRELADDR + hex 'amp zreladdr' + depends on ARCH_HISI_BVT_AMP + default "0x32008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3568V100 + default "0x82008000" if ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V200 || ARCH_HI3562V100 || ARCH_HI3566V100 + default "0x42008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200 +config HI_ZRELADDR + hex 'zreladdr' + default "0x40008000" if ARCH_HI3521DV200 + default "0x40008000" if ARCH_HI3520DV500 + default "0x80008000" if ARCH_HI3516CV500 + default "0x80008000" if ARCH_HI3516DV300 + default "0x80008000" if ARCH_HI3556V200 + default "0x80008000" if ARCH_HI3559V200 + default "0x80008000" if ARCH_HI3562V100 + default "0x80008000" if ARCH_HI3566V100 + default "0x80008000" if ARCH_HI3516A + default "0x80008000" if ARCH_HI3518EV20X + default "0x80008000" if ARCH_HI3536DV100 + default "0x80008000" if ARCH_HI3521A + default "0x40008000" if ARCH_HI3531A + default "0x40008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV200 + default "0x22008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3568V100 + +config HI_PARAMS_PHYS + hex 'params_phys' + default "0x00000100" + +config HI_INITRD_PHYS + hex 'initrd_phys' + default "0x00800000" + +endmenu + +endif diff --git a/arch/arm/mach-hibvt/Makefile b/arch/arm/mach-hibvt/Makefile new file mode 100644 index 000000000000..ec3243ec975a --- /dev/null +++ b/arch/arm/mach-hibvt/Makefile @@ -0,0 +1,27 @@ +# +# Makefile for Hisilicon processors family +# + +obj-$(CONFIG_ARCH_HI3521DV200) += mach-hi3521dv200.o +obj-$(CONFIG_ARCH_HI3520DV500) += mach-hi3521dv200.o +obj-$(CONFIG_ARCH_HI3516A) += mach-hi3516a.o +obj-$(CONFIG_ARCH_HI3516CV500) += mach-hi3516cv500.o +obj-$(CONFIG_ARCH_HI3516EV200) += mach-hi3516ev200.o +obj-$(CONFIG_ARCH_HI3516EV300) += mach-hi3516ev300.o +obj-$(CONFIG_ARCH_HI3518EV300) += mach-hi3518ev300.o +obj-$(CONFIG_ARCH_HI3516DV200) += mach-hi3516dv200.o +obj-$(CONFIG_ARCH_HI3516DV300) += mach-hi3516dv300.o +obj-$(CONFIG_ARCH_HI3556V200) += mach-hi3556v200.o +obj-$(CONFIG_ARCH_HI3559V200) += mach-hi3559v200.o +obj-$(CONFIG_ARCH_HI3562V100) += mach-hi3559v200.o +obj-$(CONFIG_ARCH_HI3566V100) += mach-hi3559v200.o +obj-$(CONFIG_ARCH_HI3518EV20X) += mach-hi3518ev20x.o +obj-$(CONFIG_ARCH_HI3536DV100) += mach-hi3536dv100.o +obj-$(CONFIG_ARCH_HI3521A) += mach-hi3521a.o +obj-$(CONFIG_ARCH_HI3531A) += mach-hi3531a.o +obj-$(CONFIG_ARCH_HI3556AV100) += mach-hi3556av100.o +obj-$(CONFIG_ARCH_HI3519AV100) += mach-hi3519av100.o +obj-$(CONFIG_ARCH_HI3568V100) += mach-hi3519av100.o + + +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-hibvt/Makefile.boot b/arch/arm/mach-hibvt/Makefile.boot new file mode 100644 index 000000000000..8c8b30077e37 --- /dev/null +++ b/arch/arm/mach-hibvt/Makefile.boot @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_ARCH_HISI_BVT_AMP), y) +zreladdr-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_AMP_ZRELADDR) +else +zreladdr-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_HI_ZRELADDR) +endif +params_phys-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_HI_PARAMS_PHYS) +initrd_phys-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_HI_INITRD_PHYS) diff --git a/arch/arm/mach-hibvt/include/mach/hi3516dv300_io.h b/arch/arm/mach-hibvt/include/mach/hi3516dv300_io.h new file mode 100644 index 000000000000..fb9071229037 --- /dev/null +++ b/arch/arm/mach-hibvt/include/mach/hi3516dv300_io.h @@ -0,0 +1,26 @@ +#ifndef __HI3516DV300_IO_H +#define __HI3516DV300_IO_H + +/* + * phy: 0x20000000 ~ 0x20700000 + * vir: 0xFE100000 ~ 0xFE800000 + */ +#define HI3516DV300_IOCH2_PHYS 0x20000000 +#define IO_OFFSET_HIGH 0xDE100000 +#define HI3516DV300_IOCH2_VIRT (HI3516DV300_IOCH2_PHYS + IO_OFFSET_HIGH) +#define HI3516DV300_IOCH2_SIZE 0x700000 + +/* phy: 0x10000000 ~ 0x100E0000 + * vir: 0xFE000000 ~ 0xFE0E0000 + */ +#define HI3516DV300_IOCH1_PHYS 0x10000000 +#define IO_OFFSET_LOW 0xEE000000 +#define HI3516DV300_IOCH1_VIRT (HI3516DV300_IOCH1_PHYS + IO_OFFSET_LOW) +#define HI3516DV300_IOCH1_SIZE 0xE0000 + +#define IO_ADDRESS(x) ((x) >= HI3516DV300_IOCH2_PHYS ? (x) + IO_OFFSET_HIGH \ + : (x) + IO_OFFSET_LOW) + +#define __io_address(n) ((void __iomem __force *)IO_ADDRESS(n)) + +#endif diff --git a/arch/arm/mach-hibvt/include/mach/hi3516dv300_platform.h b/arch/arm/mach-hibvt/include/mach/hi3516dv300_platform.h new file mode 100644 index 000000000000..94c48064b311 --- /dev/null +++ b/arch/arm/mach-hibvt/include/mach/hi3516dv300_platform.h @@ -0,0 +1,4 @@ +#ifndef __HI3516DV300_CHIP_REGS_H__ +#define __HI3516DV300_CHIP_REGS_H__ + +#endif /* End of __HI3516DV300_CHIP_REGS_H__ */ diff --git a/arch/arm/mach-hibvt/include/mach/io.h b/arch/arm/mach-hibvt/include/mach/io.h new file mode 100644 index 000000000000..b5fd58c7bfe6 --- /dev/null +++ b/arch/arm/mach-hibvt/include/mach/io.h @@ -0,0 +1,52 @@ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#ifdef CONFIG_ARCH_HI3516A +#include +#endif + +#ifdef CONFIG_ARCH_HI3518EV20X +#include +#endif + +#ifdef CONFIG_ARCH_HI3536DV100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3521A +#include +#endif + +#ifdef CONFIG_ARCH_HI3531A +#include +#endif + +#ifdef CONFIG_ARCH_HI3516CV500 +#include +#endif + +#ifdef CONFIG_ARCH_HI3516DV300 +#include +#endif + +#ifdef CONFIG_ARCH_HI3556V200 +#include +#endif + +#ifdef CONFIG_ARCH_HI3559V200 +#include +#endif + +#ifdef CONFIG_ARCH_HI3562V100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3566V100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3519AV100 +#include +#endif + +#endif diff --git a/arch/arm/mach-hibvt/include/mach/platform.h b/arch/arm/mach-hibvt/include/mach/platform.h new file mode 100644 index 000000000000..5e41d2696954 --- /dev/null +++ b/arch/arm/mach-hibvt/include/mach/platform.h @@ -0,0 +1,52 @@ +#ifndef __HISI_PLATFORM_H__ +#define __HISI_PLATFORM_H__ + +#ifdef CONFIG_ARCH_HI3536DV100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3521A +#include +#endif + +#ifdef CONFIG_ARCH_HI3531A +#include +#endif + +#ifdef CONFIG_ARCH_HI3516DV300 +#include +#endif + +#ifdef CONFIG_ARCH_HI3516CV500 +#include +#endif + +#ifdef CONFIG_ARCH_HI3556V200 +#include +#endif + +#ifdef CONFIG_ARCH_HI3559V200 +#include +#endif + +#ifdef CONFIG_ARCH_HI3562V100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3566V100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3556AV100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3519AV100 +#include +#endif + +#ifdef CONFIG_ARCH_HI3568V100 +#include +#endif + +#endif /* End of __HISI_PLATFORM_H__ */ diff --git a/arch/arm/mach-hibvt/mach-common.h b/arch/arm/mach-hibvt/mach-common.h new file mode 100644 index 000000000000..f5edadb0f0a8 --- /dev/null +++ b/arch/arm/mach-hibvt/mach-common.h @@ -0,0 +1,9 @@ +#ifndef __SMP_COMMON_H +#define __SMP_COMMON_H + +#ifdef CONFIG_SMP +void hi35xx_set_cpu(unsigned int cpu, bool enable); +void __init hi35xx_smp_prepare_cpus(unsigned int max_cpus); +int hi35xx_boot_secondary(unsigned int cpu, struct task_struct *idle); +#endif /* CONFIG_SMP */ +#endif /* __SMP_COMMON_H */ diff --git a/arch/arm/mach-hibvt/mach-hi3516dv300.c b/arch/arm/mach-hibvt/mach-hi3516dv300.c new file mode 100644 index 000000000000..3061683bb711 --- /dev/null +++ b/arch/arm/mach-hibvt/mach-hi3516dv300.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * +*/ + +#include +#include + +#include "mach-common.h" + +#ifdef CONFIG_SMP + +#define REG_CPU_SRST_CRG 0x78 +#define CPU1_SRST_REQ BIT(2) +#define DBG1_SRST_REQ BIT(4) + +void hi35xx_set_cpu(unsigned int cpu, bool enable) +{ + struct device_node *np = NULL; + unsigned int regval; + void __iomem *crg_base; + + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv300-clock"); + if (!np) { + pr_err("failed to find hisilicon clock node\n"); + return; + } + + crg_base = of_iomap(np, 0); + if (!crg_base) { + pr_err("failed to map address\n"); + return; + } + + if (enable) { + /* clear the slave cpu reset */ + regval = readl(crg_base + REG_CPU_SRST_CRG); + regval &= ~CPU1_SRST_REQ; + writel(regval, (crg_base + REG_CPU_SRST_CRG)); + } else { + regval = readl(crg_base + REG_CPU_SRST_CRG); + regval |= (DBG1_SRST_REQ | CPU1_SRST_REQ); + writel(regval, (crg_base + REG_CPU_SRST_CRG)); + } + iounmap(crg_base); +} + +static const struct smp_operations hi35xx_smp_ops __initconst = { + .smp_prepare_cpus = hi35xx_smp_prepare_cpus, + .smp_boot_secondary = hi35xx_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(hi3516dv300_smp, "hisilicon,hi3516dv300", + &hi35xx_smp_ops); +#endif /* CONFIG_SMP */ diff --git a/arch/arm/mach-hibvt/platsmp.c b/arch/arm/mach-hibvt/platsmp.c new file mode 100644 index 000000000000..a73be20b133c --- /dev/null +++ b/arch/arm/mach-hibvt/platsmp.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include +#include +#include + +#include "mach-common.h" + +#define HI35XX_BOOT_ADDRESS 0x00000000 + +void __init hi35xx_smp_prepare_cpus(unsigned int max_cpus) +{ + unsigned long base = 0; + void __iomem *scu_base = NULL; + + if (scu_a9_has_base()) { + base = scu_a9_get_base(); + scu_base = ioremap(base, PAGE_SIZE); + if (!scu_base) { + pr_err("ioremap(scu_base) failed\n"); + return; + } + + scu_enable(scu_base); + iounmap(scu_base); + } +} + +void hi35xx_set_scu_boot_addr(phys_addr_t start_addr, phys_addr_t jump_addr) +{ + void __iomem *virt; + + virt = ioremap(start_addr, PAGE_SIZE); + if (!virt) { + pr_err("ioremap(start_addr) failed\n"); + return; + } + + writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ + writel_relaxed(jump_addr, virt + 4); /* pc jump phy address */ + iounmap(virt); +} + +int hi35xx_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + phys_addr_t jumpaddr; + + jumpaddr = virt_to_phys(secondary_startup); + hi35xx_set_scu_boot_addr(HI35XX_BOOT_ADDRESS, jumpaddr); + hi35xx_set_cpu(cpu, true); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; +} + -- Gitee From 0f986ef44039023fd923f6dd7fa0f85ad92d8d62 Mon Sep 17 00:00:00 2001 From: taolan Date: Mon, 28 Nov 2022 20:20:07 +0000 Subject: [PATCH 4/5] module:Add support for MEIG usb product to option driver. driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I5XHIQ ----------------------------------------------------------- This patch add MEIG usb product vendor id & product id to option driver id table. Signed-off-by: taolan --- drivers/usb/serial/option.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 2eb4083c5b45..a00657c9d4e6 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -97,6 +97,10 @@ static void option_instat_callback(struct urb *urb); #define YISO_VENDOR_ID 0x0EAB #define YISO_PRODUCT_U893 0xC893 +/* MEIG PRODUCTS */ +#define MEIG_VENDOR_ID 0x2DEE +#define MEIG_PRODUCT_SLM790 0x4D20 + /* * NOVATEL WIRELESS PRODUCTS * @@ -589,6 +593,7 @@ static void option_instat_callback(struct urb *urb); static const struct usb_device_id option_ids[] = { + { USB_DEVICE(MEIG_VENDOR_ID, MEIG_PRODUCT_SLM790) }, { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) }, { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) }, { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA_LIGHT) }, -- Gitee From c26946743f6a962938e742670b58a237a33cf61a Mon Sep 17 00:00:00 2001 From: taolan Date: Mon, 28 Nov 2022 20:20:08 +0000 Subject: [PATCH 5/5] module: support 16dv300 simplified defconfig driver inclusion category: bugfix bugzilla:https://gitee.com/openeuler/kernel/issues/I5XHIQ --------------------------------------------------------- add 16dv300 defconfig. Signed-off-by: taolan --- arch/arm/configs/hi3516dv300_smp_defconfig | 2181 ++++++++++++++++++++ 1 file changed, 2181 insertions(+) create mode 100644 arch/arm/configs/hi3516dv300_smp_defconfig diff --git a/arch/arm/configs/hi3516dv300_smp_defconfig b/arch/arm/configs/hi3516dv300_smp_defconfig new file mode 100644 index 000000000000..10eee5a18c1b --- /dev/null +++ b/arch/arm/configs/hi3516dv300_smp_defconfig @@ -0,0 +1,2181 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.19.90 Kernel Configuration +# + +# +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B042_20210105) 7.3.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70300 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_DEBUG is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +CONFIG_PID_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_PROFILING is not set +CONFIG_ARM=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_PGTABLE_LEVELS=2 + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +CONFIG_ARCH_HISI_BVT=y + +# +# Hisilicon BVT platform type +# +# CONFIG_ARCH_HI3521DV200 is not set +# CONFIG_ARCH_HI3520DV500 is not set +# CONFIG_ARCH_HI3516A is not set +# CONFIG_ARCH_HI3516CV500 is not set +CONFIG_ARCH_HI3516DV300=y +# CONFIG_ARCH_HI3516EV200 is not set +# CONFIG_ARCH_HI3516EV300 is not set +# CONFIG_ARCH_HI3518EV300 is not set +# CONFIG_ARCH_HI3516DV200 is not set +# CONFIG_ARCH_HI3556V200 is not set +# CONFIG_ARCH_HI3559V200 is not set +# CONFIG_ARCH_HI3536DV100 is not set +# CONFIG_ARCH_HI3521A is not set +# CONFIG_ARCH_HI3531A is not set +# CONFIG_ARCH_HI3556AV100 is not set +# CONFIG_ARCH_HI3519AV100 is not set +# CONFIG_ARCH_HI3568V100 is not set +# CONFIG_ARCH_HISI_BVT_AMP is not set +# CONFIG_HISI_MC is not set +CONFIG_HI_ZRELADDR=0x80008000 +CONFIG_HI_PARAMS_PHYS=0x00000100 +CONFIG_HI_INITRD_PHYS=0x00800000 +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NPCM is not set + +# +# TI OMAP/AM/DM/DRA Family +# +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_TANGO is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_SPECTRE=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_KUSER_HELPERS=y +CONFIG_VDSO=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_DEBUG_ALIGN_RODATA=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_818325_852422 is not set +# CONFIG_ARM_ERRATA_821420 is not set +# CONFIG_ARM_ERRATA_825619 is not set +# CONFIG_ARM_ERRATA_852421 is not set +# CONFIG_ARM_ERRATA_852423 is not set + +# +# Bus support +# +# CONFIG_PCI is not set + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_MCPM is not set +# CONFIG_BIG_LITTLE is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=2 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=0 +CONFIG_HZ_FIXED=0 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +CONFIG_HZ_1000=y +CONFIG_HZ=1000 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_ARM_PATCH_IDIV=y +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_CMDLINE="" +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y + +# +# Firmware Drivers +# +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# Tegra firmware driver +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_VIRTUALIZATION is not set + +# +# General architecture-dependent options +# +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_REFCOUNT_FULL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_PLUGIN_HOSTCC="" +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_CMDLINE_PARSER=y +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_CMDLINE_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=m +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_MQ_IOSCHED_DEADLINE=m +CONFIG_MQ_IOSCHED_KYBER=m +# CONFIG_IOSCHED_BFQ is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_ELF_FDPIC is not set +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Memory Management options +# +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +# CONFIG_NET is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_GENERIC_ARCH_TOPOLOGY=y + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_SIMPLE_PM_BUS is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_GNSS is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_OF_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# Partition parsers +# + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_ONENAND is not set +# CONFIG_HISI_NAND_FS_MAY_NO_YAFFS2 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_NAND_HIFMC100 is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +CONFIG_SPI_HISI_SFC=y +# CONFIG_MTD_SPI_IDS is not set +# CONFIG_CLOSE_SPI_8PIN_4IO is not set +CONFIG_HISI_SPI_BLOCK_PROTECT=y +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS or INET not selected +# +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_TRACE_SINK is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_HIBVT=y +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +CONFIG_DMA_MSG_MIN_LEN=5 +CONFIG_DMA_MSG_MAX_LEN=4090 +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MEM is not set + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_PL022=y +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +CONFIG_GPIO_PL061=y +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_HISI=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_VERSATILE is not set +CONFIG_POWER_RESET_SYSCON=y +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_SYSCON_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LTC3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +CONFIG_MFD_HISI_FMC=y +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8XXX is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set + +# +# Media drivers +# +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# + +# +# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Audio decoders, processors and mixers +# + +# +# RDS decoders +# + +# +# Video decoders +# + +# +# Video and audio decoders +# + +# +# Video encoders +# + +# +# Camera sensor devices +# + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Audio/Video compression chips +# + +# +# SDR tuner chips +# + +# +# Miscellaneous helper chips +# + +# +# Sensors used on soc_camera driver +# + +# +# Media SPI Adapters +# + +# +# Tools to develop new frontends +# + +# +# Graphics support +# +# CONFIG_IMX_IPUV3_CORE is not set +# CONFIG_DRM is not set +# CONFIG_DRM_DP_CEC is not set + +# +# ACP (Audio CoProcessor) Configuration +# + +# +# AMD Library routines +# + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# CONFIG_LOGO is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_HIBVT=m +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_VC5 is not set +CONFIG_COMMON_CLK_HI3516DV300=y +CONFIG_RESET_HISI=y +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set +CONFIG_ARM_TIMER_SP804=y +# CONFIG_TIMER_HISP804 is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set + +# +# NXP/Freescale QorIQ SoC drivers +# + +# +# i.MX SoC drivers +# + +# +# Qualcomm SoC drivers +# +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_HI_USB_PHY is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_PMU=y +# CONFIG_RAS is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_HI_DMAC is not set +# CONFIG_HIEDMAC is not set + +# +# Hisilicon driver support +# +# CONFIG_CMA_MEM_SHARED is not set +# CONFIG_CMA_ADVANCE_SHARE is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +CONFIG_MEMFD_CREATE=y +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NLS is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=m +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +# CONFIG_CRYPTO_SEQIV is not set +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=m +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=m +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=m +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +CONFIG_CRYPTO_DRBG=m +CONFIG_CRYPTO_JITTERENTROPY=m +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_CCREE is not set + +# +# Certificates for signature checking +# + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +# CONFIG_CRC8 is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SGL_ALLOC=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y +# CONFIG_TRACING is not set +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +# CONFIG_MEMTEST is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_IO_STRICT_DEVMEM is not set +# CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_WX is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_HI3516DV300_UART=y +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_DEBUG_SEMIHOSTING is not set +# CONFIG_DEBUG_LL_UART_8250 is not set +# CONFIG_DEBUG_LL_UART_PL01X is not set +CONFIG_DEBUG_LL_INCLUDE="debug/pl01x.S" +CONFIG_DEBUG_UART_PL01X=y +CONFIG_DEBUG_UART_PHYS=0x120a0000 +CONFIG_DEBUG_UART_VIRT=0xfe4a0000 +# CONFIG_DEBUG_UNCOMPRESS is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_EARLY_PRINTK is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_CORESIGHT is not set -- Gitee