From 4fa347e506f372feeace5a4efe8a1cf5b88f563f Mon Sep 17 00:00:00 2001 From: Wenhui Fan Date: Tue, 28 Oct 2025 14:11:03 +0800 Subject: [PATCH] EDAC/amd64: The width of hash value is 2 bits for Hygon family 18h model 6h processors hygon inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ID4KX5 CVE: N/A Reference: https://gitee.com/anolis/cloud-kernel/commit/95e0df888d5d977c100b27b627b800a2a09baba8 -------------------------------------------------------------------------------- ANBZ: #26500 It has 2 bits hash value when hash enabled for hygon family 18h model 6h. Hygon-SIG: commit none hygon anolis: EDAC/amd64: The width of hash value is 2 bits for Hygon family 18h model 6h processors Hygon-SIG: commit 95e0df888d5d anolis EDAC/amd64: The width of hash value is 2 bits for Hygon family 18h model 6h processors Add 2 bits of hash values EDAC support for Hygon Processors. Signed-off-by: Wenhui Fan Cc: hygon-arch@list.openanolis.cn Reviewed-by: Guixin Liu Link: https://gitee.com/anolis/cloud-kernel/pulls/5912 [ Aichun Shi: amend commit log and resolve the conflict ] Signed-off-by: Aichun Shi --- drivers/edac/amd64_edac.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 426e24d8ae75..96a44a4a539d 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1049,7 +1049,10 @@ static int hygon_umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sy break; case 8: - intlv_num_chan = 1; + if (boot_cpu_data.x86_model >= 0x6) + intlv_num_chan = 2; + else + intlv_num_chan = 1; hash_enabled = true; break; default: @@ -1164,10 +1167,16 @@ static int hygon_umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sy (ret_addr >> 30) ^ cs_id; - hashed_bit &= BIT(0); - - if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) - ret_addr ^= BIT(intlv_addr_bit); + if (boot_cpu_data.x86_model >= 0x6) { + hashed_bit &= 0x3; + if (hashed_bit != ((ret_addr >> intlv_addr_bit) & 0x3)) + ret_addr = (ret_addr & ~((u64)3 << intlv_addr_bit)) | + (hashed_bit << intlv_addr_bit); + } else { + hashed_bit &= BIT(0); + if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0))) + ret_addr ^= BIT(intlv_addr_bit); + } } /* Is calculated system address is above DRAM limit address? */ -- Gitee