【spec525性能分析】SR-add开启后引入iv过多

mc.c  函数：frame_init_lowres_core

C源码：
```
static void frame_init_lowres_core( uint8_t *src0, uint8_t *dst0, uint8_t *dsth, uint8_t *dstv, uint8_t *dstc,
                                    int src_stride, int dst_stride, int width, int height )
{
    for( int y = 0; y < height; y++ )
    {
        uint8_t *src1 = src0+src_stride;
        uint8_t *src2 = src1+src_stride;
        for( int x = 0; x<width; x++ )
        {
            // slower than naive bilinear, but matches asm
#define FILTER(a,b,c,d) ((((a+b+1)>>1)+((c+d+1)>>1)+1)>>1)
            dst0[x] = FILTER(src0[2*x  ], src1[2*x  ], src0[2*x+1], src1[2*x+1]);
            dsth[x] = FILTER(src0[2*x+1], src1[2*x+1], src0[2*x+2], src1[2*x+2]);
            dstv[x] = FILTER(src1[2*x  ], src2[2*x  ], src1[2*x+1], src2[2*x+1]);
            dstc[x] = FILTER(src1[2*x+1], src2[2*x+1], src1[2*x+2], src2[2*x+2]);
#undef FILTER
        }
        src0 += src_stride*2;
        dst0 += dst_stride;
        dsth += dst_stride;
        dstv += dst_stride;
        dstc += dst_stride;
    }
}
```

SR-add开启后 汇编：
```
 889 .L.482__4:
 890   ldr w10, [x29,#20]
 891   cmp w10, #0
 892   ble .L.482__1
 893   mov w0, #0
 894   ldr w10, [x29,#20]
 895   lsl w2, w10, #1
 896   ldr w10, [x29,#24]
 897   add x5, x20, w10, SXTW  // x5 = src1 = scr0 + src_stride
 898   mov x7, x23     <==== "dst0 + x"
 899   mov x8, x24     <==== "dsth + x"
 900   mov x9, x25   <==== "dstv + x"
 901   mov x11, x26   <==== "dstc + x"
 902   ldr w10, [x29,#24]
 903   add x6, x5, w10, SXTW   // x6 = src2 + 2x
 904   mov x10, x20   <=====  "src0 + 2x"
 905   mov x1, x5   <=====  "src1 + 2x"
 906   add x18, x5, w2, SXTW   // x18 = src1 + width * 2
 907   add x2, x20, #1   <=====  "src0 + 2x + 1"
 908   add x12, x20, #2   <=====  "src0 + 2x + 2"
 909   add x3, x5, #1   <=====  "src1 + 2x + 1"
 910   add x13, x5, #2  <=====  "src1 + 2x + 2"
 911   add x4, x6, #1    <=====  "src2 + 2x + 1"
 912   add x14, x6, #2   <=====  "src2 + 2x + 2"
 913 .L.482__2:
 914   ldrb  w15, [x10]
 915   ldrb  w27, [x1]
 916   add w15, w15, w27
 917   add w15, w15, #1
 918   asr w15, w15, #1
 919   ldrb  w27, [x2]
 920   ldrb  w28, [x3]
 921   add w27, w27, w28
 922   add w27, w27, #1
 923   asr w27, w27, #1
 924   add w15, w15, w27
 925   add w15, w15, #1
 926   asr w15, w15, #1
 927   strb  w15, [x7]
 928   ldrb  w15, [x2]
 929   ldrb  w27, [x3]
 930   add w15, w15, w27
 931   add w15, w15, #1
 932   asr w15, w15, #1
 933   ldrb  w27, [x12]
 934   ldrb  w28, [x13]
 935   add w27, w27, w28
 936   add w27, w27, #1
 937   asr w27, w27, #1
 938   add w15, w15, w27
 939   add w15, w15, #1
 940   asr w15, w15, #1
 941   strb  w15, [x8]
 942   ldrb  w15, [x1]
 943   ldrb  w27, [x6]
 944   add w15, w15, w27
 945   add w15, w15, #1
 946   asr w15, w15, #1
 947   sxtw  x27, w0
 948   add x27, x27, x5
 949   ldrb  w27, [x27,#1]
 950   ldrb  w28, [x4]
 951   add w27, w27, w28
 952   add w27, w27, #1
 953   asr w27, w27, #1
 954   add w15, w15, w27
 955   add w15, w15, #1
 956   asr w15, w15, #1
 957   strb  w15, [x9]
 958   sxtw  x15, w0
 959   add x15, x15, x5
 960   ldrb  w15, [x15,#1]
 961   ldrb  w27, [x4]
 962   add w15, w15, w27
 963   add w15, w15, #1
 964   asr w15, w15, #1
 965   sxtw  x27, w0
 966   add x27, x27, x5
 967   ldrb  w27, [x27,#2]
 968   ldrb  w28, [x14]
 969   add w27, w27, w28
 970   add w27, w27, #1
 971   asr w27, w27, #1
 972   add w15, w15, w27
 973   add w15, w15, #1
 974   asr w15, w15, #1
 975   strb  w15, [x11]
 976   add x11, x11, #1
 977   add x9, x9, #1
 978   add x8, x8, #1
 979   add x7, x7, #1
 980   add w0, w0, #2
 981   add x14, x14, #2
 982   add x4, x4, #2
 983   add x13, x13, #2
 984   add x3, x3, #2
 985   add x12, x12, #2
 986   add x2, x2, #2
 987   add x6, x6, #2
 988   add x1, x1, #2
 989   add x10, x10, #2
 990   cmp x1, x18
 991   blo .L.482__2
 992 .L.482__1:
 993   add x20, x20, x22
 994   add x23, x23, x19
 995   add x24, x24, x19
 996   add x25, x25, x19
 997   add x26, x26, x19
 998   add w21, w21, #1
 999   ldr w10, [x29,#16]
1000   cmp w21, w10
1001   blt .L.482__4
```

**问题1：**
w0的存在完全冗余，cvt(w0)可以外提，多引入一个iv
**问题2：**
SR-add做的过于激进导致IV数量激增,共14个iv
其中x11,x9,x8,x7 可归一为一个iv, 后续ldr使用[base, iv] 模式，base分别为dstc/dstv/dsth/dst0，iv为x
其中x14,x4,x6可以使用x6（src2 + 2x）作为iv x14,x4 表示为 x6 + offset模式
x13,x3,x1;  x12,x2,x10同理；所以最后只需4个iv即可

**修改建议：**
最贴近iread/iassign的add不作为SR-add的目标，因为这样可以充分利用后端ISA能力又不引入新的iv，同时base,offset需要进行规范化,将地址计算充分的通过 **分配率和结合律** 将base和offset模式做成如下模式：
1） 如果地址中不不存在常数，最好将当前循环的循环不变量的计算结果作为base，其余提出作为iv，这样相同步进、初值不同的iv均可归一，x11,x9,x8,x7就是这种情况
2)  如果地址中有常数，将常数作为offset，base作为iv，如果一系列的base + const中常数偏移存在负数（-c），可将base-c作为iv外提，其余常数+c后作为offset

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