# Verilog_module

**Repository Path**: jageros/Verilog_module

## Basic Information

- **Project Name**: Verilog_module
- **Description**: Verilog模块代码
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2016-12-25
- **Last Updated**: 2024-07-25

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

#Verilog_module