# chisel-empty

**Repository Path**: ha1ha1/chisel-empty

## Basic Information

- **Project Name**: chisel-empty
- **Description**: No description available
- **Primary Language**: Unknown
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 1
- **Created**: 2025-11-03
- **Last Updated**: 2025-11-03

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# chisel-empty

An almost empty chisel project (and adder) as a starting point for hardware design.

To generate Verilog code for the adder execute:
```bash
make
```

Run the tests with:
```bash
make test
```

Cleanup the repository with:
```bash
make clean
```