diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 4eacac39a5018b6f38457f618de925936fb2870f..f5e5906ae36c9dc9b8cdaabb6c630983096c0126 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -296,6 +296,9 @@ static u64 amd_pmu_event_map(int hw_event)
 	if (cpu_feature_enabled(X86_FEATURE_ZEN1))
 		return amd_zen1_perfmon_event_map[hw_event];
 
+	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+		return amd_zen1_perfmon_event_map[hw_event];
+
 	return amd_perfmon_event_map[hw_event];
 }
 
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 497ad86ef2256b27d2d05ff0d5a525f56b3aa11d..a2948b68ba83b1924462ac79242457adeb7ca18f 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -83,6 +83,7 @@ bool amd_nb_has_feature(unsigned int feature);
 struct amd_northbridge *node_to_amd_nb(int node);
 
 bool hygon_f18h_m4h(void);
+bool hygon_f18h_m10h(void);
 u16 hygon_nb_num(void);
 int get_df_id(struct pci_dev *misc, u8 *id);
 
@@ -127,6 +128,7 @@ static inline struct amd_northbridge *node_to_amd_nb(int node)
 #define amd_gart_present(x)	false
 
 #define hygon_f18h_m4h		false
+#define hygon_f18h_m10h		false
 #define hygon_nb_num(x)	0
 #define get_df_id(x, y)	NULL
 
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index cc5c9b0b72c384b8c3974c50c92cc77aa8f69daf..f2830067e174102ef6e9d16debb988012e1c0415 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -262,6 +262,20 @@ bool hygon_f18h_m4h(void)
 }
 EXPORT_SYMBOL_GPL(hygon_f18h_m4h);
 
+bool hygon_f18h_m10h(void)
+{
+	if (boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
+		return false;
+
+	if (boot_cpu_data.x86 == 0x18 &&
+	    boot_cpu_data.x86_model >= 0x10 &&
+	    boot_cpu_data.x86_model <= 0x1f)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(hygon_f18h_m10h);
+
 u16 hygon_nb_num(void)
 {
 	return nb_num;
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 5890c656590400e91c0221a987e37430b3b0c544..2286146e0ac7e43254e8589630d54d7e7f19fe4b 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1154,7 +1154,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	ctx.inst_id = umc;
 
 	/* Read DramOffset, check if base 1 is used. */
-	if (hygon_f18h_m4h() &&
+	if ((hygon_f18h_m4h() || hygon_f18h_m10h()) &&
 	    df_indirect_read_instance(nid, 0, 0x214, umc, &ctx.tmp))
 		goto out_err;
 	else if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp))
@@ -1182,7 +1182,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	}
 
 	intlv_num_sockets = 0;
-	if (hygon_f18h_m4h())
+	if (hygon_f18h_m4h() || hygon_f18h_m10h())
 		intlv_num_sockets = (ctx.tmp >> 2) & 0x3;
 	lgcy_mmio_hole_en = ctx.tmp & BIT(1);
 	intlv_num_chan	  = (ctx.tmp >> 4) & 0xF;
@@ -1200,14 +1200,15 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 	if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp))
 		goto out_err;
 
-	if (!hygon_f18h_m4h())
+	if (!hygon_f18h_m4h() && !hygon_f18h_m10h())
 		intlv_num_sockets = (ctx.tmp >> 8) & 0x1;
 	intlv_num_dies	  = (ctx.tmp >> 10) & 0x3;
 	dram_limit_addr	  = ((ctx.tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);
 
 	intlv_addr_bit = intlv_addr_sel + 8;
 
-	if (hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6) {
+	if ((hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6) ||
+	    hygon_f18h_m10h()) {
 		if (df_indirect_read_instance(nid, 0, 0x60, umc, &ctx.tmp))
 			goto out_err;
 		intlv_num_dies = ctx.tmp & 0x3;
@@ -1272,7 +1273,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
 		if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp))
 			goto out_err;
 
-		if (hygon_f18h_m4h())
+		if (hygon_f18h_m4h() || hygon_f18h_m10h())
 			cs_fabric_id = (ctx.tmp >> 8) & 0x7FF;
 		else
 			cs_fabric_id = (ctx.tmp >> 8) & 0xFF;
@@ -1655,12 +1656,29 @@ static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
 	}
 }
 
+static bool hygon_umc_channel_enabled(struct amd64_pvt *pvt, int channel)
+{
+	u32 enable;
+
+	if (hygon_f18h_m10h()) {
+		__df_indirect_read(pvt->mc_node_id, 1, 0x32c, 0xc, &enable);
+		if ((enable & BIT(channel)))
+			return true;
+		return false;
+	}
+
+	return true;
+}
+
 static void umc_dump_misc_regs(struct amd64_pvt *pvt)
 {
 	struct amd64_umc *umc;
 	u32 i, tmp, umc_base;
 
 	for_each_umc(i) {
+		if (!hygon_umc_channel_enabled(pvt, i))
+			continue;
+
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
 		else
@@ -1777,6 +1795,9 @@ static void umc_read_base_mask(struct amd64_pvt *pvt)
 	int cs, umc;
 
 	for_each_umc(umc) {
+		if (!hygon_umc_channel_enabled(pvt, umc))
+			continue;
+
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, umc);
 		else
@@ -1885,7 +1906,9 @@ static void umc_determine_memory_type(struct amd64_pvt *pvt)
 		 * Check if the system supports the "DDR Type" field in UMC Config
 		 * and has DDR5 DIMMs in use.
 		 */
-		if ((pvt->flags.zn_regs_v2 || hygon_f18h_m4h()) &&
+		if ((pvt->flags.zn_regs_v2 ||
+		     hygon_f18h_m4h() ||
+		     hygon_f18h_m10h()) &&
 		    ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
 			if (umc->dimm_cfg & BIT(5))
 				umc->dram_type = MEM_LRDDR5;
@@ -3166,7 +3189,8 @@ static void decode_umc_error(int node_id, struct mce *m)
 
 	pvt->ops->get_err_info(m, &err);
 
-	if (hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6)
+	if ((hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6) ||
+	    hygon_f18h_m10h())
 		umc = (err.channel << 1) + ((m->ipid & BIT(13)) >> 13);
 	else
 		umc = err.channel;
@@ -3245,6 +3269,9 @@ static void umc_read_mc_regs(struct amd64_pvt *pvt)
 
 	/* Read registers from each UMC */
 	for_each_umc(i) {
+		if (!hygon_umc_channel_enabled(pvt, i))
+			continue;
+
 		if (hygon_f18h_m4h())
 			umc_base = get_umc_base_f18h_m4h(pvt->mc_node_id, i);
 		else
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 06e29d2b51d1ed32071d0371369bb1e9de2a3ba1..cf0298e448498d484d18cebc34b13c25946897f2 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -168,6 +168,33 @@ static const char * const smca_ls_mce_desc[] = {
 	"L2 Fill Data error",
 };
 
+/* Hygon Model7h Scalable MCA LS error strings */
+static const char * const smca_ls_mce_hygon_desc[] = {
+	"Load queue parity error",
+	"Store queue parity error",
+	"Miss address buffer payload parity error",
+	"Level 1 TLB parity error",
+	"DC Tag error type 5",
+	"DC Tag error type 6",
+	"DC Tag error type 1",
+	"Internal error type 1",
+	"Internal error type 2",
+	"System Read Data Error 0",
+	"System Read Data Error 1",
+	"System Read Data Error 2",
+	"System Read Data Error 3",
+	"DC Tag error type 2",
+	"DC Data error type 1 and poison consumption",
+	"DC Data error type 2",
+	"DC Data error type 3",
+	"DC Tag error type 4",
+	"Level 2 TLB parity error",
+	"PDC parity error",
+	"DC Tag error type 3",
+	"DC Tag error type 5",
+	"L2 Fill Data error",
+};
+
 static const char * const smca_ls2_mce_desc[] = {
 	"An ECC error was detected on a data cache read by a probe or victimization",
 	"An ECC error or L2 poison was detected on a data cache read by a load",
@@ -217,6 +244,31 @@ static const char * const smca_if_mce_desc[] = {
 	"CT MCE",
 };
 
+/* Hygon Model7h Scalable MCA IF error strings */
+static const char * const smca_if_mce_hygon_desc[] = {
+	"Op Cache Microtag Probe Port Parity Error",
+	"IC Microtag or Full Tag Multi-hit Error",
+	"IC Full Tag Parity Error",
+	"IC Data Array Parity Error",
+	"Decoupling Queue PhysAddr Parity Error",
+	"L0 ITLB Parity Error",
+	"L1 ITLB Parity Error",
+	"L2 ITLB Parity Error",
+	"BPQ 0 Snoop Parity Error",
+	"BPQ 1 Snoop Parity Error",
+	"BPQ 2 Snoop Parity Error",
+	"BPQ 3 Snoop Parity Error",
+	"L1 BTB Multi-Match Error",
+	"L2 BTB Multi-Match Error",
+	"L2 Cache Response Poison Error",
+	"System Read Data Error",
+	"Hardware Assertion Error",
+	"L1-TLB Multi-Hit",
+	"L2-TLB Multi-Hit",
+	"BSR Parity Error",
+	"CT MCE",
+};
+
 static const char * const smca_l2_mce_desc[] = {
 	"L2M Tag Multiple-Way-Hit error",
 	"L2M Tag or State Array ECC Error",
@@ -1433,6 +1485,16 @@ static int __init mce_amd_init(void)
 out:
 	pr_info("MCE: In-kernel MCE decoding enabled.\n");
 
+	if (c->x86_vendor == X86_VENDOR_HYGON &&
+	    c->x86_model >= 0x7 && c->x86_model <= 0xf) {
+		smca_mce_descs[SMCA_LS].descs = smca_ls_mce_hygon_desc;
+		smca_mce_descs[SMCA_LS].num_descs = ARRAY_SIZE(smca_ls_mce_hygon_desc);
+		smca_mce_descs[SMCA_IF].descs = smca_if_mce_hygon_desc;
+		smca_mce_descs[SMCA_IF].num_descs = ARRAY_SIZE(smca_if_mce_hygon_desc);
+		pr_info("MCE: Hygon Fam%xh Model%xh smca mce descs setup.\n",
+				c->x86, c->x86_model);
+	}
+
 	mce_register_decode_chain(&amd_mce_dec_nb);
 
 	return 0;
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index f6c1f7e04d471d342d5ecc01067aeb49097dd08a..4beddd8cc42014cfa4dceba9d93a63034568bf84 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -3045,7 +3045,7 @@ static bool __init check_ioapic_information(void)
 			   (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&
 			    boot_cpu_data.x86 == 0x18 &&
 			    boot_cpu_data.x86_model >= 0x4 &&
-			    boot_cpu_data.x86_model <= 0xf &&
+			    boot_cpu_data.x86_model <= 0x10 &&
 			    devid == IOAPIC_SB_DEVID_FAM18H_M4H)) {
 			has_sb_ioapic = true;
 			ret           = true;